if_axe.c revision 1.111
1 /* $NetBSD: if_axe.c,v 1.111 2019/08/11 02:37:03 mrg Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.111 2019/08/11 02:37:03 mrg Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_usb.h" 94 #include "opt_net_mpsafe.h" 95 #endif 96 97 #include <sys/param.h> 98 #include <sys/kernel.h> 99 #include <sys/module.h> 100 #include <sys/socket.h> 101 #include <sys/sockio.h> 102 #include <sys/systm.h> 103 104 #include <dev/usb/usbnet.h> 105 #include <dev/usb/usbhist.h> 106 #include <dev/usb/if_axereg.h> 107 108 struct axe_type { 109 struct usb_devno axe_dev; 110 uint16_t axe_flags; 111 }; 112 113 struct axe_softc { 114 struct usbnet axe_un; 115 116 /* usbnet:un_flags values */ 117 #define AX178 __BIT(0) /* AX88178 */ 118 #define AX772 __BIT(1) /* AX88772 */ 119 #define AX772A __BIT(2) /* AX88772A */ 120 #define AX772B __BIT(3) /* AX88772B */ 121 #define AXSTD_FRAME __BIT(12) 122 #define AXCSUM_FRAME __BIT(13) 123 124 uint8_t axe_ipgs[3]; 125 uint8_t axe_phyaddrs[2]; 126 uint16_t sc_pwrcfg; 127 uint16_t sc_lenmask; 128 129 }; 130 131 #define AXE_IS_178_FAMILY(un) \ 132 ((un)->un_flags & (AX772 | AX772A | AX772B | AX178)) 133 134 #define AXE_IS_772(un) \ 135 ((un)->un_flags & (AX772 | AX772A | AX772B)) 136 137 #define AX_RXCSUM \ 138 (IFCAP_CSUM_IPv4_Rx | \ 139 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 140 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 141 142 #define AX_TXCSUM \ 143 (IFCAP_CSUM_IPv4_Tx | \ 144 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 145 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 146 147 /* 148 * AXE_178_MAX_FRAME_BURST 149 * max frame burst size for Ax88178 and Ax88772 150 * 0 2048 bytes 151 * 1 4096 bytes 152 * 2 8192 bytes 153 * 3 16384 bytes 154 * use the largest your system can handle without USB stalling. 155 * 156 * NB: 88772 parts appear to generate lots of input errors with 157 * a 2K rx buffer and 8K is only slightly faster than 4K on an 158 * EHCI port on a T42 so change at your own risk. 159 */ 160 #define AXE_178_MAX_FRAME_BURST 1 161 162 163 #ifdef USB_DEBUG 164 #ifndef AXE_DEBUG 165 #define axedebug 0 166 #else 167 static int axedebug = 20; 168 169 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 170 { 171 int err; 172 const struct sysctlnode *rnode; 173 const struct sysctlnode *cnode; 174 175 err = sysctl_createv(clog, 0, NULL, &rnode, 176 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 177 SYSCTL_DESCR("axe global controls"), 178 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 179 180 if (err) 181 goto fail; 182 183 /* control debugging printfs */ 184 err = sysctl_createv(clog, 0, &rnode, &cnode, 185 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 186 "debug", SYSCTL_DESCR("Enable debugging output"), 187 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 188 if (err) 189 goto fail; 190 191 return; 192 fail: 193 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 194 } 195 196 #endif /* AXE_DEBUG */ 197 #endif /* USB_DEBUG */ 198 199 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 200 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 201 #define AXEHIST_FUNC() USBHIST_FUNC() 202 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 203 204 /* 205 * Various supported device vendors/products. 206 */ 207 static const struct axe_type axe_devs[] = { 208 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 209 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 210 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 211 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 212 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 213 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 214 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 215 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 216 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 217 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 218 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 219 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 220 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 221 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 222 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 223 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 224 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 225 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 226 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 227 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 228 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 229 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 230 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 231 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 232 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 233 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 234 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 235 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 236 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 237 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 238 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 239 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 240 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 241 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 242 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 243 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 244 }; 245 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 246 247 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 248 { 0x8000, 0x8001, 2048 }, 249 { 0x8100, 0x8147, 4096 }, 250 { 0x8200, 0x81EB, 6144 }, 251 { 0x8300, 0x83D7, 8192 }, 252 { 0x8400, 0x851E, 16384 }, 253 { 0x8500, 0x8666, 20480 }, 254 { 0x8600, 0x87AE, 24576 }, 255 { 0x8700, 0x8A3D, 32768 } 256 }; 257 258 int axe_match(device_t, cfdata_t, void *); 259 void axe_attach(device_t, device_t, void *); 260 261 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 262 axe_match, axe_attach, usbnet_detach, usbnet_activate); 263 264 static void axe_stop(struct ifnet *, int); 265 static int axe_ioctl(struct ifnet *, u_long, void *); 266 static int axe_init(struct ifnet *); 267 static usbd_status axe_mii_read_reg(struct usbnet *, int, int, uint16_t *); 268 static usbd_status axe_mii_write_reg(struct usbnet *, int, int, uint16_t); 269 static void axe_mii_statchg(struct ifnet *); 270 static void axe_rx_loop(struct usbnet *, struct usbd_xfer *, 271 struct usbnet_chain *, uint32_t); 272 static unsigned axe_tx_prepare(struct usbnet *, struct mbuf *, 273 struct usbnet_chain *); 274 275 static void axe_ax88178_init(struct axe_softc *); 276 static void axe_ax88772_init(struct axe_softc *); 277 static void axe_ax88772a_init(struct axe_softc *); 278 static void axe_ax88772b_init(struct axe_softc *); 279 280 static struct usbnet_ops axe_ops = { 281 .uno_stop = axe_stop, 282 .uno_ioctl = axe_ioctl, 283 .uno_read_reg = axe_mii_read_reg, 284 .uno_write_reg = axe_mii_write_reg, 285 .uno_statchg = axe_mii_statchg, 286 .uno_tx_prepare = axe_tx_prepare, 287 .uno_rx_loop = axe_rx_loop, 288 .uno_init = axe_init, 289 }; 290 291 static usbd_status 292 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 293 { 294 AXEHIST_FUNC(); AXEHIST_CALLED(); 295 struct usbnet * const un = &sc->axe_un; 296 usb_device_request_t req; 297 usbd_status err; 298 299 usbnet_isowned_mii(un); 300 301 if (usbnet_isdying(un)) 302 return -1; 303 304 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 305 306 if (AXE_CMD_DIR(cmd)) 307 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 308 else 309 req.bmRequestType = UT_READ_VENDOR_DEVICE; 310 req.bRequest = AXE_CMD_CMD(cmd); 311 USETW(req.wValue, val); 312 USETW(req.wIndex, index); 313 USETW(req.wLength, AXE_CMD_LEN(cmd)); 314 315 err = usbd_do_request(un->un_udev, &req, buf); 316 if (err) 317 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 318 319 return err; 320 } 321 322 static usbd_status 323 axe_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 324 { 325 AXEHIST_FUNC(); AXEHIST_CALLED(); 326 struct axe_softc * const sc = usbnet_softc(un); 327 usbd_status err; 328 uint16_t data; 329 330 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 331 332 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 333 334 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 335 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 336 337 if (err) { 338 aprint_error_dev(un->un_dev, "read PHY failed\n"); 339 return err; 340 } 341 342 *val = le16toh(data); 343 if (AXE_IS_772(un) && reg == MII_BMSR) { 344 /* 345 * BMSR of AX88772 indicates that it supports extended 346 * capability but the extended status register is 347 * reserved for embedded ethernet PHY. So clear the 348 * extended capability bit of BMSR. 349 */ 350 *val &= ~BMSR_EXTCAP; 351 } 352 353 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 354 355 return USBD_NORMAL_COMPLETION; 356 } 357 358 static usbd_status 359 axe_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 360 { 361 struct axe_softc * const sc = usbnet_softc(un); 362 usbd_status err; 363 uint16_t aval; 364 365 aval = htole16(val); 366 367 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 368 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval); 369 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 370 371 return err; 372 } 373 374 static void 375 axe_mii_statchg(struct ifnet *ifp) 376 { 377 AXEHIST_FUNC(); AXEHIST_CALLED(); 378 379 struct usbnet * const un = ifp->if_softc; 380 struct axe_softc * const sc = usbnet_softc(un); 381 struct mii_data *mii = usbnet_mii(un); 382 int val, err; 383 384 if (usbnet_isdying(un)) 385 return; 386 387 val = 0; 388 usbnet_set_link(un, false); 389 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 390 val |= AXE_MEDIA_FULL_DUPLEX; 391 if (AXE_IS_178_FAMILY(un)) { 392 if ((IFM_OPTIONS(mii->mii_media_active) & 393 IFM_ETH_TXPAUSE) != 0) 394 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 395 if ((IFM_OPTIONS(mii->mii_media_active) & 396 IFM_ETH_RXPAUSE) != 0) 397 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 398 } 399 } 400 if (AXE_IS_178_FAMILY(un)) { 401 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 402 if (un->un_flags & AX178) 403 val |= AXE_178_MEDIA_ENCK; 404 switch (IFM_SUBTYPE(mii->mii_media_active)) { 405 case IFM_1000_T: 406 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 407 usbnet_set_link(un, true); 408 break; 409 case IFM_100_TX: 410 val |= AXE_178_MEDIA_100TX; 411 usbnet_set_link(un, true); 412 break; 413 case IFM_10_T: 414 usbnet_set_link(un, true); 415 break; 416 } 417 } 418 419 DPRINTF("val=0x%jx", val, 0, 0, 0); 420 usbnet_lock_mii(un); 421 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 422 usbnet_unlock_mii(un); 423 if (err) 424 aprint_error_dev(un->un_dev, "media change failed\n"); 425 } 426 427 static void 428 axe_setiff_locked(struct usbnet *un) 429 { 430 AXEHIST_FUNC(); AXEHIST_CALLED(); 431 struct axe_softc * const sc = usbnet_softc(un); 432 struct ifnet * const ifp = usbnet_ifp(un); 433 struct ethercom *ec = usbnet_ec(un); 434 struct ether_multi *enm; 435 struct ether_multistep step; 436 uint32_t h = 0; 437 uint16_t rxmode; 438 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 439 440 usbnet_isowned_mii(un); 441 442 if (usbnet_isdying(un)) 443 return; 444 445 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 446 aprint_error_dev(un->un_dev, "can't read rxmode"); 447 return; 448 } 449 rxmode = le16toh(rxmode); 450 451 rxmode &= 452 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 453 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 454 455 rxmode |= 456 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 457 458 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 459 if (ifp->if_flags & IFF_PROMISC) 460 rxmode |= AXE_RXCMD_PROMISC; 461 goto allmulti; 462 } 463 464 /* Now program new ones */ 465 ETHER_LOCK(ec); 466 ETHER_FIRST_MULTI(step, ec, enm); 467 while (enm != NULL) { 468 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 469 ETHER_ADDR_LEN) != 0) { 470 ETHER_UNLOCK(ec); 471 goto allmulti; 472 } 473 474 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 475 hashtbl[h >> 3] |= 1U << (h & 7); 476 ETHER_NEXT_MULTI(step, enm); 477 } 478 ETHER_UNLOCK(ec); 479 ifp->if_flags &= ~IFF_ALLMULTI; 480 rxmode |= AXE_RXCMD_MULTICAST; 481 482 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 483 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 484 return; 485 486 allmulti: 487 ifp->if_flags |= IFF_ALLMULTI; 488 rxmode |= AXE_RXCMD_ALLMULTI; 489 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 490 } 491 492 static void 493 axe_setiff(struct usbnet *un) 494 { 495 usbnet_lock_mii(un); 496 axe_setiff_locked(un); 497 usbnet_unlock_mii(un); 498 } 499 500 static void 501 axe_ax_init(struct usbnet *un) 502 { 503 struct axe_softc * const sc = usbnet_softc(un); 504 505 int cmd = AXE_178_CMD_READ_NODEID; 506 507 if (un->un_flags & AX178) { 508 axe_ax88178_init(sc); 509 } else if (un->un_flags & AX772) { 510 axe_ax88772_init(sc); 511 } else if (un->un_flags & AX772A) { 512 axe_ax88772a_init(sc); 513 } else if (un->un_flags & AX772B) { 514 axe_ax88772b_init(sc); 515 return; 516 } else { 517 cmd = AXE_172_CMD_READ_NODEID; 518 } 519 520 if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) { 521 aprint_error_dev(un->un_dev, 522 "failed to read ethernet address\n"); 523 } 524 } 525 526 527 static void 528 axe_reset(struct usbnet *un) 529 { 530 531 usbnet_isowned_mii(un); 532 533 if (usbnet_isdying(un)) 534 return; 535 536 /* 537 * softnet_lock can be taken when NET_MPAFE is not defined when calling 538 * if_addr_init -> if_init. This doesn't mix well with the 539 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 540 * can fire during the wait and attempt to take softnet_lock and then 541 * block the softclk thread meaning the wait never ends. 542 */ 543 #ifndef NET_MPSAFE 544 /* XXX What to reset? */ 545 546 /* Wait a little while for the chip to get its brains in order. */ 547 DELAY(1000); 548 #else 549 axe_ax_init(un); 550 #endif 551 } 552 553 static int 554 axe_get_phyno(struct axe_softc *sc, int sel) 555 { 556 int phyno; 557 558 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 559 case PHY_TYPE_100_HOME: 560 /* FALLTHROUGH */ 561 case PHY_TYPE_GIG: 562 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 563 break; 564 case PHY_TYPE_SPECIAL: 565 /* FALLTHROUGH */ 566 case PHY_TYPE_RSVD: 567 /* FALLTHROUGH */ 568 case PHY_TYPE_NON_SUP: 569 /* FALLTHROUGH */ 570 default: 571 phyno = -1; 572 break; 573 } 574 575 return phyno; 576 } 577 578 #define AXE_GPIO_WRITE(x, y) do { \ 579 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 580 usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \ 581 } while (0) 582 583 static void 584 axe_ax88178_init(struct axe_softc *sc) 585 { 586 AXEHIST_FUNC(); AXEHIST_CALLED(); 587 struct usbnet * const un = &sc->axe_un; 588 int gpio0, ledmode, phymode; 589 uint16_t eeprom, val; 590 591 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 592 /* XXX magic */ 593 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 594 eeprom = 0xffff; 595 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 596 597 eeprom = le16toh(eeprom); 598 599 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 600 601 /* if EEPROM is invalid we have to use to GPIO0 */ 602 if (eeprom == 0xffff) { 603 phymode = AXE_PHY_MODE_MARVELL; 604 gpio0 = 1; 605 ledmode = 0; 606 } else { 607 phymode = eeprom & 0x7f; 608 gpio0 = (eeprom & 0x80) ? 0 : 1; 609 ledmode = eeprom >> 8; 610 } 611 612 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 613 614 /* Program GPIOs depending on PHY hardware. */ 615 switch (phymode) { 616 case AXE_PHY_MODE_MARVELL: 617 if (gpio0 == 1) { 618 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 619 hz / 32); 620 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 621 hz / 32); 622 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 623 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 624 hz / 32); 625 } else { 626 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 627 AXE_GPIO1_EN, hz / 3); 628 if (ledmode == 1) { 629 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 630 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 631 hz / 3); 632 } else { 633 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 634 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 635 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 636 AXE_GPIO2_EN, hz / 4); 637 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 638 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 639 } 640 } 641 break; 642 case AXE_PHY_MODE_CICADA: 643 case AXE_PHY_MODE_CICADA_V2: 644 case AXE_PHY_MODE_CICADA_V2_ASIX: 645 if (gpio0 == 1) 646 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 647 AXE_GPIO0_EN, hz / 32); 648 else 649 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 650 AXE_GPIO1_EN, hz / 32); 651 break; 652 case AXE_PHY_MODE_AGERE: 653 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 654 AXE_GPIO1_EN, hz / 32); 655 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 656 AXE_GPIO2_EN, hz / 32); 657 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 658 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 659 AXE_GPIO2_EN, hz / 32); 660 break; 661 case AXE_PHY_MODE_REALTEK_8211CL: 662 case AXE_PHY_MODE_REALTEK_8211BN: 663 case AXE_PHY_MODE_REALTEK_8251CL: 664 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 665 AXE_GPIO1 | AXE_GPIO1_EN; 666 AXE_GPIO_WRITE(val, hz / 32); 667 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 668 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 669 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 670 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 671 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005); 672 axe_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000); 673 axe_mii_read_reg(un, un->un_phyno, 0x0001, &val); 674 axe_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080); 675 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000); 676 } 677 break; 678 default: 679 /* Unknown PHY model or no need to program GPIOs. */ 680 break; 681 } 682 683 /* soft reset */ 684 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 685 usbd_delay_ms(un->un_udev, 150); 686 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 687 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 688 usbd_delay_ms(un->un_udev, 150); 689 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 690 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 691 usbd_delay_ms(un->un_udev, 10); 692 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 693 } 694 695 static void 696 axe_ax88772_init(struct axe_softc *sc) 697 { 698 AXEHIST_FUNC(); AXEHIST_CALLED(); 699 struct usbnet * const un = &sc->axe_un; 700 701 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 702 usbd_delay_ms(un->un_udev, 40); 703 704 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 705 /* ask for the embedded PHY */ 706 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 707 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 708 usbd_delay_ms(un->un_udev, 10); 709 710 /* power down and reset state, pin reset state */ 711 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 712 usbd_delay_ms(un->un_udev, 60); 713 714 /* power down/reset state, pin operating state */ 715 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 716 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 717 usbd_delay_ms(un->un_udev, 150); 718 719 /* power up, reset */ 720 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 721 722 /* power up, operating */ 723 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 724 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 725 } else { 726 /* ask for external PHY */ 727 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 728 NULL); 729 usbd_delay_ms(un->un_udev, 10); 730 731 /* power down internal PHY */ 732 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 733 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 734 } 735 736 usbd_delay_ms(un->un_udev, 150); 737 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 738 } 739 740 static void 741 axe_ax88772_phywake(struct axe_softc *sc) 742 { 743 AXEHIST_FUNC(); AXEHIST_CALLED(); 744 struct usbnet * const un = &sc->axe_un; 745 746 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 747 /* Manually select internal(embedded) PHY - MAC mode. */ 748 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 749 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 750 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 751 } else { 752 /* 753 * Manually select external PHY - MAC mode. 754 * Reverse MII/RMII is for AX88772A PHY mode. 755 */ 756 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 757 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 758 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 759 } 760 761 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 762 AXE_SW_RESET_IPRL, NULL); 763 764 /* T1 = min 500ns everywhere */ 765 usbd_delay_ms(un->un_udev, 150); 766 767 /* Take PHY out of power down. */ 768 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 769 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 770 } else { 771 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 772 } 773 774 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 775 usbd_delay_ms(un->un_udev, 600); 776 777 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 778 779 /* T3 = 500ns everywhere */ 780 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 781 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 782 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 783 } 784 785 static void 786 axe_ax88772a_init(struct axe_softc *sc) 787 { 788 AXEHIST_FUNC(); AXEHIST_CALLED(); 789 790 /* Reload EEPROM. */ 791 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 792 axe_ax88772_phywake(sc); 793 /* Stop MAC. */ 794 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 795 } 796 797 static void 798 axe_ax88772b_init(struct axe_softc *sc) 799 { 800 AXEHIST_FUNC(); AXEHIST_CALLED(); 801 struct usbnet * const un = &sc->axe_un; 802 uint16_t eeprom; 803 int i; 804 805 /* Reload EEPROM. */ 806 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 807 808 /* 809 * Save PHY power saving configuration(high byte) and 810 * clear EEPROM checksum value(low byte). 811 */ 812 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 813 &eeprom)) { 814 aprint_error_dev(un->un_dev, "failed to read eeprom\n"); 815 return; 816 } 817 818 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 819 820 /* 821 * Auto-loaded default station address from internal ROM is 822 * 00:00:00:00:00:00 such that an explicit access to EEPROM 823 * is required to get real station address. 824 */ 825 uint8_t *eaddr = un->un_eaddr; 826 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 827 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 828 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 829 aprint_error_dev(un->un_dev, 830 "failed to read eeprom\n"); 831 eeprom = 0; 832 } 833 eeprom = le16toh(eeprom); 834 *eaddr++ = (uint8_t)(eeprom & 0xFF); 835 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 836 } 837 /* Wakeup PHY. */ 838 axe_ax88772_phywake(sc); 839 /* Stop MAC. */ 840 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 841 } 842 843 #undef AXE_GPIO_WRITE 844 845 /* 846 * Probe for a AX88172 chip. 847 */ 848 int 849 axe_match(device_t parent, cfdata_t match, void *aux) 850 { 851 struct usb_attach_arg *uaa = aux; 852 853 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 854 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 855 } 856 857 /* 858 * Attach the interface. Allocate softc structures, do ifmedia 859 * setup and ethernet/BPF attach. 860 */ 861 void 862 axe_attach(device_t parent, device_t self, void *aux) 863 { 864 AXEHIST_FUNC(); AXEHIST_CALLED(); 865 struct axe_softc *sc = device_private(self); 866 struct usbnet * const un = &sc->axe_un; 867 struct usb_attach_arg *uaa = aux; 868 struct usbd_device *dev = uaa->uaa_device; 869 usbd_status err; 870 usb_interface_descriptor_t *id; 871 usb_endpoint_descriptor_t *ed; 872 char *devinfop; 873 unsigned bufsz; 874 int i; 875 876 /* Switch to usbnet for device_private() */ 877 self->dv_private = un; 878 879 aprint_naive("\n"); 880 aprint_normal("\n"); 881 devinfop = usbd_devinfo_alloc(dev, 0); 882 aprint_normal_dev(self, "%s\n", devinfop); 883 usbd_devinfo_free(devinfop); 884 885 un->un_dev = self; 886 un->un_udev = dev; 887 un->un_sc = sc; 888 un->un_ops = &axe_ops; 889 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 890 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 891 un->un_rx_list_cnt = AXE_RX_LIST_CNT; 892 un->un_tx_list_cnt = AXE_TX_LIST_CNT; 893 894 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 895 if (err) { 896 aprint_error_dev(self, "failed to set configuration" 897 ", err=%s\n", usbd_errstr(err)); 898 return; 899 } 900 901 un->un_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 902 903 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface); 904 if (err) { 905 aprint_error_dev(self, "getting interface handle failed\n"); 906 return; 907 } 908 909 id = usbd_get_interface_descriptor(un->un_iface); 910 911 /* decide on what our bufsize will be */ 912 if (AXE_IS_178_FAMILY(un)) 913 bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 914 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 915 else 916 bufsz = AXE_172_BUFSZ; 917 un->un_rx_bufsz = un->un_tx_bufsz = bufsz; 918 919 un->un_ed[USBNET_ENDPT_RX] = 0; 920 un->un_ed[USBNET_ENDPT_TX] = 0; 921 un->un_ed[USBNET_ENDPT_INTR] = 0; 922 923 /* Find endpoints. */ 924 for (i = 0; i < id->bNumEndpoints; i++) { 925 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 926 if (ed == NULL) { 927 aprint_error_dev(self, "couldn't get ep %d\n", i); 928 return; 929 } 930 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 931 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 932 933 if (dir == UE_DIR_IN && xt == UE_BULK && 934 un->un_ed[USBNET_ENDPT_RX] == 0) { 935 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 936 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 937 un->un_ed[USBNET_ENDPT_TX] == 0) { 938 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 939 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 940 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 941 } 942 } 943 944 /* Set these up now for axe_cmd(). */ 945 usbnet_attach(un, "axedet"); 946 947 /* We need the PHYID for init dance in some cases */ 948 usbnet_lock_mii(un); 949 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 950 aprint_error_dev(self, "failed to read phyaddrs\n"); 951 952 return; 953 } 954 955 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 956 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 957 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 958 if (un->un_phyno == -1) 959 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 960 if (un->un_phyno == -1) { 961 DPRINTF(" no valid PHY address found, assuming PHY address 0", 962 0, 0, 0, 0); 963 un->un_phyno = 0; 964 } 965 966 /* Initialize controller and get station address. */ 967 968 axe_ax_init(un); 969 970 /* 971 * Fetch IPG values. 972 */ 973 if (un->un_flags & (AX772A | AX772B)) { 974 /* Set IPG values. */ 975 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 976 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 977 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 978 } else { 979 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 980 aprint_error_dev(self, "failed to read ipg\n"); 981 usbnet_unlock_mii(un); 982 return; 983 } 984 } 985 986 usbnet_unlock_mii(un); 987 988 if (AXE_IS_178_FAMILY(un)) 989 usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU; 990 if (un->un_flags & AX772B) { 991 struct ifnet *ifp = usbnet_ifp(un); 992 993 ifp->if_capabilities = 994 IFCAP_CSUM_IPv4_Rx | 995 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 996 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 997 /* 998 * Checksum offloading of AX88772B also works with VLAN 999 * tagged frames but there is no way to take advantage 1000 * of the feature because vlan(4) assumes 1001 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1002 * support checksum offloading with VLAN. VLAN hardware 1003 * tagging support of AX88772B is very limited so it's 1004 * not possible to announce IFCAP_VLAN_HWTAGGING. 1005 */ 1006 } 1007 u_int adv_pause; 1008 if (un->un_flags & (AX772A | AX772B | AX178)) 1009 adv_pause = MIIF_DOPAUSE; 1010 else 1011 adv_pause = 0; 1012 adv_pause = 0; 1013 1014 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 1015 0, adv_pause); 1016 } 1017 1018 static void 1019 axe_rx_loop(struct usbnet * un, struct usbd_xfer *xfer, 1020 struct usbnet_chain *c, uint32_t total_len) 1021 { 1022 AXEHIST_FUNC(); AXEHIST_CALLED(); 1023 struct axe_softc * const sc = usbnet_softc(un); 1024 struct ifnet *ifp = usbnet_ifp(un); 1025 uint8_t *buf = c->unc_buf; 1026 1027 do { 1028 u_int pktlen = 0; 1029 u_int rxlen = 0; 1030 int flags = 0; 1031 1032 if ((un->un_flags & AXSTD_FRAME) != 0) { 1033 struct axe_sframe_hdr hdr; 1034 1035 if (total_len < sizeof(hdr)) { 1036 ifp->if_ierrors++; 1037 break; 1038 } 1039 1040 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1041 /* 1042 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1043 * For some architectures, __builtin_memcpy() of 1044 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1045 * at onece, which results in alignment error. 1046 */ 1047 hdr.len = *(uint16_t *)buf; 1048 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1049 #else 1050 memcpy(&hdr, buf, sizeof(hdr)); 1051 #endif 1052 1053 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1054 total_len, 1055 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1056 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1057 1058 total_len -= sizeof(hdr); 1059 buf += sizeof(hdr); 1060 1061 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1062 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1063 AXE_RH1M_RXLEN_MASK) { 1064 ifp->if_ierrors++; 1065 break; 1066 } 1067 1068 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1069 if (total_len < rxlen) { 1070 pktlen = total_len; 1071 total_len = 0; 1072 } else { 1073 pktlen = rxlen; 1074 rxlen = roundup2(rxlen, 2); 1075 total_len -= rxlen; 1076 } 1077 1078 } else if ((un->un_flags & AXCSUM_FRAME) != 0) { 1079 struct axe_csum_hdr csum_hdr; 1080 1081 if (total_len < sizeof(csum_hdr)) { 1082 ifp->if_ierrors++; 1083 break; 1084 } 1085 1086 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1087 1088 csum_hdr.len = le16toh(csum_hdr.len); 1089 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1090 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1091 1092 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1093 " cstatus %#jx", total_len, 1094 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1095 1096 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1097 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1098 sc->sc_lenmask) { 1099 /* we lost sync */ 1100 ifp->if_ierrors++; 1101 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1102 "err", 1103 AXE_CSUM_RXBYTES(csum_hdr.len), 1104 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1105 sc->sc_lenmask, 0); 1106 break; 1107 } 1108 /* 1109 * Get total transferred frame length including 1110 * checksum header. The length should be multiple 1111 * of 4. 1112 */ 1113 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1114 u_int len = sizeof(csum_hdr) + pktlen; 1115 len = (len + 3) & ~3; 1116 if (total_len < len) { 1117 DPRINTFN(20, "total_len %#jx < len %#jx", 1118 total_len, len, 0, 0); 1119 /* invalid length */ 1120 ifp->if_ierrors++; 1121 break; 1122 } 1123 buf += sizeof(csum_hdr); 1124 1125 const uint16_t cstatus = csum_hdr.cstatus; 1126 1127 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1128 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1129 flags |= M_CSUM_TCP_UDP_BAD; 1130 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1131 flags |= M_CSUM_IPv4_BAD; 1132 1133 const uint16_t l4type = 1134 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1135 1136 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1137 flags |= M_CSUM_TCPv4; 1138 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1139 flags |= M_CSUM_UDPv4; 1140 } 1141 if (total_len < len) { 1142 pktlen = total_len; 1143 total_len = 0; 1144 } else { 1145 total_len -= len; 1146 rxlen = len - sizeof(csum_hdr); 1147 } 1148 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1149 " rxlen %#jx", total_len, len, pktlen, rxlen); 1150 } else { /* AX172 */ 1151 pktlen = rxlen = total_len; 1152 total_len = 0; 1153 } 1154 1155 usbnet_enqueue(un, buf, pktlen, flags, 0, 0); 1156 buf += rxlen; 1157 1158 } while (total_len > 0); 1159 1160 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1161 } 1162 1163 static unsigned 1164 axe_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1165 { 1166 AXEHIST_FUNC(); AXEHIST_CALLED(); 1167 struct axe_sframe_hdr hdr, tlr; 1168 size_t hdr_len = 0, tlr_len = 0; 1169 int length, boundary; 1170 1171 usbnet_isowned_tx(un); 1172 1173 if (AXE_IS_178_FAMILY(un)) { 1174 /* 1175 * Copy the mbuf data into a contiguous buffer, leaving two 1176 * bytes at the beginning to hold the frame length. 1177 */ 1178 boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1179 1180 hdr.len = htole16(m->m_pkthdr.len); 1181 hdr.ilen = ~hdr.len; 1182 hdr_len = sizeof(hdr); 1183 1184 length = hdr_len + m->m_pkthdr.len; 1185 1186 if ((length % boundary) == 0) { 1187 tlr.len = 0x0000; 1188 tlr.ilen = 0xffff; 1189 tlr_len = sizeof(tlr); 1190 } 1191 DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx", 1192 length, m->m_pkthdr.len, sizeof(hdr), 0); 1193 } 1194 1195 if (m->m_pkthdr.len > un->un_tx_bufsz - hdr_len - tlr_len) 1196 return 0; 1197 length = hdr_len + m->m_pkthdr.len + tlr_len; 1198 1199 if (hdr_len) 1200 memcpy(c->unc_buf, &hdr, hdr_len); 1201 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + hdr_len); 1202 if (tlr_len) 1203 memcpy(c->unc_buf + length, &tlr, tlr_len); 1204 1205 return length; 1206 } 1207 1208 static void 1209 axe_csum_cfg(struct axe_softc *sc) 1210 { 1211 struct usbnet * const un = &sc->axe_un; 1212 struct ifnet * const ifp = usbnet_ifp(un); 1213 uint16_t csum1, csum2; 1214 1215 if ((un->un_flags & AX772B) != 0) { 1216 csum1 = 0; 1217 csum2 = 0; 1218 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1219 csum1 |= AXE_TXCSUM_IP; 1220 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1221 csum1 |= AXE_TXCSUM_TCP; 1222 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1223 csum1 |= AXE_TXCSUM_UDP; 1224 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1225 csum1 |= AXE_TXCSUM_TCPV6; 1226 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1227 csum1 |= AXE_TXCSUM_UDPV6; 1228 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1229 csum1 = 0; 1230 csum2 = 0; 1231 1232 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1233 csum1 |= AXE_RXCSUM_IP; 1234 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1235 csum1 |= AXE_RXCSUM_TCP; 1236 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1237 csum1 |= AXE_RXCSUM_UDP; 1238 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1239 csum1 |= AXE_RXCSUM_TCPV6; 1240 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1241 csum1 |= AXE_RXCSUM_UDPV6; 1242 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1243 } 1244 } 1245 1246 static int 1247 axe_init_locked(struct ifnet *ifp) 1248 { 1249 AXEHIST_FUNC(); AXEHIST_CALLED(); 1250 struct usbnet * const un = ifp->if_softc; 1251 struct axe_softc * const sc = usbnet_softc(un); 1252 int rxmode; 1253 1254 usbnet_isowned(un); 1255 1256 if (usbnet_isdying(un)) 1257 return EIO; 1258 1259 /* Cancel pending I/O */ 1260 usbnet_stop(un, ifp, 1); 1261 1262 usbnet_lock_mii_un_locked(un); 1263 1264 /* Reset the ethernet interface. */ 1265 axe_reset(un); 1266 1267 #if 0 1268 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1269 AX_GPIO_GPO2EN, 5, in_pm); 1270 #endif 1271 /* Set MAC address and transmitter IPG values. */ 1272 if (AXE_IS_178_FAMILY(un)) { 1273 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1274 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1275 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1276 } else { 1277 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1278 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1279 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1280 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1281 } 1282 if (AXE_IS_178_FAMILY(un)) { 1283 un->un_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1284 if ((un->un_flags & AX772B) != 0 && 1285 (ifp->if_capenable & AX_RXCSUM) != 0) { 1286 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1287 un->un_flags |= AXCSUM_FRAME; 1288 } else { 1289 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1290 un->un_flags |= AXSTD_FRAME; 1291 } 1292 } 1293 1294 /* Configure TX/RX checksum offloading. */ 1295 axe_csum_cfg(sc); 1296 1297 if (un->un_flags & AX772B) { 1298 /* AX88772B uses different maximum frame burst configuration. */ 1299 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1300 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1301 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1302 } 1303 /* Enable receiver, set RX mode */ 1304 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1305 if (AXE_IS_178_FAMILY(un)) { 1306 if (un->un_flags & AX772B) { 1307 /* 1308 * Select RX header format type 1. Aligning IP 1309 * header on 4 byte boundary is not needed when 1310 * checksum offloading feature is not used 1311 * because we always copy the received frame in 1312 * RX handler. When RX checksum offloading is 1313 * active, aligning IP header is required to 1314 * reflect actual frame length including RX 1315 * header size. 1316 */ 1317 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1318 if (un->un_flags & AXCSUM_FRAME) 1319 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1320 } else { 1321 /* 1322 * Default Rx buffer size is too small to get 1323 * maximum performance. 1324 */ 1325 #if 0 1326 if (un->un_udev->ud_speed == USB_SPEED_HIGH) { 1327 /* Largest possible USB buffer size for AX88178 */ 1328 } 1329 #endif 1330 rxmode |= AXE_178_RXCMD_MFB_16384; 1331 } 1332 } else { 1333 rxmode |= AXE_172_RXCMD_UNICAST; 1334 } 1335 1336 1337 /* If we want promiscuous mode, set the allframes bit. */ 1338 if (ifp->if_flags & IFF_PROMISC) 1339 rxmode |= AXE_RXCMD_PROMISC; 1340 1341 if (ifp->if_flags & IFF_BROADCAST) 1342 rxmode |= AXE_RXCMD_BROADCAST; 1343 1344 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1345 1346 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1347 1348 /* Load the multicast filter. */ 1349 axe_setiff_locked(un); 1350 1351 usbnet_unlock_mii_un_locked(un); 1352 1353 return usbnet_init_rx_tx(un); 1354 } 1355 1356 static int 1357 axe_init(struct ifnet *ifp) 1358 { 1359 struct usbnet * const un = ifp->if_softc; 1360 1361 usbnet_lock(un); 1362 int ret = axe_init_locked(ifp); 1363 usbnet_unlock(un); 1364 1365 return ret; 1366 } 1367 1368 static int 1369 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1370 { 1371 struct usbnet * const un = ifp->if_softc; 1372 1373 switch (cmd) { 1374 case SIOCADDMULTI: 1375 case SIOCDELMULTI: 1376 axe_setiff(un); 1377 break; 1378 default: 1379 break; 1380 } 1381 1382 return 0; 1383 } 1384 1385 static void 1386 axe_stop(struct ifnet *ifp, int disable) 1387 { 1388 struct usbnet * const un = ifp->if_softc; 1389 1390 usbnet_lock_mii_un_locked(un); 1391 axe_reset(un); 1392 usbnet_unlock_mii_un_locked(un); 1393 } 1394 1395 MODULE(MODULE_CLASS_DRIVER, if_axe, "usbnet"); 1396 1397 #ifdef _MODULE 1398 #include "ioconf.c" 1399 #endif 1400 1401 static int 1402 if_axe_modcmd(modcmd_t cmd, void *aux) 1403 { 1404 int error = 0; 1405 1406 switch (cmd) { 1407 case MODULE_CMD_INIT: 1408 #ifdef _MODULE 1409 error = config_init_component(cfdriver_ioconf_axe, 1410 cfattach_ioconf_axe, cfdata_ioconf_axe); 1411 #endif 1412 return error; 1413 case MODULE_CMD_FINI: 1414 #ifdef _MODULE 1415 error = config_fini_component(cfdriver_ioconf_axe, 1416 cfattach_ioconf_axe, cfdata_ioconf_axe); 1417 #endif 1418 return error; 1419 default: 1420 return ENOTTY; 1421 } 1422 } 1423
Indexes created Tue Sep 23 14:10:03 GMT 2025