if_axe.c revision 1.114
1 /* $NetBSD: if_axe.c,v 1.114 2019/08/14 03:44:58 mrg Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.114 2019/08/14 03:44:58 mrg Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_usb.h" 94 #include "opt_net_mpsafe.h" 95 #endif 96 97 #include <sys/param.h> 98 99 #include <dev/usb/usbnet.h> 100 #include <dev/usb/usbhist.h> 101 #include <dev/usb/if_axereg.h> 102 103 struct axe_type { 104 struct usb_devno axe_dev; 105 uint16_t axe_flags; 106 }; 107 108 struct axe_softc { 109 struct usbnet axe_un; 110 111 /* usbnet:un_flags values */ 112 #define AX178 __BIT(0) /* AX88178 */ 113 #define AX772 __BIT(1) /* AX88772 */ 114 #define AX772A __BIT(2) /* AX88772A */ 115 #define AX772B __BIT(3) /* AX88772B */ 116 #define AXSTD_FRAME __BIT(12) 117 #define AXCSUM_FRAME __BIT(13) 118 119 uint8_t axe_ipgs[3]; 120 uint8_t axe_phyaddrs[2]; 121 uint16_t sc_pwrcfg; 122 uint16_t sc_lenmask; 123 124 }; 125 126 #define AXE_IS_178_FAMILY(un) \ 127 ((un)->un_flags & (AX772 | AX772A | AX772B | AX178)) 128 129 #define AXE_IS_772(un) \ 130 ((un)->un_flags & (AX772 | AX772A | AX772B)) 131 132 #define AX_RXCSUM \ 133 (IFCAP_CSUM_IPv4_Rx | \ 134 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 135 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 136 137 #define AX_TXCSUM \ 138 (IFCAP_CSUM_IPv4_Tx | \ 139 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 140 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 141 142 /* 143 * AXE_178_MAX_FRAME_BURST 144 * max frame burst size for Ax88178 and Ax88772 145 * 0 2048 bytes 146 * 1 4096 bytes 147 * 2 8192 bytes 148 * 3 16384 bytes 149 * use the largest your system can handle without USB stalling. 150 * 151 * NB: 88772 parts appear to generate lots of input errors with 152 * a 2K rx buffer and 8K is only slightly faster than 4K on an 153 * EHCI port on a T42 so change at your own risk. 154 */ 155 #define AXE_178_MAX_FRAME_BURST 1 156 157 158 #ifdef USB_DEBUG 159 #ifndef AXE_DEBUG 160 #define axedebug 0 161 #else 162 static int axedebug = 20; 163 164 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 165 { 166 int err; 167 const struct sysctlnode *rnode; 168 const struct sysctlnode *cnode; 169 170 err = sysctl_createv(clog, 0, NULL, &rnode, 171 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 172 SYSCTL_DESCR("axe global controls"), 173 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 174 175 if (err) 176 goto fail; 177 178 /* control debugging printfs */ 179 err = sysctl_createv(clog, 0, &rnode, &cnode, 180 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 181 "debug", SYSCTL_DESCR("Enable debugging output"), 182 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 183 if (err) 184 goto fail; 185 186 return; 187 fail: 188 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 189 } 190 191 #endif /* AXE_DEBUG */ 192 #endif /* USB_DEBUG */ 193 194 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 195 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 196 #define AXEHIST_FUNC() USBHIST_FUNC() 197 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 198 199 /* 200 * Various supported device vendors/products. 201 */ 202 static const struct axe_type axe_devs[] = { 203 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 204 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 205 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 206 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 207 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 208 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 209 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 210 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 211 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 212 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 213 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 214 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 215 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 216 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 217 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 218 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 219 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 220 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 221 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 222 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 223 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 224 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 225 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 226 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 227 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 228 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 229 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 230 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 231 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 232 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 233 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 234 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 235 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 236 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 237 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 238 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 239 }; 240 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 241 242 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 243 { 0x8000, 0x8001, 2048 }, 244 { 0x8100, 0x8147, 4096 }, 245 { 0x8200, 0x81EB, 6144 }, 246 { 0x8300, 0x83D7, 8192 }, 247 { 0x8400, 0x851E, 16384 }, 248 { 0x8500, 0x8666, 20480 }, 249 { 0x8600, 0x87AE, 24576 }, 250 { 0x8700, 0x8A3D, 32768 } 251 }; 252 253 int axe_match(device_t, cfdata_t, void *); 254 void axe_attach(device_t, device_t, void *); 255 256 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 257 axe_match, axe_attach, usbnet_detach, usbnet_activate); 258 259 static void axe_stop(struct ifnet *, int); 260 static int axe_ioctl(struct ifnet *, u_long, void *); 261 static int axe_init(struct ifnet *); 262 static usbd_status axe_mii_read_reg(struct usbnet *, int, int, uint16_t *); 263 static usbd_status axe_mii_write_reg(struct usbnet *, int, int, uint16_t); 264 static void axe_mii_statchg(struct ifnet *); 265 static void axe_rx_loop(struct usbnet *, struct usbd_xfer *, 266 struct usbnet_chain *, uint32_t); 267 static unsigned axe_tx_prepare(struct usbnet *, struct mbuf *, 268 struct usbnet_chain *); 269 270 static void axe_ax88178_init(struct axe_softc *); 271 static void axe_ax88772_init(struct axe_softc *); 272 static void axe_ax88772a_init(struct axe_softc *); 273 static void axe_ax88772b_init(struct axe_softc *); 274 275 static struct usbnet_ops axe_ops = { 276 .uno_stop = axe_stop, 277 .uno_ioctl = axe_ioctl, 278 .uno_read_reg = axe_mii_read_reg, 279 .uno_write_reg = axe_mii_write_reg, 280 .uno_statchg = axe_mii_statchg, 281 .uno_tx_prepare = axe_tx_prepare, 282 .uno_rx_loop = axe_rx_loop, 283 .uno_init = axe_init, 284 }; 285 286 static usbd_status 287 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 288 { 289 AXEHIST_FUNC(); AXEHIST_CALLED(); 290 struct usbnet * const un = &sc->axe_un; 291 usb_device_request_t req; 292 usbd_status err; 293 294 usbnet_isowned_mii(un); 295 296 if (usbnet_isdying(un)) 297 return -1; 298 299 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 300 301 if (AXE_CMD_DIR(cmd)) 302 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 303 else 304 req.bmRequestType = UT_READ_VENDOR_DEVICE; 305 req.bRequest = AXE_CMD_CMD(cmd); 306 USETW(req.wValue, val); 307 USETW(req.wIndex, index); 308 USETW(req.wLength, AXE_CMD_LEN(cmd)); 309 310 err = usbd_do_request(un->un_udev, &req, buf); 311 if (err) 312 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 313 314 return err; 315 } 316 317 static usbd_status 318 axe_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 319 { 320 AXEHIST_FUNC(); AXEHIST_CALLED(); 321 struct axe_softc * const sc = usbnet_softc(un); 322 usbd_status err; 323 uint16_t data; 324 325 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 326 327 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 328 329 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 330 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 331 332 if (err) { 333 aprint_error_dev(un->un_dev, "read PHY failed\n"); 334 return err; 335 } 336 337 *val = le16toh(data); 338 if (AXE_IS_772(un) && reg == MII_BMSR) { 339 /* 340 * BMSR of AX88772 indicates that it supports extended 341 * capability but the extended status register is 342 * reserved for embedded ethernet PHY. So clear the 343 * extended capability bit of BMSR. 344 */ 345 *val &= ~BMSR_EXTCAP; 346 } 347 348 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 349 350 return USBD_NORMAL_COMPLETION; 351 } 352 353 static usbd_status 354 axe_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 355 { 356 struct axe_softc * const sc = usbnet_softc(un); 357 usbd_status err; 358 uint16_t aval; 359 360 aval = htole16(val); 361 362 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 363 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval); 364 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 365 366 return err; 367 } 368 369 static void 370 axe_mii_statchg(struct ifnet *ifp) 371 { 372 AXEHIST_FUNC(); AXEHIST_CALLED(); 373 374 struct usbnet * const un = ifp->if_softc; 375 struct axe_softc * const sc = usbnet_softc(un); 376 struct mii_data *mii = usbnet_mii(un); 377 int val, err; 378 379 if (usbnet_isdying(un)) 380 return; 381 382 val = 0; 383 usbnet_set_link(un, false); 384 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 385 val |= AXE_MEDIA_FULL_DUPLEX; 386 if (AXE_IS_178_FAMILY(un)) { 387 if ((IFM_OPTIONS(mii->mii_media_active) & 388 IFM_ETH_TXPAUSE) != 0) 389 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 390 if ((IFM_OPTIONS(mii->mii_media_active) & 391 IFM_ETH_RXPAUSE) != 0) 392 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 393 } 394 } 395 if (AXE_IS_178_FAMILY(un)) { 396 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 397 if (un->un_flags & AX178) 398 val |= AXE_178_MEDIA_ENCK; 399 switch (IFM_SUBTYPE(mii->mii_media_active)) { 400 case IFM_1000_T: 401 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 402 usbnet_set_link(un, true); 403 break; 404 case IFM_100_TX: 405 val |= AXE_178_MEDIA_100TX; 406 usbnet_set_link(un, true); 407 break; 408 case IFM_10_T: 409 usbnet_set_link(un, true); 410 break; 411 } 412 } 413 414 DPRINTF("val=0x%jx", val, 0, 0, 0); 415 usbnet_lock_mii(un); 416 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 417 usbnet_unlock_mii(un); 418 if (err) 419 aprint_error_dev(un->un_dev, "media change failed\n"); 420 } 421 422 static void 423 axe_setiff_locked(struct usbnet *un) 424 { 425 AXEHIST_FUNC(); AXEHIST_CALLED(); 426 struct axe_softc * const sc = usbnet_softc(un); 427 struct ifnet * const ifp = usbnet_ifp(un); 428 struct ethercom *ec = usbnet_ec(un); 429 struct ether_multi *enm; 430 struct ether_multistep step; 431 uint32_t h = 0; 432 uint16_t rxmode; 433 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 434 435 usbnet_isowned_mii(un); 436 437 if (usbnet_isdying(un)) 438 return; 439 440 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 441 aprint_error_dev(un->un_dev, "can't read rxmode"); 442 return; 443 } 444 rxmode = le16toh(rxmode); 445 446 rxmode &= 447 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 448 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 449 450 rxmode |= 451 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 452 453 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 454 if (ifp->if_flags & IFF_PROMISC) 455 rxmode |= AXE_RXCMD_PROMISC; 456 goto allmulti; 457 } 458 459 /* Now program new ones */ 460 ETHER_LOCK(ec); 461 ETHER_FIRST_MULTI(step, ec, enm); 462 while (enm != NULL) { 463 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 464 ETHER_ADDR_LEN) != 0) { 465 ETHER_UNLOCK(ec); 466 goto allmulti; 467 } 468 469 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 470 hashtbl[h >> 3] |= 1U << (h & 7); 471 ETHER_NEXT_MULTI(step, enm); 472 } 473 ETHER_UNLOCK(ec); 474 ifp->if_flags &= ~IFF_ALLMULTI; 475 rxmode |= AXE_RXCMD_MULTICAST; 476 477 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 478 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 479 return; 480 481 allmulti: 482 ifp->if_flags |= IFF_ALLMULTI; 483 rxmode |= AXE_RXCMD_ALLMULTI; 484 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 485 } 486 487 static void 488 axe_setiff(struct usbnet *un) 489 { 490 usbnet_lock_mii(un); 491 axe_setiff_locked(un); 492 usbnet_unlock_mii(un); 493 } 494 495 static void 496 axe_ax_init(struct usbnet *un) 497 { 498 struct axe_softc * const sc = usbnet_softc(un); 499 500 int cmd = AXE_178_CMD_READ_NODEID; 501 502 if (un->un_flags & AX178) { 503 axe_ax88178_init(sc); 504 } else if (un->un_flags & AX772) { 505 axe_ax88772_init(sc); 506 } else if (un->un_flags & AX772A) { 507 axe_ax88772a_init(sc); 508 } else if (un->un_flags & AX772B) { 509 axe_ax88772b_init(sc); 510 return; 511 } else { 512 cmd = AXE_172_CMD_READ_NODEID; 513 } 514 515 if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) { 516 aprint_error_dev(un->un_dev, 517 "failed to read ethernet address\n"); 518 } 519 } 520 521 522 static void 523 axe_reset(struct usbnet *un) 524 { 525 526 usbnet_isowned_mii(un); 527 528 if (usbnet_isdying(un)) 529 return; 530 531 /* 532 * softnet_lock can be taken when NET_MPAFE is not defined when calling 533 * if_addr_init -> if_init. This doesn't mix well with the 534 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 535 * can fire during the wait and attempt to take softnet_lock and then 536 * block the softclk thread meaning the wait never ends. 537 */ 538 #ifndef NET_MPSAFE 539 /* XXX What to reset? */ 540 541 /* Wait a little while for the chip to get its brains in order. */ 542 DELAY(1000); 543 #else 544 axe_ax_init(un); 545 #endif 546 } 547 548 static int 549 axe_get_phyno(struct axe_softc *sc, int sel) 550 { 551 int phyno; 552 553 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 554 case PHY_TYPE_100_HOME: 555 /* FALLTHROUGH */ 556 case PHY_TYPE_GIG: 557 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 558 break; 559 case PHY_TYPE_SPECIAL: 560 /* FALLTHROUGH */ 561 case PHY_TYPE_RSVD: 562 /* FALLTHROUGH */ 563 case PHY_TYPE_NON_SUP: 564 /* FALLTHROUGH */ 565 default: 566 phyno = -1; 567 break; 568 } 569 570 return phyno; 571 } 572 573 #define AXE_GPIO_WRITE(x, y) do { \ 574 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 575 usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \ 576 } while (0) 577 578 static void 579 axe_ax88178_init(struct axe_softc *sc) 580 { 581 AXEHIST_FUNC(); AXEHIST_CALLED(); 582 struct usbnet * const un = &sc->axe_un; 583 int gpio0, ledmode, phymode; 584 uint16_t eeprom, val; 585 586 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 587 /* XXX magic */ 588 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 589 eeprom = 0xffff; 590 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 591 592 eeprom = le16toh(eeprom); 593 594 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 595 596 /* if EEPROM is invalid we have to use to GPIO0 */ 597 if (eeprom == 0xffff) { 598 phymode = AXE_PHY_MODE_MARVELL; 599 gpio0 = 1; 600 ledmode = 0; 601 } else { 602 phymode = eeprom & 0x7f; 603 gpio0 = (eeprom & 0x80) ? 0 : 1; 604 ledmode = eeprom >> 8; 605 } 606 607 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 608 609 /* Program GPIOs depending on PHY hardware. */ 610 switch (phymode) { 611 case AXE_PHY_MODE_MARVELL: 612 if (gpio0 == 1) { 613 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 614 hz / 32); 615 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 616 hz / 32); 617 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 618 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 619 hz / 32); 620 } else { 621 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 622 AXE_GPIO1_EN, hz / 3); 623 if (ledmode == 1) { 624 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 625 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 626 hz / 3); 627 } else { 628 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 629 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 630 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 631 AXE_GPIO2_EN, hz / 4); 632 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 633 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 634 } 635 } 636 break; 637 case AXE_PHY_MODE_CICADA: 638 case AXE_PHY_MODE_CICADA_V2: 639 case AXE_PHY_MODE_CICADA_V2_ASIX: 640 if (gpio0 == 1) 641 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 642 AXE_GPIO0_EN, hz / 32); 643 else 644 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 645 AXE_GPIO1_EN, hz / 32); 646 break; 647 case AXE_PHY_MODE_AGERE: 648 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 649 AXE_GPIO1_EN, hz / 32); 650 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 651 AXE_GPIO2_EN, hz / 32); 652 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 653 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 654 AXE_GPIO2_EN, hz / 32); 655 break; 656 case AXE_PHY_MODE_REALTEK_8211CL: 657 case AXE_PHY_MODE_REALTEK_8211BN: 658 case AXE_PHY_MODE_REALTEK_8251CL: 659 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 660 AXE_GPIO1 | AXE_GPIO1_EN; 661 AXE_GPIO_WRITE(val, hz / 32); 662 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 663 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 664 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 665 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 666 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005); 667 axe_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000); 668 axe_mii_read_reg(un, un->un_phyno, 0x0001, &val); 669 axe_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080); 670 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000); 671 } 672 break; 673 default: 674 /* Unknown PHY model or no need to program GPIOs. */ 675 break; 676 } 677 678 /* soft reset */ 679 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 680 usbd_delay_ms(un->un_udev, 150); 681 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 682 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 683 usbd_delay_ms(un->un_udev, 150); 684 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 685 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 686 usbd_delay_ms(un->un_udev, 10); 687 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 688 } 689 690 static void 691 axe_ax88772_init(struct axe_softc *sc) 692 { 693 AXEHIST_FUNC(); AXEHIST_CALLED(); 694 struct usbnet * const un = &sc->axe_un; 695 696 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 697 usbd_delay_ms(un->un_udev, 40); 698 699 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 700 /* ask for the embedded PHY */ 701 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 702 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 703 usbd_delay_ms(un->un_udev, 10); 704 705 /* power down and reset state, pin reset state */ 706 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 707 usbd_delay_ms(un->un_udev, 60); 708 709 /* power down/reset state, pin operating state */ 710 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 711 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 712 usbd_delay_ms(un->un_udev, 150); 713 714 /* power up, reset */ 715 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 716 717 /* power up, operating */ 718 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 719 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 720 } else { 721 /* ask for external PHY */ 722 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 723 NULL); 724 usbd_delay_ms(un->un_udev, 10); 725 726 /* power down internal PHY */ 727 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 728 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 729 } 730 731 usbd_delay_ms(un->un_udev, 150); 732 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 733 } 734 735 static void 736 axe_ax88772_phywake(struct axe_softc *sc) 737 { 738 AXEHIST_FUNC(); AXEHIST_CALLED(); 739 struct usbnet * const un = &sc->axe_un; 740 741 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 742 /* Manually select internal(embedded) PHY - MAC mode. */ 743 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 744 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 745 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 746 } else { 747 /* 748 * Manually select external PHY - MAC mode. 749 * Reverse MII/RMII is for AX88772A PHY mode. 750 */ 751 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 752 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 753 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 754 } 755 756 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 757 AXE_SW_RESET_IPRL, NULL); 758 759 /* T1 = min 500ns everywhere */ 760 usbd_delay_ms(un->un_udev, 150); 761 762 /* Take PHY out of power down. */ 763 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 764 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 765 } else { 766 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 767 } 768 769 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 770 usbd_delay_ms(un->un_udev, 600); 771 772 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 773 774 /* T3 = 500ns everywhere */ 775 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 776 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 777 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 778 } 779 780 static void 781 axe_ax88772a_init(struct axe_softc *sc) 782 { 783 AXEHIST_FUNC(); AXEHIST_CALLED(); 784 785 /* Reload EEPROM. */ 786 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 787 axe_ax88772_phywake(sc); 788 /* Stop MAC. */ 789 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 790 } 791 792 static void 793 axe_ax88772b_init(struct axe_softc *sc) 794 { 795 AXEHIST_FUNC(); AXEHIST_CALLED(); 796 struct usbnet * const un = &sc->axe_un; 797 uint16_t eeprom; 798 int i; 799 800 /* Reload EEPROM. */ 801 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 802 803 /* 804 * Save PHY power saving configuration(high byte) and 805 * clear EEPROM checksum value(low byte). 806 */ 807 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 808 &eeprom)) { 809 aprint_error_dev(un->un_dev, "failed to read eeprom\n"); 810 return; 811 } 812 813 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 814 815 /* 816 * Auto-loaded default station address from internal ROM is 817 * 00:00:00:00:00:00 such that an explicit access to EEPROM 818 * is required to get real station address. 819 */ 820 uint8_t *eaddr = un->un_eaddr; 821 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 822 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 823 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 824 aprint_error_dev(un->un_dev, 825 "failed to read eeprom\n"); 826 eeprom = 0; 827 } 828 eeprom = le16toh(eeprom); 829 *eaddr++ = (uint8_t)(eeprom & 0xFF); 830 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 831 } 832 /* Wakeup PHY. */ 833 axe_ax88772_phywake(sc); 834 /* Stop MAC. */ 835 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 836 } 837 838 #undef AXE_GPIO_WRITE 839 840 /* 841 * Probe for a AX88172 chip. 842 */ 843 int 844 axe_match(device_t parent, cfdata_t match, void *aux) 845 { 846 struct usb_attach_arg *uaa = aux; 847 848 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 849 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 850 } 851 852 /* 853 * Attach the interface. Allocate softc structures, do ifmedia 854 * setup and ethernet/BPF attach. 855 */ 856 void 857 axe_attach(device_t parent, device_t self, void *aux) 858 { 859 AXEHIST_FUNC(); AXEHIST_CALLED(); 860 struct axe_softc *sc = device_private(self); 861 struct usbnet * const un = &sc->axe_un; 862 struct usb_attach_arg *uaa = aux; 863 struct usbd_device *dev = uaa->uaa_device; 864 usbd_status err; 865 usb_interface_descriptor_t *id; 866 usb_endpoint_descriptor_t *ed; 867 char *devinfop; 868 unsigned bufsz; 869 int i; 870 871 KASSERT((void *)sc == un); 872 873 aprint_naive("\n"); 874 aprint_normal("\n"); 875 devinfop = usbd_devinfo_alloc(dev, 0); 876 aprint_normal_dev(self, "%s\n", devinfop); 877 usbd_devinfo_free(devinfop); 878 879 un->un_dev = self; 880 un->un_udev = dev; 881 un->un_sc = sc; 882 un->un_ops = &axe_ops; 883 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 884 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 885 un->un_rx_list_cnt = AXE_RX_LIST_CNT; 886 un->un_tx_list_cnt = AXE_TX_LIST_CNT; 887 888 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 889 if (err) { 890 aprint_error_dev(self, "failed to set configuration" 891 ", err=%s\n", usbd_errstr(err)); 892 return; 893 } 894 895 un->un_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 896 897 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface); 898 if (err) { 899 aprint_error_dev(self, "getting interface handle failed\n"); 900 return; 901 } 902 903 id = usbd_get_interface_descriptor(un->un_iface); 904 905 /* decide on what our bufsize will be */ 906 if (AXE_IS_178_FAMILY(un)) 907 bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 908 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 909 else 910 bufsz = AXE_172_BUFSZ; 911 un->un_rx_bufsz = un->un_tx_bufsz = bufsz; 912 913 un->un_ed[USBNET_ENDPT_RX] = 0; 914 un->un_ed[USBNET_ENDPT_TX] = 0; 915 un->un_ed[USBNET_ENDPT_INTR] = 0; 916 917 /* Find endpoints. */ 918 for (i = 0; i < id->bNumEndpoints; i++) { 919 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 920 if (ed == NULL) { 921 aprint_error_dev(self, "couldn't get ep %d\n", i); 922 return; 923 } 924 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 925 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 926 927 if (dir == UE_DIR_IN && xt == UE_BULK && 928 un->un_ed[USBNET_ENDPT_RX] == 0) { 929 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 930 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 931 un->un_ed[USBNET_ENDPT_TX] == 0) { 932 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 933 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 934 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 935 } 936 } 937 938 /* Set these up now for axe_cmd(). */ 939 usbnet_attach(un, "axedet"); 940 941 /* We need the PHYID for init dance in some cases */ 942 usbnet_lock_mii(un); 943 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 944 aprint_error_dev(self, "failed to read phyaddrs\n"); 945 946 return; 947 } 948 949 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 950 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 951 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 952 if (un->un_phyno == -1) 953 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 954 if (un->un_phyno == -1) { 955 DPRINTF(" no valid PHY address found, assuming PHY address 0", 956 0, 0, 0, 0); 957 un->un_phyno = 0; 958 } 959 960 /* Initialize controller and get station address. */ 961 962 axe_ax_init(un); 963 964 /* 965 * Fetch IPG values. 966 */ 967 if (un->un_flags & (AX772A | AX772B)) { 968 /* Set IPG values. */ 969 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 970 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 971 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 972 } else { 973 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 974 aprint_error_dev(self, "failed to read ipg\n"); 975 usbnet_unlock_mii(un); 976 return; 977 } 978 } 979 980 usbnet_unlock_mii(un); 981 982 if (AXE_IS_178_FAMILY(un)) 983 usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU; 984 if (un->un_flags & AX772B) { 985 struct ifnet *ifp = usbnet_ifp(un); 986 987 ifp->if_capabilities = 988 IFCAP_CSUM_IPv4_Rx | 989 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 990 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 991 /* 992 * Checksum offloading of AX88772B also works with VLAN 993 * tagged frames but there is no way to take advantage 994 * of the feature because vlan(4) assumes 995 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 996 * support checksum offloading with VLAN. VLAN hardware 997 * tagging support of AX88772B is very limited so it's 998 * not possible to announce IFCAP_VLAN_HWTAGGING. 999 */ 1000 } 1001 u_int adv_pause; 1002 if (un->un_flags & (AX772A | AX772B | AX178)) 1003 adv_pause = MIIF_DOPAUSE; 1004 else 1005 adv_pause = 0; 1006 adv_pause = 0; 1007 1008 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 1009 0, adv_pause); 1010 } 1011 1012 static void 1013 axe_rx_loop(struct usbnet * un, struct usbd_xfer *xfer, 1014 struct usbnet_chain *c, uint32_t total_len) 1015 { 1016 AXEHIST_FUNC(); AXEHIST_CALLED(); 1017 struct axe_softc * const sc = usbnet_softc(un); 1018 struct ifnet *ifp = usbnet_ifp(un); 1019 uint8_t *buf = c->unc_buf; 1020 1021 do { 1022 u_int pktlen = 0; 1023 u_int rxlen = 0; 1024 int flags = 0; 1025 1026 if ((un->un_flags & AXSTD_FRAME) != 0) { 1027 struct axe_sframe_hdr hdr; 1028 1029 if (total_len < sizeof(hdr)) { 1030 ifp->if_ierrors++; 1031 break; 1032 } 1033 1034 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1035 /* 1036 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1037 * For some architectures, __builtin_memcpy() of 1038 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1039 * at onece, which results in alignment error. 1040 */ 1041 hdr.len = *(uint16_t *)buf; 1042 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1043 #else 1044 memcpy(&hdr, buf, sizeof(hdr)); 1045 #endif 1046 1047 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1048 total_len, 1049 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1050 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1051 1052 total_len -= sizeof(hdr); 1053 buf += sizeof(hdr); 1054 1055 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1056 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1057 AXE_RH1M_RXLEN_MASK) { 1058 ifp->if_ierrors++; 1059 break; 1060 } 1061 1062 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1063 if (total_len < rxlen) { 1064 pktlen = total_len; 1065 total_len = 0; 1066 } else { 1067 pktlen = rxlen; 1068 rxlen = roundup2(rxlen, 2); 1069 total_len -= rxlen; 1070 } 1071 1072 } else if ((un->un_flags & AXCSUM_FRAME) != 0) { 1073 struct axe_csum_hdr csum_hdr; 1074 1075 if (total_len < sizeof(csum_hdr)) { 1076 ifp->if_ierrors++; 1077 break; 1078 } 1079 1080 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1081 1082 csum_hdr.len = le16toh(csum_hdr.len); 1083 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1084 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1085 1086 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1087 " cstatus %#jx", total_len, 1088 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1089 1090 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1091 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1092 sc->sc_lenmask) { 1093 /* we lost sync */ 1094 ifp->if_ierrors++; 1095 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1096 "err", 1097 AXE_CSUM_RXBYTES(csum_hdr.len), 1098 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1099 sc->sc_lenmask, 0); 1100 break; 1101 } 1102 /* 1103 * Get total transferred frame length including 1104 * checksum header. The length should be multiple 1105 * of 4. 1106 */ 1107 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1108 u_int len = sizeof(csum_hdr) + pktlen; 1109 len = (len + 3) & ~3; 1110 if (total_len < len) { 1111 DPRINTFN(20, "total_len %#jx < len %#jx", 1112 total_len, len, 0, 0); 1113 /* invalid length */ 1114 ifp->if_ierrors++; 1115 break; 1116 } 1117 buf += sizeof(csum_hdr); 1118 1119 const uint16_t cstatus = csum_hdr.cstatus; 1120 1121 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1122 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1123 flags |= M_CSUM_TCP_UDP_BAD; 1124 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1125 flags |= M_CSUM_IPv4_BAD; 1126 1127 const uint16_t l4type = 1128 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1129 1130 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1131 flags |= M_CSUM_TCPv4; 1132 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1133 flags |= M_CSUM_UDPv4; 1134 } 1135 if (total_len < len) { 1136 pktlen = total_len; 1137 total_len = 0; 1138 } else { 1139 total_len -= len; 1140 rxlen = len - sizeof(csum_hdr); 1141 } 1142 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1143 " rxlen %#jx", total_len, len, pktlen, rxlen); 1144 } else { /* AX172 */ 1145 pktlen = rxlen = total_len; 1146 total_len = 0; 1147 } 1148 1149 usbnet_enqueue(un, buf, pktlen, flags, 0, 0); 1150 buf += rxlen; 1151 1152 } while (total_len > 0); 1153 1154 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1155 } 1156 1157 static unsigned 1158 axe_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1159 { 1160 AXEHIST_FUNC(); AXEHIST_CALLED(); 1161 struct axe_sframe_hdr hdr, tlr; 1162 size_t hdr_len = 0, tlr_len = 0; 1163 int length, boundary; 1164 1165 usbnet_isowned_tx(un); 1166 1167 if (AXE_IS_178_FAMILY(un)) { 1168 /* 1169 * Copy the mbuf data into a contiguous buffer, leaving two 1170 * bytes at the beginning to hold the frame length. 1171 */ 1172 boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1173 1174 hdr.len = htole16(m->m_pkthdr.len); 1175 hdr.ilen = ~hdr.len; 1176 hdr_len = sizeof(hdr); 1177 1178 length = hdr_len + m->m_pkthdr.len; 1179 1180 if ((length % boundary) == 0) { 1181 tlr.len = 0x0000; 1182 tlr.ilen = 0xffff; 1183 tlr_len = sizeof(tlr); 1184 } 1185 DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx", 1186 length, m->m_pkthdr.len, sizeof(hdr), 0); 1187 } 1188 1189 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - hdr_len - tlr_len) 1190 return 0; 1191 length = hdr_len + m->m_pkthdr.len + tlr_len; 1192 1193 if (hdr_len) 1194 memcpy(c->unc_buf, &hdr, hdr_len); 1195 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + hdr_len); 1196 if (tlr_len) 1197 memcpy(c->unc_buf + length, &tlr, tlr_len); 1198 1199 return length; 1200 } 1201 1202 static void 1203 axe_csum_cfg(struct axe_softc *sc) 1204 { 1205 struct usbnet * const un = &sc->axe_un; 1206 struct ifnet * const ifp = usbnet_ifp(un); 1207 uint16_t csum1, csum2; 1208 1209 if ((un->un_flags & AX772B) != 0) { 1210 csum1 = 0; 1211 csum2 = 0; 1212 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1213 csum1 |= AXE_TXCSUM_IP; 1214 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1215 csum1 |= AXE_TXCSUM_TCP; 1216 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1217 csum1 |= AXE_TXCSUM_UDP; 1218 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1219 csum1 |= AXE_TXCSUM_TCPV6; 1220 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1221 csum1 |= AXE_TXCSUM_UDPV6; 1222 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1223 csum1 = 0; 1224 csum2 = 0; 1225 1226 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1227 csum1 |= AXE_RXCSUM_IP; 1228 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1229 csum1 |= AXE_RXCSUM_TCP; 1230 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1231 csum1 |= AXE_RXCSUM_UDP; 1232 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1233 csum1 |= AXE_RXCSUM_TCPV6; 1234 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1235 csum1 |= AXE_RXCSUM_UDPV6; 1236 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1237 } 1238 } 1239 1240 static int 1241 axe_init_locked(struct ifnet *ifp) 1242 { 1243 AXEHIST_FUNC(); AXEHIST_CALLED(); 1244 struct usbnet * const un = ifp->if_softc; 1245 struct axe_softc * const sc = usbnet_softc(un); 1246 int rxmode; 1247 1248 usbnet_isowned(un); 1249 1250 if (usbnet_isdying(un)) 1251 return EIO; 1252 1253 /* Cancel pending I/O */ 1254 usbnet_stop(un, ifp, 1); 1255 1256 usbnet_lock_mii_un_locked(un); 1257 1258 /* Reset the ethernet interface. */ 1259 axe_reset(un); 1260 1261 #if 0 1262 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1263 AX_GPIO_GPO2EN, 5, in_pm); 1264 #endif 1265 /* Set MAC address and transmitter IPG values. */ 1266 if (AXE_IS_178_FAMILY(un)) { 1267 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1268 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1269 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1270 } else { 1271 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1272 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1273 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1274 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1275 } 1276 if (AXE_IS_178_FAMILY(un)) { 1277 un->un_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1278 if ((un->un_flags & AX772B) != 0 && 1279 (ifp->if_capenable & AX_RXCSUM) != 0) { 1280 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1281 un->un_flags |= AXCSUM_FRAME; 1282 } else { 1283 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1284 un->un_flags |= AXSTD_FRAME; 1285 } 1286 } 1287 1288 /* Configure TX/RX checksum offloading. */ 1289 axe_csum_cfg(sc); 1290 1291 if (un->un_flags & AX772B) { 1292 /* AX88772B uses different maximum frame burst configuration. */ 1293 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1294 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1295 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1296 } 1297 /* Enable receiver, set RX mode */ 1298 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1299 if (AXE_IS_178_FAMILY(un)) { 1300 if (un->un_flags & AX772B) { 1301 /* 1302 * Select RX header format type 1. Aligning IP 1303 * header on 4 byte boundary is not needed when 1304 * checksum offloading feature is not used 1305 * because we always copy the received frame in 1306 * RX handler. When RX checksum offloading is 1307 * active, aligning IP header is required to 1308 * reflect actual frame length including RX 1309 * header size. 1310 */ 1311 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1312 if (un->un_flags & AXCSUM_FRAME) 1313 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1314 } else { 1315 /* 1316 * Default Rx buffer size is too small to get 1317 * maximum performance. 1318 */ 1319 #if 0 1320 if (un->un_udev->ud_speed == USB_SPEED_HIGH) { 1321 /* Largest possible USB buffer size for AX88178 */ 1322 } 1323 #endif 1324 rxmode |= AXE_178_RXCMD_MFB_16384; 1325 } 1326 } else { 1327 rxmode |= AXE_172_RXCMD_UNICAST; 1328 } 1329 1330 1331 /* If we want promiscuous mode, set the allframes bit. */ 1332 if (ifp->if_flags & IFF_PROMISC) 1333 rxmode |= AXE_RXCMD_PROMISC; 1334 1335 if (ifp->if_flags & IFF_BROADCAST) 1336 rxmode |= AXE_RXCMD_BROADCAST; 1337 1338 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1339 1340 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1341 1342 /* Load the multicast filter. */ 1343 axe_setiff_locked(un); 1344 1345 usbnet_unlock_mii_un_locked(un); 1346 1347 return usbnet_init_rx_tx(un); 1348 } 1349 1350 static int 1351 axe_init(struct ifnet *ifp) 1352 { 1353 struct usbnet * const un = ifp->if_softc; 1354 1355 usbnet_lock(un); 1356 int ret = axe_init_locked(ifp); 1357 usbnet_unlock(un); 1358 1359 return ret; 1360 } 1361 1362 static int 1363 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1364 { 1365 struct usbnet * const un = ifp->if_softc; 1366 1367 switch (cmd) { 1368 case SIOCADDMULTI: 1369 case SIOCDELMULTI: 1370 axe_setiff(un); 1371 break; 1372 default: 1373 break; 1374 } 1375 1376 return 0; 1377 } 1378 1379 static void 1380 axe_stop(struct ifnet *ifp, int disable) 1381 { 1382 struct usbnet * const un = ifp->if_softc; 1383 1384 usbnet_lock_mii_un_locked(un); 1385 axe_reset(un); 1386 usbnet_unlock_mii_un_locked(un); 1387 } 1388 1389 #ifdef _MODULE 1390 #include "ioconf.c" 1391 #endif 1392 1393 USBNET_MODULE(axe) 1394
Indexes created Thu Sep 25 06:09:39 GMT 2025