if_axe.c revision 1.116
1 /* $NetBSD: if_axe.c,v 1.116 2019/08/16 08:29:20 mrg Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.116 2019/08/16 08:29:20 mrg Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_usb.h" 94 #include "opt_net_mpsafe.h" 95 #endif 96 97 #include <sys/param.h> 98 99 #include <dev/usb/usbnet.h> 100 #include <dev/usb/usbhist.h> 101 #include <dev/usb/if_axereg.h> 102 103 struct axe_type { 104 struct usb_devno axe_dev; 105 uint16_t axe_flags; 106 }; 107 108 struct axe_softc { 109 struct usbnet axe_un; 110 111 /* usbnet:un_flags values */ 112 #define AX178 __BIT(0) /* AX88178 */ 113 #define AX772 __BIT(1) /* AX88772 */ 114 #define AX772A __BIT(2) /* AX88772A */ 115 #define AX772B __BIT(3) /* AX88772B */ 116 #define AXSTD_FRAME __BIT(12) 117 #define AXCSUM_FRAME __BIT(13) 118 119 uint8_t axe_ipgs[3]; 120 uint8_t axe_phyaddrs[2]; 121 uint16_t sc_pwrcfg; 122 uint16_t sc_lenmask; 123 124 }; 125 126 #define AXE_IS_178_FAMILY(un) \ 127 ((un)->un_flags & (AX772 | AX772A | AX772B | AX178)) 128 129 #define AXE_IS_772(un) \ 130 ((un)->un_flags & (AX772 | AX772A | AX772B)) 131 132 #define AX_RXCSUM \ 133 (IFCAP_CSUM_IPv4_Rx | \ 134 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 135 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 136 137 #define AX_TXCSUM \ 138 (IFCAP_CSUM_IPv4_Tx | \ 139 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 140 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 141 142 /* 143 * AXE_178_MAX_FRAME_BURST 144 * max frame burst size for Ax88178 and Ax88772 145 * 0 2048 bytes 146 * 1 4096 bytes 147 * 2 8192 bytes 148 * 3 16384 bytes 149 * use the largest your system can handle without USB stalling. 150 * 151 * NB: 88772 parts appear to generate lots of input errors with 152 * a 2K rx buffer and 8K is only slightly faster than 4K on an 153 * EHCI port on a T42 so change at your own risk. 154 */ 155 #define AXE_178_MAX_FRAME_BURST 1 156 157 158 #ifdef USB_DEBUG 159 #ifndef AXE_DEBUG 160 #define axedebug 0 161 #else 162 static int axedebug = 0; 163 164 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 165 { 166 int err; 167 const struct sysctlnode *rnode; 168 const struct sysctlnode *cnode; 169 170 err = sysctl_createv(clog, 0, NULL, &rnode, 171 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 172 SYSCTL_DESCR("axe global controls"), 173 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 174 175 if (err) 176 goto fail; 177 178 /* control debugging printfs */ 179 err = sysctl_createv(clog, 0, &rnode, &cnode, 180 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 181 "debug", SYSCTL_DESCR("Enable debugging output"), 182 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 183 if (err) 184 goto fail; 185 186 return; 187 fail: 188 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 189 } 190 191 #endif /* AXE_DEBUG */ 192 #endif /* USB_DEBUG */ 193 194 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 195 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 196 #define AXEHIST_FUNC() USBHIST_FUNC() 197 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 198 199 /* 200 * Various supported device vendors/products. 201 */ 202 static const struct axe_type axe_devs[] = { 203 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 204 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 205 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 206 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 207 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 208 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 209 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 210 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 211 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 212 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 213 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 214 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 215 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 216 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 217 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 218 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 219 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 220 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 221 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 222 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 223 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 224 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 225 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 226 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 227 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 228 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 229 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 230 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 231 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 232 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 233 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 234 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 235 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 236 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 237 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 238 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 239 }; 240 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 241 242 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 243 { 0x8000, 0x8001, 2048 }, 244 { 0x8100, 0x8147, 4096 }, 245 { 0x8200, 0x81EB, 6144 }, 246 { 0x8300, 0x83D7, 8192 }, 247 { 0x8400, 0x851E, 16384 }, 248 { 0x8500, 0x8666, 20480 }, 249 { 0x8600, 0x87AE, 24576 }, 250 { 0x8700, 0x8A3D, 32768 } 251 }; 252 253 int axe_match(device_t, cfdata_t, void *); 254 void axe_attach(device_t, device_t, void *); 255 256 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 257 axe_match, axe_attach, usbnet_detach, usbnet_activate); 258 259 static void axe_stop(struct ifnet *, int); 260 static int axe_ioctl(struct ifnet *, u_long, void *); 261 static int axe_init(struct ifnet *); 262 static usbd_status axe_mii_read_reg(struct usbnet *, int, int, uint16_t *); 263 static usbd_status axe_mii_write_reg(struct usbnet *, int, int, uint16_t); 264 static void axe_mii_statchg(struct ifnet *); 265 static void axe_rx_loop(struct usbnet *, struct usbnet_chain *, uint32_t); 266 static unsigned axe_tx_prepare(struct usbnet *, struct mbuf *, 267 struct usbnet_chain *); 268 269 static void axe_ax88178_init(struct axe_softc *); 270 static void axe_ax88772_init(struct axe_softc *); 271 static void axe_ax88772a_init(struct axe_softc *); 272 static void axe_ax88772b_init(struct axe_softc *); 273 274 static struct usbnet_ops axe_ops = { 275 .uno_stop = axe_stop, 276 .uno_ioctl = axe_ioctl, 277 .uno_read_reg = axe_mii_read_reg, 278 .uno_write_reg = axe_mii_write_reg, 279 .uno_statchg = axe_mii_statchg, 280 .uno_tx_prepare = axe_tx_prepare, 281 .uno_rx_loop = axe_rx_loop, 282 .uno_init = axe_init, 283 }; 284 285 static usbd_status 286 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 287 { 288 AXEHIST_FUNC(); AXEHIST_CALLED(); 289 struct usbnet * const un = &sc->axe_un; 290 usb_device_request_t req; 291 usbd_status err; 292 293 usbnet_isowned_mii(un); 294 295 if (usbnet_isdying(un)) 296 return -1; 297 298 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 299 300 if (AXE_CMD_DIR(cmd)) 301 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 302 else 303 req.bmRequestType = UT_READ_VENDOR_DEVICE; 304 req.bRequest = AXE_CMD_CMD(cmd); 305 USETW(req.wValue, val); 306 USETW(req.wIndex, index); 307 USETW(req.wLength, AXE_CMD_LEN(cmd)); 308 309 err = usbd_do_request(un->un_udev, &req, buf); 310 if (err) 311 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 312 313 return err; 314 } 315 316 static usbd_status 317 axe_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 318 { 319 AXEHIST_FUNC(); AXEHIST_CALLED(); 320 struct axe_softc * const sc = usbnet_softc(un); 321 usbd_status err; 322 uint16_t data; 323 324 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 325 326 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 327 328 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 329 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 330 331 if (err) { 332 aprint_error_dev(un->un_dev, "read PHY failed\n"); 333 return err; 334 } 335 336 *val = le16toh(data); 337 if (AXE_IS_772(un) && reg == MII_BMSR) { 338 /* 339 * BMSR of AX88772 indicates that it supports extended 340 * capability but the extended status register is 341 * reserved for embedded ethernet PHY. So clear the 342 * extended capability bit of BMSR. 343 */ 344 *val &= ~BMSR_EXTCAP; 345 } 346 347 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 348 349 return USBD_NORMAL_COMPLETION; 350 } 351 352 static usbd_status 353 axe_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 354 { 355 struct axe_softc * const sc = usbnet_softc(un); 356 usbd_status err; 357 uint16_t aval; 358 359 aval = htole16(val); 360 361 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 362 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval); 363 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 364 365 return err; 366 } 367 368 static void 369 axe_mii_statchg(struct ifnet *ifp) 370 { 371 AXEHIST_FUNC(); AXEHIST_CALLED(); 372 373 struct usbnet * const un = ifp->if_softc; 374 struct axe_softc * const sc = usbnet_softc(un); 375 struct mii_data *mii = usbnet_mii(un); 376 int val, err; 377 378 if (usbnet_isdying(un)) 379 return; 380 381 val = 0; 382 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 383 val |= AXE_MEDIA_FULL_DUPLEX; 384 if (AXE_IS_178_FAMILY(un)) { 385 if ((IFM_OPTIONS(mii->mii_media_active) & 386 IFM_ETH_TXPAUSE) != 0) 387 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 388 if ((IFM_OPTIONS(mii->mii_media_active) & 389 IFM_ETH_RXPAUSE) != 0) 390 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 391 } 392 } 393 if (AXE_IS_178_FAMILY(un)) { 394 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 395 if (un->un_flags & AX178) 396 val |= AXE_178_MEDIA_ENCK; 397 switch (IFM_SUBTYPE(mii->mii_media_active)) { 398 case IFM_1000_T: 399 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 400 usbnet_set_link(un, true); 401 break; 402 case IFM_100_TX: 403 val |= AXE_178_MEDIA_100TX; 404 usbnet_set_link(un, true); 405 break; 406 case IFM_10_T: 407 usbnet_set_link(un, true); 408 break; 409 } 410 } 411 412 DPRINTF("val=0x%jx", val, 0, 0, 0); 413 usbnet_lock_mii(un); 414 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 415 usbnet_unlock_mii(un); 416 if (err) 417 aprint_error_dev(un->un_dev, "media change failed\n"); 418 } 419 420 static void 421 axe_setiff_locked(struct usbnet *un) 422 { 423 AXEHIST_FUNC(); AXEHIST_CALLED(); 424 struct axe_softc * const sc = usbnet_softc(un); 425 struct ifnet * const ifp = usbnet_ifp(un); 426 struct ethercom *ec = usbnet_ec(un); 427 struct ether_multi *enm; 428 struct ether_multistep step; 429 uint32_t h = 0; 430 uint16_t rxmode; 431 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 432 433 usbnet_isowned_mii(un); 434 435 if (usbnet_isdying(un)) 436 return; 437 438 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 439 aprint_error_dev(un->un_dev, "can't read rxmode"); 440 return; 441 } 442 rxmode = le16toh(rxmode); 443 444 rxmode &= 445 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 446 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 447 448 rxmode |= 449 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 450 451 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 452 if (ifp->if_flags & IFF_PROMISC) 453 rxmode |= AXE_RXCMD_PROMISC; 454 goto allmulti; 455 } 456 457 /* Now program new ones */ 458 ETHER_LOCK(ec); 459 ETHER_FIRST_MULTI(step, ec, enm); 460 while (enm != NULL) { 461 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 462 ETHER_ADDR_LEN) != 0) { 463 ETHER_UNLOCK(ec); 464 goto allmulti; 465 } 466 467 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 468 hashtbl[h >> 3] |= 1U << (h & 7); 469 ETHER_NEXT_MULTI(step, enm); 470 } 471 ETHER_UNLOCK(ec); 472 ifp->if_flags &= ~IFF_ALLMULTI; 473 rxmode |= AXE_RXCMD_MULTICAST; 474 475 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 476 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 477 return; 478 479 allmulti: 480 ifp->if_flags |= IFF_ALLMULTI; 481 rxmode |= AXE_RXCMD_ALLMULTI; 482 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 483 } 484 485 static void 486 axe_setiff(struct usbnet *un) 487 { 488 usbnet_lock_mii(un); 489 axe_setiff_locked(un); 490 usbnet_unlock_mii(un); 491 } 492 493 static void 494 axe_ax_init(struct usbnet *un) 495 { 496 struct axe_softc * const sc = usbnet_softc(un); 497 498 int cmd = AXE_178_CMD_READ_NODEID; 499 500 if (un->un_flags & AX178) { 501 axe_ax88178_init(sc); 502 } else if (un->un_flags & AX772) { 503 axe_ax88772_init(sc); 504 } else if (un->un_flags & AX772A) { 505 axe_ax88772a_init(sc); 506 } else if (un->un_flags & AX772B) { 507 axe_ax88772b_init(sc); 508 return; 509 } else { 510 cmd = AXE_172_CMD_READ_NODEID; 511 } 512 513 if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) { 514 aprint_error_dev(un->un_dev, 515 "failed to read ethernet address\n"); 516 } 517 } 518 519 520 static void 521 axe_reset(struct usbnet *un) 522 { 523 524 usbnet_isowned_mii(un); 525 526 if (usbnet_isdying(un)) 527 return; 528 529 /* 530 * softnet_lock can be taken when NET_MPAFE is not defined when calling 531 * if_addr_init -> if_init. This doesn't mix well with the 532 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 533 * can fire during the wait and attempt to take softnet_lock and then 534 * block the softclk thread meaning the wait never ends. 535 */ 536 #ifndef NET_MPSAFE 537 /* XXX What to reset? */ 538 539 /* Wait a little while for the chip to get its brains in order. */ 540 DELAY(1000); 541 #else 542 axe_ax_init(un); 543 #endif 544 } 545 546 static int 547 axe_get_phyno(struct axe_softc *sc, int sel) 548 { 549 int phyno; 550 551 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 552 case PHY_TYPE_100_HOME: 553 /* FALLTHROUGH */ 554 case PHY_TYPE_GIG: 555 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 556 break; 557 case PHY_TYPE_SPECIAL: 558 /* FALLTHROUGH */ 559 case PHY_TYPE_RSVD: 560 /* FALLTHROUGH */ 561 case PHY_TYPE_NON_SUP: 562 /* FALLTHROUGH */ 563 default: 564 phyno = -1; 565 break; 566 } 567 568 return phyno; 569 } 570 571 #define AXE_GPIO_WRITE(x, y) do { \ 572 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 573 usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \ 574 } while (0) 575 576 static void 577 axe_ax88178_init(struct axe_softc *sc) 578 { 579 AXEHIST_FUNC(); AXEHIST_CALLED(); 580 struct usbnet * const un = &sc->axe_un; 581 int gpio0, ledmode, phymode; 582 uint16_t eeprom, val; 583 584 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 585 /* XXX magic */ 586 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 587 eeprom = 0xffff; 588 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 589 590 eeprom = le16toh(eeprom); 591 592 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 593 594 /* if EEPROM is invalid we have to use to GPIO0 */ 595 if (eeprom == 0xffff) { 596 phymode = AXE_PHY_MODE_MARVELL; 597 gpio0 = 1; 598 ledmode = 0; 599 } else { 600 phymode = eeprom & 0x7f; 601 gpio0 = (eeprom & 0x80) ? 0 : 1; 602 ledmode = eeprom >> 8; 603 } 604 605 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 606 607 /* Program GPIOs depending on PHY hardware. */ 608 switch (phymode) { 609 case AXE_PHY_MODE_MARVELL: 610 if (gpio0 == 1) { 611 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 612 hz / 32); 613 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 614 hz / 32); 615 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 616 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 617 hz / 32); 618 } else { 619 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 620 AXE_GPIO1_EN, hz / 3); 621 if (ledmode == 1) { 622 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 623 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 624 hz / 3); 625 } else { 626 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 627 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 628 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 629 AXE_GPIO2_EN, hz / 4); 630 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 631 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 632 } 633 } 634 break; 635 case AXE_PHY_MODE_CICADA: 636 case AXE_PHY_MODE_CICADA_V2: 637 case AXE_PHY_MODE_CICADA_V2_ASIX: 638 if (gpio0 == 1) 639 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 640 AXE_GPIO0_EN, hz / 32); 641 else 642 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 643 AXE_GPIO1_EN, hz / 32); 644 break; 645 case AXE_PHY_MODE_AGERE: 646 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 647 AXE_GPIO1_EN, hz / 32); 648 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 649 AXE_GPIO2_EN, hz / 32); 650 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 651 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 652 AXE_GPIO2_EN, hz / 32); 653 break; 654 case AXE_PHY_MODE_REALTEK_8211CL: 655 case AXE_PHY_MODE_REALTEK_8211BN: 656 case AXE_PHY_MODE_REALTEK_8251CL: 657 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 658 AXE_GPIO1 | AXE_GPIO1_EN; 659 AXE_GPIO_WRITE(val, hz / 32); 660 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 661 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 662 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 663 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 664 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005); 665 axe_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000); 666 axe_mii_read_reg(un, un->un_phyno, 0x0001, &val); 667 axe_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080); 668 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000); 669 } 670 break; 671 default: 672 /* Unknown PHY model or no need to program GPIOs. */ 673 break; 674 } 675 676 /* soft reset */ 677 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 678 usbd_delay_ms(un->un_udev, 150); 679 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 680 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 681 usbd_delay_ms(un->un_udev, 150); 682 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 683 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 684 usbd_delay_ms(un->un_udev, 10); 685 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 686 } 687 688 static void 689 axe_ax88772_init(struct axe_softc *sc) 690 { 691 AXEHIST_FUNC(); AXEHIST_CALLED(); 692 struct usbnet * const un = &sc->axe_un; 693 694 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 695 usbd_delay_ms(un->un_udev, 40); 696 697 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 698 /* ask for the embedded PHY */ 699 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 700 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 701 usbd_delay_ms(un->un_udev, 10); 702 703 /* power down and reset state, pin reset state */ 704 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 705 usbd_delay_ms(un->un_udev, 60); 706 707 /* power down/reset state, pin operating state */ 708 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 709 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 710 usbd_delay_ms(un->un_udev, 150); 711 712 /* power up, reset */ 713 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 714 715 /* power up, operating */ 716 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 717 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 718 } else { 719 /* ask for external PHY */ 720 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 721 NULL); 722 usbd_delay_ms(un->un_udev, 10); 723 724 /* power down internal PHY */ 725 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 726 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 727 } 728 729 usbd_delay_ms(un->un_udev, 150); 730 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 731 } 732 733 static void 734 axe_ax88772_phywake(struct axe_softc *sc) 735 { 736 AXEHIST_FUNC(); AXEHIST_CALLED(); 737 struct usbnet * const un = &sc->axe_un; 738 739 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 740 /* Manually select internal(embedded) PHY - MAC mode. */ 741 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 742 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 743 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 744 } else { 745 /* 746 * Manually select external PHY - MAC mode. 747 * Reverse MII/RMII is for AX88772A PHY mode. 748 */ 749 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 750 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 751 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 752 } 753 754 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 755 AXE_SW_RESET_IPRL, NULL); 756 757 /* T1 = min 500ns everywhere */ 758 usbd_delay_ms(un->un_udev, 150); 759 760 /* Take PHY out of power down. */ 761 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 762 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 763 } else { 764 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 765 } 766 767 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 768 usbd_delay_ms(un->un_udev, 600); 769 770 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 771 772 /* T3 = 500ns everywhere */ 773 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 774 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 775 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 776 } 777 778 static void 779 axe_ax88772a_init(struct axe_softc *sc) 780 { 781 AXEHIST_FUNC(); AXEHIST_CALLED(); 782 783 /* Reload EEPROM. */ 784 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 785 axe_ax88772_phywake(sc); 786 /* Stop MAC. */ 787 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 788 } 789 790 static void 791 axe_ax88772b_init(struct axe_softc *sc) 792 { 793 AXEHIST_FUNC(); AXEHIST_CALLED(); 794 struct usbnet * const un = &sc->axe_un; 795 uint16_t eeprom; 796 int i; 797 798 /* Reload EEPROM. */ 799 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 800 801 /* 802 * Save PHY power saving configuration(high byte) and 803 * clear EEPROM checksum value(low byte). 804 */ 805 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 806 &eeprom)) { 807 aprint_error_dev(un->un_dev, "failed to read eeprom\n"); 808 return; 809 } 810 811 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 812 813 /* 814 * Auto-loaded default station address from internal ROM is 815 * 00:00:00:00:00:00 such that an explicit access to EEPROM 816 * is required to get real station address. 817 */ 818 uint8_t *eaddr = un->un_eaddr; 819 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 820 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 821 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 822 aprint_error_dev(un->un_dev, 823 "failed to read eeprom\n"); 824 eeprom = 0; 825 } 826 eeprom = le16toh(eeprom); 827 *eaddr++ = (uint8_t)(eeprom & 0xFF); 828 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 829 } 830 /* Wakeup PHY. */ 831 axe_ax88772_phywake(sc); 832 /* Stop MAC. */ 833 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 834 } 835 836 #undef AXE_GPIO_WRITE 837 838 /* 839 * Probe for a AX88172 chip. 840 */ 841 int 842 axe_match(device_t parent, cfdata_t match, void *aux) 843 { 844 struct usb_attach_arg *uaa = aux; 845 846 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 847 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 848 } 849 850 /* 851 * Attach the interface. Allocate softc structures, do ifmedia 852 * setup and ethernet/BPF attach. 853 */ 854 void 855 axe_attach(device_t parent, device_t self, void *aux) 856 { 857 AXEHIST_FUNC(); AXEHIST_CALLED(); 858 struct axe_softc *sc = device_private(self); 859 struct usbnet * const un = &sc->axe_un; 860 struct usb_attach_arg *uaa = aux; 861 struct usbd_device *dev = uaa->uaa_device; 862 usbd_status err; 863 usb_interface_descriptor_t *id; 864 usb_endpoint_descriptor_t *ed; 865 char *devinfop; 866 unsigned bufsz; 867 int i; 868 869 KASSERT((void *)sc == un); 870 871 aprint_naive("\n"); 872 aprint_normal("\n"); 873 devinfop = usbd_devinfo_alloc(dev, 0); 874 aprint_normal_dev(self, "%s\n", devinfop); 875 usbd_devinfo_free(devinfop); 876 877 un->un_dev = self; 878 un->un_udev = dev; 879 un->un_sc = sc; 880 un->un_ops = &axe_ops; 881 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 882 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 883 un->un_rx_list_cnt = AXE_RX_LIST_CNT; 884 un->un_tx_list_cnt = AXE_TX_LIST_CNT; 885 886 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 887 if (err) { 888 aprint_error_dev(self, "failed to set configuration" 889 ", err=%s\n", usbd_errstr(err)); 890 return; 891 } 892 893 un->un_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 894 895 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface); 896 if (err) { 897 aprint_error_dev(self, "getting interface handle failed\n"); 898 return; 899 } 900 901 id = usbd_get_interface_descriptor(un->un_iface); 902 903 /* decide on what our bufsize will be */ 904 if (AXE_IS_178_FAMILY(un)) 905 bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 906 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 907 else 908 bufsz = AXE_172_BUFSZ; 909 un->un_rx_bufsz = un->un_tx_bufsz = bufsz; 910 911 un->un_ed[USBNET_ENDPT_RX] = 0; 912 un->un_ed[USBNET_ENDPT_TX] = 0; 913 un->un_ed[USBNET_ENDPT_INTR] = 0; 914 915 /* Find endpoints. */ 916 for (i = 0; i < id->bNumEndpoints; i++) { 917 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 918 if (ed == NULL) { 919 aprint_error_dev(self, "couldn't get ep %d\n", i); 920 return; 921 } 922 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 923 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 924 925 if (dir == UE_DIR_IN && xt == UE_BULK && 926 un->un_ed[USBNET_ENDPT_RX] == 0) { 927 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 928 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 929 un->un_ed[USBNET_ENDPT_TX] == 0) { 930 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 931 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 932 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 933 } 934 } 935 936 /* Set these up now for axe_cmd(). */ 937 usbnet_attach(un, "axedet"); 938 939 /* We need the PHYID for init dance in some cases */ 940 usbnet_lock_mii(un); 941 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 942 aprint_error_dev(self, "failed to read phyaddrs\n"); 943 944 return; 945 } 946 947 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 948 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 949 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 950 if (un->un_phyno == -1) 951 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 952 if (un->un_phyno == -1) { 953 DPRINTF(" no valid PHY address found, assuming PHY address 0", 954 0, 0, 0, 0); 955 un->un_phyno = 0; 956 } 957 958 /* Initialize controller and get station address. */ 959 960 axe_ax_init(un); 961 962 /* 963 * Fetch IPG values. 964 */ 965 if (un->un_flags & (AX772A | AX772B)) { 966 /* Set IPG values. */ 967 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 968 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 969 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 970 } else { 971 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 972 aprint_error_dev(self, "failed to read ipg\n"); 973 usbnet_unlock_mii(un); 974 return; 975 } 976 } 977 978 usbnet_unlock_mii(un); 979 980 if (AXE_IS_178_FAMILY(un)) 981 usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU; 982 if (un->un_flags & AX772B) { 983 struct ifnet *ifp = usbnet_ifp(un); 984 985 ifp->if_capabilities = 986 IFCAP_CSUM_IPv4_Rx | 987 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 988 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 989 /* 990 * Checksum offloading of AX88772B also works with VLAN 991 * tagged frames but there is no way to take advantage 992 * of the feature because vlan(4) assumes 993 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 994 * support checksum offloading with VLAN. VLAN hardware 995 * tagging support of AX88772B is very limited so it's 996 * not possible to announce IFCAP_VLAN_HWTAGGING. 997 */ 998 } 999 u_int adv_pause; 1000 if (un->un_flags & (AX772A | AX772B | AX178)) 1001 adv_pause = MIIF_DOPAUSE; 1002 else 1003 adv_pause = 0; 1004 adv_pause = 0; 1005 1006 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 1007 0, adv_pause); 1008 } 1009 1010 static void 1011 axe_rx_loop(struct usbnet * un, struct usbnet_chain *c, uint32_t total_len) 1012 { 1013 AXEHIST_FUNC(); AXEHIST_CALLED(); 1014 struct axe_softc * const sc = usbnet_softc(un); 1015 struct ifnet *ifp = usbnet_ifp(un); 1016 uint8_t *buf = c->unc_buf; 1017 1018 do { 1019 u_int pktlen = 0; 1020 u_int rxlen = 0; 1021 int flags = 0; 1022 1023 if ((un->un_flags & AXSTD_FRAME) != 0) { 1024 struct axe_sframe_hdr hdr; 1025 1026 if (total_len < sizeof(hdr)) { 1027 ifp->if_ierrors++; 1028 break; 1029 } 1030 1031 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1032 /* 1033 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1034 * For some architectures, __builtin_memcpy() of 1035 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1036 * at onece, which results in alignment error. 1037 */ 1038 hdr.len = *(uint16_t *)buf; 1039 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1040 #else 1041 memcpy(&hdr, buf, sizeof(hdr)); 1042 #endif 1043 1044 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1045 total_len, 1046 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1047 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1048 1049 total_len -= sizeof(hdr); 1050 buf += sizeof(hdr); 1051 1052 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1053 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1054 AXE_RH1M_RXLEN_MASK) { 1055 ifp->if_ierrors++; 1056 break; 1057 } 1058 1059 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1060 if (total_len < rxlen) { 1061 pktlen = total_len; 1062 total_len = 0; 1063 } else { 1064 pktlen = rxlen; 1065 rxlen = roundup2(rxlen, 2); 1066 total_len -= rxlen; 1067 } 1068 1069 } else if ((un->un_flags & AXCSUM_FRAME) != 0) { 1070 struct axe_csum_hdr csum_hdr; 1071 1072 if (total_len < sizeof(csum_hdr)) { 1073 ifp->if_ierrors++; 1074 break; 1075 } 1076 1077 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1078 1079 csum_hdr.len = le16toh(csum_hdr.len); 1080 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1081 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1082 1083 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1084 " cstatus %#jx", total_len, 1085 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1086 1087 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1088 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1089 sc->sc_lenmask) { 1090 /* we lost sync */ 1091 ifp->if_ierrors++; 1092 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1093 "err", 1094 AXE_CSUM_RXBYTES(csum_hdr.len), 1095 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1096 sc->sc_lenmask, 0); 1097 break; 1098 } 1099 /* 1100 * Get total transferred frame length including 1101 * checksum header. The length should be multiple 1102 * of 4. 1103 */ 1104 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1105 u_int len = sizeof(csum_hdr) + pktlen; 1106 len = (len + 3) & ~3; 1107 if (total_len < len) { 1108 DPRINTFN(20, "total_len %#jx < len %#jx", 1109 total_len, len, 0, 0); 1110 /* invalid length */ 1111 ifp->if_ierrors++; 1112 break; 1113 } 1114 buf += sizeof(csum_hdr); 1115 1116 const uint16_t cstatus = csum_hdr.cstatus; 1117 1118 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1119 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1120 flags |= M_CSUM_TCP_UDP_BAD; 1121 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1122 flags |= M_CSUM_IPv4_BAD; 1123 1124 const uint16_t l4type = 1125 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1126 1127 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1128 flags |= M_CSUM_TCPv4; 1129 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1130 flags |= M_CSUM_UDPv4; 1131 } 1132 if (total_len < len) { 1133 pktlen = total_len; 1134 total_len = 0; 1135 } else { 1136 total_len -= len; 1137 rxlen = len - sizeof(csum_hdr); 1138 } 1139 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1140 " rxlen %#jx", total_len, len, pktlen, rxlen); 1141 } else { /* AX172 */ 1142 pktlen = rxlen = total_len; 1143 total_len = 0; 1144 } 1145 1146 usbnet_enqueue(un, buf, pktlen, flags, 0, 0); 1147 buf += rxlen; 1148 1149 } while (total_len > 0); 1150 1151 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1152 } 1153 1154 static unsigned 1155 axe_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1156 { 1157 AXEHIST_FUNC(); AXEHIST_CALLED(); 1158 struct axe_sframe_hdr hdr, tlr; 1159 size_t hdr_len = 0, tlr_len = 0; 1160 int length, boundary; 1161 1162 usbnet_isowned_tx(un); 1163 1164 if (AXE_IS_178_FAMILY(un)) { 1165 /* 1166 * Copy the mbuf data into a contiguous buffer, leaving two 1167 * bytes at the beginning to hold the frame length. 1168 */ 1169 boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1170 1171 hdr.len = htole16(m->m_pkthdr.len); 1172 hdr.ilen = ~hdr.len; 1173 hdr_len = sizeof(hdr); 1174 1175 length = hdr_len + m->m_pkthdr.len; 1176 1177 if ((length % boundary) == 0) { 1178 tlr.len = 0x0000; 1179 tlr.ilen = 0xffff; 1180 tlr_len = sizeof(tlr); 1181 } 1182 DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx", 1183 length, m->m_pkthdr.len, sizeof(hdr), 0); 1184 } 1185 1186 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - hdr_len - tlr_len) 1187 return 0; 1188 length = hdr_len + m->m_pkthdr.len + tlr_len; 1189 1190 if (hdr_len) 1191 memcpy(c->unc_buf, &hdr, hdr_len); 1192 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + hdr_len); 1193 if (tlr_len) 1194 memcpy(c->unc_buf + length, &tlr, tlr_len); 1195 1196 return length; 1197 } 1198 1199 static void 1200 axe_csum_cfg(struct axe_softc *sc) 1201 { 1202 struct usbnet * const un = &sc->axe_un; 1203 struct ifnet * const ifp = usbnet_ifp(un); 1204 uint16_t csum1, csum2; 1205 1206 if ((un->un_flags & AX772B) != 0) { 1207 csum1 = 0; 1208 csum2 = 0; 1209 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1210 csum1 |= AXE_TXCSUM_IP; 1211 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1212 csum1 |= AXE_TXCSUM_TCP; 1213 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1214 csum1 |= AXE_TXCSUM_UDP; 1215 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1216 csum1 |= AXE_TXCSUM_TCPV6; 1217 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1218 csum1 |= AXE_TXCSUM_UDPV6; 1219 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1220 csum1 = 0; 1221 csum2 = 0; 1222 1223 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1224 csum1 |= AXE_RXCSUM_IP; 1225 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1226 csum1 |= AXE_RXCSUM_TCP; 1227 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1228 csum1 |= AXE_RXCSUM_UDP; 1229 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1230 csum1 |= AXE_RXCSUM_TCPV6; 1231 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1232 csum1 |= AXE_RXCSUM_UDPV6; 1233 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1234 } 1235 } 1236 1237 static int 1238 axe_init_locked(struct ifnet *ifp) 1239 { 1240 AXEHIST_FUNC(); AXEHIST_CALLED(); 1241 struct usbnet * const un = ifp->if_softc; 1242 struct axe_softc * const sc = usbnet_softc(un); 1243 int rxmode; 1244 1245 usbnet_isowned(un); 1246 1247 if (usbnet_isdying(un)) 1248 return EIO; 1249 1250 /* Cancel pending I/O */ 1251 usbnet_stop(un, ifp, 1); 1252 1253 usbnet_lock_mii_un_locked(un); 1254 1255 /* Reset the ethernet interface. */ 1256 axe_reset(un); 1257 1258 #if 0 1259 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1260 AX_GPIO_GPO2EN, 5, in_pm); 1261 #endif 1262 /* Set MAC address and transmitter IPG values. */ 1263 if (AXE_IS_178_FAMILY(un)) { 1264 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1265 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1266 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1267 } else { 1268 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1269 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1270 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1271 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1272 } 1273 if (AXE_IS_178_FAMILY(un)) { 1274 un->un_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1275 if ((un->un_flags & AX772B) != 0 && 1276 (ifp->if_capenable & AX_RXCSUM) != 0) { 1277 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1278 un->un_flags |= AXCSUM_FRAME; 1279 } else { 1280 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1281 un->un_flags |= AXSTD_FRAME; 1282 } 1283 } 1284 1285 /* Configure TX/RX checksum offloading. */ 1286 axe_csum_cfg(sc); 1287 1288 if (un->un_flags & AX772B) { 1289 /* AX88772B uses different maximum frame burst configuration. */ 1290 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1291 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1292 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1293 } 1294 /* Enable receiver, set RX mode */ 1295 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1296 if (AXE_IS_178_FAMILY(un)) { 1297 if (un->un_flags & AX772B) { 1298 /* 1299 * Select RX header format type 1. Aligning IP 1300 * header on 4 byte boundary is not needed when 1301 * checksum offloading feature is not used 1302 * because we always copy the received frame in 1303 * RX handler. When RX checksum offloading is 1304 * active, aligning IP header is required to 1305 * reflect actual frame length including RX 1306 * header size. 1307 */ 1308 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1309 if (un->un_flags & AXCSUM_FRAME) 1310 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1311 } else { 1312 /* 1313 * Default Rx buffer size is too small to get 1314 * maximum performance. 1315 */ 1316 #if 0 1317 if (un->un_udev->ud_speed == USB_SPEED_HIGH) { 1318 /* Largest possible USB buffer size for AX88178 */ 1319 } 1320 #endif 1321 rxmode |= AXE_178_RXCMD_MFB_16384; 1322 } 1323 } else { 1324 rxmode |= AXE_172_RXCMD_UNICAST; 1325 } 1326 1327 1328 /* If we want promiscuous mode, set the allframes bit. */ 1329 if (ifp->if_flags & IFF_PROMISC) 1330 rxmode |= AXE_RXCMD_PROMISC; 1331 1332 if (ifp->if_flags & IFF_BROADCAST) 1333 rxmode |= AXE_RXCMD_BROADCAST; 1334 1335 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1336 1337 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1338 1339 /* Load the multicast filter. */ 1340 axe_setiff_locked(un); 1341 1342 usbnet_unlock_mii_un_locked(un); 1343 1344 return usbnet_init_rx_tx(un); 1345 } 1346 1347 static int 1348 axe_init(struct ifnet *ifp) 1349 { 1350 struct usbnet * const un = ifp->if_softc; 1351 1352 usbnet_lock(un); 1353 int ret = axe_init_locked(ifp); 1354 usbnet_unlock(un); 1355 1356 return ret; 1357 } 1358 1359 static int 1360 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1361 { 1362 struct usbnet * const un = ifp->if_softc; 1363 1364 switch (cmd) { 1365 case SIOCADDMULTI: 1366 case SIOCDELMULTI: 1367 axe_setiff(un); 1368 break; 1369 default: 1370 break; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static void 1377 axe_stop(struct ifnet *ifp, int disable) 1378 { 1379 struct usbnet * const un = ifp->if_softc; 1380 1381 usbnet_lock_mii_un_locked(un); 1382 axe_reset(un); 1383 usbnet_unlock_mii_un_locked(un); 1384 } 1385 1386 #ifdef _MODULE 1387 #include "ioconf.c" 1388 #endif 1389 1390 USBNET_MODULE(axe) 1391
Indexes created Mon Sep 22 21:09:42 GMT 2025