if_axe.c revision 1.117
1 /* $NetBSD: if_axe.c,v 1.117 2019/08/19 07:33:37 mrg Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.117 2019/08/19 07:33:37 mrg Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_usb.h" 94 #include "opt_net_mpsafe.h" 95 #endif 96 97 #include <sys/param.h> 98 99 #include <dev/usb/usbnet.h> 100 #include <dev/usb/usbhist.h> 101 #include <dev/usb/if_axereg.h> 102 103 struct axe_type { 104 struct usb_devno axe_dev; 105 uint16_t axe_flags; 106 }; 107 108 struct axe_softc { 109 struct usbnet axe_un; 110 111 /* usbnet:un_flags values */ 112 #define AX178 __BIT(0) /* AX88178 */ 113 #define AX772 __BIT(1) /* AX88772 */ 114 #define AX772A __BIT(2) /* AX88772A */ 115 #define AX772B __BIT(3) /* AX88772B */ 116 #define AXSTD_FRAME __BIT(12) 117 #define AXCSUM_FRAME __BIT(13) 118 119 uint8_t axe_ipgs[3]; 120 uint8_t axe_phyaddrs[2]; 121 uint16_t sc_pwrcfg; 122 uint16_t sc_lenmask; 123 124 }; 125 126 #define AXE_IS_178_FAMILY(un) \ 127 ((un)->un_flags & (AX772 | AX772A | AX772B | AX178)) 128 129 #define AXE_IS_772(un) \ 130 ((un)->un_flags & (AX772 | AX772A | AX772B)) 131 132 #define AX_RXCSUM \ 133 (IFCAP_CSUM_IPv4_Rx | \ 134 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 135 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 136 137 #define AX_TXCSUM \ 138 (IFCAP_CSUM_IPv4_Tx | \ 139 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 140 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 141 142 /* 143 * AXE_178_MAX_FRAME_BURST 144 * max frame burst size for Ax88178 and Ax88772 145 * 0 2048 bytes 146 * 1 4096 bytes 147 * 2 8192 bytes 148 * 3 16384 bytes 149 * use the largest your system can handle without USB stalling. 150 * 151 * NB: 88772 parts appear to generate lots of input errors with 152 * a 2K rx buffer and 8K is only slightly faster than 4K on an 153 * EHCI port on a T42 so change at your own risk. 154 */ 155 #define AXE_178_MAX_FRAME_BURST 1 156 157 158 #ifdef USB_DEBUG 159 #ifndef AXE_DEBUG 160 #define axedebug 0 161 #else 162 static int axedebug = 0; 163 164 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 165 { 166 int err; 167 const struct sysctlnode *rnode; 168 const struct sysctlnode *cnode; 169 170 err = sysctl_createv(clog, 0, NULL, &rnode, 171 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 172 SYSCTL_DESCR("axe global controls"), 173 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 174 175 if (err) 176 goto fail; 177 178 /* control debugging printfs */ 179 err = sysctl_createv(clog, 0, &rnode, &cnode, 180 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 181 "debug", SYSCTL_DESCR("Enable debugging output"), 182 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 183 if (err) 184 goto fail; 185 186 return; 187 fail: 188 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 189 } 190 191 #endif /* AXE_DEBUG */ 192 #endif /* USB_DEBUG */ 193 194 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 195 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 196 #define AXEHIST_FUNC() USBHIST_FUNC() 197 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 198 199 /* 200 * Various supported device vendors/products. 201 */ 202 static const struct axe_type axe_devs[] = { 203 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 204 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 205 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 206 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 207 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 208 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 209 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 210 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 211 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 212 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 213 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 214 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 215 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 216 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 217 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 218 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 219 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 220 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 221 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 222 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 223 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 224 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 225 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 226 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 227 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 228 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 229 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 230 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 231 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 232 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 233 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 234 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 235 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 236 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 237 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 238 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 239 }; 240 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 241 242 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 243 { 0x8000, 0x8001, 2048 }, 244 { 0x8100, 0x8147, 4096 }, 245 { 0x8200, 0x81EB, 6144 }, 246 { 0x8300, 0x83D7, 8192 }, 247 { 0x8400, 0x851E, 16384 }, 248 { 0x8500, 0x8666, 20480 }, 249 { 0x8600, 0x87AE, 24576 }, 250 { 0x8700, 0x8A3D, 32768 } 251 }; 252 253 int axe_match(device_t, cfdata_t, void *); 254 void axe_attach(device_t, device_t, void *); 255 256 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 257 axe_match, axe_attach, usbnet_detach, usbnet_activate); 258 259 static void axe_stop(struct ifnet *, int); 260 static int axe_ioctl(struct ifnet *, u_long, void *); 261 static int axe_init(struct ifnet *); 262 static usbd_status axe_mii_read_reg(struct usbnet *, int, int, uint16_t *); 263 static usbd_status axe_mii_write_reg(struct usbnet *, int, int, uint16_t); 264 static void axe_mii_statchg(struct ifnet *); 265 static void axe_rx_loop(struct usbnet *, struct usbnet_chain *, uint32_t); 266 static unsigned axe_tx_prepare(struct usbnet *, struct mbuf *, 267 struct usbnet_chain *); 268 269 static void axe_ax88178_init(struct axe_softc *); 270 static void axe_ax88772_init(struct axe_softc *); 271 static void axe_ax88772a_init(struct axe_softc *); 272 static void axe_ax88772b_init(struct axe_softc *); 273 274 static struct usbnet_ops axe_ops = { 275 .uno_stop = axe_stop, 276 .uno_ioctl = axe_ioctl, 277 .uno_read_reg = axe_mii_read_reg, 278 .uno_write_reg = axe_mii_write_reg, 279 .uno_statchg = axe_mii_statchg, 280 .uno_tx_prepare = axe_tx_prepare, 281 .uno_rx_loop = axe_rx_loop, 282 .uno_init = axe_init, 283 }; 284 285 static usbd_status 286 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 287 { 288 AXEHIST_FUNC(); AXEHIST_CALLED(); 289 struct usbnet * const un = &sc->axe_un; 290 usb_device_request_t req; 291 usbd_status err; 292 293 usbnet_isowned_mii(un); 294 295 if (usbnet_isdying(un)) 296 return -1; 297 298 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 299 300 if (AXE_CMD_DIR(cmd)) 301 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 302 else 303 req.bmRequestType = UT_READ_VENDOR_DEVICE; 304 req.bRequest = AXE_CMD_CMD(cmd); 305 USETW(req.wValue, val); 306 USETW(req.wIndex, index); 307 USETW(req.wLength, AXE_CMD_LEN(cmd)); 308 309 err = usbd_do_request(un->un_udev, &req, buf); 310 if (err) 311 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 312 313 return err; 314 } 315 316 static usbd_status 317 axe_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 318 { 319 AXEHIST_FUNC(); AXEHIST_CALLED(); 320 struct axe_softc * const sc = usbnet_softc(un); 321 usbd_status err; 322 uint16_t data; 323 324 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 325 326 if (un->un_phyno != phy) 327 return USBD_INVAL; 328 329 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 330 331 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 332 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 333 334 if (err) { 335 aprint_error_dev(un->un_dev, "read PHY failed\n"); 336 return err; 337 } 338 339 *val = le16toh(data); 340 if (AXE_IS_772(un) && reg == MII_BMSR) { 341 /* 342 * BMSR of AX88772 indicates that it supports extended 343 * capability but the extended status register is 344 * reserved for embedded ethernet PHY. So clear the 345 * extended capability bit of BMSR. 346 */ 347 *val &= ~BMSR_EXTCAP; 348 } 349 350 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 351 352 return USBD_NORMAL_COMPLETION; 353 } 354 355 static usbd_status 356 axe_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 357 { 358 struct axe_softc * const sc = usbnet_softc(un); 359 usbd_status err; 360 uint16_t aval; 361 362 if (un->un_phyno != phy) 363 return USBD_INVAL; 364 365 aval = htole16(val); 366 367 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 368 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval); 369 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 370 371 return err; 372 } 373 374 static void 375 axe_mii_statchg(struct ifnet *ifp) 376 { 377 AXEHIST_FUNC(); AXEHIST_CALLED(); 378 379 struct usbnet * const un = ifp->if_softc; 380 struct axe_softc * const sc = usbnet_softc(un); 381 struct mii_data *mii = usbnet_mii(un); 382 int val, err; 383 384 if (usbnet_isdying(un)) 385 return; 386 387 val = 0; 388 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 389 val |= AXE_MEDIA_FULL_DUPLEX; 390 if (AXE_IS_178_FAMILY(un)) { 391 if ((IFM_OPTIONS(mii->mii_media_active) & 392 IFM_ETH_TXPAUSE) != 0) 393 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 394 if ((IFM_OPTIONS(mii->mii_media_active) & 395 IFM_ETH_RXPAUSE) != 0) 396 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 397 } 398 } 399 if (AXE_IS_178_FAMILY(un)) { 400 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 401 if (un->un_flags & AX178) 402 val |= AXE_178_MEDIA_ENCK; 403 switch (IFM_SUBTYPE(mii->mii_media_active)) { 404 case IFM_1000_T: 405 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 406 usbnet_set_link(un, true); 407 break; 408 case IFM_100_TX: 409 val |= AXE_178_MEDIA_100TX; 410 usbnet_set_link(un, true); 411 break; 412 case IFM_10_T: 413 usbnet_set_link(un, true); 414 break; 415 } 416 } 417 418 DPRINTF("val=0x%jx", val, 0, 0, 0); 419 usbnet_lock_mii(un); 420 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 421 usbnet_unlock_mii(un); 422 if (err) 423 aprint_error_dev(un->un_dev, "media change failed\n"); 424 } 425 426 static void 427 axe_setiff_locked(struct usbnet *un) 428 { 429 AXEHIST_FUNC(); AXEHIST_CALLED(); 430 struct axe_softc * const sc = usbnet_softc(un); 431 struct ifnet * const ifp = usbnet_ifp(un); 432 struct ethercom *ec = usbnet_ec(un); 433 struct ether_multi *enm; 434 struct ether_multistep step; 435 uint32_t h = 0; 436 uint16_t rxmode; 437 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 438 439 usbnet_isowned_mii(un); 440 441 if (usbnet_isdying(un)) 442 return; 443 444 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 445 aprint_error_dev(un->un_dev, "can't read rxmode"); 446 return; 447 } 448 rxmode = le16toh(rxmode); 449 450 rxmode &= 451 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 452 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 453 454 rxmode |= 455 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 456 457 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 458 if (ifp->if_flags & IFF_PROMISC) 459 rxmode |= AXE_RXCMD_PROMISC; 460 goto allmulti; 461 } 462 463 /* Now program new ones */ 464 ETHER_LOCK(ec); 465 ETHER_FIRST_MULTI(step, ec, enm); 466 while (enm != NULL) { 467 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 468 ETHER_ADDR_LEN) != 0) { 469 ETHER_UNLOCK(ec); 470 goto allmulti; 471 } 472 473 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 474 hashtbl[h >> 3] |= 1U << (h & 7); 475 ETHER_NEXT_MULTI(step, enm); 476 } 477 ETHER_UNLOCK(ec); 478 ifp->if_flags &= ~IFF_ALLMULTI; 479 rxmode |= AXE_RXCMD_MULTICAST; 480 481 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 482 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 483 return; 484 485 allmulti: 486 ifp->if_flags |= IFF_ALLMULTI; 487 rxmode |= AXE_RXCMD_ALLMULTI; 488 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 489 } 490 491 static void 492 axe_setiff(struct usbnet *un) 493 { 494 usbnet_lock_mii(un); 495 axe_setiff_locked(un); 496 usbnet_unlock_mii(un); 497 } 498 499 static void 500 axe_ax_init(struct usbnet *un) 501 { 502 struct axe_softc * const sc = usbnet_softc(un); 503 504 int cmd = AXE_178_CMD_READ_NODEID; 505 506 if (un->un_flags & AX178) { 507 axe_ax88178_init(sc); 508 } else if (un->un_flags & AX772) { 509 axe_ax88772_init(sc); 510 } else if (un->un_flags & AX772A) { 511 axe_ax88772a_init(sc); 512 } else if (un->un_flags & AX772B) { 513 axe_ax88772b_init(sc); 514 return; 515 } else { 516 cmd = AXE_172_CMD_READ_NODEID; 517 } 518 519 if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) { 520 aprint_error_dev(un->un_dev, 521 "failed to read ethernet address\n"); 522 } 523 } 524 525 526 static void 527 axe_reset(struct usbnet *un) 528 { 529 530 usbnet_isowned_mii(un); 531 532 if (usbnet_isdying(un)) 533 return; 534 535 /* 536 * softnet_lock can be taken when NET_MPAFE is not defined when calling 537 * if_addr_init -> if_init. This doesn't mix well with the 538 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 539 * can fire during the wait and attempt to take softnet_lock and then 540 * block the softclk thread meaning the wait never ends. 541 */ 542 #ifndef NET_MPSAFE 543 /* XXX What to reset? */ 544 545 /* Wait a little while for the chip to get its brains in order. */ 546 DELAY(1000); 547 #else 548 axe_ax_init(un); 549 #endif 550 } 551 552 static int 553 axe_get_phyno(struct axe_softc *sc, int sel) 554 { 555 int phyno; 556 557 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 558 case PHY_TYPE_100_HOME: 559 /* FALLTHROUGH */ 560 case PHY_TYPE_GIG: 561 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 562 break; 563 case PHY_TYPE_SPECIAL: 564 /* FALLTHROUGH */ 565 case PHY_TYPE_RSVD: 566 /* FALLTHROUGH */ 567 case PHY_TYPE_NON_SUP: 568 /* FALLTHROUGH */ 569 default: 570 phyno = -1; 571 break; 572 } 573 574 return phyno; 575 } 576 577 #define AXE_GPIO_WRITE(x, y) do { \ 578 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 579 usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \ 580 } while (0) 581 582 static void 583 axe_ax88178_init(struct axe_softc *sc) 584 { 585 AXEHIST_FUNC(); AXEHIST_CALLED(); 586 struct usbnet * const un = &sc->axe_un; 587 int gpio0, ledmode, phymode; 588 uint16_t eeprom, val; 589 590 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 591 /* XXX magic */ 592 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 593 eeprom = 0xffff; 594 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 595 596 eeprom = le16toh(eeprom); 597 598 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 599 600 /* if EEPROM is invalid we have to use to GPIO0 */ 601 if (eeprom == 0xffff) { 602 phymode = AXE_PHY_MODE_MARVELL; 603 gpio0 = 1; 604 ledmode = 0; 605 } else { 606 phymode = eeprom & 0x7f; 607 gpio0 = (eeprom & 0x80) ? 0 : 1; 608 ledmode = eeprom >> 8; 609 } 610 611 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 612 613 /* Program GPIOs depending on PHY hardware. */ 614 switch (phymode) { 615 case AXE_PHY_MODE_MARVELL: 616 if (gpio0 == 1) { 617 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 618 hz / 32); 619 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 620 hz / 32); 621 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 622 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 623 hz / 32); 624 } else { 625 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 626 AXE_GPIO1_EN, hz / 3); 627 if (ledmode == 1) { 628 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 629 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 630 hz / 3); 631 } else { 632 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 633 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 634 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 635 AXE_GPIO2_EN, hz / 4); 636 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 637 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 638 } 639 } 640 break; 641 case AXE_PHY_MODE_CICADA: 642 case AXE_PHY_MODE_CICADA_V2: 643 case AXE_PHY_MODE_CICADA_V2_ASIX: 644 if (gpio0 == 1) 645 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 646 AXE_GPIO0_EN, hz / 32); 647 else 648 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 649 AXE_GPIO1_EN, hz / 32); 650 break; 651 case AXE_PHY_MODE_AGERE: 652 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 653 AXE_GPIO1_EN, hz / 32); 654 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 655 AXE_GPIO2_EN, hz / 32); 656 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 657 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 658 AXE_GPIO2_EN, hz / 32); 659 break; 660 case AXE_PHY_MODE_REALTEK_8211CL: 661 case AXE_PHY_MODE_REALTEK_8211BN: 662 case AXE_PHY_MODE_REALTEK_8251CL: 663 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 664 AXE_GPIO1 | AXE_GPIO1_EN; 665 AXE_GPIO_WRITE(val, hz / 32); 666 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 667 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 668 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 669 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 670 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005); 671 axe_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000); 672 axe_mii_read_reg(un, un->un_phyno, 0x0001, &val); 673 axe_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080); 674 axe_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000); 675 } 676 break; 677 default: 678 /* Unknown PHY model or no need to program GPIOs. */ 679 break; 680 } 681 682 /* soft reset */ 683 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 684 usbd_delay_ms(un->un_udev, 150); 685 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 686 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 687 usbd_delay_ms(un->un_udev, 150); 688 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 689 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 690 usbd_delay_ms(un->un_udev, 10); 691 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 692 } 693 694 static void 695 axe_ax88772_init(struct axe_softc *sc) 696 { 697 AXEHIST_FUNC(); AXEHIST_CALLED(); 698 struct usbnet * const un = &sc->axe_un; 699 700 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 701 usbd_delay_ms(un->un_udev, 40); 702 703 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 704 /* ask for the embedded PHY */ 705 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 706 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 707 usbd_delay_ms(un->un_udev, 10); 708 709 /* power down and reset state, pin reset state */ 710 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 711 usbd_delay_ms(un->un_udev, 60); 712 713 /* power down/reset state, pin operating state */ 714 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 715 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 716 usbd_delay_ms(un->un_udev, 150); 717 718 /* power up, reset */ 719 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 720 721 /* power up, operating */ 722 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 723 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 724 } else { 725 /* ask for external PHY */ 726 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 727 NULL); 728 usbd_delay_ms(un->un_udev, 10); 729 730 /* power down internal PHY */ 731 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 732 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 733 } 734 735 usbd_delay_ms(un->un_udev, 150); 736 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 737 } 738 739 static void 740 axe_ax88772_phywake(struct axe_softc *sc) 741 { 742 AXEHIST_FUNC(); AXEHIST_CALLED(); 743 struct usbnet * const un = &sc->axe_un; 744 745 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 746 /* Manually select internal(embedded) PHY - MAC mode. */ 747 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 748 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 749 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 750 } else { 751 /* 752 * Manually select external PHY - MAC mode. 753 * Reverse MII/RMII is for AX88772A PHY mode. 754 */ 755 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 756 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 757 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 758 } 759 760 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 761 AXE_SW_RESET_IPRL, NULL); 762 763 /* T1 = min 500ns everywhere */ 764 usbd_delay_ms(un->un_udev, 150); 765 766 /* Take PHY out of power down. */ 767 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 768 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 769 } else { 770 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 771 } 772 773 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 774 usbd_delay_ms(un->un_udev, 600); 775 776 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 777 778 /* T3 = 500ns everywhere */ 779 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 780 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 781 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 782 } 783 784 static void 785 axe_ax88772a_init(struct axe_softc *sc) 786 { 787 AXEHIST_FUNC(); AXEHIST_CALLED(); 788 789 /* Reload EEPROM. */ 790 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 791 axe_ax88772_phywake(sc); 792 /* Stop MAC. */ 793 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 794 } 795 796 static void 797 axe_ax88772b_init(struct axe_softc *sc) 798 { 799 AXEHIST_FUNC(); AXEHIST_CALLED(); 800 struct usbnet * const un = &sc->axe_un; 801 uint16_t eeprom; 802 int i; 803 804 /* Reload EEPROM. */ 805 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 806 807 /* 808 * Save PHY power saving configuration(high byte) and 809 * clear EEPROM checksum value(low byte). 810 */ 811 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 812 &eeprom)) { 813 aprint_error_dev(un->un_dev, "failed to read eeprom\n"); 814 return; 815 } 816 817 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 818 819 /* 820 * Auto-loaded default station address from internal ROM is 821 * 00:00:00:00:00:00 such that an explicit access to EEPROM 822 * is required to get real station address. 823 */ 824 uint8_t *eaddr = un->un_eaddr; 825 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 826 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 827 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 828 aprint_error_dev(un->un_dev, 829 "failed to read eeprom\n"); 830 eeprom = 0; 831 } 832 eeprom = le16toh(eeprom); 833 *eaddr++ = (uint8_t)(eeprom & 0xFF); 834 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 835 } 836 /* Wakeup PHY. */ 837 axe_ax88772_phywake(sc); 838 /* Stop MAC. */ 839 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 840 } 841 842 #undef AXE_GPIO_WRITE 843 844 /* 845 * Probe for a AX88172 chip. 846 */ 847 int 848 axe_match(device_t parent, cfdata_t match, void *aux) 849 { 850 struct usb_attach_arg *uaa = aux; 851 852 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 853 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 854 } 855 856 /* 857 * Attach the interface. Allocate softc structures, do ifmedia 858 * setup and ethernet/BPF attach. 859 */ 860 void 861 axe_attach(device_t parent, device_t self, void *aux) 862 { 863 AXEHIST_FUNC(); AXEHIST_CALLED(); 864 struct axe_softc *sc = device_private(self); 865 struct usbnet * const un = &sc->axe_un; 866 struct usb_attach_arg *uaa = aux; 867 struct usbd_device *dev = uaa->uaa_device; 868 usbd_status err; 869 usb_interface_descriptor_t *id; 870 usb_endpoint_descriptor_t *ed; 871 char *devinfop; 872 unsigned bufsz; 873 int i; 874 875 KASSERT((void *)sc == un); 876 877 aprint_naive("\n"); 878 aprint_normal("\n"); 879 devinfop = usbd_devinfo_alloc(dev, 0); 880 aprint_normal_dev(self, "%s\n", devinfop); 881 usbd_devinfo_free(devinfop); 882 883 un->un_dev = self; 884 un->un_udev = dev; 885 un->un_sc = sc; 886 un->un_ops = &axe_ops; 887 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 888 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 889 un->un_rx_list_cnt = AXE_RX_LIST_CNT; 890 un->un_tx_list_cnt = AXE_TX_LIST_CNT; 891 892 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 893 if (err) { 894 aprint_error_dev(self, "failed to set configuration" 895 ", err=%s\n", usbd_errstr(err)); 896 return; 897 } 898 899 un->un_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 900 901 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface); 902 if (err) { 903 aprint_error_dev(self, "getting interface handle failed\n"); 904 return; 905 } 906 907 id = usbd_get_interface_descriptor(un->un_iface); 908 909 /* decide on what our bufsize will be */ 910 if (AXE_IS_178_FAMILY(un)) 911 bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 912 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 913 else 914 bufsz = AXE_172_BUFSZ; 915 un->un_rx_bufsz = un->un_tx_bufsz = bufsz; 916 917 un->un_ed[USBNET_ENDPT_RX] = 0; 918 un->un_ed[USBNET_ENDPT_TX] = 0; 919 un->un_ed[USBNET_ENDPT_INTR] = 0; 920 921 /* Find endpoints. */ 922 for (i = 0; i < id->bNumEndpoints; i++) { 923 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 924 if (ed == NULL) { 925 aprint_error_dev(self, "couldn't get ep %d\n", i); 926 return; 927 } 928 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 929 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 930 931 if (dir == UE_DIR_IN && xt == UE_BULK && 932 un->un_ed[USBNET_ENDPT_RX] == 0) { 933 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 934 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 935 un->un_ed[USBNET_ENDPT_TX] == 0) { 936 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 937 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 938 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 939 } 940 } 941 942 /* Set these up now for axe_cmd(). */ 943 usbnet_attach(un, "axedet"); 944 945 /* We need the PHYID for init dance in some cases */ 946 usbnet_lock_mii(un); 947 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 948 aprint_error_dev(self, "failed to read phyaddrs\n"); 949 950 return; 951 } 952 953 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 954 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 955 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 956 if (un->un_phyno == -1) 957 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 958 if (un->un_phyno == -1) { 959 DPRINTF(" no valid PHY address found, assuming PHY address 0", 960 0, 0, 0, 0); 961 un->un_phyno = 0; 962 } 963 964 /* Initialize controller and get station address. */ 965 966 axe_ax_init(un); 967 968 /* 969 * Fetch IPG values. 970 */ 971 if (un->un_flags & (AX772A | AX772B)) { 972 /* Set IPG values. */ 973 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 974 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 975 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 976 } else { 977 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 978 aprint_error_dev(self, "failed to read ipg\n"); 979 usbnet_unlock_mii(un); 980 return; 981 } 982 } 983 984 usbnet_unlock_mii(un); 985 986 if (AXE_IS_178_FAMILY(un)) 987 usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU; 988 if (un->un_flags & AX772B) { 989 struct ifnet *ifp = usbnet_ifp(un); 990 991 ifp->if_capabilities = 992 IFCAP_CSUM_IPv4_Rx | 993 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 994 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 995 /* 996 * Checksum offloading of AX88772B also works with VLAN 997 * tagged frames but there is no way to take advantage 998 * of the feature because vlan(4) assumes 999 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1000 * support checksum offloading with VLAN. VLAN hardware 1001 * tagging support of AX88772B is very limited so it's 1002 * not possible to announce IFCAP_VLAN_HWTAGGING. 1003 */ 1004 } 1005 u_int adv_pause; 1006 if (un->un_flags & (AX772A | AX772B | AX178)) 1007 adv_pause = MIIF_DOPAUSE; 1008 else 1009 adv_pause = 0; 1010 adv_pause = 0; 1011 1012 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 1013 0, adv_pause); 1014 } 1015 1016 static void 1017 axe_rx_loop(struct usbnet * un, struct usbnet_chain *c, uint32_t total_len) 1018 { 1019 AXEHIST_FUNC(); AXEHIST_CALLED(); 1020 struct axe_softc * const sc = usbnet_softc(un); 1021 struct ifnet *ifp = usbnet_ifp(un); 1022 uint8_t *buf = c->unc_buf; 1023 1024 do { 1025 u_int pktlen = 0; 1026 u_int rxlen = 0; 1027 int flags = 0; 1028 1029 if ((un->un_flags & AXSTD_FRAME) != 0) { 1030 struct axe_sframe_hdr hdr; 1031 1032 if (total_len < sizeof(hdr)) { 1033 ifp->if_ierrors++; 1034 break; 1035 } 1036 1037 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1038 /* 1039 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1040 * For some architectures, __builtin_memcpy() of 1041 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1042 * at onece, which results in alignment error. 1043 */ 1044 hdr.len = *(uint16_t *)buf; 1045 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1046 #else 1047 memcpy(&hdr, buf, sizeof(hdr)); 1048 #endif 1049 1050 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1051 total_len, 1052 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1053 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1054 1055 total_len -= sizeof(hdr); 1056 buf += sizeof(hdr); 1057 1058 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1059 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1060 AXE_RH1M_RXLEN_MASK) { 1061 ifp->if_ierrors++; 1062 break; 1063 } 1064 1065 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1066 if (total_len < rxlen) { 1067 pktlen = total_len; 1068 total_len = 0; 1069 } else { 1070 pktlen = rxlen; 1071 rxlen = roundup2(rxlen, 2); 1072 total_len -= rxlen; 1073 } 1074 1075 } else if ((un->un_flags & AXCSUM_FRAME) != 0) { 1076 struct axe_csum_hdr csum_hdr; 1077 1078 if (total_len < sizeof(csum_hdr)) { 1079 ifp->if_ierrors++; 1080 break; 1081 } 1082 1083 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1084 1085 csum_hdr.len = le16toh(csum_hdr.len); 1086 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1087 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1088 1089 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1090 " cstatus %#jx", total_len, 1091 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1092 1093 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1094 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1095 sc->sc_lenmask) { 1096 /* we lost sync */ 1097 ifp->if_ierrors++; 1098 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1099 "err", 1100 AXE_CSUM_RXBYTES(csum_hdr.len), 1101 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1102 sc->sc_lenmask, 0); 1103 break; 1104 } 1105 /* 1106 * Get total transferred frame length including 1107 * checksum header. The length should be multiple 1108 * of 4. 1109 */ 1110 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1111 u_int len = sizeof(csum_hdr) + pktlen; 1112 len = (len + 3) & ~3; 1113 if (total_len < len) { 1114 DPRINTFN(20, "total_len %#jx < len %#jx", 1115 total_len, len, 0, 0); 1116 /* invalid length */ 1117 ifp->if_ierrors++; 1118 break; 1119 } 1120 buf += sizeof(csum_hdr); 1121 1122 const uint16_t cstatus = csum_hdr.cstatus; 1123 1124 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1125 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1126 flags |= M_CSUM_TCP_UDP_BAD; 1127 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1128 flags |= M_CSUM_IPv4_BAD; 1129 1130 const uint16_t l4type = 1131 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1132 1133 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1134 flags |= M_CSUM_TCPv4; 1135 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1136 flags |= M_CSUM_UDPv4; 1137 } 1138 if (total_len < len) { 1139 pktlen = total_len; 1140 total_len = 0; 1141 } else { 1142 total_len -= len; 1143 rxlen = len - sizeof(csum_hdr); 1144 } 1145 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1146 " rxlen %#jx", total_len, len, pktlen, rxlen); 1147 } else { /* AX172 */ 1148 pktlen = rxlen = total_len; 1149 total_len = 0; 1150 } 1151 1152 usbnet_enqueue(un, buf, pktlen, flags, 0, 0); 1153 buf += rxlen; 1154 1155 } while (total_len > 0); 1156 1157 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1158 } 1159 1160 static unsigned 1161 axe_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1162 { 1163 AXEHIST_FUNC(); AXEHIST_CALLED(); 1164 struct axe_sframe_hdr hdr, tlr; 1165 size_t hdr_len = 0, tlr_len = 0; 1166 int length, boundary; 1167 1168 usbnet_isowned_tx(un); 1169 1170 if (AXE_IS_178_FAMILY(un)) { 1171 /* 1172 * Copy the mbuf data into a contiguous buffer, leaving two 1173 * bytes at the beginning to hold the frame length. 1174 */ 1175 boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1176 1177 hdr.len = htole16(m->m_pkthdr.len); 1178 hdr.ilen = ~hdr.len; 1179 hdr_len = sizeof(hdr); 1180 1181 length = hdr_len + m->m_pkthdr.len; 1182 1183 if ((length % boundary) == 0) { 1184 tlr.len = 0x0000; 1185 tlr.ilen = 0xffff; 1186 tlr_len = sizeof(tlr); 1187 } 1188 DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx", 1189 length, m->m_pkthdr.len, sizeof(hdr), 0); 1190 } 1191 1192 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - hdr_len - tlr_len) 1193 return 0; 1194 length = hdr_len + m->m_pkthdr.len + tlr_len; 1195 1196 if (hdr_len) 1197 memcpy(c->unc_buf, &hdr, hdr_len); 1198 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + hdr_len); 1199 if (tlr_len) 1200 memcpy(c->unc_buf + length, &tlr, tlr_len); 1201 1202 return length; 1203 } 1204 1205 static void 1206 axe_csum_cfg(struct axe_softc *sc) 1207 { 1208 struct usbnet * const un = &sc->axe_un; 1209 struct ifnet * const ifp = usbnet_ifp(un); 1210 uint16_t csum1, csum2; 1211 1212 if ((un->un_flags & AX772B) != 0) { 1213 csum1 = 0; 1214 csum2 = 0; 1215 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1216 csum1 |= AXE_TXCSUM_IP; 1217 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1218 csum1 |= AXE_TXCSUM_TCP; 1219 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1220 csum1 |= AXE_TXCSUM_UDP; 1221 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1222 csum1 |= AXE_TXCSUM_TCPV6; 1223 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1224 csum1 |= AXE_TXCSUM_UDPV6; 1225 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1226 csum1 = 0; 1227 csum2 = 0; 1228 1229 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1230 csum1 |= AXE_RXCSUM_IP; 1231 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1232 csum1 |= AXE_RXCSUM_TCP; 1233 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1234 csum1 |= AXE_RXCSUM_UDP; 1235 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1236 csum1 |= AXE_RXCSUM_TCPV6; 1237 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1238 csum1 |= AXE_RXCSUM_UDPV6; 1239 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1240 } 1241 } 1242 1243 static int 1244 axe_init_locked(struct ifnet *ifp) 1245 { 1246 AXEHIST_FUNC(); AXEHIST_CALLED(); 1247 struct usbnet * const un = ifp->if_softc; 1248 struct axe_softc * const sc = usbnet_softc(un); 1249 int rxmode; 1250 1251 usbnet_isowned(un); 1252 1253 if (usbnet_isdying(un)) 1254 return EIO; 1255 1256 /* Cancel pending I/O */ 1257 usbnet_stop(un, ifp, 1); 1258 1259 usbnet_lock_mii_un_locked(un); 1260 1261 /* Reset the ethernet interface. */ 1262 axe_reset(un); 1263 1264 #if 0 1265 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1266 AX_GPIO_GPO2EN, 5, in_pm); 1267 #endif 1268 /* Set MAC address and transmitter IPG values. */ 1269 if (AXE_IS_178_FAMILY(un)) { 1270 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1271 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1272 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1273 } else { 1274 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1275 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1276 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1277 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1278 } 1279 if (AXE_IS_178_FAMILY(un)) { 1280 un->un_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1281 if ((un->un_flags & AX772B) != 0 && 1282 (ifp->if_capenable & AX_RXCSUM) != 0) { 1283 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1284 un->un_flags |= AXCSUM_FRAME; 1285 } else { 1286 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1287 un->un_flags |= AXSTD_FRAME; 1288 } 1289 } 1290 1291 /* Configure TX/RX checksum offloading. */ 1292 axe_csum_cfg(sc); 1293 1294 if (un->un_flags & AX772B) { 1295 /* AX88772B uses different maximum frame burst configuration. */ 1296 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1297 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1298 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1299 } 1300 /* Enable receiver, set RX mode */ 1301 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1302 if (AXE_IS_178_FAMILY(un)) { 1303 if (un->un_flags & AX772B) { 1304 /* 1305 * Select RX header format type 1. Aligning IP 1306 * header on 4 byte boundary is not needed when 1307 * checksum offloading feature is not used 1308 * because we always copy the received frame in 1309 * RX handler. When RX checksum offloading is 1310 * active, aligning IP header is required to 1311 * reflect actual frame length including RX 1312 * header size. 1313 */ 1314 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1315 if (un->un_flags & AXCSUM_FRAME) 1316 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1317 } else { 1318 /* 1319 * Default Rx buffer size is too small to get 1320 * maximum performance. 1321 */ 1322 #if 0 1323 if (un->un_udev->ud_speed == USB_SPEED_HIGH) { 1324 /* Largest possible USB buffer size for AX88178 */ 1325 } 1326 #endif 1327 rxmode |= AXE_178_RXCMD_MFB_16384; 1328 } 1329 } else { 1330 rxmode |= AXE_172_RXCMD_UNICAST; 1331 } 1332 1333 1334 /* If we want promiscuous mode, set the allframes bit. */ 1335 if (ifp->if_flags & IFF_PROMISC) 1336 rxmode |= AXE_RXCMD_PROMISC; 1337 1338 if (ifp->if_flags & IFF_BROADCAST) 1339 rxmode |= AXE_RXCMD_BROADCAST; 1340 1341 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1342 1343 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1344 1345 /* Load the multicast filter. */ 1346 axe_setiff_locked(un); 1347 1348 usbnet_unlock_mii_un_locked(un); 1349 1350 return usbnet_init_rx_tx(un); 1351 } 1352 1353 static int 1354 axe_init(struct ifnet *ifp) 1355 { 1356 struct usbnet * const un = ifp->if_softc; 1357 1358 usbnet_lock(un); 1359 int ret = axe_init_locked(ifp); 1360 usbnet_unlock(un); 1361 1362 return ret; 1363 } 1364 1365 static int 1366 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1367 { 1368 struct usbnet * const un = ifp->if_softc; 1369 1370 switch (cmd) { 1371 case SIOCADDMULTI: 1372 case SIOCDELMULTI: 1373 axe_setiff(un); 1374 break; 1375 default: 1376 break; 1377 } 1378 1379 return 0; 1380 } 1381 1382 static void 1383 axe_stop(struct ifnet *ifp, int disable) 1384 { 1385 struct usbnet * const un = ifp->if_softc; 1386 1387 usbnet_lock_mii_un_locked(un); 1388 axe_reset(un); 1389 usbnet_unlock_mii_un_locked(un); 1390 } 1391 1392 #ifdef _MODULE 1393 #include "ioconf.c" 1394 #endif 1395 1396 USBNET_MODULE(axe) 1397
Indexes created Wed Sep 24 22:09:59 GMT 2025