if_axe.c revision 1.130
1 /* $NetBSD: if_axe.c,v 1.130 2020/03/15 23:04:50 thorpej Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.130 2020/03/15 23:04:50 thorpej Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_usb.h" 94 #include "opt_net_mpsafe.h" 95 #endif 96 97 #include <sys/param.h> 98 99 #include <dev/usb/usbnet.h> 100 #include <dev/usb/usbhist.h> 101 #include <dev/usb/if_axereg.h> 102 103 struct axe_type { 104 struct usb_devno axe_dev; 105 uint16_t axe_flags; 106 }; 107 108 struct axe_softc { 109 struct usbnet axe_un; 110 111 /* usbnet:un_flags values */ 112 #define AX178 __BIT(0) /* AX88178 */ 113 #define AX772 __BIT(1) /* AX88772 */ 114 #define AX772A __BIT(2) /* AX88772A */ 115 #define AX772B __BIT(3) /* AX88772B */ 116 #define AXSTD_FRAME __BIT(12) 117 #define AXCSUM_FRAME __BIT(13) 118 119 uint8_t axe_ipgs[3]; 120 uint8_t axe_phyaddrs[2]; 121 uint16_t sc_pwrcfg; 122 uint16_t sc_lenmask; 123 124 }; 125 126 #define AXE_IS_178_FAMILY(un) \ 127 ((un)->un_flags & (AX178 | AX772 | AX772A | AX772B)) 128 129 #define AXE_IS_772(un) \ 130 ((un)->un_flags & (AX772 | AX772A | AX772B)) 131 132 #define AXE_IS_172(un) (AXE_IS_178_FAMILY(un) == 0) 133 134 #define AX_RXCSUM \ 135 (IFCAP_CSUM_IPv4_Rx | \ 136 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 137 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 138 139 #define AX_TXCSUM \ 140 (IFCAP_CSUM_IPv4_Tx | \ 141 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 142 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 143 144 /* 145 * AXE_178_MAX_FRAME_BURST 146 * max frame burst size for Ax88178 and Ax88772 147 * 0 2048 bytes 148 * 1 4096 bytes 149 * 2 8192 bytes 150 * 3 16384 bytes 151 * use the largest your system can handle without USB stalling. 152 * 153 * NB: 88772 parts appear to generate lots of input errors with 154 * a 2K rx buffer and 8K is only slightly faster than 4K on an 155 * EHCI port on a T42 so change at your own risk. 156 */ 157 #define AXE_178_MAX_FRAME_BURST 1 158 159 160 #ifdef USB_DEBUG 161 #ifndef AXE_DEBUG 162 #define axedebug 0 163 #else 164 static int axedebug = 0; 165 166 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 167 { 168 int err; 169 const struct sysctlnode *rnode; 170 const struct sysctlnode *cnode; 171 172 err = sysctl_createv(clog, 0, NULL, &rnode, 173 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 174 SYSCTL_DESCR("axe global controls"), 175 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 176 177 if (err) 178 goto fail; 179 180 /* control debugging printfs */ 181 err = sysctl_createv(clog, 0, &rnode, &cnode, 182 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 183 "debug", SYSCTL_DESCR("Enable debugging output"), 184 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 185 if (err) 186 goto fail; 187 188 return; 189 fail: 190 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 191 } 192 193 #endif /* AXE_DEBUG */ 194 #endif /* USB_DEBUG */ 195 196 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 197 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 198 #define AXEHIST_FUNC() USBHIST_FUNC() 199 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 200 201 /* 202 * Various supported device vendors/products. 203 */ 204 static const struct axe_type axe_devs[] = { 205 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000 }, 0 }, 206 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2 }, 0 }, 207 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 208 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172 }, 0 }, 209 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772 }, AX772 }, 210 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A }, AX772 }, 211 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B }, AX772B }, 212 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1 }, AX772B }, 213 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178 }, AX178 }, 214 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T }, 0 }, 215 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 216 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR }, 0}, 217 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2 }, AX772A }, 218 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0 }, 219 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100 }, 0 }, 220 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 221 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 222 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 223 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E }, 0 }, 224 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 225 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1 }, 0 }, 226 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 227 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9 }, AX772B }, 228 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M }, 0 }, 229 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 230 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2 }, AX178 }, 231 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT }, AX178 }, 232 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX }, 0 }, 233 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A }, AX772 }, 234 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120 }, 0 }, 235 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 236 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 237 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029 }, 0 }, 238 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 239 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 240 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL }, 0 }, 241 }; 242 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 243 244 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 245 { 0x8000, 0x8001, 2048 }, 246 { 0x8100, 0x8147, 4096 }, 247 { 0x8200, 0x81EB, 6144 }, 248 { 0x8300, 0x83D7, 8192 }, 249 { 0x8400, 0x851E, 16384 }, 250 { 0x8500, 0x8666, 20480 }, 251 { 0x8600, 0x87AE, 24576 }, 252 { 0x8700, 0x8A3D, 32768 } 253 }; 254 255 static int axe_match(device_t, cfdata_t, void *); 256 static void axe_attach(device_t, device_t, void *); 257 258 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 259 axe_match, axe_attach, usbnet_detach, usbnet_activate); 260 261 static void axe_uno_stop(struct ifnet *, int); 262 static int axe_uno_ioctl(struct ifnet *, u_long, void *); 263 static int axe_uno_init(struct ifnet *); 264 static int axe_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 265 static int axe_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 266 static void axe_uno_mii_statchg(struct ifnet *); 267 static void axe_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 268 uint32_t); 269 static unsigned axe_uno_tx_prepare(struct usbnet *, struct mbuf *, 270 struct usbnet_chain *); 271 272 static void axe_ax88178_init(struct axe_softc *); 273 static void axe_ax88772_init(struct axe_softc *); 274 static void axe_ax88772a_init(struct axe_softc *); 275 static void axe_ax88772b_init(struct axe_softc *); 276 277 static const struct usbnet_ops axe_ops = { 278 .uno_stop = axe_uno_stop, 279 .uno_ioctl = axe_uno_ioctl, 280 .uno_read_reg = axe_uno_mii_read_reg, 281 .uno_write_reg = axe_uno_mii_write_reg, 282 .uno_statchg = axe_uno_mii_statchg, 283 .uno_tx_prepare = axe_uno_tx_prepare, 284 .uno_rx_loop = axe_uno_rx_loop, 285 .uno_init = axe_uno_init, 286 }; 287 288 static usbd_status 289 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 290 { 291 AXEHIST_FUNC(); AXEHIST_CALLED(); 292 struct usbnet * const un = &sc->axe_un; 293 usb_device_request_t req; 294 usbd_status err; 295 296 usbnet_isowned_core(un); 297 298 if (usbnet_isdying(un)) 299 return -1; 300 301 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 302 303 if (AXE_CMD_DIR(cmd)) 304 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 305 else 306 req.bmRequestType = UT_READ_VENDOR_DEVICE; 307 req.bRequest = AXE_CMD_CMD(cmd); 308 USETW(req.wValue, val); 309 USETW(req.wIndex, index); 310 USETW(req.wLength, AXE_CMD_LEN(cmd)); 311 312 err = usbd_do_request(un->un_udev, &req, buf); 313 if (err) 314 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 315 316 return err; 317 } 318 319 static int 320 axe_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 321 { 322 AXEHIST_FUNC(); AXEHIST_CALLED(); 323 struct axe_softc * const sc = usbnet_softc(un); 324 usbd_status err; 325 uint16_t data; 326 327 DPRINTFN(30, "phy %#jx reg %#jx\n", phy, reg, 0, 0); 328 329 if (un->un_phyno != phy) 330 return EINVAL; 331 332 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 333 334 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 335 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 336 337 if (err) { 338 aprint_error_dev(un->un_dev, "read PHY failed\n"); 339 return EIO; 340 } 341 342 *val = le16toh(data); 343 if (AXE_IS_772(un) && reg == MII_BMSR) { 344 /* 345 * BMSR of AX88772 indicates that it supports extended 346 * capability but the extended status register is 347 * reserved for embedded ethernet PHY. So clear the 348 * extended capability bit of BMSR. 349 */ 350 *val &= ~BMSR_EXTCAP; 351 } 352 353 DPRINTFN(30, "phy %#jx reg %#jx val %#jx", phy, reg, *val, 0); 354 355 return 0; 356 } 357 358 static int 359 axe_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 360 { 361 struct axe_softc * const sc = usbnet_softc(un); 362 usbd_status err; 363 uint16_t aval; 364 365 if (un->un_phyno != phy) 366 return EINVAL; 367 368 aval = htole16(val); 369 370 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 371 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval); 372 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 373 374 if (err) 375 return EIO; 376 return 0; 377 } 378 379 static void 380 axe_uno_mii_statchg(struct ifnet *ifp) 381 { 382 AXEHIST_FUNC(); AXEHIST_CALLED(); 383 384 struct usbnet * const un = ifp->if_softc; 385 struct axe_softc * const sc = usbnet_softc(un); 386 struct mii_data *mii = usbnet_mii(un); 387 int val, err; 388 389 if (usbnet_isdying(un)) 390 return; 391 392 val = 0; 393 if (AXE_IS_172(un)) { 394 if (mii->mii_media_active & IFM_FDX) 395 val |= AXE_MEDIA_FULL_DUPLEX; 396 } else { 397 if (mii->mii_media_active & IFM_FDX) { 398 val |= AXE_MEDIA_FULL_DUPLEX; 399 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 400 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 401 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 402 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 403 } 404 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 405 if (un->un_flags & AX178) 406 val |= AXE_178_MEDIA_ENCK; 407 switch (IFM_SUBTYPE(mii->mii_media_active)) { 408 case IFM_1000_T: 409 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 410 usbnet_set_link(un, true); 411 break; 412 case IFM_100_TX: 413 val |= AXE_178_MEDIA_100TX; 414 usbnet_set_link(un, true); 415 break; 416 case IFM_10_T: 417 usbnet_set_link(un, true); 418 break; 419 } 420 } 421 422 DPRINTF("val=%#jx", val, 0, 0, 0); 423 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 424 if (err) 425 aprint_error_dev(un->un_dev, "media change failed\n"); 426 } 427 428 static void 429 axe_setiff_locked(struct usbnet *un) 430 { 431 AXEHIST_FUNC(); AXEHIST_CALLED(); 432 struct axe_softc * const sc = usbnet_softc(un); 433 struct ifnet * const ifp = usbnet_ifp(un); 434 struct ethercom *ec = usbnet_ec(un); 435 struct ether_multi *enm; 436 struct ether_multistep step; 437 uint32_t h = 0; 438 uint16_t rxmode; 439 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 440 441 if (usbnet_isdying(un)) 442 return; 443 444 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 445 aprint_error_dev(un->un_dev, "can't read rxmode"); 446 return; 447 } 448 rxmode = le16toh(rxmode); 449 450 rxmode &= 451 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | AXE_RXCMD_MULTICAST); 452 453 if (ifp->if_flags & IFF_PROMISC) { 454 ifp->if_flags |= IFF_ALLMULTI; 455 goto allmulti; 456 } 457 ifp->if_flags &= ~IFF_ALLMULTI; 458 459 /* Now program new ones */ 460 ETHER_LOCK(ec); 461 ETHER_FIRST_MULTI(step, ec, enm); 462 while (enm != NULL) { 463 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 464 ETHER_ADDR_LEN) != 0) { 465 ETHER_UNLOCK(ec); 466 ifp->if_flags |= IFF_ALLMULTI; 467 goto allmulti; 468 } 469 470 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 471 hashtbl[h >> 3] |= 1U << (h & 7); 472 ETHER_NEXT_MULTI(step, enm); 473 } 474 ETHER_UNLOCK(ec); 475 476 rxmode |= AXE_RXCMD_MULTICAST; /* activate mcast hash filter */ 477 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 478 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 479 return; 480 481 allmulti: 482 if (ifp->if_flags & IFF_PROMISC) 483 rxmode |= AXE_RXCMD_PROMISC; /* run promisc. mode */ 484 rxmode |= AXE_RXCMD_ALLMULTI; /* accept all mcast frames */ 485 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 486 } 487 488 static void 489 axe_ax_init(struct usbnet *un) 490 { 491 struct axe_softc * const sc = usbnet_softc(un); 492 493 int cmd = AXE_178_CMD_READ_NODEID; 494 495 if (un->un_flags & AX178) { 496 axe_ax88178_init(sc); 497 } else if (un->un_flags & AX772) { 498 axe_ax88772_init(sc); 499 } else if (un->un_flags & AX772A) { 500 axe_ax88772a_init(sc); 501 } else if (un->un_flags & AX772B) { 502 axe_ax88772b_init(sc); 503 return; 504 } else { 505 cmd = AXE_172_CMD_READ_NODEID; 506 } 507 508 if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) { 509 aprint_error_dev(un->un_dev, 510 "failed to read ethernet address\n"); 511 } 512 } 513 514 515 static void 516 axe_reset(struct usbnet *un) 517 { 518 519 usbnet_isowned_core(un); 520 521 if (usbnet_isdying(un)) 522 return; 523 524 /* 525 * softnet_lock can be taken when NET_MPAFE is not defined when calling 526 * if_addr_init -> if_init. This doesn't mix well with the 527 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 528 * can fire during the wait and attempt to take softnet_lock and then 529 * block the softclk thread meaning the wait never ends. 530 */ 531 #ifndef NET_MPSAFE 532 /* XXX What to reset? */ 533 534 /* Wait a little while for the chip to get its brains in order. */ 535 DELAY(1000); 536 #else 537 axe_ax_init(un); 538 #endif 539 } 540 541 static int 542 axe_get_phyno(struct axe_softc *sc, int sel) 543 { 544 int phyno; 545 546 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 547 case PHY_TYPE_100_HOME: 548 /* FALLTHROUGH */ 549 case PHY_TYPE_GIG: 550 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 551 break; 552 case PHY_TYPE_SPECIAL: 553 /* FALLTHROUGH */ 554 case PHY_TYPE_RSVD: 555 /* FALLTHROUGH */ 556 case PHY_TYPE_NON_SUP: 557 /* FALLTHROUGH */ 558 default: 559 phyno = -1; 560 break; 561 } 562 563 return phyno; 564 } 565 566 #define AXE_GPIO_WRITE(x, y) do { \ 567 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 568 usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \ 569 } while (0) 570 571 static void 572 axe_ax88178_init(struct axe_softc *sc) 573 { 574 AXEHIST_FUNC(); AXEHIST_CALLED(); 575 struct usbnet * const un = &sc->axe_un; 576 int gpio0, ledmode, phymode; 577 uint16_t eeprom, val; 578 579 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 580 /* XXX magic */ 581 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 582 eeprom = 0xffff; 583 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 584 585 eeprom = le16toh(eeprom); 586 587 DPRINTF("EEPROM is %#jx", eeprom, 0, 0, 0); 588 589 /* if EEPROM is invalid we have to use to GPIO0 */ 590 if (eeprom == 0xffff) { 591 phymode = AXE_PHY_MODE_MARVELL; 592 gpio0 = 1; 593 ledmode = 0; 594 } else { 595 phymode = eeprom & 0x7f; 596 gpio0 = (eeprom & 0x80) ? 0 : 1; 597 ledmode = eeprom >> 8; 598 } 599 600 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 601 602 /* Program GPIOs depending on PHY hardware. */ 603 switch (phymode) { 604 case AXE_PHY_MODE_MARVELL: 605 if (gpio0 == 1) { 606 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 607 hz / 32); 608 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 609 hz / 32); 610 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 611 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 612 hz / 32); 613 } else { 614 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 615 AXE_GPIO1_EN, hz / 3); 616 if (ledmode == 1) { 617 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 618 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 619 hz / 3); 620 } else { 621 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 622 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 623 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 624 AXE_GPIO2_EN, hz / 4); 625 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 626 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 627 } 628 } 629 break; 630 case AXE_PHY_MODE_CICADA: 631 case AXE_PHY_MODE_CICADA_V2: 632 case AXE_PHY_MODE_CICADA_V2_ASIX: 633 if (gpio0 == 1) 634 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 635 AXE_GPIO0_EN, hz / 32); 636 else 637 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 638 AXE_GPIO1_EN, hz / 32); 639 break; 640 case AXE_PHY_MODE_AGERE: 641 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 642 AXE_GPIO1_EN, hz / 32); 643 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 644 AXE_GPIO2_EN, hz / 32); 645 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 646 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 647 AXE_GPIO2_EN, hz / 32); 648 break; 649 case AXE_PHY_MODE_REALTEK_8211CL: 650 case AXE_PHY_MODE_REALTEK_8211BN: 651 case AXE_PHY_MODE_REALTEK_8251CL: 652 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 653 AXE_GPIO1 | AXE_GPIO1_EN; 654 AXE_GPIO_WRITE(val, hz / 32); 655 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 656 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 657 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 658 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 659 axe_uno_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005); 660 axe_uno_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000); 661 axe_uno_mii_read_reg(un, un->un_phyno, 0x0001, &val); 662 axe_uno_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080); 663 axe_uno_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000); 664 } 665 break; 666 default: 667 /* Unknown PHY model or no need to program GPIOs. */ 668 break; 669 } 670 671 /* soft reset */ 672 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 673 usbd_delay_ms(un->un_udev, 150); 674 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 675 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 676 usbd_delay_ms(un->un_udev, 150); 677 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 678 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 679 usbd_delay_ms(un->un_udev, 10); 680 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 681 } 682 683 static void 684 axe_ax88772_init(struct axe_softc *sc) 685 { 686 AXEHIST_FUNC(); AXEHIST_CALLED(); 687 struct usbnet * const un = &sc->axe_un; 688 689 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 690 usbd_delay_ms(un->un_udev, 40); 691 692 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 693 /* ask for the embedded PHY */ 694 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 695 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 696 usbd_delay_ms(un->un_udev, 10); 697 698 /* power down and reset state, pin reset state */ 699 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 700 usbd_delay_ms(un->un_udev, 60); 701 702 /* power down/reset state, pin operating state */ 703 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 704 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 705 usbd_delay_ms(un->un_udev, 150); 706 707 /* power up, reset */ 708 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 709 710 /* power up, operating */ 711 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 712 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 713 } else { 714 /* ask for external PHY */ 715 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 716 NULL); 717 usbd_delay_ms(un->un_udev, 10); 718 719 /* power down internal PHY */ 720 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 721 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 722 } 723 724 usbd_delay_ms(un->un_udev, 150); 725 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 726 } 727 728 static void 729 axe_ax88772_phywake(struct axe_softc *sc) 730 { 731 AXEHIST_FUNC(); AXEHIST_CALLED(); 732 struct usbnet * const un = &sc->axe_un; 733 734 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 735 /* Manually select internal(embedded) PHY - MAC mode. */ 736 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 737 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 738 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 739 } else { 740 /* 741 * Manually select external PHY - MAC mode. 742 * Reverse MII/RMII is for AX88772A PHY mode. 743 */ 744 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 745 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 746 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 747 } 748 749 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 750 AXE_SW_RESET_IPRL, NULL); 751 752 /* T1 = min 500ns everywhere */ 753 usbd_delay_ms(un->un_udev, 150); 754 755 /* Take PHY out of power down. */ 756 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 757 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 758 } else { 759 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 760 } 761 762 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 763 usbd_delay_ms(un->un_udev, 600); 764 765 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 766 767 /* T3 = 500ns everywhere */ 768 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 769 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 770 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 771 } 772 773 static void 774 axe_ax88772a_init(struct axe_softc *sc) 775 { 776 AXEHIST_FUNC(); AXEHIST_CALLED(); 777 778 /* Reload EEPROM. */ 779 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 780 axe_ax88772_phywake(sc); 781 /* Stop MAC. */ 782 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 783 } 784 785 static void 786 axe_ax88772b_init(struct axe_softc *sc) 787 { 788 AXEHIST_FUNC(); AXEHIST_CALLED(); 789 struct usbnet * const un = &sc->axe_un; 790 uint16_t eeprom; 791 int i; 792 793 /* Reload EEPROM. */ 794 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 795 796 /* 797 * Save PHY power saving configuration(high byte) and 798 * clear EEPROM checksum value(low byte). 799 */ 800 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 801 &eeprom)) { 802 aprint_error_dev(un->un_dev, "failed to read eeprom\n"); 803 return; 804 } 805 806 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 807 808 /* 809 * Auto-loaded default station address from internal ROM is 810 * 00:00:00:00:00:00 such that an explicit access to EEPROM 811 * is required to get real station address. 812 */ 813 uint8_t *eaddr = un->un_eaddr; 814 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 815 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 816 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 817 aprint_error_dev(un->un_dev, 818 "failed to read eeprom\n"); 819 eeprom = 0; 820 } 821 eeprom = le16toh(eeprom); 822 *eaddr++ = (uint8_t)(eeprom & 0xFF); 823 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 824 } 825 /* Wakeup PHY. */ 826 axe_ax88772_phywake(sc); 827 /* Stop MAC. */ 828 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 829 } 830 831 #undef AXE_GPIO_WRITE 832 833 /* 834 * Probe for a AX88172 chip. 835 */ 836 static int 837 axe_match(device_t parent, cfdata_t match, void *aux) 838 { 839 struct usb_attach_arg *uaa = aux; 840 841 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 842 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 843 } 844 845 /* 846 * Attach the interface. Allocate softc structures, do ifmedia 847 * setup and ethernet/BPF attach. 848 */ 849 static void 850 axe_attach(device_t parent, device_t self, void *aux) 851 { 852 AXEHIST_FUNC(); AXEHIST_CALLED(); 853 USBNET_MII_DECL_DEFAULT(unm); 854 struct axe_softc *sc = device_private(self); 855 struct usbnet * const un = &sc->axe_un; 856 struct usb_attach_arg *uaa = aux; 857 struct usbd_device *dev = uaa->uaa_device; 858 usbd_status err; 859 usb_interface_descriptor_t *id; 860 usb_endpoint_descriptor_t *ed; 861 char *devinfop; 862 unsigned bufsz; 863 int i; 864 865 KASSERT((void *)sc == un); 866 867 aprint_naive("\n"); 868 aprint_normal("\n"); 869 devinfop = usbd_devinfo_alloc(dev, 0); 870 aprint_normal_dev(self, "%s\n", devinfop); 871 usbd_devinfo_free(devinfop); 872 873 un->un_dev = self; 874 un->un_udev = dev; 875 un->un_sc = sc; 876 un->un_ops = &axe_ops; 877 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 878 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 879 un->un_rx_list_cnt = AXE_RX_LIST_CNT; 880 un->un_tx_list_cnt = AXE_TX_LIST_CNT; 881 882 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 883 if (err) { 884 aprint_error_dev(self, "failed to set configuration" 885 ", err=%s\n", usbd_errstr(err)); 886 return; 887 } 888 889 un->un_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 890 891 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface); 892 if (err) { 893 aprint_error_dev(self, "getting interface handle failed\n"); 894 return; 895 } 896 897 id = usbd_get_interface_descriptor(un->un_iface); 898 899 /* decide on what our bufsize will be */ 900 if (AXE_IS_172(un)) 901 bufsz = AXE_172_BUFSZ; 902 else 903 bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 904 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 905 un->un_rx_bufsz = un->un_tx_bufsz = bufsz; 906 907 un->un_ed[USBNET_ENDPT_RX] = 0; 908 un->un_ed[USBNET_ENDPT_TX] = 0; 909 un->un_ed[USBNET_ENDPT_INTR] = 0; 910 911 /* Find endpoints. */ 912 for (i = 0; i < id->bNumEndpoints; i++) { 913 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 914 if (ed == NULL) { 915 aprint_error_dev(self, "couldn't get ep %d\n", i); 916 return; 917 } 918 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 919 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 920 921 if (dir == UE_DIR_IN && xt == UE_BULK && 922 un->un_ed[USBNET_ENDPT_RX] == 0) { 923 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 924 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 925 un->un_ed[USBNET_ENDPT_TX] == 0) { 926 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 927 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 928 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 929 } 930 } 931 932 /* Set these up now for axe_cmd(). */ 933 usbnet_attach(un, "axedet"); 934 935 /* We need the PHYID for init dance in some cases */ 936 usbnet_lock_core(un); 937 usbnet_busy(un); 938 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 939 aprint_error_dev(self, "failed to read phyaddrs\n"); 940 usbnet_unbusy(un); 941 usbnet_unlock_core(un); 942 return; 943 } 944 945 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 946 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 947 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 948 if (un->un_phyno == -1) 949 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 950 if (un->un_phyno == -1) { 951 DPRINTF(" no valid PHY address found, assuming PHY address 0", 952 0, 0, 0, 0); 953 un->un_phyno = 0; 954 } 955 956 /* Initialize controller and get station address. */ 957 958 axe_ax_init(un); 959 960 /* 961 * Fetch IPG values. 962 */ 963 if (un->un_flags & (AX772A | AX772B)) { 964 /* Set IPG values. */ 965 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 966 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 967 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 968 } else { 969 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 970 aprint_error_dev(self, "failed to read ipg\n"); 971 usbnet_unbusy(un); 972 usbnet_unlock_core(un); 973 return; 974 } 975 } 976 977 usbnet_unbusy(un); 978 usbnet_unlock_core(un); 979 980 if (!AXE_IS_172(un)) 981 usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU; 982 if (un->un_flags & AX772B) { 983 struct ifnet *ifp = usbnet_ifp(un); 984 985 ifp->if_capabilities = 986 IFCAP_CSUM_IPv4_Rx | 987 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 988 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 989 /* 990 * Checksum offloading of AX88772B also works with VLAN 991 * tagged frames but there is no way to take advantage 992 * of the feature because vlan(4) assumes 993 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 994 * support checksum offloading with VLAN. VLAN hardware 995 * tagging support of AX88772B is very limited so it's 996 * not possible to announce IFCAP_VLAN_HWTAGGING. 997 */ 998 } 999 if (un->un_flags & (AX772A | AX772B | AX178)) 1000 unm.un_mii_flags = MIIF_DOPAUSE; 1001 1002 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 1003 0, &unm); 1004 } 1005 1006 static void 1007 axe_uno_rx_loop(struct usbnet * un, struct usbnet_chain *c, uint32_t total_len) 1008 { 1009 AXEHIST_FUNC(); AXEHIST_CALLED(); 1010 struct axe_softc * const sc = usbnet_softc(un); 1011 struct ifnet *ifp = usbnet_ifp(un); 1012 uint8_t *buf = c->unc_buf; 1013 1014 do { 1015 u_int pktlen = 0; 1016 u_int rxlen = 0; 1017 int flags = 0; 1018 1019 if ((un->un_flags & AXSTD_FRAME) != 0) { 1020 struct axe_sframe_hdr hdr; 1021 1022 if (total_len < sizeof(hdr)) { 1023 if_statinc(ifp, if_ierrors); 1024 break; 1025 } 1026 1027 memcpy(&hdr, buf, sizeof(hdr)); 1028 1029 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx", 1030 total_len, 1031 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1032 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1033 1034 total_len -= sizeof(hdr); 1035 buf += sizeof(hdr); 1036 1037 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1038 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1039 AXE_RH1M_RXLEN_MASK) { 1040 if_statinc(ifp, if_ierrors); 1041 break; 1042 } 1043 1044 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1045 if (total_len < rxlen) { 1046 pktlen = total_len; 1047 total_len = 0; 1048 } else { 1049 pktlen = rxlen; 1050 rxlen = roundup2(rxlen, 2); 1051 total_len -= rxlen; 1052 } 1053 1054 } else if ((un->un_flags & AXCSUM_FRAME) != 0) { 1055 struct axe_csum_hdr csum_hdr; 1056 1057 if (total_len < sizeof(csum_hdr)) { 1058 if_statinc(ifp, if_ierrors); 1059 break; 1060 } 1061 1062 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1063 1064 csum_hdr.len = le16toh(csum_hdr.len); 1065 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1066 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1067 1068 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1069 " cstatus %#jx", total_len, 1070 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1071 1072 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1073 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1074 sc->sc_lenmask) { 1075 /* we lost sync */ 1076 if_statinc(ifp, if_ierrors); 1077 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1078 "err", 1079 AXE_CSUM_RXBYTES(csum_hdr.len), 1080 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1081 sc->sc_lenmask, 0); 1082 break; 1083 } 1084 /* 1085 * Get total transferred frame length including 1086 * checksum header. The length should be multiple 1087 * of 4. 1088 */ 1089 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1090 u_int len = sizeof(csum_hdr) + pktlen; 1091 len = (len + 3) & ~3; 1092 if (total_len < len) { 1093 DPRINTFN(20, "total_len %#jx < len %#jx", 1094 total_len, len, 0, 0); 1095 /* invalid length */ 1096 if_statinc(ifp, if_ierrors); 1097 break; 1098 } 1099 buf += sizeof(csum_hdr); 1100 1101 const uint16_t cstatus = csum_hdr.cstatus; 1102 1103 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1104 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1105 flags |= M_CSUM_TCP_UDP_BAD; 1106 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1107 flags |= M_CSUM_IPv4_BAD; 1108 1109 const uint16_t l4type = 1110 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1111 1112 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1113 flags |= M_CSUM_TCPv4; 1114 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1115 flags |= M_CSUM_UDPv4; 1116 } 1117 if (total_len < len) { 1118 pktlen = total_len; 1119 total_len = 0; 1120 } else { 1121 total_len -= len; 1122 rxlen = len - sizeof(csum_hdr); 1123 } 1124 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1125 " rxlen %#jx", total_len, len, pktlen, rxlen); 1126 } else { /* AX172 */ 1127 pktlen = rxlen = total_len; 1128 total_len = 0; 1129 } 1130 1131 usbnet_enqueue(un, buf, pktlen, flags, 0, 0); 1132 buf += rxlen; 1133 1134 } while (total_len > 0); 1135 1136 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1137 } 1138 1139 static unsigned 1140 axe_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1141 { 1142 AXEHIST_FUNC(); AXEHIST_CALLED(); 1143 struct axe_sframe_hdr hdr, tlr; 1144 size_t hdr_len = 0, tlr_len = 0; 1145 int length, boundary; 1146 1147 usbnet_isowned_tx(un); 1148 1149 if (!AXE_IS_172(un)) { 1150 /* 1151 * Copy the mbuf data into a contiguous buffer, leaving two 1152 * bytes at the beginning to hold the frame length. 1153 */ 1154 boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1155 1156 hdr.len = htole16(m->m_pkthdr.len); 1157 hdr.ilen = ~hdr.len; 1158 hdr_len = sizeof(hdr); 1159 1160 length = hdr_len + m->m_pkthdr.len; 1161 1162 if ((length % boundary) == 0) { 1163 tlr.len = 0x0000; 1164 tlr.ilen = 0xffff; 1165 tlr_len = sizeof(tlr); 1166 } 1167 DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx", 1168 length, m->m_pkthdr.len, sizeof(hdr), 0); 1169 } 1170 1171 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - hdr_len - tlr_len) 1172 return 0; 1173 length = hdr_len + m->m_pkthdr.len + tlr_len; 1174 1175 if (hdr_len) 1176 memcpy(c->unc_buf, &hdr, hdr_len); 1177 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + hdr_len); 1178 if (tlr_len) 1179 memcpy(c->unc_buf + length - tlr_len, &tlr, tlr_len); 1180 1181 return length; 1182 } 1183 1184 static void 1185 axe_csum_cfg(struct axe_softc *sc) 1186 { 1187 struct usbnet * const un = &sc->axe_un; 1188 struct ifnet * const ifp = usbnet_ifp(un); 1189 uint16_t csum1, csum2; 1190 1191 if ((un->un_flags & AX772B) != 0) { 1192 csum1 = 0; 1193 csum2 = 0; 1194 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1195 csum1 |= AXE_TXCSUM_IP; 1196 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1197 csum1 |= AXE_TXCSUM_TCP; 1198 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1199 csum1 |= AXE_TXCSUM_UDP; 1200 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1201 csum1 |= AXE_TXCSUM_TCPV6; 1202 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1203 csum1 |= AXE_TXCSUM_UDPV6; 1204 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1205 csum1 = 0; 1206 csum2 = 0; 1207 1208 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1209 csum1 |= AXE_RXCSUM_IP; 1210 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1211 csum1 |= AXE_RXCSUM_TCP; 1212 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1213 csum1 |= AXE_RXCSUM_UDP; 1214 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1215 csum1 |= AXE_RXCSUM_TCPV6; 1216 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1217 csum1 |= AXE_RXCSUM_UDPV6; 1218 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1219 } 1220 } 1221 1222 static int 1223 axe_init_locked(struct ifnet *ifp) 1224 { 1225 AXEHIST_FUNC(); AXEHIST_CALLED(); 1226 struct usbnet * const un = ifp->if_softc; 1227 struct axe_softc * const sc = usbnet_softc(un); 1228 int rxmode; 1229 1230 usbnet_isowned_core(un); 1231 1232 if (usbnet_isdying(un)) 1233 return EIO; 1234 1235 /* Cancel pending I/O */ 1236 usbnet_stop(un, ifp, 1); 1237 1238 /* Reset the ethernet interface. */ 1239 axe_reset(un); 1240 1241 #if 0 1242 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1243 AX_GPIO_GPO2EN, 5, in_pm); 1244 #endif 1245 /* Set MAC address and transmitter IPG values. */ 1246 if (AXE_IS_172(un)) { 1247 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1248 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1249 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1250 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1251 } else { 1252 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1253 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1254 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1255 1256 un->un_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1257 if ((un->un_flags & AX772B) != 0 && 1258 (ifp->if_capenable & AX_RXCSUM) != 0) { 1259 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1260 un->un_flags |= AXCSUM_FRAME; 1261 } else { 1262 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1263 un->un_flags |= AXSTD_FRAME; 1264 } 1265 } 1266 1267 /* Configure TX/RX checksum offloading. */ 1268 axe_csum_cfg(sc); 1269 1270 if (un->un_flags & AX772B) { 1271 /* AX88772B uses different maximum frame burst configuration. */ 1272 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1273 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1274 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1275 } 1276 /* Enable receiver, set RX mode */ 1277 rxmode = (AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1278 if (AXE_IS_172(un)) 1279 rxmode |= AXE_172_RXCMD_UNICAST; 1280 else { 1281 if (un->un_flags & AX772B) { 1282 /* 1283 * Select RX header format type 1. Aligning IP 1284 * header on 4 byte boundary is not needed when 1285 * checksum offloading feature is not used 1286 * because we always copy the received frame in 1287 * RX handler. When RX checksum offloading is 1288 * active, aligning IP header is required to 1289 * reflect actual frame length including RX 1290 * header size. 1291 */ 1292 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1293 if (un->un_flags & AXCSUM_FRAME) 1294 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1295 } else { 1296 /* 1297 * Default Rx buffer size is too small to get 1298 * maximum performance. 1299 */ 1300 #if 0 1301 if (un->un_udev->ud_speed == USB_SPEED_HIGH) { 1302 /* Largest possible USB buffer size for AX88178 */ 1303 } 1304 #endif 1305 rxmode |= AXE_178_RXCMD_MFB_16384; 1306 } 1307 } 1308 1309 DPRINTF("rxmode %#jx", rxmode, 0, 0, 0); 1310 1311 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1312 1313 /* Accept multicast frame or run promisc. mode */ 1314 axe_setiff_locked(un); 1315 1316 return usbnet_init_rx_tx(un); 1317 } 1318 1319 static int 1320 axe_uno_init(struct ifnet *ifp) 1321 { 1322 struct usbnet * const un = ifp->if_softc; 1323 1324 usbnet_lock_core(un); 1325 usbnet_busy(un); 1326 int ret = axe_init_locked(ifp); 1327 usbnet_unbusy(un); 1328 usbnet_unlock_core(un); 1329 1330 return ret; 1331 } 1332 1333 static int 1334 axe_uno_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1335 { 1336 struct usbnet * const un = ifp->if_softc; 1337 1338 usbnet_lock_core(un); 1339 usbnet_busy(un); 1340 1341 switch (cmd) { 1342 case SIOCADDMULTI: 1343 case SIOCDELMULTI: 1344 axe_setiff_locked(un); 1345 break; 1346 default: 1347 break; 1348 } 1349 1350 usbnet_unbusy(un); 1351 usbnet_unlock_core(un); 1352 1353 return 0; 1354 } 1355 1356 static void 1357 axe_uno_stop(struct ifnet *ifp, int disable) 1358 { 1359 struct usbnet * const un = ifp->if_softc; 1360 1361 axe_reset(un); 1362 } 1363 1364 #ifdef _MODULE 1365 #include "ioconf.c" 1366 #endif 1367 1368 USBNET_MODULE(axe) 1369
Indexes created Tue Sep 23 14:10:03 GMT 2025