if_axe.c revision 1.132
1 /* $NetBSD: if_axe.c,v 1.132 2021/03/01 17:41:00 jakllsch Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.132 2021/03/01 17:41:00 jakllsch Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_usb.h" 94 #include "opt_net_mpsafe.h" 95 #endif 96 97 #include <sys/param.h> 98 99 #include <dev/usb/usbnet.h> 100 #include <dev/usb/usbhist.h> 101 #include <dev/usb/if_axereg.h> 102 103 struct axe_type { 104 struct usb_devno axe_dev; 105 uint16_t axe_flags; 106 }; 107 108 struct axe_softc { 109 struct usbnet axe_un; 110 111 /* usbnet:un_flags values */ 112 #define AX178 __BIT(0) /* AX88178 */ 113 #define AX772 __BIT(1) /* AX88772 */ 114 #define AX772A __BIT(2) /* AX88772A */ 115 #define AX772B __BIT(3) /* AX88772B */ 116 #define AXSTD_FRAME __BIT(12) 117 #define AXCSUM_FRAME __BIT(13) 118 119 uint8_t axe_ipgs[3]; 120 uint8_t axe_phyaddrs[2]; 121 uint16_t sc_pwrcfg; 122 uint16_t sc_lenmask; 123 124 }; 125 126 #define AXE_IS_178_FAMILY(un) \ 127 ((un)->un_flags & (AX178 | AX772 | AX772A | AX772B)) 128 129 #define AXE_IS_772(un) \ 130 ((un)->un_flags & (AX772 | AX772A | AX772B)) 131 132 #define AXE_IS_172(un) (AXE_IS_178_FAMILY(un) == 0) 133 134 #define AX_RXCSUM \ 135 (IFCAP_CSUM_IPv4_Rx | \ 136 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | \ 137 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx) 138 139 #define AX_TXCSUM \ 140 (IFCAP_CSUM_IPv4_Tx | \ 141 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx | \ 142 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx) 143 144 /* 145 * AXE_178_MAX_FRAME_BURST 146 * max frame burst size for Ax88178 and Ax88772 147 * 0 2048 bytes 148 * 1 4096 bytes 149 * 2 8192 bytes 150 * 3 16384 bytes 151 * use the largest your system can handle without USB stalling. 152 * 153 * NB: 88772 parts appear to generate lots of input errors with 154 * a 2K rx buffer and 8K is only slightly faster than 4K on an 155 * EHCI port on a T42 so change at your own risk. 156 */ 157 #define AXE_178_MAX_FRAME_BURST 1 158 159 160 #ifdef USB_DEBUG 161 #ifndef AXE_DEBUG 162 #define axedebug 0 163 #else 164 static int axedebug = 0; 165 166 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 167 { 168 int err; 169 const struct sysctlnode *rnode; 170 const struct sysctlnode *cnode; 171 172 err = sysctl_createv(clog, 0, NULL, &rnode, 173 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 174 SYSCTL_DESCR("axe global controls"), 175 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 176 177 if (err) 178 goto fail; 179 180 /* control debugging printfs */ 181 err = sysctl_createv(clog, 0, &rnode, &cnode, 182 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 183 "debug", SYSCTL_DESCR("Enable debugging output"), 184 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 185 if (err) 186 goto fail; 187 188 return; 189 fail: 190 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 191 } 192 193 #endif /* AXE_DEBUG */ 194 #endif /* USB_DEBUG */ 195 196 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 197 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 198 #define AXEHIST_FUNC() USBHIST_FUNC() 199 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 200 201 /* 202 * Various supported device vendors/products. 203 */ 204 static const struct axe_type axe_devs[] = { 205 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000 }, 0 }, 206 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2 }, 0 }, 207 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 208 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172 }, 0 }, 209 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772 }, AX772 }, 210 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A }, AX772 }, 211 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B }, AX772B }, 212 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1 }, AX772B }, 213 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178 }, AX178 }, 214 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T }, 0 }, 215 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 216 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR }, 0}, 217 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2 }, AX772A }, 218 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0 }, 219 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100 }, 0 }, 220 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 221 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 222 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 223 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E }, 0 }, 224 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 225 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1 }, 0 }, 226 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 227 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9 }, AX772B }, 228 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M }, 0 }, 229 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 230 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2 }, AX178 }, 231 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT }, AX178 }, 232 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX }, 0 }, 233 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A }, AX772 }, 234 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120 }, 0 }, 235 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 236 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 237 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029 }, 0 }, 238 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 239 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 240 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL }, 0 }, 241 }; 242 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 243 244 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 245 { 0x8000, 0x8001, 2048 }, 246 { 0x8100, 0x8147, 4096 }, 247 { 0x8200, 0x81EB, 6144 }, 248 { 0x8300, 0x83D7, 8192 }, 249 { 0x8400, 0x851E, 16384 }, 250 { 0x8500, 0x8666, 20480 }, 251 { 0x8600, 0x87AE, 24576 }, 252 { 0x8700, 0x8A3D, 32768 } 253 }; 254 255 static int axe_match(device_t, cfdata_t, void *); 256 static void axe_attach(device_t, device_t, void *); 257 258 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 259 axe_match, axe_attach, usbnet_detach, usbnet_activate); 260 261 static void axe_uno_stop(struct ifnet *, int); 262 static int axe_uno_ioctl(struct ifnet *, u_long, void *); 263 static int axe_uno_init(struct ifnet *); 264 static int axe_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 265 static int axe_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 266 static void axe_uno_mii_statchg(struct ifnet *); 267 static void axe_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 268 uint32_t); 269 static unsigned axe_uno_tx_prepare(struct usbnet *, struct mbuf *, 270 struct usbnet_chain *); 271 272 static void axe_ax88178_init(struct axe_softc *); 273 static void axe_ax88772_init(struct axe_softc *); 274 static void axe_ax88772a_init(struct axe_softc *); 275 static void axe_ax88772b_init(struct axe_softc *); 276 277 static const struct usbnet_ops axe_ops = { 278 .uno_stop = axe_uno_stop, 279 .uno_ioctl = axe_uno_ioctl, 280 .uno_read_reg = axe_uno_mii_read_reg, 281 .uno_write_reg = axe_uno_mii_write_reg, 282 .uno_statchg = axe_uno_mii_statchg, 283 .uno_tx_prepare = axe_uno_tx_prepare, 284 .uno_rx_loop = axe_uno_rx_loop, 285 .uno_init = axe_uno_init, 286 }; 287 288 static usbd_status 289 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 290 { 291 AXEHIST_FUNC(); AXEHIST_CALLED(); 292 struct usbnet * const un = &sc->axe_un; 293 usb_device_request_t req; 294 usbd_status err; 295 296 usbnet_isowned_core(un); 297 298 if (usbnet_isdying(un)) 299 return -1; 300 301 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 302 303 if (AXE_CMD_DIR(cmd)) 304 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 305 else 306 req.bmRequestType = UT_READ_VENDOR_DEVICE; 307 req.bRequest = AXE_CMD_CMD(cmd); 308 USETW(req.wValue, val); 309 USETW(req.wIndex, index); 310 USETW(req.wLength, AXE_CMD_LEN(cmd)); 311 312 err = usbd_do_request(un->un_udev, &req, buf); 313 if (err) 314 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 315 316 return err; 317 } 318 319 static int 320 axe_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 321 { 322 AXEHIST_FUNC(); AXEHIST_CALLED(); 323 struct axe_softc * const sc = usbnet_softc(un); 324 usbd_status err; 325 uint16_t data; 326 327 DPRINTFN(30, "phy %#jx reg %#jx\n", phy, reg, 0, 0); 328 329 if (un->un_phyno != phy) 330 return EINVAL; 331 332 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 333 334 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 335 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 336 337 if (err) { 338 device_printf(un->un_dev, "read PHY failed\n"); 339 return EIO; 340 } 341 342 *val = le16toh(data); 343 if (AXE_IS_772(un) && reg == MII_BMSR) { 344 /* 345 * BMSR of AX88772 indicates that it supports extended 346 * capability but the extended status register is 347 * reserved for embedded ethernet PHY. So clear the 348 * extended capability bit of BMSR. 349 */ 350 *val &= ~BMSR_EXTCAP; 351 } 352 353 DPRINTFN(30, "phy %#jx reg %#jx val %#jx", phy, reg, *val, 0); 354 355 return 0; 356 } 357 358 static int 359 axe_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 360 { 361 struct axe_softc * const sc = usbnet_softc(un); 362 usbd_status err; 363 uint16_t aval; 364 365 if (un->un_phyno != phy) 366 return EINVAL; 367 368 aval = htole16(val); 369 370 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 371 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &aval); 372 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 373 374 if (err) 375 return EIO; 376 return 0; 377 } 378 379 static void 380 axe_uno_mii_statchg(struct ifnet *ifp) 381 { 382 AXEHIST_FUNC(); AXEHIST_CALLED(); 383 384 struct usbnet * const un = ifp->if_softc; 385 struct axe_softc * const sc = usbnet_softc(un); 386 struct mii_data *mii = usbnet_mii(un); 387 int val, err; 388 389 if (usbnet_isdying(un)) 390 return; 391 392 val = 0; 393 if (AXE_IS_172(un)) { 394 if (mii->mii_media_active & IFM_FDX) 395 val |= AXE_MEDIA_FULL_DUPLEX; 396 } else { 397 if (mii->mii_media_active & IFM_FDX) { 398 val |= AXE_MEDIA_FULL_DUPLEX; 399 if (mii->mii_media_active & IFM_ETH_TXPAUSE) 400 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 401 if (mii->mii_media_active & IFM_ETH_RXPAUSE) 402 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 403 } 404 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 405 if (un->un_flags & AX178) 406 val |= AXE_178_MEDIA_ENCK; 407 switch (IFM_SUBTYPE(mii->mii_media_active)) { 408 case IFM_1000_T: 409 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 410 usbnet_set_link(un, true); 411 break; 412 case IFM_100_TX: 413 val |= AXE_178_MEDIA_100TX; 414 usbnet_set_link(un, true); 415 break; 416 case IFM_10_T: 417 usbnet_set_link(un, true); 418 break; 419 } 420 } 421 422 DPRINTF("val=%#jx", val, 0, 0, 0); 423 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 424 if (err) 425 device_printf(un->un_dev, "media change failed\n"); 426 } 427 428 static void 429 axe_rcvfilt_locked(struct usbnet *un) 430 { 431 AXEHIST_FUNC(); AXEHIST_CALLED(); 432 struct axe_softc * const sc = usbnet_softc(un); 433 struct ifnet * const ifp = usbnet_ifp(un); 434 struct ethercom *ec = usbnet_ec(un); 435 struct ether_multi *enm; 436 struct ether_multistep step; 437 uint16_t rxmode; 438 uint32_t h = 0; 439 uint8_t mchash[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 440 441 if (usbnet_isdying(un)) 442 return; 443 444 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 445 device_printf(un->un_dev, "can't read rxmode"); 446 return; 447 } 448 rxmode = le16toh(rxmode); 449 450 rxmode &= 451 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | AXE_RXCMD_MULTICAST); 452 453 ETHER_LOCK(ec); 454 if (ifp->if_flags & IFF_PROMISC) { 455 ec->ec_flags |= ETHER_F_ALLMULTI; 456 ETHER_UNLOCK(ec); 457 /* run promisc. mode */ 458 rxmode |= AXE_RXCMD_ALLMULTI; /* ??? */ 459 rxmode |= AXE_RXCMD_PROMISC; 460 goto update; 461 } 462 ec->ec_flags &= ~ETHER_F_ALLMULTI; 463 ETHER_FIRST_MULTI(step, ec, enm); 464 while (enm != NULL) { 465 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 466 ec->ec_flags |= ETHER_F_ALLMULTI; 467 ETHER_UNLOCK(ec); 468 /* accept all mcast frames */ 469 rxmode |= AXE_RXCMD_ALLMULTI; 470 goto update; 471 } 472 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 473 mchash[h >> 29] |= 1U << ((h >> 26) & 7); 474 ETHER_NEXT_MULTI(step, enm); 475 } 476 ETHER_UNLOCK(ec); 477 if (h != 0) 478 rxmode |= AXE_RXCMD_MULTICAST; /* activate mcast hash filter */ 479 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, mchash); 480 update: 481 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 482 } 483 484 static void 485 axe_ax_init(struct usbnet *un) 486 { 487 struct axe_softc * const sc = usbnet_softc(un); 488 489 int cmd = AXE_178_CMD_READ_NODEID; 490 491 if (un->un_flags & AX178) { 492 axe_ax88178_init(sc); 493 } else if (un->un_flags & AX772) { 494 axe_ax88772_init(sc); 495 } else if (un->un_flags & AX772A) { 496 axe_ax88772a_init(sc); 497 } else if (un->un_flags & AX772B) { 498 axe_ax88772b_init(sc); 499 return; 500 } else { 501 cmd = AXE_172_CMD_READ_NODEID; 502 } 503 504 if (axe_cmd(sc, cmd, 0, 0, un->un_eaddr)) { 505 aprint_error_dev(un->un_dev, 506 "failed to read ethernet address\n"); 507 } 508 } 509 510 511 static void 512 axe_reset(struct usbnet *un) 513 { 514 515 usbnet_isowned_core(un); 516 517 if (usbnet_isdying(un)) 518 return; 519 520 /* 521 * softnet_lock can be taken when NET_MPAFE is not defined when calling 522 * if_addr_init -> if_init. This doesn't mix well with the 523 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 524 * can fire during the wait and attempt to take softnet_lock and then 525 * block the softclk thread meaning the wait never ends. 526 */ 527 #ifndef NET_MPSAFE 528 /* XXX What to reset? */ 529 530 /* Wait a little while for the chip to get its brains in order. */ 531 DELAY(1000); 532 #else 533 axe_ax_init(un); 534 #endif 535 } 536 537 static int 538 axe_get_phyno(struct axe_softc *sc, int sel) 539 { 540 int phyno; 541 542 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 543 case PHY_TYPE_100_HOME: 544 /* FALLTHROUGH */ 545 case PHY_TYPE_GIG: 546 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 547 break; 548 case PHY_TYPE_SPECIAL: 549 /* FALLTHROUGH */ 550 case PHY_TYPE_RSVD: 551 /* FALLTHROUGH */ 552 case PHY_TYPE_NON_SUP: 553 /* FALLTHROUGH */ 554 default: 555 phyno = -1; 556 break; 557 } 558 559 return phyno; 560 } 561 562 #define AXE_GPIO_WRITE(x, y) do { \ 563 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 564 usbd_delay_ms(sc->axe_un.un_udev, hztoms(y)); \ 565 } while (0) 566 567 static void 568 axe_ax88178_init(struct axe_softc *sc) 569 { 570 AXEHIST_FUNC(); AXEHIST_CALLED(); 571 struct usbnet * const un = &sc->axe_un; 572 int gpio0, ledmode, phymode; 573 uint16_t eeprom, val; 574 575 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 576 /* XXX magic */ 577 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 578 eeprom = 0xffff; 579 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 580 581 eeprom = le16toh(eeprom); 582 583 DPRINTF("EEPROM is %#jx", eeprom, 0, 0, 0); 584 585 /* if EEPROM is invalid we have to use to GPIO0 */ 586 if (eeprom == 0xffff) { 587 phymode = AXE_PHY_MODE_MARVELL; 588 gpio0 = 1; 589 ledmode = 0; 590 } else { 591 phymode = eeprom & 0x7f; 592 gpio0 = (eeprom & 0x80) ? 0 : 1; 593 ledmode = eeprom >> 8; 594 } 595 596 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 597 598 /* Program GPIOs depending on PHY hardware. */ 599 switch (phymode) { 600 case AXE_PHY_MODE_MARVELL: 601 if (gpio0 == 1) { 602 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 603 hz / 32); 604 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 605 hz / 32); 606 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 607 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 608 hz / 32); 609 } else { 610 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 611 AXE_GPIO1_EN, hz / 3); 612 if (ledmode == 1) { 613 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 614 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 615 hz / 3); 616 } else { 617 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 618 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 619 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 620 AXE_GPIO2_EN, hz / 4); 621 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 622 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 623 } 624 } 625 break; 626 case AXE_PHY_MODE_CICADA: 627 case AXE_PHY_MODE_CICADA_V2: 628 case AXE_PHY_MODE_CICADA_V2_ASIX: 629 if (gpio0 == 1) 630 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 631 AXE_GPIO0_EN, hz / 32); 632 else 633 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 634 AXE_GPIO1_EN, hz / 32); 635 break; 636 case AXE_PHY_MODE_AGERE: 637 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 638 AXE_GPIO1_EN, hz / 32); 639 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 640 AXE_GPIO2_EN, hz / 32); 641 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 642 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 643 AXE_GPIO2_EN, hz / 32); 644 break; 645 case AXE_PHY_MODE_REALTEK_8211CL: 646 case AXE_PHY_MODE_REALTEK_8211BN: 647 case AXE_PHY_MODE_REALTEK_8251CL: 648 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 649 AXE_GPIO1 | AXE_GPIO1_EN; 650 AXE_GPIO_WRITE(val, hz / 32); 651 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 652 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 653 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 654 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 655 axe_uno_mii_write_reg(un, un->un_phyno, 0x1F, 0x0005); 656 axe_uno_mii_write_reg(un, un->un_phyno, 0x0C, 0x0000); 657 axe_uno_mii_read_reg(un, un->un_phyno, 0x0001, &val); 658 axe_uno_mii_write_reg(un, un->un_phyno, 0x01, val | 0x0080); 659 axe_uno_mii_write_reg(un, un->un_phyno, 0x1F, 0x0000); 660 } 661 break; 662 default: 663 /* Unknown PHY model or no need to program GPIOs. */ 664 break; 665 } 666 667 /* soft reset */ 668 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 669 usbd_delay_ms(un->un_udev, 150); 670 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 671 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 672 usbd_delay_ms(un->un_udev, 150); 673 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 674 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 675 usbd_delay_ms(un->un_udev, 10); 676 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 677 } 678 679 static void 680 axe_ax88772_init(struct axe_softc *sc) 681 { 682 AXEHIST_FUNC(); AXEHIST_CALLED(); 683 struct usbnet * const un = &sc->axe_un; 684 685 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 686 usbd_delay_ms(un->un_udev, 40); 687 688 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 689 /* ask for the embedded PHY */ 690 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 691 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 692 usbd_delay_ms(un->un_udev, 10); 693 694 /* power down and reset state, pin reset state */ 695 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 696 usbd_delay_ms(un->un_udev, 60); 697 698 /* power down/reset state, pin operating state */ 699 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 700 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 701 usbd_delay_ms(un->un_udev, 150); 702 703 /* power up, reset */ 704 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 705 706 /* power up, operating */ 707 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 708 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 709 } else { 710 /* ask for external PHY */ 711 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 712 NULL); 713 usbd_delay_ms(un->un_udev, 10); 714 715 /* power down internal PHY */ 716 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 717 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 718 } 719 720 usbd_delay_ms(un->un_udev, 150); 721 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 722 } 723 724 static void 725 axe_ax88772_phywake(struct axe_softc *sc) 726 { 727 AXEHIST_FUNC(); AXEHIST_CALLED(); 728 struct usbnet * const un = &sc->axe_un; 729 730 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 731 /* Manually select internal(embedded) PHY - MAC mode. */ 732 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 733 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 734 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 735 } else { 736 /* 737 * Manually select external PHY - MAC mode. 738 * Reverse MII/RMII is for AX88772A PHY mode. 739 */ 740 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 741 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 742 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 743 } 744 745 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 746 AXE_SW_RESET_IPRL, NULL); 747 748 /* T1 = min 500ns everywhere */ 749 usbd_delay_ms(un->un_udev, 150); 750 751 /* Take PHY out of power down. */ 752 if (un->un_phyno == AXE_772_PHY_NO_EPHY) { 753 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 754 } else { 755 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 756 } 757 758 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 759 usbd_delay_ms(un->un_udev, 600); 760 761 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 762 763 /* T3 = 500ns everywhere */ 764 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 765 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 766 usbd_delay_ms(un->un_udev, hztoms(hz / 32)); 767 } 768 769 static void 770 axe_ax88772a_init(struct axe_softc *sc) 771 { 772 AXEHIST_FUNC(); AXEHIST_CALLED(); 773 774 /* Reload EEPROM. */ 775 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 776 axe_ax88772_phywake(sc); 777 /* Stop MAC. */ 778 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 779 } 780 781 static void 782 axe_ax88772b_init(struct axe_softc *sc) 783 { 784 AXEHIST_FUNC(); AXEHIST_CALLED(); 785 struct usbnet * const un = &sc->axe_un; 786 uint16_t eeprom; 787 int i; 788 789 /* Reload EEPROM. */ 790 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 791 792 /* 793 * Save PHY power saving configuration(high byte) and 794 * clear EEPROM checksum value(low byte). 795 */ 796 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 797 &eeprom)) { 798 aprint_error_dev(un->un_dev, "failed to read eeprom\n"); 799 return; 800 } 801 802 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 803 804 /* 805 * Auto-loaded default station address from internal ROM is 806 * 00:00:00:00:00:00 such that an explicit access to EEPROM 807 * is required to get real station address. 808 */ 809 uint8_t *eaddr = un->un_eaddr; 810 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 811 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 812 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 813 aprint_error_dev(un->un_dev, 814 "failed to read eeprom\n"); 815 eeprom = 0; 816 } 817 eeprom = le16toh(eeprom); 818 *eaddr++ = (uint8_t)(eeprom & 0xFF); 819 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 820 } 821 /* Wakeup PHY. */ 822 axe_ax88772_phywake(sc); 823 /* Stop MAC. */ 824 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 825 } 826 827 #undef AXE_GPIO_WRITE 828 829 /* 830 * Probe for a AX88172 chip. 831 */ 832 static int 833 axe_match(device_t parent, cfdata_t match, void *aux) 834 { 835 struct usb_attach_arg *uaa = aux; 836 837 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 838 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 839 } 840 841 /* 842 * Attach the interface. Allocate softc structures, do ifmedia 843 * setup and ethernet/BPF attach. 844 */ 845 static void 846 axe_attach(device_t parent, device_t self, void *aux) 847 { 848 AXEHIST_FUNC(); AXEHIST_CALLED(); 849 USBNET_MII_DECL_DEFAULT(unm); 850 struct axe_softc *sc = device_private(self); 851 struct usbnet * const un = &sc->axe_un; 852 struct usb_attach_arg *uaa = aux; 853 struct usbd_device *dev = uaa->uaa_device; 854 usbd_status err; 855 usb_interface_descriptor_t *id; 856 usb_endpoint_descriptor_t *ed; 857 char *devinfop; 858 unsigned bufsz; 859 int i; 860 861 KASSERT((void *)sc == un); 862 863 aprint_naive("\n"); 864 aprint_normal("\n"); 865 devinfop = usbd_devinfo_alloc(dev, 0); 866 aprint_normal_dev(self, "%s\n", devinfop); 867 usbd_devinfo_free(devinfop); 868 869 un->un_dev = self; 870 un->un_udev = dev; 871 un->un_sc = sc; 872 un->un_ops = &axe_ops; 873 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 874 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 875 un->un_rx_list_cnt = AXE_RX_LIST_CNT; 876 un->un_tx_list_cnt = AXE_TX_LIST_CNT; 877 878 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 879 if (err) { 880 aprint_error_dev(self, "failed to set configuration" 881 ", err=%s\n", usbd_errstr(err)); 882 return; 883 } 884 885 un->un_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 886 887 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &un->un_iface); 888 if (err) { 889 aprint_error_dev(self, "getting interface handle failed\n"); 890 return; 891 } 892 893 id = usbd_get_interface_descriptor(un->un_iface); 894 895 /* decide on what our bufsize will be */ 896 if (AXE_IS_172(un)) 897 bufsz = AXE_172_BUFSZ; 898 else 899 bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 900 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 901 un->un_rx_bufsz = un->un_tx_bufsz = bufsz; 902 903 un->un_ed[USBNET_ENDPT_RX] = 0; 904 un->un_ed[USBNET_ENDPT_TX] = 0; 905 un->un_ed[USBNET_ENDPT_INTR] = 0; 906 907 /* Find endpoints. */ 908 for (i = 0; i < id->bNumEndpoints; i++) { 909 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 910 if (ed == NULL) { 911 aprint_error_dev(self, "couldn't get ep %d\n", i); 912 return; 913 } 914 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 915 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 916 917 if (dir == UE_DIR_IN && xt == UE_BULK && 918 un->un_ed[USBNET_ENDPT_RX] == 0) { 919 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 920 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 921 un->un_ed[USBNET_ENDPT_TX] == 0) { 922 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 923 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 924 un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress; 925 } 926 } 927 928 /* Set these up now for axe_cmd(). */ 929 usbnet_attach(un, "axedet"); 930 931 /* We need the PHYID for init dance in some cases */ 932 usbnet_lock_core(un); 933 usbnet_busy(un); 934 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 935 aprint_error_dev(self, "failed to read phyaddrs\n"); 936 usbnet_unbusy(un); 937 usbnet_unlock_core(un); 938 return; 939 } 940 941 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 942 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 943 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 944 if (un->un_phyno == -1) 945 un->un_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 946 if (un->un_phyno == -1) { 947 DPRINTF(" no valid PHY address found, assuming PHY address 0", 948 0, 0, 0, 0); 949 un->un_phyno = 0; 950 } 951 952 /* Initialize controller and get station address. */ 953 954 axe_ax_init(un); 955 956 /* 957 * Fetch IPG values. 958 */ 959 if (un->un_flags & (AX772A | AX772B)) { 960 /* Set IPG values. */ 961 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 962 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 963 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 964 } else { 965 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 966 aprint_error_dev(self, "failed to read ipg\n"); 967 usbnet_unbusy(un); 968 usbnet_unlock_core(un); 969 return; 970 } 971 } 972 973 usbnet_unbusy(un); 974 usbnet_unlock_core(un); 975 976 if (!AXE_IS_172(un)) 977 usbnet_ec(un)->ec_capabilities = ETHERCAP_VLAN_MTU; 978 if (un->un_flags & AX772B) { 979 struct ifnet *ifp = usbnet_ifp(un); 980 981 ifp->if_capabilities = 982 IFCAP_CSUM_IPv4_Rx | 983 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 984 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 985 /* 986 * Checksum offloading of AX88772B also works with VLAN 987 * tagged frames but there is no way to take advantage 988 * of the feature because vlan(4) assumes 989 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 990 * support checksum offloading with VLAN. VLAN hardware 991 * tagging support of AX88772B is very limited so it's 992 * not possible to announce IFCAP_VLAN_HWTAGGING. 993 */ 994 } 995 if (un->un_flags & (AX772A | AX772B | AX178)) 996 unm.un_mii_flags = MIIF_DOPAUSE; 997 998 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 999 0, &unm); 1000 } 1001 1002 static void 1003 axe_uno_rx_loop(struct usbnet * un, struct usbnet_chain *c, uint32_t total_len) 1004 { 1005 AXEHIST_FUNC(); AXEHIST_CALLED(); 1006 struct axe_softc * const sc = usbnet_softc(un); 1007 struct ifnet *ifp = usbnet_ifp(un); 1008 uint8_t *buf = c->unc_buf; 1009 1010 do { 1011 u_int pktlen = 0; 1012 u_int rxlen = 0; 1013 int flags = 0; 1014 1015 if ((un->un_flags & AXSTD_FRAME) != 0) { 1016 struct axe_sframe_hdr hdr; 1017 1018 if (total_len < sizeof(hdr)) { 1019 if_statinc(ifp, if_ierrors); 1020 break; 1021 } 1022 1023 memcpy(&hdr, buf, sizeof(hdr)); 1024 1025 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx", 1026 total_len, 1027 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1028 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1029 1030 total_len -= sizeof(hdr); 1031 buf += sizeof(hdr); 1032 1033 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1034 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1035 AXE_RH1M_RXLEN_MASK) { 1036 if_statinc(ifp, if_ierrors); 1037 break; 1038 } 1039 1040 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1041 if (total_len < rxlen) { 1042 pktlen = total_len; 1043 total_len = 0; 1044 } else { 1045 pktlen = rxlen; 1046 rxlen = roundup2(rxlen, 2); 1047 total_len -= rxlen; 1048 } 1049 1050 } else if ((un->un_flags & AXCSUM_FRAME) != 0) { 1051 struct axe_csum_hdr csum_hdr; 1052 1053 if (total_len < sizeof(csum_hdr)) { 1054 if_statinc(ifp, if_ierrors); 1055 break; 1056 } 1057 1058 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1059 1060 csum_hdr.len = le16toh(csum_hdr.len); 1061 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1062 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1063 1064 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1065 " cstatus %#jx", total_len, 1066 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1067 1068 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1069 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1070 sc->sc_lenmask) { 1071 /* we lost sync */ 1072 if_statinc(ifp, if_ierrors); 1073 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1074 "err", 1075 AXE_CSUM_RXBYTES(csum_hdr.len), 1076 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1077 sc->sc_lenmask, 0); 1078 break; 1079 } 1080 /* 1081 * Get total transferred frame length including 1082 * checksum header. The length should be multiple 1083 * of 4. 1084 */ 1085 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1086 u_int len = sizeof(csum_hdr) + pktlen; 1087 len = (len + 3) & ~3; 1088 if (total_len < len) { 1089 DPRINTFN(20, "total_len %#jx < len %#jx", 1090 total_len, len, 0, 0); 1091 /* invalid length */ 1092 if_statinc(ifp, if_ierrors); 1093 break; 1094 } 1095 buf += sizeof(csum_hdr); 1096 1097 const uint16_t cstatus = csum_hdr.cstatus; 1098 1099 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1100 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1101 flags |= M_CSUM_TCP_UDP_BAD; 1102 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1103 flags |= M_CSUM_IPv4_BAD; 1104 1105 const uint16_t l4type = 1106 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1107 1108 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1109 flags |= M_CSUM_TCPv4; 1110 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1111 flags |= M_CSUM_UDPv4; 1112 } 1113 if (total_len < len) { 1114 pktlen = total_len; 1115 total_len = 0; 1116 } else { 1117 total_len -= len; 1118 rxlen = len - sizeof(csum_hdr); 1119 } 1120 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1121 " rxlen %#jx", total_len, len, pktlen, rxlen); 1122 } else { /* AX172 */ 1123 pktlen = rxlen = total_len; 1124 total_len = 0; 1125 } 1126 1127 usbnet_enqueue(un, buf, pktlen, flags, 0, 0); 1128 buf += rxlen; 1129 1130 } while (total_len > 0); 1131 1132 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1133 } 1134 1135 static unsigned 1136 axe_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1137 { 1138 AXEHIST_FUNC(); AXEHIST_CALLED(); 1139 struct axe_sframe_hdr hdr, tlr; 1140 size_t hdr_len = 0, tlr_len = 0; 1141 int length, boundary; 1142 1143 usbnet_isowned_tx(un); 1144 1145 if (!AXE_IS_172(un)) { 1146 /* 1147 * Copy the mbuf data into a contiguous buffer, leaving two 1148 * bytes at the beginning to hold the frame length. 1149 */ 1150 boundary = (un->un_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1151 1152 hdr.len = htole16(m->m_pkthdr.len); 1153 hdr.ilen = ~hdr.len; 1154 hdr_len = sizeof(hdr); 1155 1156 length = hdr_len + m->m_pkthdr.len; 1157 1158 if ((length % boundary) == 0) { 1159 tlr.len = 0x0000; 1160 tlr.ilen = 0xffff; 1161 tlr_len = sizeof(tlr); 1162 } 1163 DPRINTFN(20, "length %jx m_pkthdr.len %jx hdrsize %#jx", 1164 length, m->m_pkthdr.len, sizeof(hdr), 0); 1165 } 1166 1167 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - hdr_len - tlr_len) 1168 return 0; 1169 length = hdr_len + m->m_pkthdr.len + tlr_len; 1170 1171 if (hdr_len) 1172 memcpy(c->unc_buf, &hdr, hdr_len); 1173 m_copydata(m, 0, m->m_pkthdr.len, c->unc_buf + hdr_len); 1174 if (tlr_len) 1175 memcpy(c->unc_buf + length - tlr_len, &tlr, tlr_len); 1176 1177 return length; 1178 } 1179 1180 static void 1181 axe_csum_cfg(struct axe_softc *sc) 1182 { 1183 struct usbnet * const un = &sc->axe_un; 1184 struct ifnet * const ifp = usbnet_ifp(un); 1185 uint16_t csum1, csum2; 1186 1187 if ((un->un_flags & AX772B) != 0) { 1188 csum1 = 0; 1189 csum2 = 0; 1190 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1191 csum1 |= AXE_TXCSUM_IP; 1192 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1193 csum1 |= AXE_TXCSUM_TCP; 1194 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1195 csum1 |= AXE_TXCSUM_UDP; 1196 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1197 csum1 |= AXE_TXCSUM_TCPV6; 1198 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1199 csum1 |= AXE_TXCSUM_UDPV6; 1200 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1201 csum1 = 0; 1202 csum2 = 0; 1203 1204 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1205 csum1 |= AXE_RXCSUM_IP; 1206 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1207 csum1 |= AXE_RXCSUM_TCP; 1208 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1209 csum1 |= AXE_RXCSUM_UDP; 1210 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1211 csum1 |= AXE_RXCSUM_TCPV6; 1212 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1213 csum1 |= AXE_RXCSUM_UDPV6; 1214 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1215 } 1216 } 1217 1218 static int 1219 axe_init_locked(struct ifnet *ifp) 1220 { 1221 AXEHIST_FUNC(); AXEHIST_CALLED(); 1222 struct usbnet * const un = ifp->if_softc; 1223 struct axe_softc * const sc = usbnet_softc(un); 1224 int rxmode; 1225 1226 usbnet_isowned_core(un); 1227 1228 if (usbnet_isdying(un)) 1229 return EIO; 1230 1231 /* Cancel pending I/O */ 1232 usbnet_stop(un, ifp, 1); 1233 1234 /* Reset the ethernet interface. */ 1235 axe_reset(un); 1236 1237 #if 0 1238 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1239 AX_GPIO_GPO2EN, 5, in_pm); 1240 #endif 1241 /* Set MAC address and transmitter IPG values. */ 1242 if (AXE_IS_172(un)) { 1243 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1244 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1245 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1246 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1247 } else { 1248 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, un->un_eaddr); 1249 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1250 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1251 1252 un->un_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1253 if ((un->un_flags & AX772B) != 0 && 1254 (ifp->if_capenable & AX_RXCSUM) != 0) { 1255 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1256 un->un_flags |= AXCSUM_FRAME; 1257 } else { 1258 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1259 un->un_flags |= AXSTD_FRAME; 1260 } 1261 } 1262 1263 /* Configure TX/RX checksum offloading. */ 1264 axe_csum_cfg(sc); 1265 1266 if (un->un_flags & AX772B) { 1267 /* AX88772B uses different maximum frame burst configuration. */ 1268 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1269 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1270 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1271 } 1272 /* Enable receiver, set RX mode */ 1273 rxmode = (AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1274 if (AXE_IS_172(un)) 1275 rxmode |= AXE_172_RXCMD_UNICAST; 1276 else { 1277 if (un->un_flags & AX772B) { 1278 /* 1279 * Select RX header format type 1. Aligning IP 1280 * header on 4 byte boundary is not needed when 1281 * checksum offloading feature is not used 1282 * because we always copy the received frame in 1283 * RX handler. When RX checksum offloading is 1284 * active, aligning IP header is required to 1285 * reflect actual frame length including RX 1286 * header size. 1287 */ 1288 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1289 if (un->un_flags & AXCSUM_FRAME) 1290 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1291 } else { 1292 /* 1293 * Default Rx buffer size is too small to get 1294 * maximum performance. 1295 */ 1296 #if 0 1297 if (un->un_udev->ud_speed == USB_SPEED_HIGH) { 1298 /* Largest possible USB buffer size for AX88178 */ 1299 } 1300 #endif 1301 rxmode |= AXE_178_RXCMD_MFB_16384; 1302 } 1303 } 1304 1305 DPRINTF("rxmode %#jx", rxmode, 0, 0, 0); 1306 1307 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1308 1309 /* Accept multicast frame or run promisc. mode */ 1310 axe_rcvfilt_locked(un); 1311 1312 return usbnet_init_rx_tx(un); 1313 } 1314 1315 static int 1316 axe_uno_init(struct ifnet *ifp) 1317 { 1318 struct usbnet * const un = ifp->if_softc; 1319 1320 usbnet_lock_core(un); 1321 usbnet_busy(un); 1322 int ret = axe_init_locked(ifp); 1323 usbnet_unbusy(un); 1324 usbnet_unlock_core(un); 1325 1326 return ret; 1327 } 1328 1329 static int 1330 axe_uno_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1331 { 1332 struct usbnet * const un = ifp->if_softc; 1333 1334 usbnet_lock_core(un); 1335 usbnet_busy(un); 1336 1337 switch (cmd) { 1338 case SIOCADDMULTI: 1339 case SIOCDELMULTI: 1340 axe_rcvfilt_locked(un); 1341 break; 1342 default: 1343 break; 1344 } 1345 1346 usbnet_unbusy(un); 1347 usbnet_unlock_core(un); 1348 1349 return 0; 1350 } 1351 1352 static void 1353 axe_uno_stop(struct ifnet *ifp, int disable) 1354 { 1355 struct usbnet * const un = ifp->if_softc; 1356 1357 axe_reset(un); 1358 } 1359 1360 #ifdef _MODULE 1361 #include "ioconf.c" 1362 #endif 1363 1364 USBNET_MODULE(axe) 1365
Indexes created Tue Sep 23 07:09:52 GMT 2025