if_axe.c revision 1.67.2.4
1 /* $NetBSD: if_axe.c,v 1.67.2.4 2018/08/08 10:17:11 martin Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.67.2.4 2018/08/08 10:17:11 martin Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #endif 96 97 #include <sys/param.h> 98 #include <sys/bus.h> 99 #include <sys/device.h> 100 #include <sys/kernel.h> 101 #include <sys/mbuf.h> 102 #include <sys/module.h> 103 #include <sys/mutex.h> 104 #include <sys/socket.h> 105 #include <sys/sockio.h> 106 #include <sys/systm.h> 107 108 #include <sys/rnd.h> 109 110 #include <net/if.h> 111 #include <net/if_dl.h> 112 #include <net/if_ether.h> 113 #include <net/if_media.h> 114 115 #include <net/bpf.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/usb/usb.h> 121 #include <dev/usb/usbhist.h> 122 #include <dev/usb/usbdi.h> 123 #include <dev/usb/usbdi_util.h> 124 #include <dev/usb/usbdivar.h> 125 #include <dev/usb/usbdevs.h> 126 127 #include <dev/usb/if_axereg.h> 128 129 /* 130 * AXE_178_MAX_FRAME_BURST 131 * max frame burst size for Ax88178 and Ax88772 132 * 0 2048 bytes 133 * 1 4096 bytes 134 * 2 8192 bytes 135 * 3 16384 bytes 136 * use the largest your system can handle without USB stalling. 137 * 138 * NB: 88772 parts appear to generate lots of input errors with 139 * a 2K rx buffer and 8K is only slightly faster than 4K on an 140 * EHCI port on a T42 so change at your own risk. 141 */ 142 #define AXE_178_MAX_FRAME_BURST 1 143 144 145 #ifdef USB_DEBUG 146 #ifndef AXE_DEBUG 147 #define axedebug 0 148 #else 149 static int axedebug = 20; 150 151 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 152 { 153 int err; 154 const struct sysctlnode *rnode; 155 const struct sysctlnode *cnode; 156 157 err = sysctl_createv(clog, 0, NULL, &rnode, 158 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 159 SYSCTL_DESCR("axe global controls"), 160 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 161 162 if (err) 163 goto fail; 164 165 /* control debugging printfs */ 166 err = sysctl_createv(clog, 0, &rnode, &cnode, 167 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 168 "debug", SYSCTL_DESCR("Enable debugging output"), 169 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 170 if (err) 171 goto fail; 172 173 return; 174 fail: 175 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 176 } 177 178 #endif /* AXE_DEBUG */ 179 #endif /* USB_DEBUG */ 180 181 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 182 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 183 #define AXEHIST_FUNC() USBHIST_FUNC() 184 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 185 186 /* 187 * Various supported device vendors/products. 188 */ 189 static const struct axe_type axe_devs[] = { 190 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 191 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 192 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 193 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 199 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 200 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 201 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 202 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 203 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 204 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 206 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 208 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 209 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 210 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 211 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 212 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 213 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 214 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 215 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 216 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 218 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 219 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 220 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 221 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 222 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 223 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 225 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 226 }; 227 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 228 229 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 230 { 0x8000, 0x8001, 2048 }, 231 { 0x8100, 0x8147, 4096 }, 232 { 0x8200, 0x81EB, 6144 }, 233 { 0x8300, 0x83D7, 8192 }, 234 { 0x8400, 0x851E, 16384 }, 235 { 0x8500, 0x8666, 20480 }, 236 { 0x8600, 0x87AE, 24576 }, 237 { 0x8700, 0x8A3D, 32768 } 238 }; 239 240 int axe_match(device_t, cfdata_t, void *); 241 void axe_attach(device_t, device_t, void *); 242 int axe_detach(device_t, int); 243 int axe_activate(device_t, devact_t); 244 245 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 246 axe_match, axe_attach, axe_detach, axe_activate); 247 248 static int axe_tx_list_init(struct axe_softc *); 249 #if 0 250 static void axe_tx_list_free(struct axe_softc *); 251 #endif 252 static int axe_rx_list_init(struct axe_softc *); 253 static void axe_rx_list_free(struct axe_softc *); 254 static int axe_encap(struct axe_softc *, struct mbuf *, int); 255 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 256 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 257 static void axe_tick(void *); 258 static void axe_tick_task(void *); 259 static void axe_start(struct ifnet *); 260 static void axe_start_locked(struct ifnet *); 261 static int axe_ioctl(struct ifnet *, u_long, void *); 262 static int axe_init(struct ifnet *); 263 static int axe_init_locked(struct ifnet *); 264 static void axe_stop(struct ifnet *, int); 265 static void axe_stop_locked(struct ifnet *, int); 266 static void axe_watchdog(struct ifnet *); 267 static int axe_miibus_readreg_locked(device_t, int, int); 268 static int axe_miibus_readreg(device_t, int, int); 269 static void axe_miibus_writereg_locked(device_t, int, int, int); 270 static void axe_miibus_writereg(device_t, int, int, int); 271 static void axe_miibus_statchg(struct ifnet *); 272 static int axe_cmd(struct axe_softc *, int, int, int, void *); 273 static void axe_reset(struct axe_softc *); 274 275 static void axe_setmulti(struct axe_softc *); 276 static void axe_lock_mii(struct axe_softc *); 277 static void axe_unlock_mii(struct axe_softc *); 278 279 static void axe_ax88178_init(struct axe_softc *); 280 static void axe_ax88772_init(struct axe_softc *); 281 static void axe_ax88772a_init(struct axe_softc *); 282 static void axe_ax88772b_init(struct axe_softc *); 283 284 /* Get exclusive access to the MII registers */ 285 static void 286 axe_lock_mii(struct axe_softc *sc) 287 { 288 289 sc->axe_refcnt++; 290 mutex_enter(&sc->axe_mii_lock); 291 } 292 293 static void 294 axe_unlock_mii(struct axe_softc *sc) 295 { 296 297 mutex_exit(&sc->axe_mii_lock); 298 if (--sc->axe_refcnt < 0) 299 usb_detach_wakeupold((sc->axe_dev)); 300 } 301 302 static int 303 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 304 { 305 AXEHIST_FUNC(); AXEHIST_CALLED(); 306 usb_device_request_t req; 307 usbd_status err; 308 309 KASSERT(mutex_owned(&sc->axe_mii_lock)); 310 311 if (sc->axe_dying) 312 return 0; 313 314 DPRINTFN(20, "cmd %#x index %#x val %#x", cmd, index, val, 0); 315 316 if (AXE_CMD_DIR(cmd)) 317 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 318 else 319 req.bmRequestType = UT_READ_VENDOR_DEVICE; 320 req.bRequest = AXE_CMD_CMD(cmd); 321 USETW(req.wValue, val); 322 USETW(req.wIndex, index); 323 USETW(req.wLength, AXE_CMD_LEN(cmd)); 324 325 err = usbd_do_request(sc->axe_udev, &req, buf); 326 327 if (err) { 328 DPRINTF("cmd %d err %d", cmd, err, 0, 0); 329 return -1; 330 } 331 return 0; 332 } 333 334 static int 335 axe_miibus_readreg_locked(device_t dev, int phy, int reg) 336 { 337 AXEHIST_FUNC(); AXEHIST_CALLED(); 338 struct axe_softc *sc = device_private(dev); 339 usbd_status err; 340 uint16_t val; 341 342 DPRINTFN(30, "phy 0x%x reg 0x%x\n", phy, reg, 0, 0); 343 344 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 345 346 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, (void *)&val); 347 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 348 if (err) { 349 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 350 return -1; 351 } 352 353 val = le16toh(val); 354 if (AXE_IS_772(sc) && reg == MII_BMSR) { 355 /* 356 * BMSR of AX88772 indicates that it supports extended 357 * capability but the extended status register is 358 * reserved for embedded ethernet PHY. So clear the 359 * extended capability bit of BMSR. 360 */ 361 val &= ~BMSR_EXTCAP; 362 } 363 364 DPRINTFN(30, "phy 0x%x reg 0x%x val %#x", phy, reg, val, 0); 365 366 return val; 367 } 368 369 static int 370 axe_miibus_readreg(device_t dev, int phy, int reg) 371 { 372 struct axe_softc *sc = device_private(dev); 373 int val; 374 375 if (sc->axe_dying) 376 return 0; 377 378 if (sc->axe_phyno != phy) 379 return 0; 380 381 axe_lock_mii(sc); 382 val = axe_miibus_readreg_locked(dev, phy, reg); 383 axe_unlock_mii(sc); 384 385 return val; 386 } 387 388 static void 389 axe_miibus_writereg_locked(device_t dev, int phy, int reg, int aval) 390 { 391 struct axe_softc *sc = device_private(dev); 392 usbd_status err; 393 uint16_t val; 394 395 val = htole16(aval); 396 397 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 398 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, (void *)&val); 399 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 400 401 if (err) { 402 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 403 return; 404 } 405 } 406 407 static void 408 axe_miibus_writereg(device_t dev, int phy, int reg, int aval) 409 { 410 struct axe_softc *sc = device_private(dev); 411 412 if (sc->axe_dying) 413 return; 414 415 if (sc->axe_phyno != phy) 416 return; 417 418 axe_lock_mii(sc); 419 axe_miibus_writereg_locked(dev, phy, reg, aval); 420 axe_unlock_mii(sc); 421 } 422 423 static void 424 axe_miibus_statchg(struct ifnet *ifp) 425 { 426 AXEHIST_FUNC(); AXEHIST_CALLED(); 427 428 struct axe_softc *sc = ifp->if_softc; 429 struct mii_data *mii = &sc->axe_mii; 430 int val, err; 431 432 val = 0; 433 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 434 val |= AXE_MEDIA_FULL_DUPLEX; 435 if (AXE_IS_178_FAMILY(sc)) { 436 if ((IFM_OPTIONS(mii->mii_media_active) & 437 IFM_ETH_TXPAUSE) != 0) 438 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 439 if ((IFM_OPTIONS(mii->mii_media_active) & 440 IFM_ETH_RXPAUSE) != 0) 441 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 442 } 443 } 444 if (AXE_IS_178_FAMILY(sc)) { 445 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 446 if (sc->axe_flags & AX178) 447 val |= AXE_178_MEDIA_ENCK; 448 switch (IFM_SUBTYPE(mii->mii_media_active)) { 449 case IFM_1000_T: 450 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 451 break; 452 case IFM_100_TX: 453 val |= AXE_178_MEDIA_100TX; 454 break; 455 case IFM_10_T: 456 /* doesn't need to be handled */ 457 break; 458 } 459 } 460 461 DPRINTF("val=0x%x", val, 0, 0, 0); 462 axe_lock_mii(sc); 463 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 464 axe_unlock_mii(sc); 465 if (err) { 466 aprint_error_dev(sc->axe_dev, "media change failed\n"); 467 return; 468 } 469 } 470 471 static void 472 axe_setmulti(struct axe_softc *sc) 473 { 474 AXEHIST_FUNC(); AXEHIST_CALLED(); 475 struct ifnet *ifp = &sc->sc_if; 476 struct ether_multi *enm; 477 struct ether_multistep step; 478 uint32_t h = 0; 479 uint16_t rxmode; 480 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 481 482 if (sc->axe_dying) 483 return; 484 485 axe_lock_mii(sc); 486 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, (void *)&rxmode); 487 rxmode = le16toh(rxmode); 488 489 rxmode &= 490 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 491 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 492 493 rxmode |= 494 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 495 496 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 497 if (ifp->if_flags & IFF_PROMISC) 498 rxmode |= AXE_RXCMD_PROMISC; 499 goto allmulti; 500 } 501 502 /* Now program new ones */ 503 ETHER_FIRST_MULTI(step, &sc->axe_ec, enm); 504 while (enm != NULL) { 505 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 506 ETHER_ADDR_LEN) != 0) 507 goto allmulti; 508 509 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 510 hashtbl[h >> 3] |= 1U << (h & 7); 511 ETHER_NEXT_MULTI(step, enm); 512 } 513 ifp->if_flags &= ~IFF_ALLMULTI; 514 rxmode |= AXE_RXCMD_MULTICAST; 515 516 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 517 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 518 axe_unlock_mii(sc); 519 return; 520 521 allmulti: 522 ifp->if_flags |= IFF_ALLMULTI; 523 rxmode |= AXE_RXCMD_ALLMULTI; 524 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 525 axe_unlock_mii(sc); 526 } 527 528 529 static void 530 axe_reset(struct axe_softc *sc) 531 { 532 533 if (sc->axe_dying) 534 return; 535 536 /* 537 * softnet_lock can be taken when NET_MPAFE is not defined when calling 538 * if_addr_init -> if_init. This doesn't mixe well with the 539 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 540 * can fire during the wait and attempt to take softnet_lock and then 541 * block the softclk thread meaing the wait never ends. 542 */ 543 #ifndef NET_MPSAFE 544 /* XXX What to reset? */ 545 546 /* Wait a little while for the chip to get its brains in order. */ 547 DELAY(1000); 548 #else 549 axe_lock_mii(sc); 550 551 if (sc->axe_flags & AX178) { 552 axe_ax88178_init(sc); 553 } else if (sc->axe_flags & AX772) { 554 axe_ax88772_init(sc); 555 } else if (sc->axe_flags & AX772A) { 556 axe_ax88772a_init(sc); 557 } else if (sc->axe_flags & AX772B) { 558 axe_ax88772b_init(sc); 559 } 560 axe_unlock_mii(sc); 561 #endif 562 } 563 564 static int 565 axe_get_phyno(struct axe_softc *sc, int sel) 566 { 567 int phyno; 568 569 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 570 case PHY_TYPE_100_HOME: 571 /* FALLTHROUGH */ 572 case PHY_TYPE_GIG: 573 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 574 break; 575 case PHY_TYPE_SPECIAL: 576 /* FALLTHROUGH */ 577 case PHY_TYPE_RSVD: 578 /* FALLTHROUGH */ 579 case PHY_TYPE_NON_SUP: 580 /* FALLTHROUGH */ 581 default: 582 phyno = -1; 583 break; 584 } 585 586 return phyno; 587 } 588 589 #define AXE_GPIO_WRITE(x, y) do { \ 590 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 591 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 592 } while (0) 593 594 static void 595 axe_ax88178_init(struct axe_softc *sc) 596 { 597 AXEHIST_FUNC(); AXEHIST_CALLED(); 598 int gpio0, ledmode, phymode; 599 uint16_t eeprom, val; 600 601 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 602 /* XXX magic */ 603 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 604 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 605 606 eeprom = le16toh(eeprom); 607 608 DPRINTF("EEPROM is 0x%x", eeprom, 0, 0, 0); 609 610 /* if EEPROM is invalid we have to use to GPIO0 */ 611 if (eeprom == 0xffff) { 612 phymode = AXE_PHY_MODE_MARVELL; 613 gpio0 = 1; 614 ledmode = 0; 615 } else { 616 phymode = eeprom & 0x7f; 617 gpio0 = (eeprom & 0x80) ? 0 : 1; 618 ledmode = eeprom >> 8; 619 } 620 621 DPRINTF("use gpio0: %d, phymode %d", gpio0, phymode, 0, 0); 622 623 /* Program GPIOs depending on PHY hardware. */ 624 switch (phymode) { 625 case AXE_PHY_MODE_MARVELL: 626 if (gpio0 == 1) { 627 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 628 hz / 32); 629 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 630 hz / 32); 631 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 632 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 633 hz / 32); 634 } else { 635 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 636 AXE_GPIO1_EN, hz / 3); 637 if (ledmode == 1) { 638 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 639 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 640 hz / 3); 641 } else { 642 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 643 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 644 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 645 AXE_GPIO2_EN, hz / 4); 646 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 647 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 648 } 649 } 650 break; 651 case AXE_PHY_MODE_CICADA: 652 case AXE_PHY_MODE_CICADA_V2: 653 case AXE_PHY_MODE_CICADA_V2_ASIX: 654 if (gpio0 == 1) 655 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 656 AXE_GPIO0_EN, hz / 32); 657 else 658 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 659 AXE_GPIO1_EN, hz / 32); 660 break; 661 case AXE_PHY_MODE_AGERE: 662 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 663 AXE_GPIO1_EN, hz / 32); 664 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 665 AXE_GPIO2_EN, hz / 32); 666 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 667 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 668 AXE_GPIO2_EN, hz / 32); 669 break; 670 case AXE_PHY_MODE_REALTEK_8211CL: 671 case AXE_PHY_MODE_REALTEK_8211BN: 672 case AXE_PHY_MODE_REALTEK_8251CL: 673 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 674 AXE_GPIO1 | AXE_GPIO1_EN; 675 AXE_GPIO_WRITE(val, hz / 32); 676 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 677 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 678 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 679 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 680 axe_miibus_writereg_locked(sc->axe_dev, 681 sc->axe_phyno, 0x1F, 0x0005); 682 axe_miibus_writereg_locked(sc->axe_dev, 683 sc->axe_phyno, 0x0C, 0x0000); 684 val = axe_miibus_readreg_locked(sc->axe_dev, 685 sc->axe_phyno, 0x0001); 686 axe_miibus_writereg_locked(sc->axe_dev, 687 sc->axe_phyno, 0x01, val | 0x0080); 688 axe_miibus_writereg_locked(sc->axe_dev, 689 sc->axe_phyno, 0x1F, 0x0000); 690 } 691 break; 692 default: 693 /* Unknown PHY model or no need to program GPIOs. */ 694 break; 695 } 696 697 /* soft reset */ 698 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 699 usbd_delay_ms(sc->axe_udev, 150); 700 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 701 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 702 usbd_delay_ms(sc->axe_udev, 150); 703 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 704 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 705 usbd_delay_ms(sc->axe_udev, 10); 706 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 707 } 708 709 static void 710 axe_ax88772_init(struct axe_softc *sc) 711 { 712 AXEHIST_FUNC(); AXEHIST_CALLED(); 713 714 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 715 usbd_delay_ms(sc->axe_udev, 40); 716 717 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 718 /* ask for the embedded PHY */ 719 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 720 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 721 usbd_delay_ms(sc->axe_udev, 10); 722 723 /* power down and reset state, pin reset state */ 724 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 725 usbd_delay_ms(sc->axe_udev, 60); 726 727 /* power down/reset state, pin operating state */ 728 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 729 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 730 usbd_delay_ms(sc->axe_udev, 150); 731 732 /* power up, reset */ 733 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 734 735 /* power up, operating */ 736 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 737 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 738 } else { 739 /* ask for external PHY */ 740 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 741 NULL); 742 usbd_delay_ms(sc->axe_udev, 10); 743 744 /* power down internal PHY */ 745 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 746 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 747 } 748 749 usbd_delay_ms(sc->axe_udev, 150); 750 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 751 } 752 753 static int 754 axe_ifflags_cb(struct ethercom *ec) 755 { 756 struct ifnet *ifp = &ec->ec_if; 757 struct axe_softc *sc = ifp->if_softc; 758 int rc = 0; 759 760 mutex_enter(&sc->axe_lock); 761 int change = ifp->if_flags ^ sc->axe_if_flags; 762 sc->axe_if_flags = ifp->if_flags; 763 764 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 765 rc = ENETRESET; 766 goto out; 767 } 768 769 if ((change & IFF_PROMISC) != 0) { 770 axe_setmulti(sc); 771 } 772 773 out: 774 mutex_exit(&sc->axe_lock); 775 776 return rc; 777 } 778 779 static void 780 axe_ax88772_phywake(struct axe_softc *sc) 781 { 782 AXEHIST_FUNC(); AXEHIST_CALLED(); 783 784 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 785 /* Manually select internal(embedded) PHY - MAC mode. */ 786 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 787 AXE_SW_PHY_SELECT_EMBEDDED, 788 NULL); 789 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 790 } else { 791 /* 792 * Manually select external PHY - MAC mode. 793 * Reverse MII/RMII is for AX88772A PHY mode. 794 */ 795 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 796 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 797 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 798 } 799 800 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 801 AXE_SW_RESET_IPRL, NULL); 802 803 /* T1 = min 500ns everywhere */ 804 usbd_delay_ms(sc->axe_udev, 150); 805 806 /* Take PHY out of power down. */ 807 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 808 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 809 } else { 810 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 811 } 812 813 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 814 usbd_delay_ms(sc->axe_udev, 600); 815 816 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 817 818 /* T3 = 500ns everywhere */ 819 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 820 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 821 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 822 } 823 824 static void 825 axe_ax88772a_init(struct axe_softc *sc) 826 { 827 AXEHIST_FUNC(); AXEHIST_CALLED(); 828 829 /* Reload EEPROM. */ 830 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 831 axe_ax88772_phywake(sc); 832 /* Stop MAC. */ 833 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 834 } 835 836 static void 837 axe_ax88772b_init(struct axe_softc *sc) 838 { 839 AXEHIST_FUNC(); AXEHIST_CALLED(); 840 uint16_t eeprom; 841 int i; 842 843 /* Reload EEPROM. */ 844 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 845 846 /* 847 * Save PHY power saving configuration(high byte) and 848 * clear EEPROM checksum value(low byte). 849 */ 850 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 851 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 852 853 /* 854 * Auto-loaded default station address from internal ROM is 855 * 00:00:00:00:00:00 such that an explicit access to EEPROM 856 * is required to get real station address. 857 */ 858 uint8_t *eaddr = sc->axe_enaddr; 859 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 860 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 861 &eeprom); 862 eeprom = le16toh(eeprom); 863 *eaddr++ = (uint8_t)(eeprom & 0xFF); 864 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 865 } 866 /* Wakeup PHY. */ 867 axe_ax88772_phywake(sc); 868 /* Stop MAC. */ 869 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 870 } 871 872 #undef AXE_GPIO_WRITE 873 874 /* 875 * Probe for a AX88172 chip. 876 */ 877 int 878 axe_match(device_t parent, cfdata_t match, void *aux) 879 { 880 struct usb_attach_arg *uaa = aux; 881 882 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 883 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 884 } 885 886 /* 887 * Attach the interface. Allocate softc structures, do ifmedia 888 * setup and ethernet/BPF attach. 889 */ 890 void 891 axe_attach(device_t parent, device_t self, void *aux) 892 { 893 AXEHIST_FUNC(); AXEHIST_CALLED(); 894 struct axe_softc *sc = device_private(self); 895 struct usb_attach_arg *uaa = aux; 896 struct usbd_device *dev = uaa->uaa_device; 897 usbd_status err; 898 usb_interface_descriptor_t *id; 899 usb_endpoint_descriptor_t *ed; 900 struct mii_data *mii; 901 char *devinfop; 902 const char *devname = device_xname(self); 903 struct ifnet *ifp; 904 int i, s; 905 906 aprint_naive("\n"); 907 aprint_normal("\n"); 908 909 sc->axe_dev = self; 910 sc->axe_udev = dev; 911 912 devinfop = usbd_devinfo_alloc(dev, 0); 913 aprint_normal_dev(self, "%s\n", devinfop); 914 usbd_devinfo_free(devinfop); 915 916 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 917 if (err) { 918 aprint_error_dev(self, "failed to set configuration" 919 ", err=%s\n", usbd_errstr(err)); 920 return; 921 } 922 923 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 924 925 mutex_init(&sc->axe_lock, MUTEX_DEFAULT, IPL_NONE); 926 mutex_init(&sc->axe_txlock, MUTEX_DEFAULT, IPL_SOFTUSB); 927 mutex_init(&sc->axe_rxlock, MUTEX_DEFAULT, IPL_SOFTUSB); 928 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 929 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 930 931 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 932 if (err) { 933 aprint_error_dev(self, "getting interface handle failed\n"); 934 return; 935 } 936 937 sc->axe_product = uaa->uaa_product; 938 sc->axe_vendor = uaa->uaa_vendor; 939 940 id = usbd_get_interface_descriptor(sc->axe_iface); 941 942 /* decide on what our bufsize will be */ 943 if (AXE_IS_178_FAMILY(sc)) 944 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 945 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 946 else 947 sc->axe_bufsz = AXE_172_BUFSZ; 948 949 sc->axe_ed[AXE_ENDPT_RX] = -1; 950 sc->axe_ed[AXE_ENDPT_TX] = -1; 951 sc->axe_ed[AXE_ENDPT_INTR] = -1; 952 953 /* Find endpoints. */ 954 for (i = 0; i < id->bNumEndpoints; i++) { 955 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 956 if (ed == NULL) { 957 aprint_error_dev(self, "couldn't get ep %d\n", i); 958 return; 959 } 960 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 961 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 962 963 if (dir == UE_DIR_IN && xt == UE_BULK && 964 sc->axe_ed[AXE_ENDPT_RX] == -1) { 965 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 966 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 967 sc->axe_ed[AXE_ENDPT_TX] == -1) { 968 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 969 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 970 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 971 } 972 } 973 974 s = splnet(); 975 976 /* We need the PHYID for init dance in some cases */ 977 axe_lock_mii(sc); 978 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, (void *)&sc->axe_phyaddrs); 979 980 DPRINTF(" phyaddrs[0]: %x phyaddrs[1]: %x", 981 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 982 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 983 if (sc->axe_phyno == -1) 984 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 985 if (sc->axe_phyno == -1) { 986 DPRINTF(" no valid PHY address found, assuming PHY address 0", 987 0, 0, 0, 0); 988 sc->axe_phyno = 0; 989 } 990 991 /* Initialize controller and get station address. */ 992 993 if (sc->axe_flags & AX178) { 994 axe_ax88178_init(sc); 995 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 996 } else if (sc->axe_flags & AX772) { 997 axe_ax88772_init(sc); 998 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 999 } else if (sc->axe_flags & AX772A) { 1000 axe_ax88772a_init(sc); 1001 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 1002 } else if (sc->axe_flags & AX772B) { 1003 axe_ax88772b_init(sc); 1004 } else 1005 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 1006 1007 /* 1008 * Fetch IPG values. 1009 */ 1010 if (sc->axe_flags & (AX772A | AX772B)) { 1011 /* Set IPG values. */ 1012 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 1013 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 1014 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1015 } else 1016 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs); 1017 1018 axe_unlock_mii(sc); 1019 1020 /* 1021 * An ASIX chip was detected. Inform the world. 1022 */ 1023 aprint_normal_dev(self, "Ethernet address %s\n", 1024 ether_sprintf(sc->axe_enaddr)); 1025 1026 /* Initialize interface info.*/ 1027 ifp = &sc->sc_if; 1028 ifp->if_softc = sc; 1029 strncpy(ifp->if_xname, devname, IFNAMSIZ); 1030 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1031 ifp->if_ioctl = axe_ioctl; 1032 ifp->if_start = axe_start; 1033 ifp->if_init = axe_init; 1034 ifp->if_stop = axe_stop; 1035 ifp->if_watchdog = axe_watchdog; 1036 1037 IFQ_SET_READY(&ifp->if_snd); 1038 1039 if (AXE_IS_178_FAMILY(sc)) 1040 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1041 if (sc->axe_flags & AX772B) { 1042 ifp->if_capabilities = 1043 IFCAP_CSUM_IPv4_Rx | 1044 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1045 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1046 /* 1047 * Checksum offloading of AX88772B also works with VLAN 1048 * tagged frames but there is no way to take advantage 1049 * of the feature because vlan(4) assumes 1050 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1051 * support checksum offloading with VLAN. VLAN hardware 1052 * tagging support of AX88772B is very limited so it's 1053 * not possible to announce IFCAP_VLAN_HWTAGGING. 1054 */ 1055 } 1056 u_int adv_pause; 1057 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1058 adv_pause = MIIF_DOPAUSE; 1059 else 1060 adv_pause = 0; 1061 adv_pause = 0; 1062 1063 /* Initialize MII/media info. */ 1064 mii = &sc->axe_mii; 1065 mii->mii_ifp = ifp; 1066 mii->mii_readreg = axe_miibus_readreg; 1067 mii->mii_writereg = axe_miibus_writereg; 1068 mii->mii_statchg = axe_miibus_statchg; 1069 mii->mii_flags = MIIF_AUTOTSLEEP; 1070 1071 sc->axe_ec.ec_mii = mii; 1072 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1073 1074 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1075 adv_pause); 1076 1077 if (LIST_EMPTY(&mii->mii_phys)) { 1078 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1079 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1080 } else 1081 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1082 1083 /* Attach the interface. */ 1084 if_attach(ifp); 1085 ether_ifattach(ifp, sc->axe_enaddr); 1086 ether_set_ifflags_cb(&sc->axe_ec, axe_ifflags_cb); 1087 1088 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1089 RND_TYPE_NET, RND_FLAG_DEFAULT); 1090 1091 callout_init(&sc->axe_stat_ch, 0); 1092 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1093 1094 sc->axe_attached = true; 1095 splx(s); 1096 1097 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1098 1099 if (!pmf_device_register(self, NULL, NULL)) 1100 aprint_error_dev(self, "couldn't establish power handler\n"); 1101 } 1102 1103 int 1104 axe_detach(device_t self, int flags) 1105 { 1106 AXEHIST_FUNC(); AXEHIST_CALLED(); 1107 struct axe_softc *sc = device_private(self); 1108 int s; 1109 struct ifnet *ifp = &sc->sc_if; 1110 1111 /* Detached before attached finished, so just bail out. */ 1112 if (!sc->axe_attached) 1113 return 0; 1114 1115 pmf_device_deregister(self); 1116 1117 sc->axe_dying = true; 1118 1119 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1120 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1121 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1122 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1123 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1124 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1125 1126 callout_halt(&sc->axe_stat_ch, NULL); 1127 usb_rem_task_wait(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER, 1128 NULL); 1129 1130 s = splusb(); 1131 1132 if (ifp->if_flags & IFF_RUNNING) 1133 axe_stop(ifp, 1); 1134 1135 1136 if (--sc->axe_refcnt >= 0) { 1137 /* Wait for processes to go away. */ 1138 usb_detach_waitold(sc->axe_dev); 1139 } 1140 1141 callout_destroy(&sc->axe_stat_ch); 1142 mutex_destroy(&sc->axe_lock); 1143 mutex_destroy(&sc->axe_txlock); 1144 mutex_destroy(&sc->axe_rxlock); 1145 mutex_destroy(&sc->axe_mii_lock); 1146 rnd_detach_source(&sc->rnd_source); 1147 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1148 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1149 ether_ifdetach(ifp); 1150 if_detach(ifp); 1151 1152 #ifdef DIAGNOSTIC 1153 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1154 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1155 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1156 aprint_debug_dev(self, "detach has active endpoints\n"); 1157 #endif 1158 1159 sc->axe_attached = false; 1160 1161 splx(s); 1162 1163 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1164 1165 return 0; 1166 } 1167 1168 int 1169 axe_activate(device_t self, devact_t act) 1170 { 1171 AXEHIST_FUNC(); AXEHIST_CALLED(); 1172 struct axe_softc *sc = device_private(self); 1173 1174 switch (act) { 1175 case DVACT_DEACTIVATE: 1176 if_deactivate(&sc->axe_ec.ec_if); 1177 sc->axe_dying = true; 1178 return 0; 1179 default: 1180 return EOPNOTSUPP; 1181 } 1182 } 1183 1184 static int 1185 axe_rx_list_init(struct axe_softc *sc) 1186 { 1187 AXEHIST_FUNC(); AXEHIST_CALLED(); 1188 1189 struct axe_cdata *cd; 1190 struct axe_chain *c; 1191 int i; 1192 1193 cd = &sc->axe_cdata; 1194 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1195 c = &cd->axe_rx_chain[i]; 1196 c->axe_sc = sc; 1197 c->axe_idx = i; 1198 if (c->axe_xfer == NULL) { 1199 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1200 sc->axe_bufsz, 0, 0, &c->axe_xfer); 1201 if (err) 1202 return err; 1203 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1204 } 1205 } 1206 1207 return 0; 1208 } 1209 1210 static void 1211 axe_rx_list_free(struct axe_softc *sc) 1212 { 1213 /* Free RX resources */ 1214 for (size_t i = 0; i < AXE_RX_LIST_CNT; i++) { 1215 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1216 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1217 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1218 } 1219 } 1220 } 1221 1222 static int 1223 axe_tx_list_init(struct axe_softc *sc) 1224 { 1225 AXEHIST_FUNC(); AXEHIST_CALLED(); 1226 struct axe_cdata *cd; 1227 struct axe_chain *c; 1228 int i; 1229 1230 cd = &sc->axe_cdata; 1231 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1232 c = &cd->axe_tx_chain[i]; 1233 c->axe_sc = sc; 1234 c->axe_idx = i; 1235 if (c->axe_xfer == NULL) { 1236 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1237 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1238 &c->axe_xfer); 1239 if (err) 1240 return err; 1241 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1242 } 1243 } 1244 1245 return 0; 1246 } 1247 1248 static void 1249 axe_tx_list_free(struct axe_softc *sc) 1250 { 1251 /* Free TX resources */ 1252 for (size_t i = 0; i < AXE_TX_LIST_CNT; i++) { 1253 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1254 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1255 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1256 } 1257 } 1258 } 1259 1260 /* 1261 * A frame has been uploaded: pass the resulting mbuf chain up to 1262 * the higher level protocols. 1263 */ 1264 static void 1265 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1266 { 1267 AXEHIST_FUNC(); AXEHIST_CALLED(); 1268 struct axe_softc *sc; 1269 struct axe_chain *c; 1270 struct ifnet *ifp; 1271 uint8_t *buf; 1272 uint32_t total_len; 1273 struct mbuf *m; 1274 int s; 1275 1276 c = (struct axe_chain *)priv; 1277 sc = c->axe_sc; 1278 buf = c->axe_buf; 1279 ifp = &sc->sc_if; 1280 1281 if (sc->axe_dying) 1282 return; 1283 1284 if ((ifp->if_flags & IFF_RUNNING) == 0) 1285 return; 1286 1287 if (status != USBD_NORMAL_COMPLETION) { 1288 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1289 return; 1290 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1291 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1292 usbd_errstr(status)); 1293 } 1294 if (status == USBD_STALLED) 1295 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1296 goto done; 1297 } 1298 1299 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1300 1301 do { 1302 u_int pktlen = 0; 1303 u_int rxlen = 0; 1304 int flags = 0; 1305 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1306 struct axe_sframe_hdr hdr; 1307 1308 if (total_len < sizeof(hdr)) { 1309 ifp->if_ierrors++; 1310 goto done; 1311 } 1312 1313 memcpy(&hdr, buf, sizeof(hdr)); 1314 1315 DPRINTFN(20, "total_len %#x len %x ilen %#x", 1316 total_len, 1317 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1318 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1319 1320 total_len -= sizeof(hdr); 1321 buf += sizeof(hdr); 1322 1323 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1324 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1325 AXE_RH1M_RXLEN_MASK) { 1326 ifp->if_ierrors++; 1327 goto done; 1328 } 1329 1330 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1331 if (total_len < rxlen) { 1332 pktlen = total_len; 1333 total_len = 0; 1334 } else { 1335 pktlen = rxlen; 1336 rxlen = roundup2(rxlen, 2); 1337 total_len -= rxlen; 1338 } 1339 1340 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1341 struct axe_csum_hdr csum_hdr; 1342 1343 if (total_len < sizeof(csum_hdr)) { 1344 ifp->if_ierrors++; 1345 goto done; 1346 } 1347 1348 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1349 1350 csum_hdr.len = le16toh(csum_hdr.len); 1351 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1352 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1353 1354 DPRINTFN(20, "total_len %#x len %#x ilen %#x" 1355 " cstatus %#x", total_len, 1356 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1357 1358 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1359 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1360 sc->sc_lenmask) { 1361 /* we lost sync */ 1362 ifp->if_ierrors++; 1363 DPRINTFN(20, "len %#x ilen %#x lenmask %#x err", 1364 AXE_CSUM_RXBYTES(csum_hdr.len), 1365 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1366 sc->sc_lenmask, 0); 1367 goto done; 1368 } 1369 /* 1370 * Get total transferred frame length including 1371 * checksum header. The length should be multiple 1372 * of 4. 1373 */ 1374 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1375 u_int len = sizeof(csum_hdr) + pktlen; 1376 len = (len + 3) & ~3; 1377 if (total_len < len) { 1378 DPRINTFN(20, "total_len %#x < len %#x", 1379 total_len, len, 0, 0); 1380 /* invalid length */ 1381 ifp->if_ierrors++; 1382 goto done; 1383 } 1384 buf += sizeof(csum_hdr); 1385 1386 const uint16_t cstatus = csum_hdr.cstatus; 1387 1388 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1389 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1390 flags |= M_CSUM_TCP_UDP_BAD; 1391 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1392 flags |= M_CSUM_IPv4_BAD; 1393 1394 const uint16_t l4type = 1395 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1396 1397 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1398 flags |= M_CSUM_TCPv4; 1399 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1400 flags |= M_CSUM_UDPv4; 1401 } 1402 if (total_len < len) { 1403 pktlen = total_len; 1404 total_len = 0; 1405 } else { 1406 total_len -= len; 1407 rxlen = len - sizeof(csum_hdr); 1408 } 1409 DPRINTFN(20, "total_len %#x len %#x pktlen %#x" 1410 " rxlen %#x", total_len, len, pktlen, rxlen); 1411 } else { /* AX172 */ 1412 pktlen = rxlen = total_len; 1413 total_len = 0; 1414 } 1415 1416 MGETHDR(m, M_DONTWAIT, MT_DATA); 1417 if (m == NULL) { 1418 ifp->if_ierrors++; 1419 goto done; 1420 } 1421 1422 if (pktlen > MHLEN - ETHER_ALIGN) { 1423 MCLGET(m, M_DONTWAIT); 1424 if ((m->m_flags & M_EXT) == 0) { 1425 m_freem(m); 1426 ifp->if_ierrors++; 1427 goto done; 1428 } 1429 } 1430 m->m_data += ETHER_ALIGN; 1431 1432 ifp->if_ipackets++; 1433 m->m_pkthdr.rcvif = ifp; 1434 m->m_pkthdr.len = m->m_len = pktlen; 1435 m->m_pkthdr.csum_flags = flags; 1436 1437 memcpy(mtod(m, uint8_t *), buf, pktlen); 1438 buf += rxlen; 1439 1440 DPRINTFN(10, "deliver %d (%#x)", m->m_len, m->m_len, 0, 0); 1441 s = splnet(); 1442 1443 bpf_mtap(ifp, m); 1444 1445 (*(ifp)->if_input)((ifp), (m)); 1446 1447 splx(s); 1448 1449 } while (total_len > 0); 1450 1451 done: 1452 1453 /* Setup new transfer. */ 1454 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1455 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1456 usbd_transfer(xfer); 1457 1458 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1459 } 1460 1461 /* 1462 * A frame was downloaded to the chip. It's safe for us to clean up 1463 * the list buffers. 1464 */ 1465 1466 static void 1467 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1468 { 1469 AXEHIST_FUNC(); AXEHIST_CALLED(); 1470 struct axe_chain *c = priv; 1471 struct axe_softc *sc = c->axe_sc; 1472 struct ifnet *ifp = &sc->sc_if; 1473 int s; 1474 1475 1476 if (sc->axe_dying) 1477 return; 1478 1479 s = splnet(); 1480 1481 ifp->if_timer = 0; 1482 ifp->if_flags &= ~IFF_OACTIVE; 1483 1484 if (status != USBD_NORMAL_COMPLETION) { 1485 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1486 splx(s); 1487 return; 1488 } 1489 ifp->if_oerrors++; 1490 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1491 usbd_errstr(status)); 1492 if (status == USBD_STALLED) 1493 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1494 splx(s); 1495 return; 1496 } 1497 ifp->if_opackets++; 1498 1499 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1500 axe_start(ifp); 1501 1502 splx(s); 1503 } 1504 1505 static void 1506 axe_tick(void *xsc) 1507 { 1508 AXEHIST_FUNC(); AXEHIST_CALLED(); 1509 struct axe_softc *sc = xsc; 1510 1511 if (sc == NULL) 1512 return; 1513 1514 if (sc->axe_dying) 1515 return; 1516 1517 /* Perform periodic stuff in process context */ 1518 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1519 } 1520 1521 static void 1522 axe_tick_task(void *xsc) 1523 { 1524 AXEHIST_FUNC(); AXEHIST_CALLED(); 1525 int s; 1526 struct axe_softc *sc = xsc; 1527 struct ifnet *ifp; 1528 struct mii_data *mii; 1529 1530 if (sc == NULL) 1531 return; 1532 1533 if (sc->axe_dying) 1534 return; 1535 1536 ifp = &sc->sc_if; 1537 mii = &sc->axe_mii; 1538 1539 if (mii == NULL) 1540 return; 1541 1542 s = splnet(); 1543 1544 mii_tick(mii); 1545 if (sc->axe_link == 0 && 1546 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1547 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1548 DPRINTF("got link", 0, 0, 0, 0); 1549 sc->axe_link++; 1550 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1551 axe_start(ifp); 1552 } 1553 1554 callout_schedule(&sc->axe_stat_ch, hz); 1555 1556 splx(s); 1557 } 1558 1559 static int 1560 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1561 { 1562 struct ifnet *ifp = &sc->sc_if; 1563 struct axe_chain *c; 1564 usbd_status err; 1565 int length, boundary; 1566 1567 c = &sc->axe_cdata.axe_tx_chain[idx]; 1568 1569 /* 1570 * Copy the mbuf data into a contiguous buffer, leaving two 1571 * bytes at the beginning to hold the frame length. 1572 */ 1573 if (AXE_IS_178_FAMILY(sc)) { 1574 struct axe_sframe_hdr hdr; 1575 1576 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1577 1578 hdr.len = htole16(m->m_pkthdr.len); 1579 hdr.ilen = ~hdr.len; 1580 1581 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1582 length = sizeof(hdr); 1583 1584 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1585 length += m->m_pkthdr.len; 1586 1587 if ((length % boundary) == 0) { 1588 hdr.len = 0x0000; 1589 hdr.ilen = 0xffff; 1590 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1591 length += sizeof(hdr); 1592 } 1593 } else { 1594 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1595 length = m->m_pkthdr.len; 1596 } 1597 1598 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1599 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1600 1601 /* Transmit */ 1602 err = usbd_transfer(c->axe_xfer); 1603 if (err != USBD_IN_PROGRESS) { 1604 axe_stop(ifp, 0); 1605 return EIO; 1606 } 1607 1608 sc->axe_cdata.axe_tx_cnt++; 1609 1610 return 0; 1611 } 1612 1613 1614 static void 1615 axe_csum_cfg(struct axe_softc *sc) 1616 { 1617 struct ifnet *ifp = &sc->sc_if; 1618 uint16_t csum1, csum2; 1619 1620 if ((sc->axe_flags & AX772B) != 0) { 1621 csum1 = 0; 1622 csum2 = 0; 1623 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1624 csum1 |= AXE_TXCSUM_IP; 1625 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1626 csum1 |= AXE_TXCSUM_TCP; 1627 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1628 csum1 |= AXE_TXCSUM_UDP; 1629 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1630 csum1 |= AXE_TXCSUM_TCPV6; 1631 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1632 csum1 |= AXE_TXCSUM_UDPV6; 1633 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1634 csum1 = 0; 1635 csum2 = 0; 1636 1637 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1638 csum1 |= AXE_RXCSUM_IP; 1639 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1640 csum1 |= AXE_RXCSUM_TCP; 1641 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1642 csum1 |= AXE_RXCSUM_UDP; 1643 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1644 csum1 |= AXE_RXCSUM_TCPV6; 1645 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1646 csum1 |= AXE_RXCSUM_UDPV6; 1647 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1648 } 1649 } 1650 1651 static void 1652 axe_start(struct ifnet *ifp) 1653 { 1654 struct axe_softc *sc = ifp->if_softc; 1655 1656 mutex_enter(&sc->axe_txlock); 1657 axe_start_locked(ifp); 1658 mutex_exit(&sc->axe_txlock); 1659 } 1660 1661 static void 1662 axe_start_locked(struct ifnet *ifp) 1663 { 1664 struct axe_softc *sc = ifp->if_softc; 1665 struct mbuf *m; 1666 1667 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) 1668 return; 1669 1670 IFQ_POLL(&ifp->if_snd, m); 1671 if (m == NULL) { 1672 return; 1673 } 1674 1675 if (axe_encap(sc, m, 0)) { 1676 return; 1677 } 1678 IFQ_DEQUEUE(&ifp->if_snd, m); 1679 1680 /* 1681 * If there's a BPF listener, bounce a copy of this frame 1682 * to him. 1683 */ 1684 bpf_mtap(ifp, m); 1685 m_freem(m); 1686 1687 ifp->if_flags |= IFF_OACTIVE; 1688 1689 /* 1690 * Set a timeout in case the chip goes out to lunch. 1691 */ 1692 ifp->if_timer = 5; 1693 1694 return; 1695 } 1696 1697 static int 1698 axe_init(struct ifnet *ifp) 1699 { 1700 struct axe_softc *sc = ifp->if_softc; 1701 1702 mutex_enter(&sc->axe_lock); 1703 int ret = axe_init_locked(ifp); 1704 mutex_exit(&sc->axe_lock); 1705 1706 return ret; 1707 } 1708 1709 static int 1710 axe_init_locked(struct ifnet *ifp) 1711 { 1712 AXEHIST_FUNC(); AXEHIST_CALLED(); 1713 struct axe_softc *sc = ifp->if_softc; 1714 usbd_status err; 1715 int rxmode; 1716 int i, error; 1717 1718 axe_stop_locked(ifp, 0); 1719 1720 /* 1721 * Cancel pending I/O and free all RX/TX buffers. 1722 */ 1723 axe_reset(sc); 1724 1725 axe_lock_mii(sc); 1726 1727 #if 0 1728 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1729 AX_GPIO_GPO2EN, 5, in_pm); 1730 #endif 1731 /* Set MAC address and transmitter IPG values. */ 1732 if (AXE_IS_178_FAMILY(sc)) { 1733 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1734 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1735 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1736 } else { 1737 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1738 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1739 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1740 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1741 } 1742 if (AXE_IS_178_FAMILY(sc)) { 1743 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1744 if ((sc->axe_flags & AX772B) != 0 && 1745 (ifp->if_capenable & AX_RXCSUM) != 0) { 1746 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1747 sc->axe_flags |= AXCSUM_FRAME; 1748 } else { 1749 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1750 sc->axe_flags |= AXSTD_FRAME; 1751 } 1752 } 1753 1754 /* Configure TX/RX checksum offloading. */ 1755 axe_csum_cfg(sc); 1756 1757 if (sc->axe_flags & AX772B) { 1758 /* AX88772B uses different maximum frame burst configuration. */ 1759 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1760 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1761 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1762 } 1763 /* Enable receiver, set RX mode */ 1764 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1765 if (AXE_IS_178_FAMILY(sc)) { 1766 if (sc->axe_flags & AX772B) { 1767 /* 1768 * Select RX header format type 1. Aligning IP 1769 * header on 4 byte boundary is not needed when 1770 * checksum offloading feature is not used 1771 * because we always copy the received frame in 1772 * RX handler. When RX checksum offloading is 1773 * active, aligning IP header is required to 1774 * reflect actual frame length including RX 1775 * header size. 1776 */ 1777 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1778 if (sc->axe_flags & AXCSUM_FRAME) 1779 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1780 } else { 1781 /* 1782 * Default Rx buffer size is too small to get 1783 * maximum performance. 1784 */ 1785 #if 0 1786 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1787 /* Largest possible USB buffer size for AX88178 */ 1788 #endif 1789 rxmode |= AXE_178_RXCMD_MFB_16384; 1790 } 1791 } else { 1792 rxmode |= AXE_172_RXCMD_UNICAST; 1793 } 1794 1795 1796 /* If we want promiscuous mode, set the allframes bit. */ 1797 if (ifp->if_flags & IFF_PROMISC) 1798 rxmode |= AXE_RXCMD_PROMISC; 1799 1800 if (ifp->if_flags & IFF_BROADCAST) 1801 rxmode |= AXE_RXCMD_BROADCAST; 1802 1803 DPRINTF("rxmode 0x%#x", rxmode, 0, 0, 0); 1804 1805 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1806 axe_unlock_mii(sc); 1807 1808 /* Load the multicast filter. */ 1809 axe_setmulti(sc); 1810 1811 /* Open RX and TX pipes. */ 1812 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1813 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1814 if (err) { 1815 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1816 usbd_errstr(err)); 1817 error = EIO; 1818 goto fail; 1819 } 1820 1821 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1822 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1823 if (err) { 1824 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1825 usbd_errstr(err)); 1826 error = EIO; 1827 goto fail1; 1828 } 1829 1830 /* Init RX ring. */ 1831 if (axe_rx_list_init(sc) != 0) { 1832 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1833 error = ENOBUFS; 1834 goto fail2; 1835 } 1836 1837 /* Init TX ring. */ 1838 if (axe_tx_list_init(sc) != 0) { 1839 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1840 error = ENOBUFS; 1841 goto fail3; 1842 } 1843 1844 /* Start up the receive pipe. */ 1845 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1846 struct axe_chain *c = &sc->axe_cdata.axe_rx_chain[i]; 1847 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1848 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1849 usbd_transfer(c->axe_xfer); 1850 } 1851 1852 ifp->if_flags |= IFF_RUNNING; 1853 ifp->if_flags &= ~IFF_OACTIVE; 1854 1855 callout_schedule(&sc->axe_stat_ch, hz); 1856 1857 return 0; 1858 fail3: 1859 axe_rx_list_free(sc); 1860 fail2: 1861 usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1862 fail1: 1863 usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1864 fail: 1865 return error; 1866 } 1867 1868 static int 1869 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1870 { 1871 struct axe_softc *sc = ifp->if_softc; 1872 int s; 1873 int error = 0; 1874 1875 s = splnet(); 1876 error = ether_ioctl(ifp, cmd, data); 1877 splx(s); 1878 1879 if (error == ENETRESET) { 1880 error = 0; 1881 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1882 ; 1883 else if (ifp->if_flags & IFF_RUNNING) { 1884 mutex_enter(&sc->axe_lock); 1885 axe_setmulti(sc); 1886 mutex_exit(&sc->axe_lock); 1887 } 1888 } 1889 1890 return error; 1891 } 1892 1893 static void 1894 axe_watchdog(struct ifnet *ifp) 1895 { 1896 struct axe_softc *sc; 1897 struct axe_chain *c; 1898 usbd_status stat; 1899 int s; 1900 1901 sc = ifp->if_softc; 1902 1903 ifp->if_oerrors++; 1904 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1905 1906 s = splusb(); 1907 c = &sc->axe_cdata.axe_tx_chain[0]; 1908 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1909 axe_txeof(c->axe_xfer, c, stat); 1910 1911 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1912 axe_start(ifp); 1913 splx(s); 1914 } 1915 1916 /* 1917 * Stop the adapter and free any mbufs allocated to the 1918 * RX and TX lists. 1919 */ 1920 1921 static void 1922 axe_stop(struct ifnet *ifp, int disable) 1923 { 1924 struct axe_softc *sc = ifp->if_softc; 1925 1926 mutex_enter(&sc->axe_lock); 1927 axe_stop_locked(ifp, disable); 1928 mutex_exit(&sc->axe_lock); 1929 } 1930 1931 static void 1932 axe_stop_locked(struct ifnet *ifp, int disable) 1933 { 1934 struct axe_softc *sc = ifp->if_softc; 1935 usbd_status err; 1936 1937 ifp->if_timer = 0; 1938 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1939 1940 callout_stop(&sc->axe_stat_ch); 1941 1942 /* Stop transfers. */ 1943 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1944 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1945 if (err) { 1946 aprint_error_dev(sc->axe_dev, 1947 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1948 } 1949 } 1950 1951 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1952 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1953 if (err) { 1954 aprint_error_dev(sc->axe_dev, 1955 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1956 } 1957 } 1958 1959 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1960 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1961 if (err) { 1962 aprint_error_dev(sc->axe_dev, 1963 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1964 } 1965 } 1966 1967 axe_reset(sc); 1968 1969 axe_rx_list_free(sc); 1970 1971 axe_tx_list_free(sc); 1972 1973 /* Close pipes. */ 1974 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1975 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1976 if (err) { 1977 aprint_error_dev(sc->axe_dev, 1978 "close rx pipe failed: %s\n", usbd_errstr(err)); 1979 } 1980 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1981 } 1982 1983 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1984 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1985 if (err) { 1986 aprint_error_dev(sc->axe_dev, 1987 "close tx pipe failed: %s\n", usbd_errstr(err)); 1988 } 1989 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1990 } 1991 1992 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1993 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1994 if (err) { 1995 aprint_error_dev(sc->axe_dev, 1996 "close intr pipe failed: %s\n", usbd_errstr(err)); 1997 } 1998 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1999 } 2000 2001 sc->axe_link = 0; 2002 } 2003 2004 MODULE(MODULE_CLASS_DRIVER, if_axe, "bpf"); 2005 2006 #ifdef _MODULE 2007 #include "ioconf.c" 2008 #endif 2009 2010 static int 2011 if_axe_modcmd(modcmd_t cmd, void *aux) 2012 { 2013 int error = 0; 2014 2015 switch (cmd) { 2016 case MODULE_CMD_INIT: 2017 #ifdef _MODULE 2018 error = config_init_component(cfdriver_ioconf_axe, 2019 cfattach_ioconf_axe, cfdata_ioconf_axe); 2020 #endif 2021 return error; 2022 case MODULE_CMD_FINI: 2023 #ifdef _MODULE 2024 error = config_fini_component(cfdriver_ioconf_axe, 2025 cfattach_ioconf_axe, cfdata_ioconf_axe); 2026 #endif 2027 return error; 2028 default: 2029 return ENOTTY; 2030 } 2031 } 2032
Indexes created Wed Oct 01 18:09:54 GMT 2025