if_axe.c revision 1.67.4.13
1 /* $NetBSD: if_axe.c,v 1.67.4.13 2016/12/12 13:15:39 skrll Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.67.4.13 2016/12/12 13:15:39 skrll Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #endif 96 97 #include <sys/param.h> 98 #include <sys/bus.h> 99 #include <sys/device.h> 100 #include <sys/kernel.h> 101 #include <sys/mbuf.h> 102 #include <sys/module.h> 103 #include <sys/mutex.h> 104 #include <sys/socket.h> 105 #include <sys/sockio.h> 106 #include <sys/systm.h> 107 108 #include <sys/rndsource.h> 109 110 #include <net/if.h> 111 #include <net/if_dl.h> 112 #include <net/if_ether.h> 113 #include <net/if_media.h> 114 115 #include <net/bpf.h> 116 117 #include <dev/mii/mii.h> 118 #include <dev/mii/miivar.h> 119 120 #include <dev/usb/usb.h> 121 #include <dev/usb/usbhist.h> 122 #include <dev/usb/usbdi.h> 123 #include <dev/usb/usbdi_util.h> 124 #include <dev/usb/usbdivar.h> 125 #include <dev/usb/usbdevs.h> 126 127 #include <dev/usb/if_axereg.h> 128 129 /* 130 * AXE_178_MAX_FRAME_BURST 131 * max frame burst size for Ax88178 and Ax88772 132 * 0 2048 bytes 133 * 1 4096 bytes 134 * 2 8192 bytes 135 * 3 16384 bytes 136 * use the largest your system can handle without USB stalling. 137 * 138 * NB: 88772 parts appear to generate lots of input errors with 139 * a 2K rx buffer and 8K is only slightly faster than 4K on an 140 * EHCI port on a T42 so change at your own risk. 141 */ 142 #define AXE_178_MAX_FRAME_BURST 1 143 144 145 #ifdef USB_DEBUG 146 #ifndef AXE_DEBUG 147 #define axedebug 0 148 #else 149 static int axedebug = 20; 150 151 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 152 { 153 int err; 154 const struct sysctlnode *rnode; 155 const struct sysctlnode *cnode; 156 157 err = sysctl_createv(clog, 0, NULL, &rnode, 158 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 159 SYSCTL_DESCR("axe global controls"), 160 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 161 162 if (err) 163 goto fail; 164 165 /* control debugging printfs */ 166 err = sysctl_createv(clog, 0, &rnode, &cnode, 167 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 168 "debug", SYSCTL_DESCR("Enable debugging output"), 169 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 170 if (err) 171 goto fail; 172 173 return; 174 fail: 175 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 176 } 177 178 #endif /* AXE_DEBUG */ 179 #endif /* USB_DEBUG */ 180 181 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 182 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 183 #define AXEHIST_FUNC() USBHIST_FUNC() 184 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 185 186 /* 187 * Various supported device vendors/products. 188 */ 189 static const struct axe_type axe_devs[] = { 190 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 191 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 192 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 193 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 199 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 200 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 201 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 202 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 203 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 204 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 206 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 208 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 209 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 210 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 211 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 212 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 213 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 214 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 215 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 216 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 218 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 219 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 220 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 221 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 222 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 223 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 225 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 226 }; 227 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 228 229 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 230 { 0x8000, 0x8001, 2048 }, 231 { 0x8100, 0x8147, 4096 }, 232 { 0x8200, 0x81EB, 6144 }, 233 { 0x8300, 0x83D7, 8192 }, 234 { 0x8400, 0x851E, 16384 }, 235 { 0x8500, 0x8666, 20480 }, 236 { 0x8600, 0x87AE, 24576 }, 237 { 0x8700, 0x8A3D, 32768 } 238 }; 239 240 int axe_match(device_t, cfdata_t, void *); 241 void axe_attach(device_t, device_t, void *); 242 int axe_detach(device_t, int); 243 int axe_activate(device_t, devact_t); 244 245 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 246 axe_match, axe_attach, axe_detach, axe_activate); 247 248 static int axe_tx_list_init(struct axe_softc *); 249 #if 0 250 static void axe_tx_list_free(struct axe_softc *); 251 #endif 252 static int axe_rx_list_init(struct axe_softc *); 253 static void axe_rx_list_free(struct axe_softc *); 254 static int axe_encap(struct axe_softc *, struct mbuf *, int); 255 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 256 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 257 static void axe_tick(void *); 258 static void axe_tick_task(void *); 259 static void axe_start(struct ifnet *); 260 static void axe_start_locked(struct ifnet *); 261 static int axe_ioctl(struct ifnet *, u_long, void *); 262 static int axe_init(struct ifnet *); 263 static int axe_init_locked(struct ifnet *); 264 static void axe_stop(struct ifnet *, int); 265 static void axe_stop_locked(struct ifnet *, int); 266 static void axe_watchdog(struct ifnet *); 267 static int axe_miibus_readreg_locked(device_t, int, int); 268 static int axe_miibus_readreg(device_t, int, int); 269 static void axe_miibus_writereg_locked(device_t, int, int, int); 270 static void axe_miibus_writereg(device_t, int, int, int); 271 static void axe_miibus_statchg(struct ifnet *); 272 static int axe_cmd(struct axe_softc *, int, int, int, void *); 273 static void axe_reset(struct axe_softc *); 274 275 static void axe_setmulti(struct axe_softc *); 276 static void axe_lock_mii(struct axe_softc *); 277 static void axe_unlock_mii(struct axe_softc *); 278 279 static void axe_ax88178_init(struct axe_softc *); 280 static void axe_ax88772_init(struct axe_softc *); 281 282 /* Get exclusive access to the MII registers */ 283 static void 284 axe_lock_mii(struct axe_softc *sc) 285 { 286 287 sc->axe_refcnt++; 288 mutex_enter(&sc->axe_mii_lock); 289 } 290 291 static void 292 axe_unlock_mii(struct axe_softc *sc) 293 { 294 295 mutex_exit(&sc->axe_mii_lock); 296 if (--sc->axe_refcnt < 0) 297 usb_detach_wakeupold((sc->axe_dev)); 298 } 299 300 static int 301 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 302 { 303 AXEHIST_FUNC(); AXEHIST_CALLED(); 304 usb_device_request_t req; 305 usbd_status err; 306 307 KASSERT(mutex_owned(&sc->axe_mii_lock)); 308 309 if (sc->axe_dying) 310 return 0; 311 312 DPRINTFN(20, "cmd %#x index %#x val %#x", cmd, index, val, 0); 313 314 if (AXE_CMD_DIR(cmd)) 315 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 316 else 317 req.bmRequestType = UT_READ_VENDOR_DEVICE; 318 req.bRequest = AXE_CMD_CMD(cmd); 319 USETW(req.wValue, val); 320 USETW(req.wIndex, index); 321 USETW(req.wLength, AXE_CMD_LEN(cmd)); 322 323 err = usbd_do_request(sc->axe_udev, &req, buf); 324 325 if (err) { 326 DPRINTF("cmd %d err %d", cmd, err, 0, 0); 327 return -1; 328 } 329 return 0; 330 } 331 332 static int 333 axe_miibus_readreg_locked(device_t dev, int phy, int reg) 334 { 335 AXEHIST_FUNC(); AXEHIST_CALLED(); 336 struct axe_softc *sc = device_private(dev); 337 usbd_status err; 338 uint16_t val; 339 340 DPRINTFN(30, "phy 0x%x reg 0x%x\n", phy, reg, 0, 0); 341 342 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 343 344 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, (void *)&val); 345 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 346 if (err) { 347 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 348 return -1; 349 } 350 351 val = le16toh(val); 352 if (AXE_IS_772(sc) && reg == MII_BMSR) { 353 /* 354 * BMSR of AX88772 indicates that it supports extended 355 * capability but the extended status register is 356 * reserved for embedded ethernet PHY. So clear the 357 * extended capability bit of BMSR. 358 */ 359 val &= ~BMSR_EXTCAP; 360 } 361 362 DPRINTFN(30, "phy 0x%x reg 0x%x val %#x", phy, reg, val, 0); 363 364 return val; 365 } 366 367 static int 368 axe_miibus_readreg(device_t dev, int phy, int reg) 369 { 370 struct axe_softc *sc = device_private(dev); 371 int val; 372 373 if (sc->axe_dying) 374 return 0; 375 376 if (sc->axe_phyno != phy) 377 return 0; 378 379 axe_lock_mii(sc); 380 val = axe_miibus_readreg_locked(dev, phy, reg); 381 axe_unlock_mii(sc); 382 383 return val; 384 } 385 386 static void 387 axe_miibus_writereg_locked(device_t dev, int phy, int reg, int aval) 388 { 389 struct axe_softc *sc = device_private(dev); 390 usbd_status err; 391 uint16_t val; 392 393 val = htole16(aval); 394 395 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 396 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, (void *)&val); 397 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 398 399 if (err) { 400 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 401 return; 402 } 403 } 404 405 static void 406 axe_miibus_writereg(device_t dev, int phy, int reg, int aval) 407 { 408 struct axe_softc *sc = device_private(dev); 409 410 if (sc->axe_dying) 411 return; 412 413 if (sc->axe_phyno != phy) 414 return; 415 416 axe_lock_mii(sc); 417 axe_miibus_writereg_locked(dev, phy, reg, aval); 418 axe_unlock_mii(sc); 419 } 420 421 static void 422 axe_miibus_statchg(struct ifnet *ifp) 423 { 424 AXEHIST_FUNC(); AXEHIST_CALLED(); 425 426 struct axe_softc *sc = ifp->if_softc; 427 struct mii_data *mii = &sc->axe_mii; 428 int val, err; 429 430 val = 0; 431 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 432 val |= AXE_MEDIA_FULL_DUPLEX; 433 if (AXE_IS_178_FAMILY(sc)) { 434 if ((IFM_OPTIONS(mii->mii_media_active) & 435 IFM_ETH_TXPAUSE) != 0) 436 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 437 if ((IFM_OPTIONS(mii->mii_media_active) & 438 IFM_ETH_RXPAUSE) != 0) 439 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 440 } 441 } 442 if (AXE_IS_178_FAMILY(sc)) { 443 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 444 if (sc->axe_flags & AX178) 445 val |= AXE_178_MEDIA_ENCK; 446 switch (IFM_SUBTYPE(mii->mii_media_active)) { 447 case IFM_1000_T: 448 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 449 break; 450 case IFM_100_TX: 451 val |= AXE_178_MEDIA_100TX; 452 break; 453 case IFM_10_T: 454 /* doesn't need to be handled */ 455 break; 456 } 457 } 458 459 DPRINTF("val=0x%x", val, 0, 0, 0); 460 axe_lock_mii(sc); 461 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 462 axe_unlock_mii(sc); 463 if (err) { 464 aprint_error_dev(sc->axe_dev, "media change failed\n"); 465 return; 466 } 467 } 468 469 static void 470 axe_setmulti(struct axe_softc *sc) 471 { 472 AXEHIST_FUNC(); AXEHIST_CALLED(); 473 struct ifnet *ifp = &sc->sc_if; 474 struct ether_multi *enm; 475 struct ether_multistep step; 476 uint32_t h = 0; 477 uint16_t rxmode; 478 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 479 480 if (sc->axe_dying) 481 return; 482 483 axe_lock_mii(sc); 484 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, (void *)&rxmode); 485 rxmode = le16toh(rxmode); 486 487 rxmode &= 488 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 489 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 490 491 rxmode |= 492 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 493 494 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 495 if (ifp->if_flags & IFF_PROMISC) 496 rxmode |= AXE_RXCMD_PROMISC; 497 goto allmulti; 498 } 499 500 /* Now program new ones */ 501 ETHER_FIRST_MULTI(step, &sc->axe_ec, enm); 502 while (enm != NULL) { 503 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 504 ETHER_ADDR_LEN) != 0) 505 goto allmulti; 506 507 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 508 hashtbl[h >> 3] |= 1U << (h & 7); 509 ETHER_NEXT_MULTI(step, enm); 510 } 511 ifp->if_flags &= ~IFF_ALLMULTI; 512 rxmode |= AXE_RXCMD_MULTICAST; 513 514 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 515 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 516 axe_unlock_mii(sc); 517 return; 518 519 allmulti: 520 ifp->if_flags |= IFF_ALLMULTI; 521 rxmode |= AXE_RXCMD_ALLMULTI; 522 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 523 axe_unlock_mii(sc); 524 } 525 526 527 static void 528 axe_reset(struct axe_softc *sc) 529 { 530 531 if (sc->axe_dying) 532 return; 533 534 /* 535 * softnet_lock can be taken when NET_MPAFE is not defined when calling 536 * if_addr_init -> if_init. This doesn't mixe well with the 537 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 538 * can fire during the wait and attempt to take softnet_lock and then 539 * block the softclk thread meaing the wait never ends. 540 */ 541 #ifndef NET_MPSAFE 542 /* XXX What to reset? */ 543 544 /* Wait a little while for the chip to get its brains in order. */ 545 DELAY(1000); 546 #else 547 axe_lock_mii(sc); 548 549 if (sc->axe_flags & AX178) { 550 axe_ax88178_init(sc); 551 } else if (sc->axe_flags & AX772) { 552 axe_ax88772_init(sc); 553 } else if (sc->axe_flags & AX772A) { 554 axe_ax88772a_init(sc); 555 } else if (sc->axe_flags & AX772B) { 556 axe_ax88772b_init(sc); 557 } 558 axe_unlock_mii(sc); 559 #endif 560 } 561 562 static int 563 axe_get_phyno(struct axe_softc *sc, int sel) 564 { 565 int phyno; 566 567 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 568 case PHY_TYPE_100_HOME: 569 /* FALLTHROUGH */ 570 case PHY_TYPE_GIG: 571 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 572 break; 573 case PHY_TYPE_SPECIAL: 574 /* FALLTHROUGH */ 575 case PHY_TYPE_RSVD: 576 /* FALLTHROUGH */ 577 case PHY_TYPE_NON_SUP: 578 /* FALLTHROUGH */ 579 default: 580 phyno = -1; 581 break; 582 } 583 584 return phyno; 585 } 586 587 #define AXE_GPIO_WRITE(x, y) do { \ 588 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 589 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 590 } while (0) 591 592 static void 593 axe_ax88178_init(struct axe_softc *sc) 594 { 595 AXEHIST_FUNC(); AXEHIST_CALLED(); 596 int gpio0, ledmode, phymode; 597 uint16_t eeprom, val; 598 599 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 600 /* XXX magic */ 601 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 602 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 603 604 eeprom = le16toh(eeprom); 605 606 DPRINTF("EEPROM is 0x%x", eeprom, 0, 0, 0); 607 608 /* if EEPROM is invalid we have to use to GPIO0 */ 609 if (eeprom == 0xffff) { 610 phymode = AXE_PHY_MODE_MARVELL; 611 gpio0 = 1; 612 ledmode = 0; 613 } else { 614 phymode = eeprom & 0x7f; 615 gpio0 = (eeprom & 0x80) ? 0 : 1; 616 ledmode = eeprom >> 8; 617 } 618 619 DPRINTF("use gpio0: %d, phymode %d", gpio0, phymode, 0, 0); 620 621 /* Program GPIOs depending on PHY hardware. */ 622 switch (phymode) { 623 case AXE_PHY_MODE_MARVELL: 624 if (gpio0 == 1) { 625 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 626 hz / 32); 627 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 628 hz / 32); 629 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 630 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 631 hz / 32); 632 } else { 633 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 634 AXE_GPIO1_EN, hz / 3); 635 if (ledmode == 1) { 636 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 637 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 638 hz / 3); 639 } else { 640 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 641 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 642 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 643 AXE_GPIO2_EN, hz / 4); 644 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 645 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 646 } 647 } 648 break; 649 case AXE_PHY_MODE_CICADA: 650 case AXE_PHY_MODE_CICADA_V2: 651 case AXE_PHY_MODE_CICADA_V2_ASIX: 652 if (gpio0 == 1) 653 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 654 AXE_GPIO0_EN, hz / 32); 655 else 656 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 657 AXE_GPIO1_EN, hz / 32); 658 break; 659 case AXE_PHY_MODE_AGERE: 660 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 661 AXE_GPIO1_EN, hz / 32); 662 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 663 AXE_GPIO2_EN, hz / 32); 664 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 665 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 666 AXE_GPIO2_EN, hz / 32); 667 break; 668 case AXE_PHY_MODE_REALTEK_8211CL: 669 case AXE_PHY_MODE_REALTEK_8211BN: 670 case AXE_PHY_MODE_REALTEK_8251CL: 671 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 672 AXE_GPIO1 | AXE_GPIO1_EN; 673 AXE_GPIO_WRITE(val, hz / 32); 674 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 675 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 676 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 677 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 678 axe_miibus_writereg_locked(sc->axe_dev, 679 sc->axe_phyno, 0x1F, 0x0005); 680 axe_miibus_writereg_locked(sc->axe_dev, 681 sc->axe_phyno, 0x0C, 0x0000); 682 val = axe_miibus_readreg_locked(sc->axe_dev, 683 sc->axe_phyno, 0x0001); 684 axe_miibus_writereg_locked(sc->axe_dev, 685 sc->axe_phyno, 0x01, val | 0x0080); 686 axe_miibus_writereg_locked(sc->axe_dev, 687 sc->axe_phyno, 0x1F, 0x0000); 688 } 689 break; 690 default: 691 /* Unknown PHY model or no need to program GPIOs. */ 692 break; 693 } 694 695 /* soft reset */ 696 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 697 usbd_delay_ms(sc->axe_udev, 150); 698 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 699 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 700 usbd_delay_ms(sc->axe_udev, 150); 701 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 702 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 703 usbd_delay_ms(sc->axe_udev, 10); 704 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 705 } 706 707 static void 708 axe_ax88772_init(struct axe_softc *sc) 709 { 710 AXEHIST_FUNC(); AXEHIST_CALLED(); 711 712 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 713 usbd_delay_ms(sc->axe_udev, 40); 714 715 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 716 /* ask for the embedded PHY */ 717 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 718 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 719 usbd_delay_ms(sc->axe_udev, 10); 720 721 /* power down and reset state, pin reset state */ 722 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 723 usbd_delay_ms(sc->axe_udev, 60); 724 725 /* power down/reset state, pin operating state */ 726 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 727 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 728 usbd_delay_ms(sc->axe_udev, 150); 729 730 /* power up, reset */ 731 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 732 733 /* power up, operating */ 734 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 735 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 736 } else { 737 /* ask for external PHY */ 738 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 739 NULL); 740 usbd_delay_ms(sc->axe_udev, 10); 741 742 /* power down internal PHY */ 743 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 744 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 745 } 746 747 usbd_delay_ms(sc->axe_udev, 150); 748 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 749 } 750 751 static int 752 axe_ifflags_cb(struct ethercom *ec) 753 { 754 struct ifnet *ifp = &ec->ec_if; 755 struct axe_softc *sc = ifp->if_softc; 756 int rc = 0; 757 758 mutex_enter(&sc->axe_lock); 759 int change = ifp->if_flags ^ sc->axe_if_flags; 760 sc->axe_if_flags = ifp->if_flags; 761 762 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 763 rc = ENETRESET; 764 goto out; 765 } 766 767 if ((change & IFF_PROMISC) != 0) { 768 axe_setmulti(sc); 769 } 770 771 out: 772 mutex_exit(&sc->axe_lock); 773 774 return rc; 775 } 776 777 static void 778 axe_ax88772_phywake(struct axe_softc *sc) 779 { 780 AXEHIST_FUNC(); AXEHIST_CALLED(); 781 782 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 783 /* Manually select internal(embedded) PHY - MAC mode. */ 784 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 785 AXE_SW_PHY_SELECT_EMBEDDED, 786 NULL); 787 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 788 } else { 789 /* 790 * Manually select external PHY - MAC mode. 791 * Reverse MII/RMII is for AX88772A PHY mode. 792 */ 793 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 794 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 795 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 796 } 797 798 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 799 AXE_SW_RESET_IPRL, NULL); 800 801 /* T1 = min 500ns everywhere */ 802 usbd_delay_ms(sc->axe_udev, 150); 803 804 /* Take PHY out of power down. */ 805 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 806 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 807 } else { 808 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 809 } 810 811 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 812 usbd_delay_ms(sc->axe_udev, 600); 813 814 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 815 816 /* T3 = 500ns everywhere */ 817 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 818 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 819 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 820 } 821 822 static void 823 axe_ax88772a_init(struct axe_softc *sc) 824 { 825 AXEHIST_FUNC(); AXEHIST_CALLED(); 826 827 /* Reload EEPROM. */ 828 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 829 axe_ax88772_phywake(sc); 830 /* Stop MAC. */ 831 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 832 } 833 834 static void 835 axe_ax88772b_init(struct axe_softc *sc) 836 { 837 AXEHIST_FUNC(); AXEHIST_CALLED(); 838 uint16_t eeprom; 839 int i; 840 841 /* Reload EEPROM. */ 842 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 843 844 /* 845 * Save PHY power saving configuration(high byte) and 846 * clear EEPROM checksum value(low byte). 847 */ 848 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 849 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 850 851 /* 852 * Auto-loaded default station address from internal ROM is 853 * 00:00:00:00:00:00 such that an explicit access to EEPROM 854 * is required to get real station address. 855 */ 856 uint8_t *eaddr = sc->axe_enaddr; 857 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 858 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 859 &eeprom); 860 eeprom = le16toh(eeprom); 861 *eaddr++ = (uint8_t)(eeprom & 0xFF); 862 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 863 } 864 /* Wakeup PHY. */ 865 axe_ax88772_phywake(sc); 866 /* Stop MAC. */ 867 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 868 } 869 870 #undef AXE_GPIO_WRITE 871 872 /* 873 * Probe for a AX88172 chip. 874 */ 875 int 876 axe_match(device_t parent, cfdata_t match, void *aux) 877 { 878 struct usb_attach_arg *uaa = aux; 879 880 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 881 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 882 } 883 884 /* 885 * Attach the interface. Allocate softc structures, do ifmedia 886 * setup and ethernet/BPF attach. 887 */ 888 void 889 axe_attach(device_t parent, device_t self, void *aux) 890 { 891 AXEHIST_FUNC(); AXEHIST_CALLED(); 892 struct axe_softc *sc = device_private(self); 893 struct usb_attach_arg *uaa = aux; 894 struct usbd_device *dev = uaa->uaa_device; 895 usbd_status err; 896 usb_interface_descriptor_t *id; 897 usb_endpoint_descriptor_t *ed; 898 struct mii_data *mii; 899 char *devinfop; 900 const char *devname = device_xname(self); 901 struct ifnet *ifp; 902 int i, s; 903 904 aprint_naive("\n"); 905 aprint_normal("\n"); 906 907 sc->axe_dev = self; 908 sc->axe_udev = dev; 909 910 devinfop = usbd_devinfo_alloc(dev, 0); 911 aprint_normal_dev(self, "%s\n", devinfop); 912 usbd_devinfo_free(devinfop); 913 914 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 915 if (err) { 916 aprint_error_dev(self, "failed to set configuration" 917 ", err=%s\n", usbd_errstr(err)); 918 return; 919 } 920 921 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 922 923 mutex_init(&sc->axe_lock, MUTEX_DEFAULT, IPL_NONE); 924 mutex_init(&sc->axe_txlock, MUTEX_DEFAULT, IPL_SOFTUSB); 925 mutex_init(&sc->axe_rxlock, MUTEX_DEFAULT, IPL_SOFTUSB); 926 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 927 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 928 929 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 930 if (err) { 931 aprint_error_dev(self, "getting interface handle failed\n"); 932 return; 933 } 934 935 sc->axe_product = uaa->uaa_product; 936 sc->axe_vendor = uaa->uaa_vendor; 937 938 id = usbd_get_interface_descriptor(sc->axe_iface); 939 940 /* decide on what our bufsize will be */ 941 if (AXE_IS_178_FAMILY(sc)) 942 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 943 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 944 else 945 sc->axe_bufsz = AXE_172_BUFSZ; 946 947 sc->axe_ed[AXE_ENDPT_RX] = -1; 948 sc->axe_ed[AXE_ENDPT_TX] = -1; 949 sc->axe_ed[AXE_ENDPT_INTR] = -1; 950 951 /* Find endpoints. */ 952 for (i = 0; i < id->bNumEndpoints; i++) { 953 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 954 if (ed == NULL) { 955 aprint_error_dev(self, "couldn't get ep %d\n", i); 956 return; 957 } 958 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 959 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 960 961 if (dir == UE_DIR_IN && xt == UE_BULK && 962 sc->axe_ed[AXE_ENDPT_RX] == -1) { 963 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 964 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 965 sc->axe_ed[AXE_ENDPT_TX] == -1) { 966 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 967 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 968 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 969 } 970 } 971 972 s = splnet(); 973 974 /* We need the PHYID for init dance in some cases */ 975 axe_lock_mii(sc); 976 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, (void *)&sc->axe_phyaddrs); 977 978 DPRINTF(" phyaddrs[0]: %x phyaddrs[1]: %x", 979 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 980 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 981 if (sc->axe_phyno == -1) 982 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 983 if (sc->axe_phyno == -1) { 984 DPRINTF(" no valid PHY address found, assuming PHY address 0", 985 0, 0, 0, 0); 986 sc->axe_phyno = 0; 987 } 988 989 /* Initialize controller and get station address. */ 990 991 if (sc->axe_flags & AX178) { 992 axe_ax88178_init(sc); 993 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 994 } else if (sc->axe_flags & AX772) { 995 axe_ax88772_init(sc); 996 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 997 } else if (sc->axe_flags & AX772A) { 998 axe_ax88772a_init(sc); 999 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 1000 } else if (sc->axe_flags & AX772B) { 1001 axe_ax88772b_init(sc); 1002 } else 1003 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 1004 1005 /* 1006 * Fetch IPG values. 1007 */ 1008 if (sc->axe_flags & (AX772A | AX772B)) { 1009 /* Set IPG values. */ 1010 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 1011 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 1012 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1013 } else 1014 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs); 1015 1016 axe_unlock_mii(sc); 1017 1018 /* 1019 * An ASIX chip was detected. Inform the world. 1020 */ 1021 aprint_normal_dev(self, "Ethernet address %s\n", 1022 ether_sprintf(sc->axe_enaddr)); 1023 1024 /* Initialize interface info.*/ 1025 ifp = &sc->sc_if; 1026 ifp->if_softc = sc; 1027 strncpy(ifp->if_xname, devname, IFNAMSIZ); 1028 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1029 ifp->if_extflags = IFEF_START_MPSAFE; 1030 ifp->if_ioctl = axe_ioctl; 1031 ifp->if_start = axe_start; 1032 ifp->if_init = axe_init; 1033 ifp->if_stop = axe_stop; 1034 ifp->if_watchdog = axe_watchdog; 1035 1036 IFQ_SET_READY(&ifp->if_snd); 1037 1038 if (AXE_IS_178_FAMILY(sc)) 1039 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1040 if (sc->axe_flags & AX772B) { 1041 ifp->if_capabilities = 1042 IFCAP_CSUM_IPv4_Rx | 1043 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1044 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1045 /* 1046 * Checksum offloading of AX88772B also works with VLAN 1047 * tagged frames but there is no way to take advantage 1048 * of the feature because vlan(4) assumes 1049 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1050 * support checksum offloading with VLAN. VLAN hardware 1051 * tagging support of AX88772B is very limited so it's 1052 * not possible to announce IFCAP_VLAN_HWTAGGING. 1053 */ 1054 } 1055 u_int adv_pause; 1056 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1057 adv_pause = MIIF_DOPAUSE; 1058 else 1059 adv_pause = 0; 1060 adv_pause = 0; 1061 1062 /* Initialize MII/media info. */ 1063 mii = &sc->axe_mii; 1064 mii->mii_ifp = ifp; 1065 mii->mii_readreg = axe_miibus_readreg; 1066 mii->mii_writereg = axe_miibus_writereg; 1067 mii->mii_statchg = axe_miibus_statchg; 1068 mii->mii_flags = MIIF_AUTOTSLEEP; 1069 1070 sc->axe_ec.ec_mii = mii; 1071 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1072 1073 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1074 adv_pause); 1075 1076 if (LIST_EMPTY(&mii->mii_phys)) { 1077 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1078 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1079 } else 1080 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1081 1082 /* Attach the interface. */ 1083 if_initialize(ifp); 1084 sc->axe_ipq = if_percpuq_create(&sc->axe_ec.ec_if); 1085 ether_ifattach(ifp, sc->axe_enaddr); 1086 if_register(ifp); 1087 ether_set_ifflags_cb(&sc->axe_ec, axe_ifflags_cb); 1088 1089 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1090 RND_TYPE_NET, RND_FLAG_DEFAULT); 1091 1092 callout_init(&sc->axe_stat_ch, 0); 1093 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1094 1095 sc->axe_attached = true; 1096 splx(s); 1097 1098 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1099 1100 if (!pmf_device_register(self, NULL, NULL)) 1101 aprint_error_dev(self, "couldn't establish power handler\n"); 1102 } 1103 1104 int 1105 axe_detach(device_t self, int flags) 1106 { 1107 AXEHIST_FUNC(); AXEHIST_CALLED(); 1108 struct axe_softc *sc = device_private(self); 1109 int s; 1110 struct ifnet *ifp = &sc->sc_if; 1111 1112 /* Detached before attached finished, so just bail out. */ 1113 if (!sc->axe_attached) 1114 return 0; 1115 1116 pmf_device_deregister(self); 1117 1118 sc->axe_dying = true; 1119 1120 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1121 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1122 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1123 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1124 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1125 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1126 1127 /* 1128 * Remove any pending tasks. They cannot be executing because they run 1129 * in the same thread as detach. 1130 */ 1131 usb_rem_task(sc->axe_udev, &sc->axe_tick_task); 1132 1133 s = splusb(); 1134 1135 if (ifp->if_flags & IFF_RUNNING) 1136 axe_stop(ifp, 1); 1137 1138 1139 if (--sc->axe_refcnt >= 0) { 1140 /* Wait for processes to go away. */ 1141 usb_detach_waitold(sc->axe_dev); 1142 } 1143 1144 callout_destroy(&sc->axe_stat_ch); 1145 mutex_destroy(&sc->axe_lock); 1146 mutex_destroy(&sc->axe_txlock); 1147 mutex_destroy(&sc->axe_rxlock); 1148 mutex_destroy(&sc->axe_mii_lock); 1149 rnd_detach_source(&sc->rnd_source); 1150 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1151 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1152 ether_ifdetach(ifp); 1153 if_detach(ifp); 1154 1155 #ifdef DIAGNOSTIC 1156 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1157 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1158 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1159 aprint_debug_dev(self, "detach has active endpoints\n"); 1160 #endif 1161 1162 sc->axe_attached = false; 1163 1164 splx(s); 1165 1166 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1167 1168 return 0; 1169 } 1170 1171 int 1172 axe_activate(device_t self, devact_t act) 1173 { 1174 AXEHIST_FUNC(); AXEHIST_CALLED(); 1175 struct axe_softc *sc = device_private(self); 1176 1177 switch (act) { 1178 case DVACT_DEACTIVATE: 1179 if_deactivate(&sc->axe_ec.ec_if); 1180 sc->axe_dying = true; 1181 return 0; 1182 default: 1183 return EOPNOTSUPP; 1184 } 1185 } 1186 1187 static int 1188 axe_rx_list_init(struct axe_softc *sc) 1189 { 1190 AXEHIST_FUNC(); AXEHIST_CALLED(); 1191 1192 struct axe_cdata *cd; 1193 struct axe_chain *c; 1194 int i; 1195 1196 cd = &sc->axe_cdata; 1197 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1198 c = &cd->axe_rx_chain[i]; 1199 c->axe_sc = sc; 1200 c->axe_idx = i; 1201 if (c->axe_xfer == NULL) { 1202 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1203 sc->axe_bufsz, USBD_SHORT_XFER_OK, 0, &c->axe_xfer); 1204 if (err) 1205 return err; 1206 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1207 } 1208 } 1209 1210 return 0; 1211 } 1212 1213 static void 1214 axe_rx_list_free(struct axe_softc *sc) 1215 { 1216 /* Free RX resources */ 1217 for (size_t i = 0; i < AXE_RX_LIST_CNT; i++) { 1218 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1219 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1220 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1221 } 1222 } 1223 } 1224 1225 static int 1226 axe_tx_list_init(struct axe_softc *sc) 1227 { 1228 AXEHIST_FUNC(); AXEHIST_CALLED(); 1229 struct axe_cdata *cd; 1230 struct axe_chain *c; 1231 int i; 1232 1233 cd = &sc->axe_cdata; 1234 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1235 c = &cd->axe_tx_chain[i]; 1236 c->axe_sc = sc; 1237 c->axe_idx = i; 1238 if (c->axe_xfer == NULL) { 1239 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1240 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1241 &c->axe_xfer); 1242 if (err) 1243 return err; 1244 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1245 } 1246 } 1247 1248 return 0; 1249 } 1250 1251 static void 1252 axe_tx_list_free(struct axe_softc *sc) 1253 { 1254 /* Free TX resources */ 1255 for (size_t i = 0; i < AXE_TX_LIST_CNT; i++) { 1256 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1257 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1258 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1259 } 1260 } 1261 } 1262 1263 /* 1264 * A frame has been uploaded: pass the resulting mbuf chain up to 1265 * the higher level protocols. 1266 */ 1267 static void 1268 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1269 { 1270 AXEHIST_FUNC(); AXEHIST_CALLED(); 1271 struct axe_softc *sc; 1272 struct axe_chain *c; 1273 struct ifnet *ifp; 1274 uint8_t *buf; 1275 uint32_t total_len; 1276 struct mbuf *m; 1277 1278 c = (struct axe_chain *)priv; 1279 sc = c->axe_sc; 1280 buf = c->axe_buf; 1281 ifp = &sc->sc_if; 1282 1283 if (sc->axe_dying) 1284 return; 1285 1286 if ((ifp->if_flags & IFF_RUNNING) == 0) 1287 return; 1288 1289 if (status != USBD_NORMAL_COMPLETION) { 1290 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1291 return; 1292 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1293 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1294 usbd_errstr(status)); 1295 } 1296 if (status == USBD_STALLED) 1297 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1298 goto done; 1299 } 1300 1301 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1302 1303 do { 1304 u_int pktlen = 0; 1305 u_int rxlen = 0; 1306 int flags = 0; 1307 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1308 struct axe_sframe_hdr hdr; 1309 1310 if (total_len < sizeof(hdr)) { 1311 ifp->if_ierrors++; 1312 goto done; 1313 } 1314 1315 memcpy(&hdr, buf, sizeof(hdr)); 1316 1317 DPRINTFN(20, "total_len %#x len %x ilen %#x", 1318 total_len, 1319 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1320 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1321 1322 total_len -= sizeof(hdr); 1323 buf += sizeof(hdr); 1324 1325 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1326 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1327 AXE_RH1M_RXLEN_MASK) { 1328 ifp->if_ierrors++; 1329 goto done; 1330 } 1331 1332 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1333 if (total_len < rxlen) { 1334 pktlen = total_len; 1335 total_len = 0; 1336 } else { 1337 pktlen = rxlen; 1338 rxlen = roundup2(rxlen, 2); 1339 total_len -= rxlen; 1340 } 1341 1342 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1343 struct axe_csum_hdr csum_hdr; 1344 1345 if (total_len < sizeof(csum_hdr)) { 1346 ifp->if_ierrors++; 1347 goto done; 1348 } 1349 1350 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1351 1352 csum_hdr.len = le16toh(csum_hdr.len); 1353 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1354 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1355 1356 DPRINTFN(20, "total_len %#x len %#x ilen %#x" 1357 " cstatus %#x", total_len, 1358 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1359 1360 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1361 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1362 sc->sc_lenmask) { 1363 /* we lost sync */ 1364 ifp->if_ierrors++; 1365 DPRINTFN(20, "len %#x ilen %#x lenmask %#x err", 1366 AXE_CSUM_RXBYTES(csum_hdr.len), 1367 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1368 sc->sc_lenmask, 0); 1369 goto done; 1370 } 1371 /* 1372 * Get total transferred frame length including 1373 * checksum header. The length should be multiple 1374 * of 4. 1375 */ 1376 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1377 u_int len = sizeof(csum_hdr) + pktlen; 1378 len = (len + 3) & ~3; 1379 if (total_len < len) { 1380 DPRINTFN(20, "total_len %#x < len %#x", 1381 total_len, len, 0, 0); 1382 /* invalid length */ 1383 ifp->if_ierrors++; 1384 goto done; 1385 } 1386 buf += sizeof(csum_hdr); 1387 1388 const uint16_t cstatus = csum_hdr.cstatus; 1389 1390 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1391 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1392 flags |= M_CSUM_TCP_UDP_BAD; 1393 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1394 flags |= M_CSUM_IPv4_BAD; 1395 1396 const uint16_t l4type = 1397 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1398 1399 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1400 flags |= M_CSUM_TCPv4; 1401 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1402 flags |= M_CSUM_UDPv4; 1403 } 1404 if (total_len < len) { 1405 pktlen = total_len; 1406 total_len = 0; 1407 } else { 1408 total_len -= len; 1409 rxlen = len - sizeof(csum_hdr); 1410 } 1411 DPRINTFN(20, "total_len %#x len %#x pktlen %#x" 1412 " rxlen %#x", total_len, len, pktlen, rxlen); 1413 } else { /* AX172 */ 1414 pktlen = rxlen = total_len; 1415 total_len = 0; 1416 } 1417 1418 MGETHDR(m, M_DONTWAIT, MT_DATA); 1419 if (m == NULL) { 1420 ifp->if_ierrors++; 1421 goto done; 1422 } 1423 1424 if (pktlen > MHLEN - ETHER_ALIGN) { 1425 MCLGET(m, M_DONTWAIT); 1426 if ((m->m_flags & M_EXT) == 0) { 1427 m_freem(m); 1428 ifp->if_ierrors++; 1429 goto done; 1430 } 1431 } 1432 m->m_data += ETHER_ALIGN; 1433 1434 ifp->if_ipackets++; 1435 m_set_rcvif(m, ifp); 1436 m->m_pkthdr.len = m->m_len = pktlen; 1437 m->m_pkthdr.csum_flags = flags; 1438 1439 memcpy(mtod(m, uint8_t *), buf, pktlen); 1440 buf += rxlen; 1441 1442 DPRINTFN(10, "deliver %d (%#x)", m->m_len, m->m_len, 0, 0); 1443 1444 bpf_mtap(ifp, m); 1445 1446 if_percpuq_enqueue(sc->axe_ipq, (m)); 1447 1448 } while (total_len > 0); 1449 1450 done: 1451 1452 /* Setup new transfer. */ 1453 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1454 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1455 usbd_transfer(xfer); 1456 1457 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1458 } 1459 1460 /* 1461 * A frame was downloaded to the chip. It's safe for us to clean up 1462 * the list buffers. 1463 */ 1464 1465 static void 1466 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1467 { 1468 AXEHIST_FUNC(); AXEHIST_CALLED(); 1469 struct axe_chain *c = priv; 1470 struct axe_softc *sc = c->axe_sc; 1471 struct ifnet *ifp = &sc->sc_if; 1472 int s; 1473 1474 1475 if (sc->axe_dying) 1476 return; 1477 1478 s = splnet(); 1479 1480 ifp->if_timer = 0; 1481 ifp->if_flags &= ~IFF_OACTIVE; 1482 1483 if (status != USBD_NORMAL_COMPLETION) { 1484 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1485 splx(s); 1486 return; 1487 } 1488 ifp->if_oerrors++; 1489 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1490 usbd_errstr(status)); 1491 if (status == USBD_STALLED) 1492 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1493 splx(s); 1494 return; 1495 } 1496 ifp->if_opackets++; 1497 1498 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1499 axe_start(ifp); 1500 1501 splx(s); 1502 } 1503 1504 static void 1505 axe_tick(void *xsc) 1506 { 1507 AXEHIST_FUNC(); AXEHIST_CALLED(); 1508 struct axe_softc *sc = xsc; 1509 1510 if (sc == NULL) 1511 return; 1512 1513 if (sc->axe_dying) 1514 return; 1515 1516 /* Perform periodic stuff in process context */ 1517 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1518 } 1519 1520 static void 1521 axe_tick_task(void *xsc) 1522 { 1523 AXEHIST_FUNC(); AXEHIST_CALLED(); 1524 int s; 1525 struct axe_softc *sc = xsc; 1526 struct ifnet *ifp; 1527 struct mii_data *mii; 1528 1529 if (sc == NULL) 1530 return; 1531 1532 if (sc->axe_dying) 1533 return; 1534 1535 ifp = &sc->sc_if; 1536 mii = &sc->axe_mii; 1537 1538 if (mii == NULL) 1539 return; 1540 1541 s = splnet(); 1542 1543 mii_tick(mii); 1544 if (sc->axe_link == 0 && 1545 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1546 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1547 DPRINTF("got link", 0, 0, 0, 0); 1548 sc->axe_link++; 1549 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1550 axe_start(ifp); 1551 } 1552 1553 callout_schedule(&sc->axe_stat_ch, hz); 1554 1555 splx(s); 1556 } 1557 1558 static int 1559 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1560 { 1561 struct ifnet *ifp = &sc->sc_if; 1562 struct axe_chain *c; 1563 usbd_status err; 1564 int length, boundary; 1565 1566 c = &sc->axe_cdata.axe_tx_chain[idx]; 1567 1568 /* 1569 * Copy the mbuf data into a contiguous buffer, leaving two 1570 * bytes at the beginning to hold the frame length. 1571 */ 1572 if (AXE_IS_178_FAMILY(sc)) { 1573 struct axe_sframe_hdr hdr; 1574 1575 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1576 1577 hdr.len = htole16(m->m_pkthdr.len); 1578 hdr.ilen = ~hdr.len; 1579 1580 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1581 length = sizeof(hdr); 1582 1583 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1584 length += m->m_pkthdr.len; 1585 1586 if ((length % boundary) == 0) { 1587 hdr.len = 0x0000; 1588 hdr.ilen = 0xffff; 1589 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1590 length += sizeof(hdr); 1591 } 1592 } else { 1593 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1594 length = m->m_pkthdr.len; 1595 } 1596 1597 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1598 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1599 1600 /* Transmit */ 1601 err = usbd_transfer(c->axe_xfer); 1602 if (err != USBD_IN_PROGRESS) { 1603 axe_stop(ifp, 0); 1604 return EIO; 1605 } 1606 1607 sc->axe_cdata.axe_tx_cnt++; 1608 1609 return 0; 1610 } 1611 1612 1613 static void 1614 axe_csum_cfg(struct axe_softc *sc) 1615 { 1616 struct ifnet *ifp = &sc->sc_if; 1617 uint16_t csum1, csum2; 1618 1619 if ((sc->axe_flags & AX772B) != 0) { 1620 csum1 = 0; 1621 csum2 = 0; 1622 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1623 csum1 |= AXE_TXCSUM_IP; 1624 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1625 csum1 |= AXE_TXCSUM_TCP; 1626 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1627 csum1 |= AXE_TXCSUM_UDP; 1628 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1629 csum1 |= AXE_TXCSUM_TCPV6; 1630 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1631 csum1 |= AXE_TXCSUM_UDPV6; 1632 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1633 csum1 = 0; 1634 csum2 = 0; 1635 1636 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1637 csum1 |= AXE_RXCSUM_IP; 1638 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1639 csum1 |= AXE_RXCSUM_TCP; 1640 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1641 csum1 |= AXE_RXCSUM_UDP; 1642 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1643 csum1 |= AXE_RXCSUM_TCPV6; 1644 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1645 csum1 |= AXE_RXCSUM_UDPV6; 1646 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1647 } 1648 } 1649 1650 static void 1651 axe_start(struct ifnet *ifp) 1652 { 1653 struct axe_softc *sc = ifp->if_softc; 1654 1655 mutex_enter(&sc->axe_txlock); 1656 axe_start_locked(ifp); 1657 mutex_exit(&sc->axe_txlock); 1658 } 1659 1660 static void 1661 axe_start_locked(struct ifnet *ifp) 1662 { 1663 struct axe_softc *sc = ifp->if_softc; 1664 struct mbuf *m; 1665 1666 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) 1667 return; 1668 1669 IFQ_POLL(&ifp->if_snd, m); 1670 if (m == NULL) { 1671 return; 1672 } 1673 1674 if (axe_encap(sc, m, 0)) { 1675 return; 1676 } 1677 IFQ_DEQUEUE(&ifp->if_snd, m); 1678 1679 /* 1680 * If there's a BPF listener, bounce a copy of this frame 1681 * to him. 1682 */ 1683 bpf_mtap(ifp, m); 1684 m_freem(m); 1685 1686 ifp->if_flags |= IFF_OACTIVE; 1687 1688 /* 1689 * Set a timeout in case the chip goes out to lunch. 1690 */ 1691 ifp->if_timer = 5; 1692 1693 return; 1694 } 1695 1696 static int 1697 axe_init(struct ifnet *ifp) 1698 { 1699 struct axe_softc *sc = ifp->if_softc; 1700 1701 mutex_enter(&sc->axe_lock); 1702 int ret = axe_init_locked(ifp); 1703 mutex_exit(&sc->axe_lock); 1704 1705 return ret; 1706 } 1707 1708 static int 1709 axe_init_locked(struct ifnet *ifp) 1710 { 1711 AXEHIST_FUNC(); AXEHIST_CALLED(); 1712 struct axe_softc *sc = ifp->if_softc; 1713 usbd_status err; 1714 int rxmode; 1715 int i, error; 1716 1717 axe_stop_locked(ifp, 0); 1718 1719 /* 1720 * Cancel pending I/O and free all RX/TX buffers. 1721 */ 1722 axe_reset(sc); 1723 1724 axe_lock_mii(sc); 1725 1726 #if 0 1727 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1728 AX_GPIO_GPO2EN, 5, in_pm); 1729 #endif 1730 /* Set MAC address and transmitter IPG values. */ 1731 if (AXE_IS_178_FAMILY(sc)) { 1732 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1733 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1734 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1735 } else { 1736 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1737 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1738 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1739 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1740 } 1741 if (AXE_IS_178_FAMILY(sc)) { 1742 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1743 if ((sc->axe_flags & AX772B) != 0 && 1744 (ifp->if_capenable & AX_RXCSUM) != 0) { 1745 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1746 sc->axe_flags |= AXCSUM_FRAME; 1747 } else { 1748 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1749 sc->axe_flags |= AXSTD_FRAME; 1750 } 1751 } 1752 1753 /* Configure TX/RX checksum offloading. */ 1754 axe_csum_cfg(sc); 1755 1756 if (sc->axe_flags & AX772B) { 1757 /* AX88772B uses different maximum frame burst configuration. */ 1758 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1759 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1760 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1761 } 1762 /* Enable receiver, set RX mode */ 1763 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1764 if (AXE_IS_178_FAMILY(sc)) { 1765 if (sc->axe_flags & AX772B) { 1766 /* 1767 * Select RX header format type 1. Aligning IP 1768 * header on 4 byte boundary is not needed when 1769 * checksum offloading feature is not used 1770 * because we always copy the received frame in 1771 * RX handler. When RX checksum offloading is 1772 * active, aligning IP header is required to 1773 * reflect actual frame length including RX 1774 * header size. 1775 */ 1776 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1777 if (sc->axe_flags & AXCSUM_FRAME) 1778 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1779 } else { 1780 /* 1781 * Default Rx buffer size is too small to get 1782 * maximum performance. 1783 */ 1784 #if 0 1785 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1786 /* Largest possible USB buffer size for AX88178 */ 1787 #endif 1788 rxmode |= AXE_178_RXCMD_MFB_16384; 1789 } 1790 } else { 1791 rxmode |= AXE_172_RXCMD_UNICAST; 1792 } 1793 1794 1795 /* If we want promiscuous mode, set the allframes bit. */ 1796 if (ifp->if_flags & IFF_PROMISC) 1797 rxmode |= AXE_RXCMD_PROMISC; 1798 1799 if (ifp->if_flags & IFF_BROADCAST) 1800 rxmode |= AXE_RXCMD_BROADCAST; 1801 1802 DPRINTF("rxmode 0x%#x", rxmode, 0, 0, 0); 1803 1804 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1805 axe_unlock_mii(sc); 1806 1807 /* Load the multicast filter. */ 1808 axe_setmulti(sc); 1809 1810 /* Open RX and TX pipes. */ 1811 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1812 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1813 if (err) { 1814 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1815 usbd_errstr(err)); 1816 error = EIO; 1817 goto fail; 1818 } 1819 1820 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1821 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1822 if (err) { 1823 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1824 usbd_errstr(err)); 1825 error = EIO; 1826 goto fail1; 1827 } 1828 1829 /* Init RX ring. */ 1830 if (axe_rx_list_init(sc) != 0) { 1831 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1832 error = ENOBUFS; 1833 goto fail2; 1834 } 1835 1836 /* Init TX ring. */ 1837 if (axe_tx_list_init(sc) != 0) { 1838 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1839 error = ENOBUFS; 1840 goto fail3; 1841 } 1842 1843 /* Start up the receive pipe. */ 1844 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1845 struct axe_chain *c = &sc->axe_cdata.axe_rx_chain[i]; 1846 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1847 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1848 usbd_transfer(c->axe_xfer); 1849 } 1850 1851 ifp->if_flags |= IFF_RUNNING; 1852 ifp->if_flags &= ~IFF_OACTIVE; 1853 1854 callout_schedule(&sc->axe_stat_ch, hz); 1855 1856 return 0; 1857 fail3: 1858 axe_rx_list_free(sc); 1859 fail2: 1860 usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1861 fail1: 1862 usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1863 fail: 1864 return error; 1865 } 1866 1867 static int 1868 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1869 { 1870 struct axe_softc *sc = ifp->if_softc; 1871 int s; 1872 int error = 0; 1873 1874 s = splnet(); 1875 error = ether_ioctl(ifp, cmd, data); 1876 splx(s); 1877 1878 if (error == ENETRESET) { 1879 error = 0; 1880 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1881 ; 1882 else if (ifp->if_flags & IFF_RUNNING) { 1883 mutex_enter(&sc->axe_lock); 1884 axe_setmulti(sc); 1885 mutex_exit(&sc->axe_lock); 1886 } 1887 } 1888 1889 return error; 1890 } 1891 1892 static void 1893 axe_watchdog(struct ifnet *ifp) 1894 { 1895 struct axe_softc *sc; 1896 struct axe_chain *c; 1897 usbd_status stat; 1898 int s; 1899 1900 sc = ifp->if_softc; 1901 1902 ifp->if_oerrors++; 1903 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1904 1905 s = splusb(); 1906 c = &sc->axe_cdata.axe_tx_chain[0]; 1907 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1908 axe_txeof(c->axe_xfer, c, stat); 1909 1910 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1911 axe_start(ifp); 1912 splx(s); 1913 } 1914 1915 /* 1916 * Stop the adapter and free any mbufs allocated to the 1917 * RX and TX lists. 1918 */ 1919 1920 static void 1921 axe_stop(struct ifnet *ifp, int disable) 1922 { 1923 struct axe_softc *sc = ifp->if_softc; 1924 1925 mutex_enter(&sc->axe_lock); 1926 axe_stop_locked(ifp, disable); 1927 mutex_exit(&sc->axe_lock); 1928 } 1929 1930 static void 1931 axe_stop_locked(struct ifnet *ifp, int disable) 1932 { 1933 struct axe_softc *sc = ifp->if_softc; 1934 usbd_status err; 1935 1936 ifp->if_timer = 0; 1937 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1938 1939 callout_stop(&sc->axe_stat_ch); 1940 1941 /* Stop transfers. */ 1942 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1943 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1944 if (err) { 1945 aprint_error_dev(sc->axe_dev, 1946 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1947 } 1948 } 1949 1950 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1951 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1952 if (err) { 1953 aprint_error_dev(sc->axe_dev, 1954 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1955 } 1956 } 1957 1958 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1959 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1960 if (err) { 1961 aprint_error_dev(sc->axe_dev, 1962 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1963 } 1964 } 1965 1966 axe_reset(sc); 1967 1968 axe_rx_list_free(sc); 1969 1970 axe_tx_list_free(sc); 1971 1972 /* Close pipes. */ 1973 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1974 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1975 if (err) { 1976 aprint_error_dev(sc->axe_dev, 1977 "close rx pipe failed: %s\n", usbd_errstr(err)); 1978 } 1979 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1980 } 1981 1982 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1983 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1984 if (err) { 1985 aprint_error_dev(sc->axe_dev, 1986 "close tx pipe failed: %s\n", usbd_errstr(err)); 1987 } 1988 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1989 } 1990 1991 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1992 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1993 if (err) { 1994 aprint_error_dev(sc->axe_dev, 1995 "close intr pipe failed: %s\n", usbd_errstr(err)); 1996 } 1997 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1998 } 1999 2000 sc->axe_link = 0; 2001 } 2002 2003 MODULE(MODULE_CLASS_DRIVER, if_axe, "bpf"); 2004 2005 #ifdef _MODULE 2006 #include "ioconf.c" 2007 #endif 2008 2009 static int 2010 if_axe_modcmd(modcmd_t cmd, void *aux) 2011 { 2012 int error = 0; 2013 2014 switch (cmd) { 2015 case MODULE_CMD_INIT: 2016 #ifdef _MODULE 2017 error = config_init_component(cfdriver_ioconf_axe, 2018 cfattach_ioconf_axe, cfdata_ioconf_axe); 2019 #endif 2020 return error; 2021 case MODULE_CMD_FINI: 2022 #ifdef _MODULE 2023 error = config_fini_component(cfdriver_ioconf_axe, 2024 cfattach_ioconf_axe, cfdata_ioconf_axe); 2025 #endif 2026 return error; 2027 default: 2028 return ENOTTY; 2029 } 2030 } 2031
Indexes created Wed Oct 01 18:09:54 GMT 2025