if_axe.c revision 1.67.4.16
1 /* $NetBSD: if_axe.c,v 1.67.4.16 2017/08/28 17:52:27 skrll Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.67.4.16 2017/08/28 17:52:27 skrll Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 /* 131 * AXE_178_MAX_FRAME_BURST 132 * max frame burst size for Ax88178 and Ax88772 133 * 0 2048 bytes 134 * 1 4096 bytes 135 * 2 8192 bytes 136 * 3 16384 bytes 137 * use the largest your system can handle without USB stalling. 138 * 139 * NB: 88772 parts appear to generate lots of input errors with 140 * a 2K rx buffer and 8K is only slightly faster than 4K on an 141 * EHCI port on a T42 so change at your own risk. 142 */ 143 #define AXE_178_MAX_FRAME_BURST 1 144 145 146 #ifdef USB_DEBUG 147 #ifndef AXE_DEBUG 148 #define axedebug 0 149 #else 150 static int axedebug = 20; 151 152 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 153 { 154 int err; 155 const struct sysctlnode *rnode; 156 const struct sysctlnode *cnode; 157 158 err = sysctl_createv(clog, 0, NULL, &rnode, 159 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 160 SYSCTL_DESCR("axe global controls"), 161 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 162 163 if (err) 164 goto fail; 165 166 /* control debugging printfs */ 167 err = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 169 "debug", SYSCTL_DESCR("Enable debugging output"), 170 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 171 if (err) 172 goto fail; 173 174 return; 175 fail: 176 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 177 } 178 179 #endif /* AXE_DEBUG */ 180 #endif /* USB_DEBUG */ 181 182 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 183 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 184 #define AXEHIST_FUNC() USBHIST_FUNC() 185 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 186 187 /* 188 * Various supported device vendors/products. 189 */ 190 static const struct axe_type axe_devs[] = { 191 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 192 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 193 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 199 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 200 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 201 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 202 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 203 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 204 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 206 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 208 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 209 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 210 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 211 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 212 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 213 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 214 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 215 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 216 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 218 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 219 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 220 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 221 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 222 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 223 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 225 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 226 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 227 }; 228 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 229 230 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 231 { 0x8000, 0x8001, 2048 }, 232 { 0x8100, 0x8147, 4096 }, 233 { 0x8200, 0x81EB, 6144 }, 234 { 0x8300, 0x83D7, 8192 }, 235 { 0x8400, 0x851E, 16384 }, 236 { 0x8500, 0x8666, 20480 }, 237 { 0x8600, 0x87AE, 24576 }, 238 { 0x8700, 0x8A3D, 32768 } 239 }; 240 241 int axe_match(device_t, cfdata_t, void *); 242 void axe_attach(device_t, device_t, void *); 243 int axe_detach(device_t, int); 244 int axe_activate(device_t, devact_t); 245 246 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 247 axe_match, axe_attach, axe_detach, axe_activate); 248 249 static int axe_tx_list_init(struct axe_softc *); 250 #if 0 251 static void axe_tx_list_free(struct axe_softc *); 252 #endif 253 static int axe_rx_list_init(struct axe_softc *); 254 static void axe_rx_list_free(struct axe_softc *); 255 static int axe_encap(struct axe_softc *, struct mbuf *, int); 256 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 257 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 258 static void axe_tick(void *); 259 static void axe_tick_task(void *); 260 static void axe_start(struct ifnet *); 261 static void axe_start_locked(struct ifnet *); 262 static int axe_ioctl(struct ifnet *, u_long, void *); 263 static int axe_init(struct ifnet *); 264 static int axe_init_locked(struct ifnet *); 265 static void axe_stop(struct ifnet *, int); 266 static void axe_stop_locked(struct ifnet *, int); 267 static void axe_watchdog(struct ifnet *); 268 static int axe_miibus_readreg_locked(device_t, int, int); 269 static int axe_miibus_readreg(device_t, int, int); 270 static void axe_miibus_writereg_locked(device_t, int, int, int); 271 static void axe_miibus_writereg(device_t, int, int, int); 272 static void axe_miibus_statchg(struct ifnet *); 273 static int axe_cmd(struct axe_softc *, int, int, int, void *); 274 static void axe_reset(struct axe_softc *); 275 276 static void axe_setmulti(struct axe_softc *); 277 static void axe_lock_mii(struct axe_softc *); 278 static void axe_unlock_mii(struct axe_softc *); 279 280 static void axe_ax88178_init(struct axe_softc *); 281 static void axe_ax88772_init(struct axe_softc *); 282 static void axe_ax88772a_init(struct axe_softc *); 283 static void axe_ax88772b_init(struct axe_softc *); 284 285 /* Get exclusive access to the MII registers */ 286 static void 287 axe_lock_mii(struct axe_softc *sc) 288 { 289 290 sc->axe_refcnt++; 291 mutex_enter(&sc->axe_mii_lock); 292 } 293 294 static void 295 axe_unlock_mii(struct axe_softc *sc) 296 { 297 298 mutex_exit(&sc->axe_mii_lock); 299 if (--sc->axe_refcnt < 0) 300 usb_detach_wakeupold((sc->axe_dev)); 301 } 302 303 static int 304 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 305 { 306 AXEHIST_FUNC(); AXEHIST_CALLED(); 307 usb_device_request_t req; 308 usbd_status err; 309 310 KASSERT(mutex_owned(&sc->axe_mii_lock)); 311 312 if (sc->axe_dying) 313 return 0; 314 315 DPRINTFN(20, "cmd %#x index %#x val %#x", cmd, index, val, 0); 316 317 if (AXE_CMD_DIR(cmd)) 318 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 319 else 320 req.bmRequestType = UT_READ_VENDOR_DEVICE; 321 req.bRequest = AXE_CMD_CMD(cmd); 322 USETW(req.wValue, val); 323 USETW(req.wIndex, index); 324 USETW(req.wLength, AXE_CMD_LEN(cmd)); 325 326 err = usbd_do_request(sc->axe_udev, &req, buf); 327 328 if (err) { 329 DPRINTF("cmd %d err %d", cmd, err, 0, 0); 330 return -1; 331 } 332 return 0; 333 } 334 335 static int 336 axe_miibus_readreg_locked(device_t dev, int phy, int reg) 337 { 338 AXEHIST_FUNC(); AXEHIST_CALLED(); 339 struct axe_softc *sc = device_private(dev); 340 usbd_status err; 341 uint16_t val; 342 343 DPRINTFN(30, "phy 0x%x reg 0x%x\n", phy, reg, 0, 0); 344 345 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 346 347 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, (void *)&val); 348 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 349 if (err) { 350 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 351 return -1; 352 } 353 354 val = le16toh(val); 355 if (AXE_IS_772(sc) && reg == MII_BMSR) { 356 /* 357 * BMSR of AX88772 indicates that it supports extended 358 * capability but the extended status register is 359 * reserved for embedded ethernet PHY. So clear the 360 * extended capability bit of BMSR. 361 */ 362 val &= ~BMSR_EXTCAP; 363 } 364 365 DPRINTFN(30, "phy 0x%x reg 0x%x val %#x", phy, reg, val, 0); 366 367 return val; 368 } 369 370 static int 371 axe_miibus_readreg(device_t dev, int phy, int reg) 372 { 373 struct axe_softc *sc = device_private(dev); 374 int val; 375 376 if (sc->axe_dying) 377 return 0; 378 379 if (sc->axe_phyno != phy) 380 return 0; 381 382 axe_lock_mii(sc); 383 val = axe_miibus_readreg_locked(dev, phy, reg); 384 axe_unlock_mii(sc); 385 386 return val; 387 } 388 389 static void 390 axe_miibus_writereg_locked(device_t dev, int phy, int reg, int aval) 391 { 392 struct axe_softc *sc = device_private(dev); 393 usbd_status err; 394 uint16_t val; 395 396 val = htole16(aval); 397 398 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 399 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, (void *)&val); 400 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 401 402 if (err) { 403 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 404 return; 405 } 406 } 407 408 static void 409 axe_miibus_writereg(device_t dev, int phy, int reg, int aval) 410 { 411 struct axe_softc *sc = device_private(dev); 412 413 if (sc->axe_dying) 414 return; 415 416 if (sc->axe_phyno != phy) 417 return; 418 419 axe_lock_mii(sc); 420 axe_miibus_writereg_locked(dev, phy, reg, aval); 421 axe_unlock_mii(sc); 422 } 423 424 static void 425 axe_miibus_statchg(struct ifnet *ifp) 426 { 427 AXEHIST_FUNC(); AXEHIST_CALLED(); 428 429 struct axe_softc *sc = ifp->if_softc; 430 struct mii_data *mii = &sc->axe_mii; 431 int val, err; 432 433 val = 0; 434 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 435 val |= AXE_MEDIA_FULL_DUPLEX; 436 if (AXE_IS_178_FAMILY(sc)) { 437 if ((IFM_OPTIONS(mii->mii_media_active) & 438 IFM_ETH_TXPAUSE) != 0) 439 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 440 if ((IFM_OPTIONS(mii->mii_media_active) & 441 IFM_ETH_RXPAUSE) != 0) 442 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 443 } 444 } 445 if (AXE_IS_178_FAMILY(sc)) { 446 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 447 if (sc->axe_flags & AX178) 448 val |= AXE_178_MEDIA_ENCK; 449 switch (IFM_SUBTYPE(mii->mii_media_active)) { 450 case IFM_1000_T: 451 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 452 break; 453 case IFM_100_TX: 454 val |= AXE_178_MEDIA_100TX; 455 break; 456 case IFM_10_T: 457 /* doesn't need to be handled */ 458 break; 459 } 460 } 461 462 DPRINTF("val=0x%x", val, 0, 0, 0); 463 axe_lock_mii(sc); 464 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 465 axe_unlock_mii(sc); 466 if (err) { 467 aprint_error_dev(sc->axe_dev, "media change failed\n"); 468 return; 469 } 470 } 471 472 static void 473 axe_setmulti(struct axe_softc *sc) 474 { 475 AXEHIST_FUNC(); AXEHIST_CALLED(); 476 struct ifnet *ifp = &sc->sc_if; 477 struct ether_multi *enm; 478 struct ether_multistep step; 479 uint32_t h = 0; 480 uint16_t rxmode; 481 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 482 483 if (sc->axe_dying) 484 return; 485 486 axe_lock_mii(sc); 487 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, (void *)&rxmode); 488 rxmode = le16toh(rxmode); 489 490 rxmode &= 491 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 492 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 493 494 rxmode |= 495 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 496 497 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 498 if (ifp->if_flags & IFF_PROMISC) 499 rxmode |= AXE_RXCMD_PROMISC; 500 goto allmulti; 501 } 502 503 /* Now program new ones */ 504 ETHER_FIRST_MULTI(step, &sc->axe_ec, enm); 505 while (enm != NULL) { 506 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 507 ETHER_ADDR_LEN) != 0) 508 goto allmulti; 509 510 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 511 hashtbl[h >> 3] |= 1U << (h & 7); 512 ETHER_NEXT_MULTI(step, enm); 513 } 514 ifp->if_flags &= ~IFF_ALLMULTI; 515 rxmode |= AXE_RXCMD_MULTICAST; 516 517 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 518 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 519 axe_unlock_mii(sc); 520 return; 521 522 allmulti: 523 ifp->if_flags |= IFF_ALLMULTI; 524 rxmode |= AXE_RXCMD_ALLMULTI; 525 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 526 axe_unlock_mii(sc); 527 } 528 529 530 static void 531 axe_reset(struct axe_softc *sc) 532 { 533 534 if (sc->axe_dying) 535 return; 536 537 /* 538 * softnet_lock can be taken when NET_MPAFE is not defined when calling 539 * if_addr_init -> if_init. This doesn't mixe well with the 540 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 541 * can fire during the wait and attempt to take softnet_lock and then 542 * block the softclk thread meaing the wait never ends. 543 */ 544 #ifndef NET_MPSAFE 545 /* XXX What to reset? */ 546 547 /* Wait a little while for the chip to get its brains in order. */ 548 DELAY(1000); 549 #else 550 axe_lock_mii(sc); 551 552 if (sc->axe_flags & AX178) { 553 axe_ax88178_init(sc); 554 } else if (sc->axe_flags & AX772) { 555 axe_ax88772_init(sc); 556 } else if (sc->axe_flags & AX772A) { 557 axe_ax88772a_init(sc); 558 } else if (sc->axe_flags & AX772B) { 559 axe_ax88772b_init(sc); 560 } 561 axe_unlock_mii(sc); 562 #endif 563 } 564 565 static int 566 axe_get_phyno(struct axe_softc *sc, int sel) 567 { 568 int phyno; 569 570 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 571 case PHY_TYPE_100_HOME: 572 /* FALLTHROUGH */ 573 case PHY_TYPE_GIG: 574 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 575 break; 576 case PHY_TYPE_SPECIAL: 577 /* FALLTHROUGH */ 578 case PHY_TYPE_RSVD: 579 /* FALLTHROUGH */ 580 case PHY_TYPE_NON_SUP: 581 /* FALLTHROUGH */ 582 default: 583 phyno = -1; 584 break; 585 } 586 587 return phyno; 588 } 589 590 #define AXE_GPIO_WRITE(x, y) do { \ 591 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 592 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 593 } while (0) 594 595 static void 596 axe_ax88178_init(struct axe_softc *sc) 597 { 598 AXEHIST_FUNC(); AXEHIST_CALLED(); 599 int gpio0, ledmode, phymode; 600 uint16_t eeprom, val; 601 602 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 603 /* XXX magic */ 604 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 605 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 606 607 eeprom = le16toh(eeprom); 608 609 DPRINTF("EEPROM is 0x%x", eeprom, 0, 0, 0); 610 611 /* if EEPROM is invalid we have to use to GPIO0 */ 612 if (eeprom == 0xffff) { 613 phymode = AXE_PHY_MODE_MARVELL; 614 gpio0 = 1; 615 ledmode = 0; 616 } else { 617 phymode = eeprom & 0x7f; 618 gpio0 = (eeprom & 0x80) ? 0 : 1; 619 ledmode = eeprom >> 8; 620 } 621 622 DPRINTF("use gpio0: %d, phymode %d", gpio0, phymode, 0, 0); 623 624 /* Program GPIOs depending on PHY hardware. */ 625 switch (phymode) { 626 case AXE_PHY_MODE_MARVELL: 627 if (gpio0 == 1) { 628 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 629 hz / 32); 630 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 631 hz / 32); 632 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 633 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 634 hz / 32); 635 } else { 636 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 637 AXE_GPIO1_EN, hz / 3); 638 if (ledmode == 1) { 639 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 640 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 641 hz / 3); 642 } else { 643 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 644 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 645 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 646 AXE_GPIO2_EN, hz / 4); 647 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 648 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 649 } 650 } 651 break; 652 case AXE_PHY_MODE_CICADA: 653 case AXE_PHY_MODE_CICADA_V2: 654 case AXE_PHY_MODE_CICADA_V2_ASIX: 655 if (gpio0 == 1) 656 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 657 AXE_GPIO0_EN, hz / 32); 658 else 659 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 660 AXE_GPIO1_EN, hz / 32); 661 break; 662 case AXE_PHY_MODE_AGERE: 663 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 664 AXE_GPIO1_EN, hz / 32); 665 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 666 AXE_GPIO2_EN, hz / 32); 667 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 668 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 669 AXE_GPIO2_EN, hz / 32); 670 break; 671 case AXE_PHY_MODE_REALTEK_8211CL: 672 case AXE_PHY_MODE_REALTEK_8211BN: 673 case AXE_PHY_MODE_REALTEK_8251CL: 674 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 675 AXE_GPIO1 | AXE_GPIO1_EN; 676 AXE_GPIO_WRITE(val, hz / 32); 677 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 678 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 679 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 680 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 681 axe_miibus_writereg_locked(sc->axe_dev, 682 sc->axe_phyno, 0x1F, 0x0005); 683 axe_miibus_writereg_locked(sc->axe_dev, 684 sc->axe_phyno, 0x0C, 0x0000); 685 val = axe_miibus_readreg_locked(sc->axe_dev, 686 sc->axe_phyno, 0x0001); 687 axe_miibus_writereg_locked(sc->axe_dev, 688 sc->axe_phyno, 0x01, val | 0x0080); 689 axe_miibus_writereg_locked(sc->axe_dev, 690 sc->axe_phyno, 0x1F, 0x0000); 691 } 692 break; 693 default: 694 /* Unknown PHY model or no need to program GPIOs. */ 695 break; 696 } 697 698 /* soft reset */ 699 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 700 usbd_delay_ms(sc->axe_udev, 150); 701 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 702 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 703 usbd_delay_ms(sc->axe_udev, 150); 704 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 705 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 706 usbd_delay_ms(sc->axe_udev, 10); 707 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 708 } 709 710 static void 711 axe_ax88772_init(struct axe_softc *sc) 712 { 713 AXEHIST_FUNC(); AXEHIST_CALLED(); 714 715 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 716 usbd_delay_ms(sc->axe_udev, 40); 717 718 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 719 /* ask for the embedded PHY */ 720 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 721 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 722 usbd_delay_ms(sc->axe_udev, 10); 723 724 /* power down and reset state, pin reset state */ 725 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 726 usbd_delay_ms(sc->axe_udev, 60); 727 728 /* power down/reset state, pin operating state */ 729 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 730 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 731 usbd_delay_ms(sc->axe_udev, 150); 732 733 /* power up, reset */ 734 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 735 736 /* power up, operating */ 737 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 738 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 739 } else { 740 /* ask for external PHY */ 741 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 742 NULL); 743 usbd_delay_ms(sc->axe_udev, 10); 744 745 /* power down internal PHY */ 746 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 747 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 748 } 749 750 usbd_delay_ms(sc->axe_udev, 150); 751 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 752 } 753 754 static int 755 axe_ifflags_cb(struct ethercom *ec) 756 { 757 struct ifnet *ifp = &ec->ec_if; 758 struct axe_softc *sc = ifp->if_softc; 759 int rc = 0; 760 761 mutex_enter(&sc->axe_lock); 762 int change = ifp->if_flags ^ sc->axe_if_flags; 763 sc->axe_if_flags = ifp->if_flags; 764 765 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) { 766 rc = ENETRESET; 767 goto out; 768 } 769 770 if ((change & IFF_PROMISC) != 0) { 771 axe_setmulti(sc); 772 } 773 774 out: 775 mutex_exit(&sc->axe_lock); 776 777 return rc; 778 } 779 780 static void 781 axe_ax88772_phywake(struct axe_softc *sc) 782 { 783 AXEHIST_FUNC(); AXEHIST_CALLED(); 784 785 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 786 /* Manually select internal(embedded) PHY - MAC mode. */ 787 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 788 AXE_SW_PHY_SELECT_EMBEDDED, 789 NULL); 790 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 791 } else { 792 /* 793 * Manually select external PHY - MAC mode. 794 * Reverse MII/RMII is for AX88772A PHY mode. 795 */ 796 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 797 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 798 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 799 } 800 801 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 802 AXE_SW_RESET_IPRL, NULL); 803 804 /* T1 = min 500ns everywhere */ 805 usbd_delay_ms(sc->axe_udev, 150); 806 807 /* Take PHY out of power down. */ 808 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 809 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 810 } else { 811 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 812 } 813 814 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 815 usbd_delay_ms(sc->axe_udev, 600); 816 817 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 818 819 /* T3 = 500ns everywhere */ 820 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 821 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 822 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 823 } 824 825 static void 826 axe_ax88772a_init(struct axe_softc *sc) 827 { 828 AXEHIST_FUNC(); AXEHIST_CALLED(); 829 830 /* Reload EEPROM. */ 831 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 832 axe_ax88772_phywake(sc); 833 /* Stop MAC. */ 834 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 835 } 836 837 static void 838 axe_ax88772b_init(struct axe_softc *sc) 839 { 840 AXEHIST_FUNC(); AXEHIST_CALLED(); 841 uint16_t eeprom; 842 int i; 843 844 /* Reload EEPROM. */ 845 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 846 847 /* 848 * Save PHY power saving configuration(high byte) and 849 * clear EEPROM checksum value(low byte). 850 */ 851 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 852 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 853 854 /* 855 * Auto-loaded default station address from internal ROM is 856 * 00:00:00:00:00:00 such that an explicit access to EEPROM 857 * is required to get real station address. 858 */ 859 uint8_t *eaddr = sc->axe_enaddr; 860 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 861 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 862 &eeprom); 863 eeprom = le16toh(eeprom); 864 *eaddr++ = (uint8_t)(eeprom & 0xFF); 865 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 866 } 867 /* Wakeup PHY. */ 868 axe_ax88772_phywake(sc); 869 /* Stop MAC. */ 870 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 871 } 872 873 #undef AXE_GPIO_WRITE 874 875 /* 876 * Probe for a AX88172 chip. 877 */ 878 int 879 axe_match(device_t parent, cfdata_t match, void *aux) 880 { 881 struct usb_attach_arg *uaa = aux; 882 883 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 884 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 885 } 886 887 /* 888 * Attach the interface. Allocate softc structures, do ifmedia 889 * setup and ethernet/BPF attach. 890 */ 891 void 892 axe_attach(device_t parent, device_t self, void *aux) 893 { 894 AXEHIST_FUNC(); AXEHIST_CALLED(); 895 struct axe_softc *sc = device_private(self); 896 struct usb_attach_arg *uaa = aux; 897 struct usbd_device *dev = uaa->uaa_device; 898 usbd_status err; 899 usb_interface_descriptor_t *id; 900 usb_endpoint_descriptor_t *ed; 901 struct mii_data *mii; 902 char *devinfop; 903 const char *devname = device_xname(self); 904 struct ifnet *ifp; 905 int i, s; 906 907 aprint_naive("\n"); 908 aprint_normal("\n"); 909 910 sc->axe_dev = self; 911 sc->axe_udev = dev; 912 913 devinfop = usbd_devinfo_alloc(dev, 0); 914 aprint_normal_dev(self, "%s\n", devinfop); 915 usbd_devinfo_free(devinfop); 916 917 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 918 if (err) { 919 aprint_error_dev(self, "failed to set configuration" 920 ", err=%s\n", usbd_errstr(err)); 921 return; 922 } 923 924 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 925 926 mutex_init(&sc->axe_lock, MUTEX_DEFAULT, IPL_NONE); 927 mutex_init(&sc->axe_txlock, MUTEX_DEFAULT, IPL_SOFTUSB); 928 mutex_init(&sc->axe_rxlock, MUTEX_DEFAULT, IPL_SOFTUSB); 929 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 930 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 931 932 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 933 if (err) { 934 aprint_error_dev(self, "getting interface handle failed\n"); 935 return; 936 } 937 938 sc->axe_product = uaa->uaa_product; 939 sc->axe_vendor = uaa->uaa_vendor; 940 941 id = usbd_get_interface_descriptor(sc->axe_iface); 942 943 /* decide on what our bufsize will be */ 944 if (AXE_IS_178_FAMILY(sc)) 945 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 946 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 947 else 948 sc->axe_bufsz = AXE_172_BUFSZ; 949 950 sc->axe_ed[AXE_ENDPT_RX] = -1; 951 sc->axe_ed[AXE_ENDPT_TX] = -1; 952 sc->axe_ed[AXE_ENDPT_INTR] = -1; 953 954 /* Find endpoints. */ 955 for (i = 0; i < id->bNumEndpoints; i++) { 956 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 957 if (ed == NULL) { 958 aprint_error_dev(self, "couldn't get ep %d\n", i); 959 return; 960 } 961 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 962 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 963 964 if (dir == UE_DIR_IN && xt == UE_BULK && 965 sc->axe_ed[AXE_ENDPT_RX] == -1) { 966 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 967 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 968 sc->axe_ed[AXE_ENDPT_TX] == -1) { 969 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 970 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 971 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 972 } 973 } 974 975 s = splnet(); 976 977 /* We need the PHYID for init dance in some cases */ 978 axe_lock_mii(sc); 979 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, (void *)&sc->axe_phyaddrs); 980 981 DPRINTF(" phyaddrs[0]: %x phyaddrs[1]: %x", 982 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 983 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 984 if (sc->axe_phyno == -1) 985 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 986 if (sc->axe_phyno == -1) { 987 DPRINTF(" no valid PHY address found, assuming PHY address 0", 988 0, 0, 0, 0); 989 sc->axe_phyno = 0; 990 } 991 992 /* Initialize controller and get station address. */ 993 994 if (sc->axe_flags & AX178) { 995 axe_ax88178_init(sc); 996 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 997 } else if (sc->axe_flags & AX772) { 998 axe_ax88772_init(sc); 999 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 1000 } else if (sc->axe_flags & AX772A) { 1001 axe_ax88772a_init(sc); 1002 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 1003 } else if (sc->axe_flags & AX772B) { 1004 axe_ax88772b_init(sc); 1005 } else 1006 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 1007 1008 /* 1009 * Fetch IPG values. 1010 */ 1011 if (sc->axe_flags & (AX772A | AX772B)) { 1012 /* Set IPG values. */ 1013 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 1014 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 1015 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1016 } else 1017 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs); 1018 1019 axe_unlock_mii(sc); 1020 1021 /* 1022 * An ASIX chip was detected. Inform the world. 1023 */ 1024 aprint_normal_dev(self, "Ethernet address %s\n", 1025 ether_sprintf(sc->axe_enaddr)); 1026 1027 /* Initialize interface info.*/ 1028 ifp = &sc->sc_if; 1029 ifp->if_softc = sc; 1030 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 1031 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1032 ifp->if_extflags = IFEF_START_MPSAFE; 1033 ifp->if_ioctl = axe_ioctl; 1034 ifp->if_start = axe_start; 1035 ifp->if_init = axe_init; 1036 ifp->if_stop = axe_stop; 1037 ifp->if_watchdog = axe_watchdog; 1038 1039 IFQ_SET_READY(&ifp->if_snd); 1040 1041 if (AXE_IS_178_FAMILY(sc)) 1042 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1043 if (sc->axe_flags & AX772B) { 1044 ifp->if_capabilities = 1045 IFCAP_CSUM_IPv4_Rx | 1046 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1047 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1048 /* 1049 * Checksum offloading of AX88772B also works with VLAN 1050 * tagged frames but there is no way to take advantage 1051 * of the feature because vlan(4) assumes 1052 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1053 * support checksum offloading with VLAN. VLAN hardware 1054 * tagging support of AX88772B is very limited so it's 1055 * not possible to announce IFCAP_VLAN_HWTAGGING. 1056 */ 1057 } 1058 u_int adv_pause; 1059 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1060 adv_pause = MIIF_DOPAUSE; 1061 else 1062 adv_pause = 0; 1063 adv_pause = 0; 1064 1065 /* Initialize MII/media info. */ 1066 mii = &sc->axe_mii; 1067 mii->mii_ifp = ifp; 1068 mii->mii_readreg = axe_miibus_readreg; 1069 mii->mii_writereg = axe_miibus_writereg; 1070 mii->mii_statchg = axe_miibus_statchg; 1071 mii->mii_flags = MIIF_AUTOTSLEEP; 1072 1073 sc->axe_ec.ec_mii = mii; 1074 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1075 1076 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1077 adv_pause); 1078 1079 if (LIST_EMPTY(&mii->mii_phys)) { 1080 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1081 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1082 } else 1083 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1084 1085 /* Attach the interface. */ 1086 if_initialize(ifp); 1087 sc->axe_ipq = if_percpuq_create(&sc->axe_ec.ec_if); 1088 ether_ifattach(ifp, sc->axe_enaddr); 1089 if_register(ifp); 1090 ether_set_ifflags_cb(&sc->axe_ec, axe_ifflags_cb); 1091 1092 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1093 RND_TYPE_NET, RND_FLAG_DEFAULT); 1094 1095 callout_init(&sc->axe_stat_ch, 0); 1096 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1097 1098 sc->axe_attached = true; 1099 splx(s); 1100 1101 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1102 1103 if (!pmf_device_register(self, NULL, NULL)) 1104 aprint_error_dev(self, "couldn't establish power handler\n"); 1105 } 1106 1107 int 1108 axe_detach(device_t self, int flags) 1109 { 1110 AXEHIST_FUNC(); AXEHIST_CALLED(); 1111 struct axe_softc *sc = device_private(self); 1112 int s; 1113 struct ifnet *ifp = &sc->sc_if; 1114 1115 /* Detached before attached finished, so just bail out. */ 1116 if (!sc->axe_attached) 1117 return 0; 1118 1119 pmf_device_deregister(self); 1120 1121 sc->axe_dying = true; 1122 1123 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1124 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1125 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1126 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1127 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1128 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1129 1130 /* 1131 * Remove any pending tasks. They cannot be executing because they run 1132 * in the same thread as detach. 1133 */ 1134 usb_rem_task(sc->axe_udev, &sc->axe_tick_task); 1135 1136 s = splusb(); 1137 1138 if (ifp->if_flags & IFF_RUNNING) 1139 axe_stop(ifp, 1); 1140 1141 1142 if (--sc->axe_refcnt >= 0) { 1143 /* Wait for processes to go away. */ 1144 usb_detach_waitold(sc->axe_dev); 1145 } 1146 1147 callout_destroy(&sc->axe_stat_ch); 1148 mutex_destroy(&sc->axe_lock); 1149 mutex_destroy(&sc->axe_txlock); 1150 mutex_destroy(&sc->axe_rxlock); 1151 mutex_destroy(&sc->axe_mii_lock); 1152 rnd_detach_source(&sc->rnd_source); 1153 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1154 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1155 ether_ifdetach(ifp); 1156 if_detach(ifp); 1157 1158 #ifdef DIAGNOSTIC 1159 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1160 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1161 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1162 aprint_debug_dev(self, "detach has active endpoints\n"); 1163 #endif 1164 1165 sc->axe_attached = false; 1166 1167 splx(s); 1168 1169 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1170 1171 return 0; 1172 } 1173 1174 int 1175 axe_activate(device_t self, devact_t act) 1176 { 1177 AXEHIST_FUNC(); AXEHIST_CALLED(); 1178 struct axe_softc *sc = device_private(self); 1179 1180 switch (act) { 1181 case DVACT_DEACTIVATE: 1182 if_deactivate(&sc->axe_ec.ec_if); 1183 sc->axe_dying = true; 1184 return 0; 1185 default: 1186 return EOPNOTSUPP; 1187 } 1188 } 1189 1190 static int 1191 axe_rx_list_init(struct axe_softc *sc) 1192 { 1193 AXEHIST_FUNC(); AXEHIST_CALLED(); 1194 1195 struct axe_cdata *cd; 1196 struct axe_chain *c; 1197 int i; 1198 1199 cd = &sc->axe_cdata; 1200 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1201 c = &cd->axe_rx_chain[i]; 1202 c->axe_sc = sc; 1203 c->axe_idx = i; 1204 if (c->axe_xfer == NULL) { 1205 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1206 sc->axe_bufsz, USBD_SHORT_XFER_OK, 0, &c->axe_xfer); 1207 if (err) 1208 return err; 1209 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1210 } 1211 } 1212 1213 return 0; 1214 } 1215 1216 static void 1217 axe_rx_list_free(struct axe_softc *sc) 1218 { 1219 /* Free RX resources */ 1220 for (size_t i = 0; i < AXE_RX_LIST_CNT; i++) { 1221 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1222 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1223 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1224 } 1225 } 1226 } 1227 1228 static int 1229 axe_tx_list_init(struct axe_softc *sc) 1230 { 1231 AXEHIST_FUNC(); AXEHIST_CALLED(); 1232 struct axe_cdata *cd; 1233 struct axe_chain *c; 1234 int i; 1235 1236 cd = &sc->axe_cdata; 1237 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1238 c = &cd->axe_tx_chain[i]; 1239 c->axe_sc = sc; 1240 c->axe_idx = i; 1241 if (c->axe_xfer == NULL) { 1242 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1243 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1244 &c->axe_xfer); 1245 if (err) 1246 return err; 1247 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1248 } 1249 } 1250 1251 return 0; 1252 } 1253 1254 static void 1255 axe_tx_list_free(struct axe_softc *sc) 1256 { 1257 /* Free TX resources */ 1258 for (size_t i = 0; i < AXE_TX_LIST_CNT; i++) { 1259 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1260 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1261 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1262 } 1263 } 1264 } 1265 1266 /* 1267 * A frame has been uploaded: pass the resulting mbuf chain up to 1268 * the higher level protocols. 1269 */ 1270 static void 1271 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1272 { 1273 AXEHIST_FUNC(); AXEHIST_CALLED(); 1274 struct axe_softc *sc; 1275 struct axe_chain *c; 1276 struct ifnet *ifp; 1277 uint8_t *buf; 1278 uint32_t total_len; 1279 struct mbuf *m; 1280 1281 c = (struct axe_chain *)priv; 1282 sc = c->axe_sc; 1283 buf = c->axe_buf; 1284 ifp = &sc->sc_if; 1285 1286 if (sc->axe_dying) 1287 return; 1288 1289 if ((ifp->if_flags & IFF_RUNNING) == 0) 1290 return; 1291 1292 if (status != USBD_NORMAL_COMPLETION) { 1293 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1294 return; 1295 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1296 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1297 usbd_errstr(status)); 1298 } 1299 if (status == USBD_STALLED) 1300 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1301 goto done; 1302 } 1303 1304 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1305 1306 do { 1307 u_int pktlen = 0; 1308 u_int rxlen = 0; 1309 int flags = 0; 1310 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1311 struct axe_sframe_hdr hdr; 1312 1313 if (total_len < sizeof(hdr)) { 1314 ifp->if_ierrors++; 1315 goto done; 1316 } 1317 1318 memcpy(&hdr, buf, sizeof(hdr)); 1319 1320 DPRINTFN(20, "total_len %#x len %x ilen %#x", 1321 total_len, 1322 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1323 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1324 1325 total_len -= sizeof(hdr); 1326 buf += sizeof(hdr); 1327 1328 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1329 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1330 AXE_RH1M_RXLEN_MASK) { 1331 ifp->if_ierrors++; 1332 goto done; 1333 } 1334 1335 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1336 if (total_len < rxlen) { 1337 pktlen = total_len; 1338 total_len = 0; 1339 } else { 1340 pktlen = rxlen; 1341 rxlen = roundup2(rxlen, 2); 1342 total_len -= rxlen; 1343 } 1344 1345 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1346 struct axe_csum_hdr csum_hdr; 1347 1348 if (total_len < sizeof(csum_hdr)) { 1349 ifp->if_ierrors++; 1350 goto done; 1351 } 1352 1353 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1354 1355 csum_hdr.len = le16toh(csum_hdr.len); 1356 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1357 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1358 1359 DPRINTFN(20, "total_len %#x len %#x ilen %#x" 1360 " cstatus %#x", total_len, 1361 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1362 1363 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1364 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1365 sc->sc_lenmask) { 1366 /* we lost sync */ 1367 ifp->if_ierrors++; 1368 DPRINTFN(20, "len %#x ilen %#x lenmask %#x err", 1369 AXE_CSUM_RXBYTES(csum_hdr.len), 1370 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1371 sc->sc_lenmask, 0); 1372 goto done; 1373 } 1374 /* 1375 * Get total transferred frame length including 1376 * checksum header. The length should be multiple 1377 * of 4. 1378 */ 1379 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1380 u_int len = sizeof(csum_hdr) + pktlen; 1381 len = (len + 3) & ~3; 1382 if (total_len < len) { 1383 DPRINTFN(20, "total_len %#x < len %#x", 1384 total_len, len, 0, 0); 1385 /* invalid length */ 1386 ifp->if_ierrors++; 1387 goto done; 1388 } 1389 buf += sizeof(csum_hdr); 1390 1391 const uint16_t cstatus = csum_hdr.cstatus; 1392 1393 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1394 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1395 flags |= M_CSUM_TCP_UDP_BAD; 1396 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1397 flags |= M_CSUM_IPv4_BAD; 1398 1399 const uint16_t l4type = 1400 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1401 1402 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1403 flags |= M_CSUM_TCPv4; 1404 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1405 flags |= M_CSUM_UDPv4; 1406 } 1407 if (total_len < len) { 1408 pktlen = total_len; 1409 total_len = 0; 1410 } else { 1411 total_len -= len; 1412 rxlen = len - sizeof(csum_hdr); 1413 } 1414 DPRINTFN(20, "total_len %#x len %#x pktlen %#x" 1415 " rxlen %#x", total_len, len, pktlen, rxlen); 1416 } else { /* AX172 */ 1417 pktlen = rxlen = total_len; 1418 total_len = 0; 1419 } 1420 1421 MGETHDR(m, M_DONTWAIT, MT_DATA); 1422 if (m == NULL) { 1423 ifp->if_ierrors++; 1424 goto done; 1425 } 1426 1427 if (pktlen > MHLEN - ETHER_ALIGN) { 1428 MCLGET(m, M_DONTWAIT); 1429 if ((m->m_flags & M_EXT) == 0) { 1430 m_freem(m); 1431 ifp->if_ierrors++; 1432 goto done; 1433 } 1434 } 1435 m->m_data += ETHER_ALIGN; 1436 1437 m_set_rcvif(m, ifp); 1438 m->m_pkthdr.len = m->m_len = pktlen; 1439 m->m_pkthdr.csum_flags = flags; 1440 1441 memcpy(mtod(m, uint8_t *), buf, pktlen); 1442 buf += rxlen; 1443 1444 DPRINTFN(10, "deliver %d (%#x)", m->m_len, m->m_len, 0, 0); 1445 1446 if_percpuq_enqueue(sc->axe_ipq, (m)); 1447 } while (total_len > 0); 1448 1449 done: 1450 1451 /* Setup new transfer. */ 1452 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1453 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1454 usbd_transfer(xfer); 1455 1456 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1457 } 1458 1459 /* 1460 * A frame was downloaded to the chip. It's safe for us to clean up 1461 * the list buffers. 1462 */ 1463 1464 static void 1465 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1466 { 1467 AXEHIST_FUNC(); AXEHIST_CALLED(); 1468 struct axe_chain *c = priv; 1469 struct axe_softc *sc = c->axe_sc; 1470 struct ifnet *ifp = &sc->sc_if; 1471 int s; 1472 1473 1474 if (sc->axe_dying) 1475 return; 1476 1477 s = splnet(); 1478 1479 ifp->if_timer = 0; 1480 ifp->if_flags &= ~IFF_OACTIVE; 1481 1482 if (status != USBD_NORMAL_COMPLETION) { 1483 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1484 splx(s); 1485 return; 1486 } 1487 ifp->if_oerrors++; 1488 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1489 usbd_errstr(status)); 1490 if (status == USBD_STALLED) 1491 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1492 splx(s); 1493 return; 1494 } 1495 ifp->if_opackets++; 1496 1497 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1498 axe_start(ifp); 1499 1500 splx(s); 1501 } 1502 1503 static void 1504 axe_tick(void *xsc) 1505 { 1506 AXEHIST_FUNC(); AXEHIST_CALLED(); 1507 struct axe_softc *sc = xsc; 1508 1509 if (sc == NULL) 1510 return; 1511 1512 if (sc->axe_dying) 1513 return; 1514 1515 /* Perform periodic stuff in process context */ 1516 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1517 } 1518 1519 static void 1520 axe_tick_task(void *xsc) 1521 { 1522 AXEHIST_FUNC(); AXEHIST_CALLED(); 1523 int s; 1524 struct axe_softc *sc = xsc; 1525 struct ifnet *ifp; 1526 struct mii_data *mii; 1527 1528 if (sc == NULL) 1529 return; 1530 1531 if (sc->axe_dying) 1532 return; 1533 1534 ifp = &sc->sc_if; 1535 mii = &sc->axe_mii; 1536 1537 if (mii == NULL) 1538 return; 1539 1540 s = splnet(); 1541 1542 mii_tick(mii); 1543 if (sc->axe_link == 0 && 1544 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1545 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1546 DPRINTF("got link", 0, 0, 0, 0); 1547 sc->axe_link++; 1548 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1549 axe_start(ifp); 1550 } 1551 1552 callout_schedule(&sc->axe_stat_ch, hz); 1553 1554 splx(s); 1555 } 1556 1557 static int 1558 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1559 { 1560 struct ifnet *ifp = &sc->sc_if; 1561 struct axe_chain *c; 1562 usbd_status err; 1563 int length, boundary; 1564 1565 c = &sc->axe_cdata.axe_tx_chain[idx]; 1566 1567 /* 1568 * Copy the mbuf data into a contiguous buffer, leaving two 1569 * bytes at the beginning to hold the frame length. 1570 */ 1571 if (AXE_IS_178_FAMILY(sc)) { 1572 struct axe_sframe_hdr hdr; 1573 1574 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1575 1576 hdr.len = htole16(m->m_pkthdr.len); 1577 hdr.ilen = ~hdr.len; 1578 1579 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1580 length = sizeof(hdr); 1581 1582 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1583 length += m->m_pkthdr.len; 1584 1585 if ((length % boundary) == 0) { 1586 hdr.len = 0x0000; 1587 hdr.ilen = 0xffff; 1588 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1589 length += sizeof(hdr); 1590 } 1591 } else { 1592 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1593 length = m->m_pkthdr.len; 1594 } 1595 1596 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1597 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1598 1599 /* Transmit */ 1600 err = usbd_transfer(c->axe_xfer); 1601 if (err != USBD_IN_PROGRESS) { 1602 axe_stop(ifp, 0); 1603 return EIO; 1604 } 1605 1606 sc->axe_cdata.axe_tx_cnt++; 1607 1608 return 0; 1609 } 1610 1611 1612 static void 1613 axe_csum_cfg(struct axe_softc *sc) 1614 { 1615 struct ifnet *ifp = &sc->sc_if; 1616 uint16_t csum1, csum2; 1617 1618 if ((sc->axe_flags & AX772B) != 0) { 1619 csum1 = 0; 1620 csum2 = 0; 1621 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1622 csum1 |= AXE_TXCSUM_IP; 1623 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1624 csum1 |= AXE_TXCSUM_TCP; 1625 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1626 csum1 |= AXE_TXCSUM_UDP; 1627 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1628 csum1 |= AXE_TXCSUM_TCPV6; 1629 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1630 csum1 |= AXE_TXCSUM_UDPV6; 1631 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1632 csum1 = 0; 1633 csum2 = 0; 1634 1635 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1636 csum1 |= AXE_RXCSUM_IP; 1637 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1638 csum1 |= AXE_RXCSUM_TCP; 1639 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1640 csum1 |= AXE_RXCSUM_UDP; 1641 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1642 csum1 |= AXE_RXCSUM_TCPV6; 1643 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1644 csum1 |= AXE_RXCSUM_UDPV6; 1645 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1646 } 1647 } 1648 1649 static void 1650 axe_start(struct ifnet *ifp) 1651 { 1652 struct axe_softc *sc = ifp->if_softc; 1653 1654 mutex_enter(&sc->axe_txlock); 1655 axe_start_locked(ifp); 1656 mutex_exit(&sc->axe_txlock); 1657 } 1658 1659 static void 1660 axe_start_locked(struct ifnet *ifp) 1661 { 1662 struct axe_softc *sc = ifp->if_softc; 1663 struct mbuf *m; 1664 1665 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) 1666 return; 1667 1668 IFQ_POLL(&ifp->if_snd, m); 1669 if (m == NULL) { 1670 return; 1671 } 1672 1673 if (axe_encap(sc, m, 0)) { 1674 return; 1675 } 1676 IFQ_DEQUEUE(&ifp->if_snd, m); 1677 1678 /* 1679 * If there's a BPF listener, bounce a copy of this frame 1680 * to him. 1681 */ 1682 bpf_mtap(ifp, m); 1683 m_freem(m); 1684 1685 ifp->if_flags |= IFF_OACTIVE; 1686 1687 /* 1688 * Set a timeout in case the chip goes out to lunch. 1689 */ 1690 ifp->if_timer = 5; 1691 1692 return; 1693 } 1694 1695 static int 1696 axe_init(struct ifnet *ifp) 1697 { 1698 struct axe_softc *sc = ifp->if_softc; 1699 1700 mutex_enter(&sc->axe_lock); 1701 int ret = axe_init_locked(ifp); 1702 mutex_exit(&sc->axe_lock); 1703 1704 return ret; 1705 } 1706 1707 static int 1708 axe_init_locked(struct ifnet *ifp) 1709 { 1710 AXEHIST_FUNC(); AXEHIST_CALLED(); 1711 struct axe_softc *sc = ifp->if_softc; 1712 usbd_status err; 1713 int rxmode; 1714 int i, error; 1715 1716 axe_stop_locked(ifp, 0); 1717 1718 /* 1719 * Cancel pending I/O and free all RX/TX buffers. 1720 */ 1721 axe_reset(sc); 1722 1723 axe_lock_mii(sc); 1724 1725 #if 0 1726 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1727 AX_GPIO_GPO2EN, 5, in_pm); 1728 #endif 1729 /* Set MAC address and transmitter IPG values. */ 1730 if (AXE_IS_178_FAMILY(sc)) { 1731 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1732 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1733 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1734 } else { 1735 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1736 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1737 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1738 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1739 } 1740 if (AXE_IS_178_FAMILY(sc)) { 1741 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1742 if ((sc->axe_flags & AX772B) != 0 && 1743 (ifp->if_capenable & AX_RXCSUM) != 0) { 1744 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1745 sc->axe_flags |= AXCSUM_FRAME; 1746 } else { 1747 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1748 sc->axe_flags |= AXSTD_FRAME; 1749 } 1750 } 1751 1752 /* Configure TX/RX checksum offloading. */ 1753 axe_csum_cfg(sc); 1754 1755 if (sc->axe_flags & AX772B) { 1756 /* AX88772B uses different maximum frame burst configuration. */ 1757 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1758 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1759 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1760 } 1761 /* Enable receiver, set RX mode */ 1762 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1763 if (AXE_IS_178_FAMILY(sc)) { 1764 if (sc->axe_flags & AX772B) { 1765 /* 1766 * Select RX header format type 1. Aligning IP 1767 * header on 4 byte boundary is not needed when 1768 * checksum offloading feature is not used 1769 * because we always copy the received frame in 1770 * RX handler. When RX checksum offloading is 1771 * active, aligning IP header is required to 1772 * reflect actual frame length including RX 1773 * header size. 1774 */ 1775 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1776 if (sc->axe_flags & AXCSUM_FRAME) 1777 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1778 } else { 1779 /* 1780 * Default Rx buffer size is too small to get 1781 * maximum performance. 1782 */ 1783 #if 0 1784 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1785 /* Largest possible USB buffer size for AX88178 */ 1786 #endif 1787 rxmode |= AXE_178_RXCMD_MFB_16384; 1788 } 1789 } else { 1790 rxmode |= AXE_172_RXCMD_UNICAST; 1791 } 1792 1793 1794 /* If we want promiscuous mode, set the allframes bit. */ 1795 if (ifp->if_flags & IFF_PROMISC) 1796 rxmode |= AXE_RXCMD_PROMISC; 1797 1798 if (ifp->if_flags & IFF_BROADCAST) 1799 rxmode |= AXE_RXCMD_BROADCAST; 1800 1801 DPRINTF("rxmode 0x%#x", rxmode, 0, 0, 0); 1802 1803 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1804 axe_unlock_mii(sc); 1805 1806 /* Load the multicast filter. */ 1807 axe_setmulti(sc); 1808 1809 /* Open RX and TX pipes. */ 1810 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1811 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1812 if (err) { 1813 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1814 usbd_errstr(err)); 1815 error = EIO; 1816 goto fail; 1817 } 1818 1819 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1820 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1821 if (err) { 1822 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1823 usbd_errstr(err)); 1824 error = EIO; 1825 goto fail1; 1826 } 1827 1828 /* Init RX ring. */ 1829 if (axe_rx_list_init(sc) != 0) { 1830 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1831 error = ENOBUFS; 1832 goto fail2; 1833 } 1834 1835 /* Init TX ring. */ 1836 if (axe_tx_list_init(sc) != 0) { 1837 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1838 error = ENOBUFS; 1839 goto fail3; 1840 } 1841 1842 /* Start up the receive pipe. */ 1843 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1844 struct axe_chain *c = &sc->axe_cdata.axe_rx_chain[i]; 1845 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1846 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1847 usbd_transfer(c->axe_xfer); 1848 } 1849 1850 ifp->if_flags |= IFF_RUNNING; 1851 ifp->if_flags &= ~IFF_OACTIVE; 1852 1853 callout_schedule(&sc->axe_stat_ch, hz); 1854 1855 return 0; 1856 fail3: 1857 axe_rx_list_free(sc); 1858 fail2: 1859 usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1860 fail1: 1861 usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1862 fail: 1863 return error; 1864 } 1865 1866 static int 1867 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1868 { 1869 struct axe_softc *sc = ifp->if_softc; 1870 int s; 1871 int error = 0; 1872 1873 s = splnet(); 1874 error = ether_ioctl(ifp, cmd, data); 1875 splx(s); 1876 1877 if (error == ENETRESET) { 1878 error = 0; 1879 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) { 1880 if (ifp->if_flags & IFF_RUNNING) { 1881 mutex_enter(&sc->axe_lock); 1882 axe_setmulti(sc); 1883 mutex_exit(&sc->axe_lock); 1884 } 1885 } 1886 } 1887 1888 return error; 1889 } 1890 1891 static void 1892 axe_watchdog(struct ifnet *ifp) 1893 { 1894 struct axe_softc *sc; 1895 struct axe_chain *c; 1896 usbd_status stat; 1897 int s; 1898 1899 sc = ifp->if_softc; 1900 1901 ifp->if_oerrors++; 1902 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1903 1904 s = splusb(); 1905 c = &sc->axe_cdata.axe_tx_chain[0]; 1906 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1907 axe_txeof(c->axe_xfer, c, stat); 1908 1909 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1910 axe_start(ifp); 1911 splx(s); 1912 } 1913 1914 /* 1915 * Stop the adapter and free any mbufs allocated to the 1916 * RX and TX lists. 1917 */ 1918 1919 static void 1920 axe_stop(struct ifnet *ifp, int disable) 1921 { 1922 struct axe_softc *sc = ifp->if_softc; 1923 1924 mutex_enter(&sc->axe_lock); 1925 axe_stop_locked(ifp, disable); 1926 mutex_exit(&sc->axe_lock); 1927 } 1928 1929 static void 1930 axe_stop_locked(struct ifnet *ifp, int disable) 1931 { 1932 struct axe_softc *sc = ifp->if_softc; 1933 usbd_status err; 1934 1935 ifp->if_timer = 0; 1936 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1937 1938 callout_stop(&sc->axe_stat_ch); 1939 1940 /* Stop transfers. */ 1941 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1942 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1943 if (err) { 1944 aprint_error_dev(sc->axe_dev, 1945 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1946 } 1947 } 1948 1949 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1950 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1951 if (err) { 1952 aprint_error_dev(sc->axe_dev, 1953 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1954 } 1955 } 1956 1957 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1958 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1959 if (err) { 1960 aprint_error_dev(sc->axe_dev, 1961 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1962 } 1963 } 1964 1965 axe_reset(sc); 1966 1967 axe_rx_list_free(sc); 1968 1969 axe_tx_list_free(sc); 1970 1971 /* Close pipes. */ 1972 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1973 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1974 if (err) { 1975 aprint_error_dev(sc->axe_dev, 1976 "close rx pipe failed: %s\n", usbd_errstr(err)); 1977 } 1978 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1979 } 1980 1981 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1982 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1983 if (err) { 1984 aprint_error_dev(sc->axe_dev, 1985 "close tx pipe failed: %s\n", usbd_errstr(err)); 1986 } 1987 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1988 } 1989 1990 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1991 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1992 if (err) { 1993 aprint_error_dev(sc->axe_dev, 1994 "close intr pipe failed: %s\n", usbd_errstr(err)); 1995 } 1996 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1997 } 1998 1999 sc->axe_link = 0; 2000 } 2001 2002 MODULE(MODULE_CLASS_DRIVER, if_axe, "bpf"); 2003 2004 #ifdef _MODULE 2005 #include "ioconf.c" 2006 #endif 2007 2008 static int 2009 if_axe_modcmd(modcmd_t cmd, void *aux) 2010 { 2011 int error = 0; 2012 2013 switch (cmd) { 2014 case MODULE_CMD_INIT: 2015 #ifdef _MODULE 2016 error = config_init_component(cfdriver_ioconf_axe, 2017 cfattach_ioconf_axe, cfdata_ioconf_axe); 2018 #endif 2019 return error; 2020 case MODULE_CMD_FINI: 2021 #ifdef _MODULE 2022 error = config_fini_component(cfdriver_ioconf_axe, 2023 cfattach_ioconf_axe, cfdata_ioconf_axe); 2024 #endif 2025 return error; 2026 default: 2027 return ENOTTY; 2028 } 2029 } 2030
Indexes created Wed Oct 01 18:09:54 GMT 2025