if_axe.c revision 1.83
1 /* $NetBSD: if_axe.c,v 1.83 2017/10/28 00:37:12 pgoyette Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.83 2017/10/28 00:37:12 pgoyette Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 /* 131 * AXE_178_MAX_FRAME_BURST 132 * max frame burst size for Ax88178 and Ax88772 133 * 0 2048 bytes 134 * 1 4096 bytes 135 * 2 8192 bytes 136 * 3 16384 bytes 137 * use the largest your system can handle without USB stalling. 138 * 139 * NB: 88772 parts appear to generate lots of input errors with 140 * a 2K rx buffer and 8K is only slightly faster than 4K on an 141 * EHCI port on a T42 so change at your own risk. 142 */ 143 #define AXE_178_MAX_FRAME_BURST 1 144 145 146 #ifdef USB_DEBUG 147 #ifndef AXE_DEBUG 148 #define axedebug 0 149 #else 150 static int axedebug = 20; 151 152 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 153 { 154 int err; 155 const struct sysctlnode *rnode; 156 const struct sysctlnode *cnode; 157 158 err = sysctl_createv(clog, 0, NULL, &rnode, 159 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 160 SYSCTL_DESCR("axe global controls"), 161 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 162 163 if (err) 164 goto fail; 165 166 /* control debugging printfs */ 167 err = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 169 "debug", SYSCTL_DESCR("Enable debugging output"), 170 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 171 if (err) 172 goto fail; 173 174 return; 175 fail: 176 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 177 } 178 179 #endif /* AXE_DEBUG */ 180 #endif /* USB_DEBUG */ 181 182 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 183 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 184 #define AXEHIST_FUNC() USBHIST_FUNC() 185 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 186 187 /* 188 * Various supported device vendors/products. 189 */ 190 static const struct axe_type axe_devs[] = { 191 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 192 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 193 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 199 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 200 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 201 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 202 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 203 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 204 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 206 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 208 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 209 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 210 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 211 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 212 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 213 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 214 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 215 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 216 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 218 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 219 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 220 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 221 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 222 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 223 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 225 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 226 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 227 }; 228 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 229 230 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 231 { 0x8000, 0x8001, 2048 }, 232 { 0x8100, 0x8147, 4096 }, 233 { 0x8200, 0x81EB, 6144 }, 234 { 0x8300, 0x83D7, 8192 }, 235 { 0x8400, 0x851E, 16384 }, 236 { 0x8500, 0x8666, 20480 }, 237 { 0x8600, 0x87AE, 24576 }, 238 { 0x8700, 0x8A3D, 32768 } 239 }; 240 241 int axe_match(device_t, cfdata_t, void *); 242 void axe_attach(device_t, device_t, void *); 243 int axe_detach(device_t, int); 244 int axe_activate(device_t, devact_t); 245 246 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 247 axe_match, axe_attach, axe_detach, axe_activate); 248 249 static int axe_tx_list_init(struct axe_softc *); 250 static int axe_rx_list_init(struct axe_softc *); 251 static int axe_encap(struct axe_softc *, struct mbuf *, int); 252 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 253 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 254 static void axe_tick(void *); 255 static void axe_tick_task(void *); 256 static void axe_start(struct ifnet *); 257 static int axe_ioctl(struct ifnet *, u_long, void *); 258 static int axe_init(struct ifnet *); 259 static void axe_stop(struct ifnet *, int); 260 static void axe_watchdog(struct ifnet *); 261 static int axe_miibus_readreg_locked(device_t, int, int); 262 static int axe_miibus_readreg(device_t, int, int); 263 static void axe_miibus_writereg_locked(device_t, int, int, int); 264 static void axe_miibus_writereg(device_t, int, int, int); 265 static void axe_miibus_statchg(struct ifnet *); 266 static int axe_cmd(struct axe_softc *, int, int, int, void *); 267 static void axe_reset(struct axe_softc *); 268 269 static void axe_setmulti(struct axe_softc *); 270 static void axe_lock_mii(struct axe_softc *); 271 static void axe_unlock_mii(struct axe_softc *); 272 273 static void axe_ax88178_init(struct axe_softc *); 274 static void axe_ax88772_init(struct axe_softc *); 275 static void axe_ax88772a_init(struct axe_softc *); 276 static void axe_ax88772b_init(struct axe_softc *); 277 278 /* Get exclusive access to the MII registers */ 279 static void 280 axe_lock_mii(struct axe_softc *sc) 281 { 282 283 sc->axe_refcnt++; 284 mutex_enter(&sc->axe_mii_lock); 285 } 286 287 static void 288 axe_unlock_mii(struct axe_softc *sc) 289 { 290 291 mutex_exit(&sc->axe_mii_lock); 292 if (--sc->axe_refcnt < 0) 293 usb_detach_wakeupold((sc->axe_dev)); 294 } 295 296 static int 297 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 298 { 299 AXEHIST_FUNC(); AXEHIST_CALLED(); 300 usb_device_request_t req; 301 usbd_status err; 302 303 KASSERT(mutex_owned(&sc->axe_mii_lock)); 304 305 if (sc->axe_dying) 306 return 0; 307 308 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 309 310 if (AXE_CMD_DIR(cmd)) 311 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 312 else 313 req.bmRequestType = UT_READ_VENDOR_DEVICE; 314 req.bRequest = AXE_CMD_CMD(cmd); 315 USETW(req.wValue, val); 316 USETW(req.wIndex, index); 317 USETW(req.wLength, AXE_CMD_LEN(cmd)); 318 319 err = usbd_do_request(sc->axe_udev, &req, buf); 320 321 if (err) { 322 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 323 return -1; 324 } 325 return 0; 326 } 327 328 static int 329 axe_miibus_readreg_locked(device_t dev, int phy, int reg) 330 { 331 AXEHIST_FUNC(); AXEHIST_CALLED(); 332 struct axe_softc *sc = device_private(dev); 333 usbd_status err; 334 uint16_t val; 335 336 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 337 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 339 340 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, (void *)&val); 341 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 342 if (err) { 343 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 344 return -1; 345 } 346 347 val = le16toh(val); 348 if (AXE_IS_772(sc) && reg == MII_BMSR) { 349 /* 350 * BMSR of AX88772 indicates that it supports extended 351 * capability but the extended status register is 352 * reserved for embedded ethernet PHY. So clear the 353 * extended capability bit of BMSR. 354 */ 355 val &= ~BMSR_EXTCAP; 356 } 357 358 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, val, 0); 359 360 return val; 361 } 362 363 static int 364 axe_miibus_readreg(device_t dev, int phy, int reg) 365 { 366 struct axe_softc *sc = device_private(dev); 367 int val; 368 369 if (sc->axe_dying) 370 return 0; 371 372 if (sc->axe_phyno != phy) 373 return 0; 374 375 axe_lock_mii(sc); 376 val = axe_miibus_readreg_locked(dev, phy, reg); 377 axe_unlock_mii(sc); 378 379 return val; 380 } 381 382 static void 383 axe_miibus_writereg_locked(device_t dev, int phy, int reg, int aval) 384 { 385 struct axe_softc *sc = device_private(dev); 386 usbd_status err; 387 uint16_t val; 388 389 val = htole16(aval); 390 391 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 392 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, (void *)&val); 393 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 394 395 if (err) { 396 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 397 return; 398 } 399 } 400 401 static void 402 axe_miibus_writereg(device_t dev, int phy, int reg, int aval) 403 { 404 struct axe_softc *sc = device_private(dev); 405 406 if (sc->axe_dying) 407 return; 408 409 if (sc->axe_phyno != phy) 410 return; 411 412 axe_lock_mii(sc); 413 axe_miibus_writereg_locked(dev, phy, reg, aval); 414 axe_unlock_mii(sc); 415 } 416 417 static void 418 axe_miibus_statchg(struct ifnet *ifp) 419 { 420 AXEHIST_FUNC(); AXEHIST_CALLED(); 421 422 struct axe_softc *sc = ifp->if_softc; 423 struct mii_data *mii = &sc->axe_mii; 424 int val, err; 425 426 val = 0; 427 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 428 val |= AXE_MEDIA_FULL_DUPLEX; 429 if (AXE_IS_178_FAMILY(sc)) { 430 if ((IFM_OPTIONS(mii->mii_media_active) & 431 IFM_ETH_TXPAUSE) != 0) 432 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 433 if ((IFM_OPTIONS(mii->mii_media_active) & 434 IFM_ETH_RXPAUSE) != 0) 435 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 436 } 437 } 438 if (AXE_IS_178_FAMILY(sc)) { 439 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 440 if (sc->axe_flags & AX178) 441 val |= AXE_178_MEDIA_ENCK; 442 switch (IFM_SUBTYPE(mii->mii_media_active)) { 443 case IFM_1000_T: 444 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 445 break; 446 case IFM_100_TX: 447 val |= AXE_178_MEDIA_100TX; 448 break; 449 case IFM_10_T: 450 /* doesn't need to be handled */ 451 break; 452 } 453 } 454 455 DPRINTF("val=0x%jx", val, 0, 0, 0); 456 axe_lock_mii(sc); 457 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 458 axe_unlock_mii(sc); 459 if (err) { 460 aprint_error_dev(sc->axe_dev, "media change failed\n"); 461 return; 462 } 463 } 464 465 static void 466 axe_setmulti(struct axe_softc *sc) 467 { 468 AXEHIST_FUNC(); AXEHIST_CALLED(); 469 struct ifnet *ifp = &sc->sc_if; 470 struct ether_multi *enm; 471 struct ether_multistep step; 472 uint32_t h = 0; 473 uint16_t rxmode; 474 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 475 476 if (sc->axe_dying) 477 return; 478 479 axe_lock_mii(sc); 480 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, (void *)&rxmode); 481 rxmode = le16toh(rxmode); 482 483 rxmode &= 484 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 485 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 486 487 rxmode |= 488 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 489 490 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 491 if (ifp->if_flags & IFF_PROMISC) 492 rxmode |= AXE_RXCMD_PROMISC; 493 goto allmulti; 494 } 495 496 /* Now program new ones */ 497 ETHER_FIRST_MULTI(step, &sc->axe_ec, enm); 498 while (enm != NULL) { 499 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 500 ETHER_ADDR_LEN) != 0) 501 goto allmulti; 502 503 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 504 hashtbl[h >> 3] |= 1U << (h & 7); 505 ETHER_NEXT_MULTI(step, enm); 506 } 507 ifp->if_flags &= ~IFF_ALLMULTI; 508 rxmode |= AXE_RXCMD_MULTICAST; 509 510 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 511 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 512 axe_unlock_mii(sc); 513 return; 514 515 allmulti: 516 ifp->if_flags |= IFF_ALLMULTI; 517 rxmode |= AXE_RXCMD_ALLMULTI; 518 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 519 axe_unlock_mii(sc); 520 } 521 522 523 static void 524 axe_reset(struct axe_softc *sc) 525 { 526 527 if (sc->axe_dying) 528 return; 529 530 /* 531 * softnet_lock can be taken when NET_MPAFE is not defined when calling 532 * if_addr_init -> if_init. This doesn't mixe well with the 533 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 534 * can fire during the wait and attempt to take softnet_lock and then 535 * block the softclk thread meaing the wait never ends. 536 */ 537 #ifndef NET_MPSAFE 538 /* XXX What to reset? */ 539 540 /* Wait a little while for the chip to get its brains in order. */ 541 DELAY(1000); 542 #else 543 axe_lock_mii(sc); 544 545 if (sc->axe_flags & AX178) { 546 axe_ax88178_init(sc); 547 } else if (sc->axe_flags & AX772) { 548 axe_ax88772_init(sc); 549 } else if (sc->axe_flags & AX772A) { 550 axe_ax88772a_init(sc); 551 } else if (sc->axe_flags & AX772B) { 552 axe_ax88772b_init(sc); 553 } 554 axe_unlock_mii(sc); 555 #endif 556 } 557 558 static int 559 axe_get_phyno(struct axe_softc *sc, int sel) 560 { 561 int phyno; 562 563 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 564 case PHY_TYPE_100_HOME: 565 /* FALLTHROUGH */ 566 case PHY_TYPE_GIG: 567 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 568 break; 569 case PHY_TYPE_SPECIAL: 570 /* FALLTHROUGH */ 571 case PHY_TYPE_RSVD: 572 /* FALLTHROUGH */ 573 case PHY_TYPE_NON_SUP: 574 /* FALLTHROUGH */ 575 default: 576 phyno = -1; 577 break; 578 } 579 580 return phyno; 581 } 582 583 #define AXE_GPIO_WRITE(x, y) do { \ 584 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 585 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 586 } while (0) 587 588 static void 589 axe_ax88178_init(struct axe_softc *sc) 590 { 591 AXEHIST_FUNC(); AXEHIST_CALLED(); 592 int gpio0, ledmode, phymode; 593 uint16_t eeprom, val; 594 595 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 596 /* XXX magic */ 597 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 598 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 599 600 eeprom = le16toh(eeprom); 601 602 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 603 604 /* if EEPROM is invalid we have to use to GPIO0 */ 605 if (eeprom == 0xffff) { 606 phymode = AXE_PHY_MODE_MARVELL; 607 gpio0 = 1; 608 ledmode = 0; 609 } else { 610 phymode = eeprom & 0x7f; 611 gpio0 = (eeprom & 0x80) ? 0 : 1; 612 ledmode = eeprom >> 8; 613 } 614 615 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 616 617 /* Program GPIOs depending on PHY hardware. */ 618 switch (phymode) { 619 case AXE_PHY_MODE_MARVELL: 620 if (gpio0 == 1) { 621 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 622 hz / 32); 623 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 624 hz / 32); 625 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 626 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 627 hz / 32); 628 } else { 629 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 630 AXE_GPIO1_EN, hz / 3); 631 if (ledmode == 1) { 632 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 633 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 634 hz / 3); 635 } else { 636 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 637 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 638 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 639 AXE_GPIO2_EN, hz / 4); 640 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 641 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 642 } 643 } 644 break; 645 case AXE_PHY_MODE_CICADA: 646 case AXE_PHY_MODE_CICADA_V2: 647 case AXE_PHY_MODE_CICADA_V2_ASIX: 648 if (gpio0 == 1) 649 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 650 AXE_GPIO0_EN, hz / 32); 651 else 652 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 653 AXE_GPIO1_EN, hz / 32); 654 break; 655 case AXE_PHY_MODE_AGERE: 656 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 657 AXE_GPIO1_EN, hz / 32); 658 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 659 AXE_GPIO2_EN, hz / 32); 660 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 661 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 662 AXE_GPIO2_EN, hz / 32); 663 break; 664 case AXE_PHY_MODE_REALTEK_8211CL: 665 case AXE_PHY_MODE_REALTEK_8211BN: 666 case AXE_PHY_MODE_REALTEK_8251CL: 667 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 668 AXE_GPIO1 | AXE_GPIO1_EN; 669 AXE_GPIO_WRITE(val, hz / 32); 670 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 671 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 672 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 673 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 674 axe_miibus_writereg_locked(sc->axe_dev, 675 sc->axe_phyno, 0x1F, 0x0005); 676 axe_miibus_writereg_locked(sc->axe_dev, 677 sc->axe_phyno, 0x0C, 0x0000); 678 val = axe_miibus_readreg_locked(sc->axe_dev, 679 sc->axe_phyno, 0x0001); 680 axe_miibus_writereg_locked(sc->axe_dev, 681 sc->axe_phyno, 0x01, val | 0x0080); 682 axe_miibus_writereg_locked(sc->axe_dev, 683 sc->axe_phyno, 0x1F, 0x0000); 684 } 685 break; 686 default: 687 /* Unknown PHY model or no need to program GPIOs. */ 688 break; 689 } 690 691 /* soft reset */ 692 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 693 usbd_delay_ms(sc->axe_udev, 150); 694 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 695 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 696 usbd_delay_ms(sc->axe_udev, 150); 697 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 698 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 699 usbd_delay_ms(sc->axe_udev, 10); 700 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 701 } 702 703 static void 704 axe_ax88772_init(struct axe_softc *sc) 705 { 706 AXEHIST_FUNC(); AXEHIST_CALLED(); 707 708 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 709 usbd_delay_ms(sc->axe_udev, 40); 710 711 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 712 /* ask for the embedded PHY */ 713 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 714 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 715 usbd_delay_ms(sc->axe_udev, 10); 716 717 /* power down and reset state, pin reset state */ 718 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 719 usbd_delay_ms(sc->axe_udev, 60); 720 721 /* power down/reset state, pin operating state */ 722 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 723 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 724 usbd_delay_ms(sc->axe_udev, 150); 725 726 /* power up, reset */ 727 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 728 729 /* power up, operating */ 730 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 731 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 732 } else { 733 /* ask for external PHY */ 734 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 735 NULL); 736 usbd_delay_ms(sc->axe_udev, 10); 737 738 /* power down internal PHY */ 739 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 740 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 741 } 742 743 usbd_delay_ms(sc->axe_udev, 150); 744 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 745 } 746 747 static void 748 axe_ax88772_phywake(struct axe_softc *sc) 749 { 750 AXEHIST_FUNC(); AXEHIST_CALLED(); 751 752 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 753 /* Manually select internal(embedded) PHY - MAC mode. */ 754 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 755 AXE_SW_PHY_SELECT_EMBEDDED, 756 NULL); 757 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 758 } else { 759 /* 760 * Manually select external PHY - MAC mode. 761 * Reverse MII/RMII is for AX88772A PHY mode. 762 */ 763 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 764 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 765 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 766 } 767 768 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 769 AXE_SW_RESET_IPRL, NULL); 770 771 /* T1 = min 500ns everywhere */ 772 usbd_delay_ms(sc->axe_udev, 150); 773 774 /* Take PHY out of power down. */ 775 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 776 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 777 } else { 778 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 779 } 780 781 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 782 usbd_delay_ms(sc->axe_udev, 600); 783 784 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 785 786 /* T3 = 500ns everywhere */ 787 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 788 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 789 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 790 } 791 792 static void 793 axe_ax88772a_init(struct axe_softc *sc) 794 { 795 AXEHIST_FUNC(); AXEHIST_CALLED(); 796 797 /* Reload EEPROM. */ 798 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 799 axe_ax88772_phywake(sc); 800 /* Stop MAC. */ 801 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 802 } 803 804 static void 805 axe_ax88772b_init(struct axe_softc *sc) 806 { 807 AXEHIST_FUNC(); AXEHIST_CALLED(); 808 uint16_t eeprom; 809 int i; 810 811 /* Reload EEPROM. */ 812 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 813 814 /* 815 * Save PHY power saving configuration(high byte) and 816 * clear EEPROM checksum value(low byte). 817 */ 818 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 819 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 820 821 /* 822 * Auto-loaded default station address from internal ROM is 823 * 00:00:00:00:00:00 such that an explicit access to EEPROM 824 * is required to get real station address. 825 */ 826 uint8_t *eaddr = sc->axe_enaddr; 827 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 828 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 829 &eeprom); 830 eeprom = le16toh(eeprom); 831 *eaddr++ = (uint8_t)(eeprom & 0xFF); 832 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 833 } 834 /* Wakeup PHY. */ 835 axe_ax88772_phywake(sc); 836 /* Stop MAC. */ 837 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 838 } 839 840 #undef AXE_GPIO_WRITE 841 842 /* 843 * Probe for a AX88172 chip. 844 */ 845 int 846 axe_match(device_t parent, cfdata_t match, void *aux) 847 { 848 struct usb_attach_arg *uaa = aux; 849 850 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 851 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 852 } 853 854 /* 855 * Attach the interface. Allocate softc structures, do ifmedia 856 * setup and ethernet/BPF attach. 857 */ 858 void 859 axe_attach(device_t parent, device_t self, void *aux) 860 { 861 AXEHIST_FUNC(); AXEHIST_CALLED(); 862 struct axe_softc *sc = device_private(self); 863 struct usb_attach_arg *uaa = aux; 864 struct usbd_device *dev = uaa->uaa_device; 865 usbd_status err; 866 usb_interface_descriptor_t *id; 867 usb_endpoint_descriptor_t *ed; 868 struct mii_data *mii; 869 char *devinfop; 870 const char *devname = device_xname(self); 871 struct ifnet *ifp; 872 int i, s; 873 874 aprint_naive("\n"); 875 aprint_normal("\n"); 876 877 sc->axe_dev = self; 878 sc->axe_udev = dev; 879 880 devinfop = usbd_devinfo_alloc(dev, 0); 881 aprint_normal_dev(self, "%s\n", devinfop); 882 usbd_devinfo_free(devinfop); 883 884 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 885 if (err) { 886 aprint_error_dev(self, "failed to set configuration" 887 ", err=%s\n", usbd_errstr(err)); 888 return; 889 } 890 891 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 892 893 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 894 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 895 896 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 897 if (err) { 898 aprint_error_dev(self, "getting interface handle failed\n"); 899 return; 900 } 901 902 sc->axe_product = uaa->uaa_product; 903 sc->axe_vendor = uaa->uaa_vendor; 904 905 id = usbd_get_interface_descriptor(sc->axe_iface); 906 907 /* decide on what our bufsize will be */ 908 if (AXE_IS_178_FAMILY(sc)) 909 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 910 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 911 else 912 sc->axe_bufsz = AXE_172_BUFSZ; 913 914 sc->axe_ed[AXE_ENDPT_RX] = -1; 915 sc->axe_ed[AXE_ENDPT_TX] = -1; 916 sc->axe_ed[AXE_ENDPT_INTR] = -1; 917 918 /* Find endpoints. */ 919 for (i = 0; i < id->bNumEndpoints; i++) { 920 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 921 if (ed == NULL) { 922 aprint_error_dev(self, "couldn't get ep %d\n", i); 923 return; 924 } 925 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 926 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 927 928 if (dir == UE_DIR_IN && xt == UE_BULK && 929 sc->axe_ed[AXE_ENDPT_RX] == -1) { 930 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 931 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 932 sc->axe_ed[AXE_ENDPT_TX] == -1) { 933 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 934 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 935 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 936 } 937 } 938 939 s = splnet(); 940 941 /* We need the PHYID for init dance in some cases */ 942 axe_lock_mii(sc); 943 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, (void *)&sc->axe_phyaddrs); 944 945 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 946 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 947 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 948 if (sc->axe_phyno == -1) 949 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 950 if (sc->axe_phyno == -1) { 951 DPRINTF(" no valid PHY address found, assuming PHY address 0", 952 0, 0, 0, 0); 953 sc->axe_phyno = 0; 954 } 955 956 /* Initialize controller and get station address. */ 957 958 if (sc->axe_flags & AX178) { 959 axe_ax88178_init(sc); 960 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 961 } else if (sc->axe_flags & AX772) { 962 axe_ax88772_init(sc); 963 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 964 } else if (sc->axe_flags & AX772A) { 965 axe_ax88772a_init(sc); 966 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 967 } else if (sc->axe_flags & AX772B) { 968 axe_ax88772b_init(sc); 969 } else 970 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, sc->axe_enaddr); 971 972 /* 973 * Fetch IPG values. 974 */ 975 if (sc->axe_flags & (AX772A | AX772B)) { 976 /* Set IPG values. */ 977 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 978 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 979 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 980 } else 981 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs); 982 983 axe_unlock_mii(sc); 984 985 /* 986 * An ASIX chip was detected. Inform the world. 987 */ 988 aprint_normal_dev(self, "Ethernet address %s\n", 989 ether_sprintf(sc->axe_enaddr)); 990 991 /* Initialize interface info.*/ 992 ifp = &sc->sc_if; 993 ifp->if_softc = sc; 994 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 995 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 996 ifp->if_ioctl = axe_ioctl; 997 ifp->if_start = axe_start; 998 ifp->if_init = axe_init; 999 ifp->if_stop = axe_stop; 1000 ifp->if_watchdog = axe_watchdog; 1001 1002 IFQ_SET_READY(&ifp->if_snd); 1003 1004 if (AXE_IS_178_FAMILY(sc)) 1005 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1006 if (sc->axe_flags & AX772B) { 1007 ifp->if_capabilities = 1008 IFCAP_CSUM_IPv4_Rx | 1009 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1010 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1011 /* 1012 * Checksum offloading of AX88772B also works with VLAN 1013 * tagged frames but there is no way to take advantage 1014 * of the feature because vlan(4) assumes 1015 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1016 * support checksum offloading with VLAN. VLAN hardware 1017 * tagging support of AX88772B is very limited so it's 1018 * not possible to announce IFCAP_VLAN_HWTAGGING. 1019 */ 1020 } 1021 u_int adv_pause; 1022 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1023 adv_pause = MIIF_DOPAUSE; 1024 else 1025 adv_pause = 0; 1026 adv_pause = 0; 1027 1028 /* Initialize MII/media info. */ 1029 mii = &sc->axe_mii; 1030 mii->mii_ifp = ifp; 1031 mii->mii_readreg = axe_miibus_readreg; 1032 mii->mii_writereg = axe_miibus_writereg; 1033 mii->mii_statchg = axe_miibus_statchg; 1034 mii->mii_flags = MIIF_AUTOTSLEEP; 1035 1036 sc->axe_ec.ec_mii = mii; 1037 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1038 1039 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1040 adv_pause); 1041 1042 if (LIST_EMPTY(&mii->mii_phys)) { 1043 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1044 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1045 } else 1046 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1047 1048 /* Attach the interface. */ 1049 if_attach(ifp); 1050 ether_ifattach(ifp, sc->axe_enaddr); 1051 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1052 RND_TYPE_NET, RND_FLAG_DEFAULT); 1053 1054 callout_init(&sc->axe_stat_ch, 0); 1055 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1056 1057 sc->axe_attached = true; 1058 splx(s); 1059 1060 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1061 1062 if (!pmf_device_register(self, NULL, NULL)) 1063 aprint_error_dev(self, "couldn't establish power handler\n"); 1064 } 1065 1066 int 1067 axe_detach(device_t self, int flags) 1068 { 1069 AXEHIST_FUNC(); AXEHIST_CALLED(); 1070 struct axe_softc *sc = device_private(self); 1071 int s; 1072 struct ifnet *ifp = &sc->sc_if; 1073 1074 /* Detached before attached finished, so just bail out. */ 1075 if (!sc->axe_attached) 1076 return 0; 1077 1078 pmf_device_deregister(self); 1079 1080 sc->axe_dying = true; 1081 1082 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1083 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1084 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1085 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1086 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1087 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1088 1089 /* 1090 * Remove any pending tasks. They cannot be executing because they run 1091 * in the same thread as detach. 1092 */ 1093 usb_rem_task(sc->axe_udev, &sc->axe_tick_task); 1094 1095 s = splusb(); 1096 1097 if (ifp->if_flags & IFF_RUNNING) 1098 axe_stop(ifp, 1); 1099 1100 1101 if (--sc->axe_refcnt >= 0) { 1102 /* Wait for processes to go away. */ 1103 usb_detach_waitold(sc->axe_dev); 1104 } 1105 1106 callout_destroy(&sc->axe_stat_ch); 1107 mutex_destroy(&sc->axe_mii_lock); 1108 rnd_detach_source(&sc->rnd_source); 1109 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1110 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1111 ether_ifdetach(ifp); 1112 if_detach(ifp); 1113 1114 #ifdef DIAGNOSTIC 1115 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1116 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1117 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1118 aprint_debug_dev(self, "detach has active endpoints\n"); 1119 #endif 1120 1121 sc->axe_attached = false; 1122 1123 splx(s); 1124 1125 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1126 1127 return 0; 1128 } 1129 1130 int 1131 axe_activate(device_t self, devact_t act) 1132 { 1133 AXEHIST_FUNC(); AXEHIST_CALLED(); 1134 struct axe_softc *sc = device_private(self); 1135 1136 switch (act) { 1137 case DVACT_DEACTIVATE: 1138 if_deactivate(&sc->axe_ec.ec_if); 1139 sc->axe_dying = true; 1140 return 0; 1141 default: 1142 return EOPNOTSUPP; 1143 } 1144 } 1145 1146 static int 1147 axe_rx_list_init(struct axe_softc *sc) 1148 { 1149 AXEHIST_FUNC(); AXEHIST_CALLED(); 1150 1151 struct axe_cdata *cd; 1152 struct axe_chain *c; 1153 int i; 1154 1155 cd = &sc->axe_cdata; 1156 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1157 c = &cd->axe_rx_chain[i]; 1158 c->axe_sc = sc; 1159 c->axe_idx = i; 1160 if (c->axe_xfer == NULL) { 1161 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1162 sc->axe_bufsz, USBD_SHORT_XFER_OK, 0, &c->axe_xfer); 1163 if (err) 1164 return err; 1165 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1166 } 1167 } 1168 1169 return 0; 1170 } 1171 1172 static int 1173 axe_tx_list_init(struct axe_softc *sc) 1174 { 1175 AXEHIST_FUNC(); AXEHIST_CALLED(); 1176 struct axe_cdata *cd; 1177 struct axe_chain *c; 1178 int i; 1179 1180 cd = &sc->axe_cdata; 1181 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1182 c = &cd->axe_tx_chain[i]; 1183 c->axe_sc = sc; 1184 c->axe_idx = i; 1185 if (c->axe_xfer == NULL) { 1186 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1187 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1188 &c->axe_xfer); 1189 if (err) 1190 return err; 1191 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1192 } 1193 } 1194 1195 return 0; 1196 } 1197 1198 /* 1199 * A frame has been uploaded: pass the resulting mbuf chain up to 1200 * the higher level protocols. 1201 */ 1202 static void 1203 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1204 { 1205 AXEHIST_FUNC(); AXEHIST_CALLED(); 1206 struct axe_softc *sc; 1207 struct axe_chain *c; 1208 struct ifnet *ifp; 1209 uint8_t *buf; 1210 uint32_t total_len; 1211 struct mbuf *m; 1212 int s; 1213 1214 c = (struct axe_chain *)priv; 1215 sc = c->axe_sc; 1216 buf = c->axe_buf; 1217 ifp = &sc->sc_if; 1218 1219 if (sc->axe_dying) 1220 return; 1221 1222 if ((ifp->if_flags & IFF_RUNNING) == 0) 1223 return; 1224 1225 if (status != USBD_NORMAL_COMPLETION) { 1226 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1227 return; 1228 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1229 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1230 usbd_errstr(status)); 1231 } 1232 if (status == USBD_STALLED) 1233 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1234 goto done; 1235 } 1236 1237 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1238 1239 do { 1240 u_int pktlen = 0; 1241 u_int rxlen = 0; 1242 int flags = 0; 1243 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1244 struct axe_sframe_hdr hdr; 1245 1246 if (total_len < sizeof(hdr)) { 1247 ifp->if_ierrors++; 1248 goto done; 1249 } 1250 1251 memcpy(&hdr, buf, sizeof(hdr)); 1252 1253 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1254 total_len, 1255 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1256 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1257 1258 total_len -= sizeof(hdr); 1259 buf += sizeof(hdr); 1260 1261 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1262 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1263 AXE_RH1M_RXLEN_MASK) { 1264 ifp->if_ierrors++; 1265 goto done; 1266 } 1267 1268 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1269 if (total_len < rxlen) { 1270 pktlen = total_len; 1271 total_len = 0; 1272 } else { 1273 pktlen = rxlen; 1274 rxlen = roundup2(rxlen, 2); 1275 total_len -= rxlen; 1276 } 1277 1278 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1279 struct axe_csum_hdr csum_hdr; 1280 1281 if (total_len < sizeof(csum_hdr)) { 1282 ifp->if_ierrors++; 1283 goto done; 1284 } 1285 1286 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1287 1288 csum_hdr.len = le16toh(csum_hdr.len); 1289 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1290 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1291 1292 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1293 " cstatus %#jx", total_len, 1294 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1295 1296 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1297 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1298 sc->sc_lenmask) { 1299 /* we lost sync */ 1300 ifp->if_ierrors++; 1301 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1302 "err", 1303 AXE_CSUM_RXBYTES(csum_hdr.len), 1304 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1305 sc->sc_lenmask, 0); 1306 goto done; 1307 } 1308 /* 1309 * Get total transferred frame length including 1310 * checksum header. The length should be multiple 1311 * of 4. 1312 */ 1313 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1314 u_int len = sizeof(csum_hdr) + pktlen; 1315 len = (len + 3) & ~3; 1316 if (total_len < len) { 1317 DPRINTFN(20, "total_len %#jx < len %#jx", 1318 total_len, len, 0, 0); 1319 /* invalid length */ 1320 ifp->if_ierrors++; 1321 goto done; 1322 } 1323 buf += sizeof(csum_hdr); 1324 1325 const uint16_t cstatus = csum_hdr.cstatus; 1326 1327 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1328 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1329 flags |= M_CSUM_TCP_UDP_BAD; 1330 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1331 flags |= M_CSUM_IPv4_BAD; 1332 1333 const uint16_t l4type = 1334 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1335 1336 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1337 flags |= M_CSUM_TCPv4; 1338 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1339 flags |= M_CSUM_UDPv4; 1340 } 1341 if (total_len < len) { 1342 pktlen = total_len; 1343 total_len = 0; 1344 } else { 1345 total_len -= len; 1346 rxlen = len - sizeof(csum_hdr); 1347 } 1348 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1349 " rxlen %#jx", total_len, len, pktlen, rxlen); 1350 } else { /* AX172 */ 1351 pktlen = rxlen = total_len; 1352 total_len = 0; 1353 } 1354 1355 MGETHDR(m, M_DONTWAIT, MT_DATA); 1356 if (m == NULL) { 1357 ifp->if_ierrors++; 1358 goto done; 1359 } 1360 1361 if (pktlen > MHLEN - ETHER_ALIGN) { 1362 MCLGET(m, M_DONTWAIT); 1363 if ((m->m_flags & M_EXT) == 0) { 1364 m_freem(m); 1365 ifp->if_ierrors++; 1366 goto done; 1367 } 1368 } 1369 m->m_data += ETHER_ALIGN; 1370 1371 m_set_rcvif(m, ifp); 1372 m->m_pkthdr.len = m->m_len = pktlen; 1373 m->m_pkthdr.csum_flags = flags; 1374 1375 memcpy(mtod(m, uint8_t *), buf, pktlen); 1376 buf += rxlen; 1377 1378 DPRINTFN(10, "deliver %jd (%#jx)", m->m_len, m->m_len, 0, 0); 1379 1380 s = splnet(); 1381 1382 if_percpuq_enqueue((ifp)->if_percpuq, (m)); 1383 1384 splx(s); 1385 1386 } while (total_len > 0); 1387 1388 done: 1389 1390 /* Setup new transfer. */ 1391 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1392 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1393 usbd_transfer(xfer); 1394 1395 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1396 } 1397 1398 /* 1399 * A frame was downloaded to the chip. It's safe for us to clean up 1400 * the list buffers. 1401 */ 1402 1403 static void 1404 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1405 { 1406 AXEHIST_FUNC(); AXEHIST_CALLED(); 1407 struct axe_chain *c = priv; 1408 struct axe_softc *sc = c->axe_sc; 1409 struct ifnet *ifp = &sc->sc_if; 1410 int s; 1411 1412 1413 if (sc->axe_dying) 1414 return; 1415 1416 s = splnet(); 1417 1418 ifp->if_timer = 0; 1419 ifp->if_flags &= ~IFF_OACTIVE; 1420 1421 if (status != USBD_NORMAL_COMPLETION) { 1422 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1423 splx(s); 1424 return; 1425 } 1426 ifp->if_oerrors++; 1427 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1428 usbd_errstr(status)); 1429 if (status == USBD_STALLED) 1430 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1431 splx(s); 1432 return; 1433 } 1434 ifp->if_opackets++; 1435 1436 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1437 axe_start(ifp); 1438 1439 splx(s); 1440 } 1441 1442 static void 1443 axe_tick(void *xsc) 1444 { 1445 AXEHIST_FUNC(); AXEHIST_CALLED(); 1446 struct axe_softc *sc = xsc; 1447 1448 if (sc == NULL) 1449 return; 1450 1451 if (sc->axe_dying) 1452 return; 1453 1454 /* Perform periodic stuff in process context */ 1455 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1456 } 1457 1458 static void 1459 axe_tick_task(void *xsc) 1460 { 1461 AXEHIST_FUNC(); AXEHIST_CALLED(); 1462 int s; 1463 struct axe_softc *sc = xsc; 1464 struct ifnet *ifp; 1465 struct mii_data *mii; 1466 1467 if (sc == NULL) 1468 return; 1469 1470 if (sc->axe_dying) 1471 return; 1472 1473 ifp = &sc->sc_if; 1474 mii = &sc->axe_mii; 1475 1476 if (mii == NULL) 1477 return; 1478 1479 s = splnet(); 1480 1481 mii_tick(mii); 1482 if (sc->axe_link == 0 && 1483 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1484 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1485 DPRINTF("got link", 0, 0, 0, 0); 1486 sc->axe_link++; 1487 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1488 axe_start(ifp); 1489 } 1490 1491 callout_schedule(&sc->axe_stat_ch, hz); 1492 1493 splx(s); 1494 } 1495 1496 static int 1497 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1498 { 1499 struct ifnet *ifp = &sc->sc_if; 1500 struct axe_chain *c; 1501 usbd_status err; 1502 int length, boundary; 1503 1504 c = &sc->axe_cdata.axe_tx_chain[idx]; 1505 1506 /* 1507 * Copy the mbuf data into a contiguous buffer, leaving two 1508 * bytes at the beginning to hold the frame length. 1509 */ 1510 if (AXE_IS_178_FAMILY(sc)) { 1511 struct axe_sframe_hdr hdr; 1512 1513 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1514 1515 hdr.len = htole16(m->m_pkthdr.len); 1516 hdr.ilen = ~hdr.len; 1517 1518 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1519 length = sizeof(hdr); 1520 1521 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1522 length += m->m_pkthdr.len; 1523 1524 if ((length % boundary) == 0) { 1525 hdr.len = 0x0000; 1526 hdr.ilen = 0xffff; 1527 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1528 length += sizeof(hdr); 1529 } 1530 } else { 1531 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1532 length = m->m_pkthdr.len; 1533 } 1534 1535 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1536 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1537 1538 /* Transmit */ 1539 err = usbd_transfer(c->axe_xfer); 1540 if (err != USBD_IN_PROGRESS) { 1541 axe_stop(ifp, 0); 1542 return EIO; 1543 } 1544 1545 sc->axe_cdata.axe_tx_cnt++; 1546 1547 return 0; 1548 } 1549 1550 1551 static void 1552 axe_csum_cfg(struct axe_softc *sc) 1553 { 1554 struct ifnet *ifp = &sc->sc_if; 1555 uint16_t csum1, csum2; 1556 1557 if ((sc->axe_flags & AX772B) != 0) { 1558 csum1 = 0; 1559 csum2 = 0; 1560 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1561 csum1 |= AXE_TXCSUM_IP; 1562 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1563 csum1 |= AXE_TXCSUM_TCP; 1564 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1565 csum1 |= AXE_TXCSUM_UDP; 1566 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1567 csum1 |= AXE_TXCSUM_TCPV6; 1568 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1569 csum1 |= AXE_TXCSUM_UDPV6; 1570 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1571 csum1 = 0; 1572 csum2 = 0; 1573 1574 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1575 csum1 |= AXE_RXCSUM_IP; 1576 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1577 csum1 |= AXE_RXCSUM_TCP; 1578 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1579 csum1 |= AXE_RXCSUM_UDP; 1580 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1581 csum1 |= AXE_RXCSUM_TCPV6; 1582 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1583 csum1 |= AXE_RXCSUM_UDPV6; 1584 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1585 } 1586 } 1587 1588 static void 1589 axe_start(struct ifnet *ifp) 1590 { 1591 struct axe_softc *sc; 1592 struct mbuf *m; 1593 1594 sc = ifp->if_softc; 1595 1596 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) 1597 return; 1598 1599 IFQ_POLL(&ifp->if_snd, m); 1600 if (m == NULL) { 1601 return; 1602 } 1603 1604 if (axe_encap(sc, m, 0)) { 1605 ifp->if_flags |= IFF_OACTIVE; 1606 return; 1607 } 1608 IFQ_DEQUEUE(&ifp->if_snd, m); 1609 1610 /* 1611 * If there's a BPF listener, bounce a copy of this frame 1612 * to him. 1613 */ 1614 bpf_mtap(ifp, m); 1615 m_freem(m); 1616 1617 ifp->if_flags |= IFF_OACTIVE; 1618 1619 /* 1620 * Set a timeout in case the chip goes out to lunch. 1621 */ 1622 ifp->if_timer = 5; 1623 1624 return; 1625 } 1626 1627 static int 1628 axe_init(struct ifnet *ifp) 1629 { 1630 AXEHIST_FUNC(); AXEHIST_CALLED(); 1631 struct axe_softc *sc = ifp->if_softc; 1632 struct axe_chain *c; 1633 usbd_status err; 1634 int rxmode; 1635 int i, s; 1636 1637 s = splnet(); 1638 1639 if (ifp->if_flags & IFF_RUNNING) 1640 axe_stop(ifp, 0); 1641 1642 /* 1643 * Cancel pending I/O and free all RX/TX buffers. 1644 */ 1645 axe_reset(sc); 1646 1647 axe_lock_mii(sc); 1648 1649 #if 0 1650 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1651 AX_GPIO_GPO2EN, 5, in_pm); 1652 #endif 1653 /* Set MAC address and transmitter IPG values. */ 1654 if (AXE_IS_178_FAMILY(sc)) { 1655 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1656 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1657 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1658 } else { 1659 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1660 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1661 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1662 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1663 } 1664 if (AXE_IS_178_FAMILY(sc)) { 1665 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1666 if ((sc->axe_flags & AX772B) != 0 && 1667 (ifp->if_capenable & AX_RXCSUM) != 0) { 1668 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1669 sc->axe_flags |= AXCSUM_FRAME; 1670 } else { 1671 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1672 sc->axe_flags |= AXSTD_FRAME; 1673 } 1674 } 1675 1676 /* Configure TX/RX checksum offloading. */ 1677 axe_csum_cfg(sc); 1678 1679 if (sc->axe_flags & AX772B) { 1680 /* AX88772B uses different maximum frame burst configuration. */ 1681 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1682 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1683 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1684 } 1685 /* Enable receiver, set RX mode */ 1686 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1687 if (AXE_IS_178_FAMILY(sc)) { 1688 if (sc->axe_flags & AX772B) { 1689 /* 1690 * Select RX header format type 1. Aligning IP 1691 * header on 4 byte boundary is not needed when 1692 * checksum offloading feature is not used 1693 * because we always copy the received frame in 1694 * RX handler. When RX checksum offloading is 1695 * active, aligning IP header is required to 1696 * reflect actual frame length including RX 1697 * header size. 1698 */ 1699 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1700 if (sc->axe_flags & AXCSUM_FRAME) 1701 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1702 } else { 1703 /* 1704 * Default Rx buffer size is too small to get 1705 * maximum performance. 1706 */ 1707 #if 0 1708 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1709 /* Largest possible USB buffer size for AX88178 */ 1710 #endif 1711 rxmode |= AXE_178_RXCMD_MFB_16384; 1712 } 1713 } else { 1714 rxmode |= AXE_172_RXCMD_UNICAST; 1715 } 1716 1717 1718 /* If we want promiscuous mode, set the allframes bit. */ 1719 if (ifp->if_flags & IFF_PROMISC) 1720 rxmode |= AXE_RXCMD_PROMISC; 1721 1722 if (ifp->if_flags & IFF_BROADCAST) 1723 rxmode |= AXE_RXCMD_BROADCAST; 1724 1725 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1726 1727 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1728 axe_unlock_mii(sc); 1729 1730 /* Load the multicast filter. */ 1731 axe_setmulti(sc); 1732 1733 /* Open RX and TX pipes. */ 1734 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1735 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1736 if (err) { 1737 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1738 usbd_errstr(err)); 1739 splx(s); 1740 return EIO; 1741 } 1742 1743 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1744 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1745 if (err) { 1746 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1747 usbd_errstr(err)); 1748 splx(s); 1749 return EIO; 1750 } 1751 1752 /* Init RX ring. */ 1753 if (axe_rx_list_init(sc) != 0) { 1754 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1755 splx(s); 1756 return ENOBUFS; 1757 } 1758 1759 /* Init TX ring. */ 1760 if (axe_tx_list_init(sc) != 0) { 1761 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1762 splx(s); 1763 return ENOBUFS; 1764 } 1765 1766 /* Start up the receive pipe. */ 1767 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1768 c = &sc->axe_cdata.axe_rx_chain[i]; 1769 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1770 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1771 usbd_transfer(c->axe_xfer); 1772 } 1773 1774 ifp->if_flags |= IFF_RUNNING; 1775 ifp->if_flags &= ~IFF_OACTIVE; 1776 1777 splx(s); 1778 1779 callout_schedule(&sc->axe_stat_ch, hz); 1780 return 0; 1781 } 1782 1783 static int 1784 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1785 { 1786 struct axe_softc *sc = ifp->if_softc; 1787 int s; 1788 int error = 0; 1789 1790 s = splnet(); 1791 1792 switch(cmd) { 1793 case SIOCSIFFLAGS: 1794 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1795 break; 1796 1797 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1798 case IFF_RUNNING: 1799 axe_stop(ifp, 1); 1800 break; 1801 case IFF_UP: 1802 axe_init(ifp); 1803 break; 1804 case IFF_UP | IFF_RUNNING: 1805 if ((ifp->if_flags ^ sc->axe_if_flags) == IFF_PROMISC) 1806 axe_setmulti(sc); 1807 else 1808 axe_init(ifp); 1809 break; 1810 } 1811 sc->axe_if_flags = ifp->if_flags; 1812 break; 1813 1814 default: 1815 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1816 break; 1817 1818 error = 0; 1819 1820 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) 1821 axe_setmulti(sc); 1822 1823 } 1824 splx(s); 1825 1826 return error; 1827 } 1828 1829 static void 1830 axe_watchdog(struct ifnet *ifp) 1831 { 1832 struct axe_softc *sc; 1833 struct axe_chain *c; 1834 usbd_status stat; 1835 int s; 1836 1837 sc = ifp->if_softc; 1838 1839 ifp->if_oerrors++; 1840 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1841 1842 s = splusb(); 1843 c = &sc->axe_cdata.axe_tx_chain[0]; 1844 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1845 axe_txeof(c->axe_xfer, c, stat); 1846 1847 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1848 axe_start(ifp); 1849 splx(s); 1850 } 1851 1852 /* 1853 * Stop the adapter and free any mbufs allocated to the 1854 * RX and TX lists. 1855 */ 1856 static void 1857 axe_stop(struct ifnet *ifp, int disable) 1858 { 1859 struct axe_softc *sc = ifp->if_softc; 1860 usbd_status err; 1861 int i; 1862 1863 ifp->if_timer = 0; 1864 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1865 1866 callout_stop(&sc->axe_stat_ch); 1867 1868 /* Stop transfers. */ 1869 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1870 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1871 if (err) { 1872 aprint_error_dev(sc->axe_dev, 1873 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1874 } 1875 } 1876 1877 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1878 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1879 if (err) { 1880 aprint_error_dev(sc->axe_dev, 1881 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1882 } 1883 } 1884 1885 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1886 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1887 if (err) { 1888 aprint_error_dev(sc->axe_dev, 1889 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1890 } 1891 } 1892 1893 axe_reset(sc); 1894 1895 /* Free RX resources. */ 1896 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1897 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1898 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1899 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1900 } 1901 } 1902 1903 /* Free TX resources. */ 1904 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1905 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1906 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1907 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1908 } 1909 } 1910 1911 /* Close pipes. */ 1912 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1913 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1914 if (err) { 1915 aprint_error_dev(sc->axe_dev, 1916 "close rx pipe failed: %s\n", usbd_errstr(err)); 1917 } 1918 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1919 } 1920 1921 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1922 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1923 if (err) { 1924 aprint_error_dev(sc->axe_dev, 1925 "close tx pipe failed: %s\n", usbd_errstr(err)); 1926 } 1927 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1928 } 1929 1930 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1931 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1932 if (err) { 1933 aprint_error_dev(sc->axe_dev, 1934 "close intr pipe failed: %s\n", usbd_errstr(err)); 1935 } 1936 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1937 } 1938 1939 sc->axe_link = 0; 1940 } 1941 1942 MODULE(MODULE_CLASS_DRIVER, if_axe, "bpf"); 1943 1944 #ifdef _MODULE 1945 #include "ioconf.c" 1946 #endif 1947 1948 static int 1949 if_axe_modcmd(modcmd_t cmd, void *aux) 1950 { 1951 int error = 0; 1952 1953 switch (cmd) { 1954 case MODULE_CMD_INIT: 1955 #ifdef _MODULE 1956 error = config_init_component(cfdriver_ioconf_axe, 1957 cfattach_ioconf_axe, cfdata_ioconf_axe); 1958 #endif 1959 return error; 1960 case MODULE_CMD_FINI: 1961 #ifdef _MODULE 1962 error = config_fini_component(cfdriver_ioconf_axe, 1963 cfattach_ioconf_axe, cfdata_ioconf_axe); 1964 #endif 1965 return error; 1966 default: 1967 return ENOTTY; 1968 } 1969 } 1970
Indexes created Wed Sep 24 15:09:51 GMT 2025