if_axe.c revision 1.84.2.1
1 /* $NetBSD: if_axe.c,v 1.84.2.1 2018/04/22 07:20:26 pgoyette Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.84.2.1 2018/04/22 07:20:26 pgoyette Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 /* 131 * AXE_178_MAX_FRAME_BURST 132 * max frame burst size for Ax88178 and Ax88772 133 * 0 2048 bytes 134 * 1 4096 bytes 135 * 2 8192 bytes 136 * 3 16384 bytes 137 * use the largest your system can handle without USB stalling. 138 * 139 * NB: 88772 parts appear to generate lots of input errors with 140 * a 2K rx buffer and 8K is only slightly faster than 4K on an 141 * EHCI port on a T42 so change at your own risk. 142 */ 143 #define AXE_178_MAX_FRAME_BURST 1 144 145 146 #ifdef USB_DEBUG 147 #ifndef AXE_DEBUG 148 #define axedebug 0 149 #else 150 static int axedebug = 20; 151 152 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 153 { 154 int err; 155 const struct sysctlnode *rnode; 156 const struct sysctlnode *cnode; 157 158 err = sysctl_createv(clog, 0, NULL, &rnode, 159 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 160 SYSCTL_DESCR("axe global controls"), 161 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 162 163 if (err) 164 goto fail; 165 166 /* control debugging printfs */ 167 err = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 169 "debug", SYSCTL_DESCR("Enable debugging output"), 170 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 171 if (err) 172 goto fail; 173 174 return; 175 fail: 176 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 177 } 178 179 #endif /* AXE_DEBUG */ 180 #endif /* USB_DEBUG */ 181 182 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 183 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 184 #define AXEHIST_FUNC() USBHIST_FUNC() 185 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 186 187 /* 188 * Various supported device vendors/products. 189 */ 190 static const struct axe_type axe_devs[] = { 191 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 192 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 193 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 199 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 200 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 201 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 202 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 203 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 204 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 206 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 208 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 209 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 210 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 211 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 212 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 213 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 214 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 215 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 216 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 218 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 219 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 220 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 221 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 222 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 223 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 225 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 226 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 227 }; 228 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 229 230 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 231 { 0x8000, 0x8001, 2048 }, 232 { 0x8100, 0x8147, 4096 }, 233 { 0x8200, 0x81EB, 6144 }, 234 { 0x8300, 0x83D7, 8192 }, 235 { 0x8400, 0x851E, 16384 }, 236 { 0x8500, 0x8666, 20480 }, 237 { 0x8600, 0x87AE, 24576 }, 238 { 0x8700, 0x8A3D, 32768 } 239 }; 240 241 int axe_match(device_t, cfdata_t, void *); 242 void axe_attach(device_t, device_t, void *); 243 int axe_detach(device_t, int); 244 int axe_activate(device_t, devact_t); 245 246 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 247 axe_match, axe_attach, axe_detach, axe_activate); 248 249 static int axe_tx_list_init(struct axe_softc *); 250 static int axe_rx_list_init(struct axe_softc *); 251 static int axe_encap(struct axe_softc *, struct mbuf *, int); 252 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 253 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 254 static void axe_tick(void *); 255 static void axe_tick_task(void *); 256 static void axe_start(struct ifnet *); 257 static int axe_ioctl(struct ifnet *, u_long, void *); 258 static int axe_init(struct ifnet *); 259 static void axe_stop(struct ifnet *, int); 260 static void axe_watchdog(struct ifnet *); 261 static int axe_miibus_readreg_locked(device_t, int, int); 262 static int axe_miibus_readreg(device_t, int, int); 263 static void axe_miibus_writereg_locked(device_t, int, int, int); 264 static void axe_miibus_writereg(device_t, int, int, int); 265 static void axe_miibus_statchg(struct ifnet *); 266 static int axe_cmd(struct axe_softc *, int, int, int, void *); 267 static void axe_reset(struct axe_softc *); 268 269 static void axe_setmulti(struct axe_softc *); 270 static void axe_lock_mii(struct axe_softc *); 271 static void axe_unlock_mii(struct axe_softc *); 272 273 static void axe_ax88178_init(struct axe_softc *); 274 static void axe_ax88772_init(struct axe_softc *); 275 static void axe_ax88772a_init(struct axe_softc *); 276 static void axe_ax88772b_init(struct axe_softc *); 277 278 /* Get exclusive access to the MII registers */ 279 static void 280 axe_lock_mii(struct axe_softc *sc) 281 { 282 283 sc->axe_refcnt++; 284 mutex_enter(&sc->axe_mii_lock); 285 } 286 287 static void 288 axe_unlock_mii(struct axe_softc *sc) 289 { 290 291 mutex_exit(&sc->axe_mii_lock); 292 if (--sc->axe_refcnt < 0) 293 usb_detach_wakeupold((sc->axe_dev)); 294 } 295 296 static int 297 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 298 { 299 AXEHIST_FUNC(); AXEHIST_CALLED(); 300 usb_device_request_t req; 301 usbd_status err; 302 303 KASSERT(mutex_owned(&sc->axe_mii_lock)); 304 305 if (sc->axe_dying) 306 return -1; 307 308 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 309 310 if (AXE_CMD_DIR(cmd)) 311 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 312 else 313 req.bmRequestType = UT_READ_VENDOR_DEVICE; 314 req.bRequest = AXE_CMD_CMD(cmd); 315 USETW(req.wValue, val); 316 USETW(req.wIndex, index); 317 USETW(req.wLength, AXE_CMD_LEN(cmd)); 318 319 err = usbd_do_request(sc->axe_udev, &req, buf); 320 321 if (err) { 322 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 323 return -1; 324 } 325 return 0; 326 } 327 328 static int 329 axe_miibus_readreg_locked(device_t dev, int phy, int reg) 330 { 331 AXEHIST_FUNC(); AXEHIST_CALLED(); 332 struct axe_softc *sc = device_private(dev); 333 usbd_status err; 334 uint16_t val; 335 336 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 337 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 339 340 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 341 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 342 if (err) { 343 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 344 return -1; 345 } 346 347 val = le16toh(val); 348 if (AXE_IS_772(sc) && reg == MII_BMSR) { 349 /* 350 * BMSR of AX88772 indicates that it supports extended 351 * capability but the extended status register is 352 * reserved for embedded ethernet PHY. So clear the 353 * extended capability bit of BMSR. 354 */ 355 val &= ~BMSR_EXTCAP; 356 } 357 358 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, val, 0); 359 360 return val; 361 } 362 363 static int 364 axe_miibus_readreg(device_t dev, int phy, int reg) 365 { 366 struct axe_softc *sc = device_private(dev); 367 int val; 368 369 if (sc->axe_dying) 370 return 0; 371 372 if (sc->axe_phyno != phy) 373 return 0; 374 375 axe_lock_mii(sc); 376 val = axe_miibus_readreg_locked(dev, phy, reg); 377 axe_unlock_mii(sc); 378 379 return val; 380 } 381 382 static void 383 axe_miibus_writereg_locked(device_t dev, int phy, int reg, int aval) 384 { 385 struct axe_softc *sc = device_private(dev); 386 usbd_status err; 387 uint16_t val; 388 389 val = htole16(aval); 390 391 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 392 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 393 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 394 395 if (err) { 396 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 397 return; 398 } 399 } 400 401 static void 402 axe_miibus_writereg(device_t dev, int phy, int reg, int aval) 403 { 404 struct axe_softc *sc = device_private(dev); 405 406 if (sc->axe_dying) 407 return; 408 409 if (sc->axe_phyno != phy) 410 return; 411 412 axe_lock_mii(sc); 413 axe_miibus_writereg_locked(dev, phy, reg, aval); 414 axe_unlock_mii(sc); 415 } 416 417 static void 418 axe_miibus_statchg(struct ifnet *ifp) 419 { 420 AXEHIST_FUNC(); AXEHIST_CALLED(); 421 422 struct axe_softc *sc = ifp->if_softc; 423 struct mii_data *mii = &sc->axe_mii; 424 int val, err; 425 426 val = 0; 427 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 428 val |= AXE_MEDIA_FULL_DUPLEX; 429 if (AXE_IS_178_FAMILY(sc)) { 430 if ((IFM_OPTIONS(mii->mii_media_active) & 431 IFM_ETH_TXPAUSE) != 0) 432 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 433 if ((IFM_OPTIONS(mii->mii_media_active) & 434 IFM_ETH_RXPAUSE) != 0) 435 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 436 } 437 } 438 if (AXE_IS_178_FAMILY(sc)) { 439 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 440 if (sc->axe_flags & AX178) 441 val |= AXE_178_MEDIA_ENCK; 442 switch (IFM_SUBTYPE(mii->mii_media_active)) { 443 case IFM_1000_T: 444 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 445 break; 446 case IFM_100_TX: 447 val |= AXE_178_MEDIA_100TX; 448 break; 449 case IFM_10_T: 450 /* doesn't need to be handled */ 451 break; 452 } 453 } 454 455 DPRINTF("val=0x%jx", val, 0, 0, 0); 456 axe_lock_mii(sc); 457 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 458 axe_unlock_mii(sc); 459 if (err) { 460 aprint_error_dev(sc->axe_dev, "media change failed\n"); 461 return; 462 } 463 } 464 465 static void 466 axe_setmulti(struct axe_softc *sc) 467 { 468 AXEHIST_FUNC(); AXEHIST_CALLED(); 469 struct ifnet *ifp = &sc->sc_if; 470 struct ether_multi *enm; 471 struct ether_multistep step; 472 uint32_t h = 0; 473 uint16_t rxmode; 474 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 475 476 if (sc->axe_dying) 477 return; 478 479 axe_lock_mii(sc); 480 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 481 axe_unlock_mii(sc); 482 aprint_error_dev(sc->axe_dev, "can't read rxmode"); 483 return; 484 } 485 rxmode = le16toh(rxmode); 486 487 rxmode &= 488 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 489 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 490 491 rxmode |= 492 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 493 494 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 495 if (ifp->if_flags & IFF_PROMISC) 496 rxmode |= AXE_RXCMD_PROMISC; 497 goto allmulti; 498 } 499 500 /* Now program new ones */ 501 ETHER_FIRST_MULTI(step, &sc->axe_ec, enm); 502 while (enm != NULL) { 503 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 504 ETHER_ADDR_LEN) != 0) 505 goto allmulti; 506 507 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 508 hashtbl[h >> 3] |= 1U << (h & 7); 509 ETHER_NEXT_MULTI(step, enm); 510 } 511 ifp->if_flags &= ~IFF_ALLMULTI; 512 rxmode |= AXE_RXCMD_MULTICAST; 513 514 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 515 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 516 axe_unlock_mii(sc); 517 return; 518 519 allmulti: 520 ifp->if_flags |= IFF_ALLMULTI; 521 rxmode |= AXE_RXCMD_ALLMULTI; 522 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 523 axe_unlock_mii(sc); 524 } 525 526 527 static void 528 axe_reset(struct axe_softc *sc) 529 { 530 531 if (sc->axe_dying) 532 return; 533 534 /* 535 * softnet_lock can be taken when NET_MPAFE is not defined when calling 536 * if_addr_init -> if_init. This doesn't mixe well with the 537 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 538 * can fire during the wait and attempt to take softnet_lock and then 539 * block the softclk thread meaing the wait never ends. 540 */ 541 #ifndef NET_MPSAFE 542 /* XXX What to reset? */ 543 544 /* Wait a little while for the chip to get its brains in order. */ 545 DELAY(1000); 546 #else 547 axe_lock_mii(sc); 548 549 if (sc->axe_flags & AX178) { 550 axe_ax88178_init(sc); 551 } else if (sc->axe_flags & AX772) { 552 axe_ax88772_init(sc); 553 } else if (sc->axe_flags & AX772A) { 554 axe_ax88772a_init(sc); 555 } else if (sc->axe_flags & AX772B) { 556 axe_ax88772b_init(sc); 557 } 558 axe_unlock_mii(sc); 559 #endif 560 } 561 562 static int 563 axe_get_phyno(struct axe_softc *sc, int sel) 564 { 565 int phyno; 566 567 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 568 case PHY_TYPE_100_HOME: 569 /* FALLTHROUGH */ 570 case PHY_TYPE_GIG: 571 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 572 break; 573 case PHY_TYPE_SPECIAL: 574 /* FALLTHROUGH */ 575 case PHY_TYPE_RSVD: 576 /* FALLTHROUGH */ 577 case PHY_TYPE_NON_SUP: 578 /* FALLTHROUGH */ 579 default: 580 phyno = -1; 581 break; 582 } 583 584 return phyno; 585 } 586 587 #define AXE_GPIO_WRITE(x, y) do { \ 588 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 589 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 590 } while (0) 591 592 static void 593 axe_ax88178_init(struct axe_softc *sc) 594 { 595 AXEHIST_FUNC(); AXEHIST_CALLED(); 596 int gpio0, ledmode, phymode; 597 uint16_t eeprom, val; 598 599 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 600 /* XXX magic */ 601 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 602 eeprom = 0xffff; 603 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 604 605 eeprom = le16toh(eeprom); 606 607 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 608 609 /* if EEPROM is invalid we have to use to GPIO0 */ 610 if (eeprom == 0xffff) { 611 phymode = AXE_PHY_MODE_MARVELL; 612 gpio0 = 1; 613 ledmode = 0; 614 } else { 615 phymode = eeprom & 0x7f; 616 gpio0 = (eeprom & 0x80) ? 0 : 1; 617 ledmode = eeprom >> 8; 618 } 619 620 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 621 622 /* Program GPIOs depending on PHY hardware. */ 623 switch (phymode) { 624 case AXE_PHY_MODE_MARVELL: 625 if (gpio0 == 1) { 626 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 627 hz / 32); 628 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 629 hz / 32); 630 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 631 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 632 hz / 32); 633 } else { 634 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 635 AXE_GPIO1_EN, hz / 3); 636 if (ledmode == 1) { 637 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 638 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 639 hz / 3); 640 } else { 641 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 642 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 643 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 644 AXE_GPIO2_EN, hz / 4); 645 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 646 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 647 } 648 } 649 break; 650 case AXE_PHY_MODE_CICADA: 651 case AXE_PHY_MODE_CICADA_V2: 652 case AXE_PHY_MODE_CICADA_V2_ASIX: 653 if (gpio0 == 1) 654 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 655 AXE_GPIO0_EN, hz / 32); 656 else 657 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 658 AXE_GPIO1_EN, hz / 32); 659 break; 660 case AXE_PHY_MODE_AGERE: 661 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 662 AXE_GPIO1_EN, hz / 32); 663 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 664 AXE_GPIO2_EN, hz / 32); 665 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 666 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 667 AXE_GPIO2_EN, hz / 32); 668 break; 669 case AXE_PHY_MODE_REALTEK_8211CL: 670 case AXE_PHY_MODE_REALTEK_8211BN: 671 case AXE_PHY_MODE_REALTEK_8251CL: 672 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 673 AXE_GPIO1 | AXE_GPIO1_EN; 674 AXE_GPIO_WRITE(val, hz / 32); 675 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 676 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 677 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 678 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 679 axe_miibus_writereg_locked(sc->axe_dev, 680 sc->axe_phyno, 0x1F, 0x0005); 681 axe_miibus_writereg_locked(sc->axe_dev, 682 sc->axe_phyno, 0x0C, 0x0000); 683 val = axe_miibus_readreg_locked(sc->axe_dev, 684 sc->axe_phyno, 0x0001); 685 axe_miibus_writereg_locked(sc->axe_dev, 686 sc->axe_phyno, 0x01, val | 0x0080); 687 axe_miibus_writereg_locked(sc->axe_dev, 688 sc->axe_phyno, 0x1F, 0x0000); 689 } 690 break; 691 default: 692 /* Unknown PHY model or no need to program GPIOs. */ 693 break; 694 } 695 696 /* soft reset */ 697 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 698 usbd_delay_ms(sc->axe_udev, 150); 699 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 700 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 701 usbd_delay_ms(sc->axe_udev, 150); 702 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 703 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 704 usbd_delay_ms(sc->axe_udev, 10); 705 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 706 } 707 708 static void 709 axe_ax88772_init(struct axe_softc *sc) 710 { 711 AXEHIST_FUNC(); AXEHIST_CALLED(); 712 713 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 714 usbd_delay_ms(sc->axe_udev, 40); 715 716 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 717 /* ask for the embedded PHY */ 718 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 719 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 720 usbd_delay_ms(sc->axe_udev, 10); 721 722 /* power down and reset state, pin reset state */ 723 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 724 usbd_delay_ms(sc->axe_udev, 60); 725 726 /* power down/reset state, pin operating state */ 727 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 728 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 729 usbd_delay_ms(sc->axe_udev, 150); 730 731 /* power up, reset */ 732 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 733 734 /* power up, operating */ 735 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 736 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 737 } else { 738 /* ask for external PHY */ 739 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 740 NULL); 741 usbd_delay_ms(sc->axe_udev, 10); 742 743 /* power down internal PHY */ 744 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 745 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 746 } 747 748 usbd_delay_ms(sc->axe_udev, 150); 749 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 750 } 751 752 static void 753 axe_ax88772_phywake(struct axe_softc *sc) 754 { 755 AXEHIST_FUNC(); AXEHIST_CALLED(); 756 757 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 758 /* Manually select internal(embedded) PHY - MAC mode. */ 759 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 760 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 761 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 762 } else { 763 /* 764 * Manually select external PHY - MAC mode. 765 * Reverse MII/RMII is for AX88772A PHY mode. 766 */ 767 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 768 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 769 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 770 } 771 772 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 773 AXE_SW_RESET_IPRL, NULL); 774 775 /* T1 = min 500ns everywhere */ 776 usbd_delay_ms(sc->axe_udev, 150); 777 778 /* Take PHY out of power down. */ 779 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 780 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 781 } else { 782 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 783 } 784 785 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 786 usbd_delay_ms(sc->axe_udev, 600); 787 788 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 789 790 /* T3 = 500ns everywhere */ 791 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 792 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 793 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 794 } 795 796 static void 797 axe_ax88772a_init(struct axe_softc *sc) 798 { 799 AXEHIST_FUNC(); AXEHIST_CALLED(); 800 801 /* Reload EEPROM. */ 802 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 803 axe_ax88772_phywake(sc); 804 /* Stop MAC. */ 805 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 806 } 807 808 static void 809 axe_ax88772b_init(struct axe_softc *sc) 810 { 811 AXEHIST_FUNC(); AXEHIST_CALLED(); 812 uint16_t eeprom; 813 int i; 814 815 /* Reload EEPROM. */ 816 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 817 818 /* 819 * Save PHY power saving configuration(high byte) and 820 * clear EEPROM checksum value(low byte). 821 */ 822 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 823 &eeprom)) { 824 aprint_error_dev(sc->axe_dev, "failed to read eeprom\n"); 825 return; 826 } 827 828 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 829 830 /* 831 * Auto-loaded default station address from internal ROM is 832 * 00:00:00:00:00:00 such that an explicit access to EEPROM 833 * is required to get real station address. 834 */ 835 uint8_t *eaddr = sc->axe_enaddr; 836 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 837 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 838 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 839 aprint_error_dev(sc->axe_dev, 840 "failed to read eeprom\n"); 841 eeprom = 0; 842 } 843 eeprom = le16toh(eeprom); 844 *eaddr++ = (uint8_t)(eeprom & 0xFF); 845 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 846 } 847 /* Wakeup PHY. */ 848 axe_ax88772_phywake(sc); 849 /* Stop MAC. */ 850 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 851 } 852 853 #undef AXE_GPIO_WRITE 854 855 /* 856 * Probe for a AX88172 chip. 857 */ 858 int 859 axe_match(device_t parent, cfdata_t match, void *aux) 860 { 861 struct usb_attach_arg *uaa = aux; 862 863 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 864 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 865 } 866 867 /* 868 * Attach the interface. Allocate softc structures, do ifmedia 869 * setup and ethernet/BPF attach. 870 */ 871 void 872 axe_attach(device_t parent, device_t self, void *aux) 873 { 874 AXEHIST_FUNC(); AXEHIST_CALLED(); 875 struct axe_softc *sc = device_private(self); 876 struct usb_attach_arg *uaa = aux; 877 struct usbd_device *dev = uaa->uaa_device; 878 usbd_status err; 879 usb_interface_descriptor_t *id; 880 usb_endpoint_descriptor_t *ed; 881 struct mii_data *mii; 882 char *devinfop; 883 const char *devname = device_xname(self); 884 struct ifnet *ifp; 885 int i, s; 886 887 aprint_naive("\n"); 888 aprint_normal("\n"); 889 890 sc->axe_dev = self; 891 sc->axe_udev = dev; 892 893 devinfop = usbd_devinfo_alloc(dev, 0); 894 aprint_normal_dev(self, "%s\n", devinfop); 895 usbd_devinfo_free(devinfop); 896 897 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 898 if (err) { 899 aprint_error_dev(self, "failed to set configuration" 900 ", err=%s\n", usbd_errstr(err)); 901 return; 902 } 903 904 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 905 906 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 907 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 908 909 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 910 if (err) { 911 aprint_error_dev(self, "getting interface handle failed\n"); 912 return; 913 } 914 915 sc->axe_product = uaa->uaa_product; 916 sc->axe_vendor = uaa->uaa_vendor; 917 918 id = usbd_get_interface_descriptor(sc->axe_iface); 919 920 /* decide on what our bufsize will be */ 921 if (AXE_IS_178_FAMILY(sc)) 922 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 923 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 924 else 925 sc->axe_bufsz = AXE_172_BUFSZ; 926 927 sc->axe_ed[AXE_ENDPT_RX] = -1; 928 sc->axe_ed[AXE_ENDPT_TX] = -1; 929 sc->axe_ed[AXE_ENDPT_INTR] = -1; 930 931 /* Find endpoints. */ 932 for (i = 0; i < id->bNumEndpoints; i++) { 933 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 934 if (ed == NULL) { 935 aprint_error_dev(self, "couldn't get ep %d\n", i); 936 return; 937 } 938 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 939 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 940 941 if (dir == UE_DIR_IN && xt == UE_BULK && 942 sc->axe_ed[AXE_ENDPT_RX] == -1) { 943 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 944 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 945 sc->axe_ed[AXE_ENDPT_TX] == -1) { 946 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 947 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 948 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 949 } 950 } 951 952 s = splnet(); 953 954 /* We need the PHYID for init dance in some cases */ 955 axe_lock_mii(sc); 956 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 957 aprint_error_dev(self, "failed to read phyaddrs\n"); 958 return; 959 } 960 961 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 962 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 963 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 964 if (sc->axe_phyno == -1) 965 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 966 if (sc->axe_phyno == -1) { 967 DPRINTF(" no valid PHY address found, assuming PHY address 0", 968 0, 0, 0, 0); 969 sc->axe_phyno = 0; 970 } 971 972 /* Initialize controller and get station address. */ 973 974 if (sc->axe_flags & AX178) { 975 axe_ax88178_init(sc); 976 } else if (sc->axe_flags & AX772) { 977 axe_ax88772_init(sc); 978 } else if (sc->axe_flags & AX772A) { 979 axe_ax88772a_init(sc); 980 } else if (sc->axe_flags & AX772B) { 981 axe_ax88772b_init(sc); 982 } 983 984 if (!(sc->axe_flags & AX772B)) { 985 if (axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, sc->axe_enaddr)) 986 { 987 aprint_debug_dev(self, 988 "failed to read ethernet address\n"); 989 } 990 } 991 992 /* 993 * Fetch IPG values. 994 */ 995 if (sc->axe_flags & (AX772A | AX772B)) { 996 /* Set IPG values. */ 997 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 998 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 999 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1000 } else { 1001 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 1002 aprint_error_dev(self, "failed to read ipg\n"); 1003 return; 1004 } 1005 } 1006 1007 axe_unlock_mii(sc); 1008 1009 /* 1010 * An ASIX chip was detected. Inform the world. 1011 */ 1012 aprint_normal_dev(self, "Ethernet address %s\n", 1013 ether_sprintf(sc->axe_enaddr)); 1014 1015 /* Initialize interface info.*/ 1016 ifp = &sc->sc_if; 1017 ifp->if_softc = sc; 1018 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 1019 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1020 ifp->if_ioctl = axe_ioctl; 1021 ifp->if_start = axe_start; 1022 ifp->if_init = axe_init; 1023 ifp->if_stop = axe_stop; 1024 ifp->if_watchdog = axe_watchdog; 1025 1026 IFQ_SET_READY(&ifp->if_snd); 1027 1028 if (AXE_IS_178_FAMILY(sc)) 1029 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1030 if (sc->axe_flags & AX772B) { 1031 ifp->if_capabilities = 1032 IFCAP_CSUM_IPv4_Rx | 1033 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1034 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1035 /* 1036 * Checksum offloading of AX88772B also works with VLAN 1037 * tagged frames but there is no way to take advantage 1038 * of the feature because vlan(4) assumes 1039 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1040 * support checksum offloading with VLAN. VLAN hardware 1041 * tagging support of AX88772B is very limited so it's 1042 * not possible to announce IFCAP_VLAN_HWTAGGING. 1043 */ 1044 } 1045 u_int adv_pause; 1046 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1047 adv_pause = MIIF_DOPAUSE; 1048 else 1049 adv_pause = 0; 1050 adv_pause = 0; 1051 1052 /* Initialize MII/media info. */ 1053 mii = &sc->axe_mii; 1054 mii->mii_ifp = ifp; 1055 mii->mii_readreg = axe_miibus_readreg; 1056 mii->mii_writereg = axe_miibus_writereg; 1057 mii->mii_statchg = axe_miibus_statchg; 1058 mii->mii_flags = MIIF_AUTOTSLEEP; 1059 1060 sc->axe_ec.ec_mii = mii; 1061 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1062 1063 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1064 adv_pause); 1065 1066 if (LIST_EMPTY(&mii->mii_phys)) { 1067 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1068 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1069 } else 1070 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1071 1072 /* Attach the interface. */ 1073 if_attach(ifp); 1074 ether_ifattach(ifp, sc->axe_enaddr); 1075 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1076 RND_TYPE_NET, RND_FLAG_DEFAULT); 1077 1078 callout_init(&sc->axe_stat_ch, 0); 1079 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1080 1081 sc->axe_attached = true; 1082 splx(s); 1083 1084 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1085 1086 if (!pmf_device_register(self, NULL, NULL)) 1087 aprint_error_dev(self, "couldn't establish power handler\n"); 1088 } 1089 1090 int 1091 axe_detach(device_t self, int flags) 1092 { 1093 AXEHIST_FUNC(); AXEHIST_CALLED(); 1094 struct axe_softc *sc = device_private(self); 1095 int s; 1096 struct ifnet *ifp = &sc->sc_if; 1097 1098 /* Detached before attached finished, so just bail out. */ 1099 if (!sc->axe_attached) 1100 return 0; 1101 1102 pmf_device_deregister(self); 1103 1104 sc->axe_dying = true; 1105 1106 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1107 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1108 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1109 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1110 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1111 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1112 1113 /* 1114 * Remove any pending tasks. They cannot be executing because they run 1115 * in the same thread as detach. 1116 */ 1117 usb_rem_task(sc->axe_udev, &sc->axe_tick_task); 1118 1119 s = splusb(); 1120 1121 if (ifp->if_flags & IFF_RUNNING) 1122 axe_stop(ifp, 1); 1123 1124 1125 if (--sc->axe_refcnt >= 0) { 1126 /* Wait for processes to go away. */ 1127 usb_detach_waitold(sc->axe_dev); 1128 } 1129 1130 callout_destroy(&sc->axe_stat_ch); 1131 mutex_destroy(&sc->axe_mii_lock); 1132 rnd_detach_source(&sc->rnd_source); 1133 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1134 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1135 ether_ifdetach(ifp); 1136 if_detach(ifp); 1137 1138 #ifdef DIAGNOSTIC 1139 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1140 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1141 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1142 aprint_debug_dev(self, "detach has active endpoints\n"); 1143 #endif 1144 1145 sc->axe_attached = false; 1146 1147 splx(s); 1148 1149 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1150 1151 return 0; 1152 } 1153 1154 int 1155 axe_activate(device_t self, devact_t act) 1156 { 1157 AXEHIST_FUNC(); AXEHIST_CALLED(); 1158 struct axe_softc *sc = device_private(self); 1159 1160 switch (act) { 1161 case DVACT_DEACTIVATE: 1162 if_deactivate(&sc->axe_ec.ec_if); 1163 sc->axe_dying = true; 1164 return 0; 1165 default: 1166 return EOPNOTSUPP; 1167 } 1168 } 1169 1170 static int 1171 axe_rx_list_init(struct axe_softc *sc) 1172 { 1173 AXEHIST_FUNC(); AXEHIST_CALLED(); 1174 1175 struct axe_cdata *cd; 1176 struct axe_chain *c; 1177 int i; 1178 1179 cd = &sc->axe_cdata; 1180 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1181 c = &cd->axe_rx_chain[i]; 1182 c->axe_sc = sc; 1183 c->axe_idx = i; 1184 if (c->axe_xfer == NULL) { 1185 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1186 sc->axe_bufsz, 0, 0, &c->axe_xfer); 1187 if (err) 1188 return err; 1189 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1190 } 1191 } 1192 1193 return 0; 1194 } 1195 1196 static int 1197 axe_tx_list_init(struct axe_softc *sc) 1198 { 1199 AXEHIST_FUNC(); AXEHIST_CALLED(); 1200 struct axe_cdata *cd; 1201 struct axe_chain *c; 1202 int i; 1203 1204 cd = &sc->axe_cdata; 1205 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1206 c = &cd->axe_tx_chain[i]; 1207 c->axe_sc = sc; 1208 c->axe_idx = i; 1209 if (c->axe_xfer == NULL) { 1210 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1211 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1212 &c->axe_xfer); 1213 if (err) 1214 return err; 1215 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1216 } 1217 } 1218 1219 return 0; 1220 } 1221 1222 /* 1223 * A frame has been uploaded: pass the resulting mbuf chain up to 1224 * the higher level protocols. 1225 */ 1226 static void 1227 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1228 { 1229 AXEHIST_FUNC(); AXEHIST_CALLED(); 1230 struct axe_softc *sc; 1231 struct axe_chain *c; 1232 struct ifnet *ifp; 1233 uint8_t *buf; 1234 uint32_t total_len; 1235 struct mbuf *m; 1236 int s; 1237 1238 c = (struct axe_chain *)priv; 1239 sc = c->axe_sc; 1240 buf = c->axe_buf; 1241 ifp = &sc->sc_if; 1242 1243 if (sc->axe_dying) 1244 return; 1245 1246 if ((ifp->if_flags & IFF_RUNNING) == 0) 1247 return; 1248 1249 if (status != USBD_NORMAL_COMPLETION) { 1250 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1251 return; 1252 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1253 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1254 usbd_errstr(status)); 1255 } 1256 if (status == USBD_STALLED) 1257 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1258 goto done; 1259 } 1260 1261 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1262 1263 do { 1264 u_int pktlen = 0; 1265 u_int rxlen = 0; 1266 int flags = 0; 1267 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1268 struct axe_sframe_hdr hdr; 1269 1270 if (total_len < sizeof(hdr)) { 1271 ifp->if_ierrors++; 1272 goto done; 1273 } 1274 1275 memcpy(&hdr, buf, sizeof(hdr)); 1276 1277 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1278 total_len, 1279 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1280 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1281 1282 total_len -= sizeof(hdr); 1283 buf += sizeof(hdr); 1284 1285 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1286 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1287 AXE_RH1M_RXLEN_MASK) { 1288 ifp->if_ierrors++; 1289 goto done; 1290 } 1291 1292 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1293 if (total_len < rxlen) { 1294 pktlen = total_len; 1295 total_len = 0; 1296 } else { 1297 pktlen = rxlen; 1298 rxlen = roundup2(rxlen, 2); 1299 total_len -= rxlen; 1300 } 1301 1302 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1303 struct axe_csum_hdr csum_hdr; 1304 1305 if (total_len < sizeof(csum_hdr)) { 1306 ifp->if_ierrors++; 1307 goto done; 1308 } 1309 1310 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1311 1312 csum_hdr.len = le16toh(csum_hdr.len); 1313 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1314 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1315 1316 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1317 " cstatus %#jx", total_len, 1318 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1319 1320 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1321 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1322 sc->sc_lenmask) { 1323 /* we lost sync */ 1324 ifp->if_ierrors++; 1325 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1326 "err", 1327 AXE_CSUM_RXBYTES(csum_hdr.len), 1328 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1329 sc->sc_lenmask, 0); 1330 goto done; 1331 } 1332 /* 1333 * Get total transferred frame length including 1334 * checksum header. The length should be multiple 1335 * of 4. 1336 */ 1337 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1338 u_int len = sizeof(csum_hdr) + pktlen; 1339 len = (len + 3) & ~3; 1340 if (total_len < len) { 1341 DPRINTFN(20, "total_len %#jx < len %#jx", 1342 total_len, len, 0, 0); 1343 /* invalid length */ 1344 ifp->if_ierrors++; 1345 goto done; 1346 } 1347 buf += sizeof(csum_hdr); 1348 1349 const uint16_t cstatus = csum_hdr.cstatus; 1350 1351 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1352 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1353 flags |= M_CSUM_TCP_UDP_BAD; 1354 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1355 flags |= M_CSUM_IPv4_BAD; 1356 1357 const uint16_t l4type = 1358 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1359 1360 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1361 flags |= M_CSUM_TCPv4; 1362 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1363 flags |= M_CSUM_UDPv4; 1364 } 1365 if (total_len < len) { 1366 pktlen = total_len; 1367 total_len = 0; 1368 } else { 1369 total_len -= len; 1370 rxlen = len - sizeof(csum_hdr); 1371 } 1372 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1373 " rxlen %#jx", total_len, len, pktlen, rxlen); 1374 } else { /* AX172 */ 1375 pktlen = rxlen = total_len; 1376 total_len = 0; 1377 } 1378 1379 MGETHDR(m, M_DONTWAIT, MT_DATA); 1380 if (m == NULL) { 1381 ifp->if_ierrors++; 1382 goto done; 1383 } 1384 1385 if (pktlen > MHLEN - ETHER_ALIGN) { 1386 MCLGET(m, M_DONTWAIT); 1387 if ((m->m_flags & M_EXT) == 0) { 1388 m_freem(m); 1389 ifp->if_ierrors++; 1390 goto done; 1391 } 1392 } 1393 m->m_data += ETHER_ALIGN; 1394 1395 m_set_rcvif(m, ifp); 1396 m->m_pkthdr.len = m->m_len = pktlen; 1397 m->m_pkthdr.csum_flags = flags; 1398 1399 memcpy(mtod(m, uint8_t *), buf, pktlen); 1400 buf += rxlen; 1401 1402 DPRINTFN(10, "deliver %jd (%#jx)", m->m_len, m->m_len, 0, 0); 1403 1404 s = splnet(); 1405 1406 if_percpuq_enqueue((ifp)->if_percpuq, (m)); 1407 1408 splx(s); 1409 1410 } while (total_len > 0); 1411 1412 done: 1413 1414 /* Setup new transfer. */ 1415 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1416 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1417 usbd_transfer(xfer); 1418 1419 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1420 } 1421 1422 /* 1423 * A frame was downloaded to the chip. It's safe for us to clean up 1424 * the list buffers. 1425 */ 1426 1427 static void 1428 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1429 { 1430 AXEHIST_FUNC(); AXEHIST_CALLED(); 1431 struct axe_chain *c = priv; 1432 struct axe_softc *sc = c->axe_sc; 1433 struct ifnet *ifp = &sc->sc_if; 1434 int s; 1435 1436 1437 if (sc->axe_dying) 1438 return; 1439 1440 s = splnet(); 1441 1442 ifp->if_timer = 0; 1443 ifp->if_flags &= ~IFF_OACTIVE; 1444 1445 if (status != USBD_NORMAL_COMPLETION) { 1446 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1447 splx(s); 1448 return; 1449 } 1450 ifp->if_oerrors++; 1451 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1452 usbd_errstr(status)); 1453 if (status == USBD_STALLED) 1454 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1455 splx(s); 1456 return; 1457 } 1458 ifp->if_opackets++; 1459 1460 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1461 axe_start(ifp); 1462 1463 splx(s); 1464 } 1465 1466 static void 1467 axe_tick(void *xsc) 1468 { 1469 AXEHIST_FUNC(); AXEHIST_CALLED(); 1470 struct axe_softc *sc = xsc; 1471 1472 if (sc == NULL) 1473 return; 1474 1475 if (sc->axe_dying) 1476 return; 1477 1478 /* Perform periodic stuff in process context */ 1479 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1480 } 1481 1482 static void 1483 axe_tick_task(void *xsc) 1484 { 1485 AXEHIST_FUNC(); AXEHIST_CALLED(); 1486 int s; 1487 struct axe_softc *sc = xsc; 1488 struct ifnet *ifp; 1489 struct mii_data *mii; 1490 1491 if (sc == NULL) 1492 return; 1493 1494 if (sc->axe_dying) 1495 return; 1496 1497 ifp = &sc->sc_if; 1498 mii = &sc->axe_mii; 1499 1500 if (mii == NULL) 1501 return; 1502 1503 s = splnet(); 1504 1505 mii_tick(mii); 1506 if (sc->axe_link == 0 && 1507 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1508 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1509 DPRINTF("got link", 0, 0, 0, 0); 1510 sc->axe_link++; 1511 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1512 axe_start(ifp); 1513 } 1514 1515 callout_schedule(&sc->axe_stat_ch, hz); 1516 1517 splx(s); 1518 } 1519 1520 static int 1521 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1522 { 1523 struct ifnet *ifp = &sc->sc_if; 1524 struct axe_chain *c; 1525 usbd_status err; 1526 int length, boundary; 1527 1528 c = &sc->axe_cdata.axe_tx_chain[idx]; 1529 1530 /* 1531 * Copy the mbuf data into a contiguous buffer, leaving two 1532 * bytes at the beginning to hold the frame length. 1533 */ 1534 if (AXE_IS_178_FAMILY(sc)) { 1535 struct axe_sframe_hdr hdr; 1536 1537 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1538 1539 hdr.len = htole16(m->m_pkthdr.len); 1540 hdr.ilen = ~hdr.len; 1541 1542 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1543 length = sizeof(hdr); 1544 1545 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1546 length += m->m_pkthdr.len; 1547 1548 if ((length % boundary) == 0) { 1549 hdr.len = 0x0000; 1550 hdr.ilen = 0xffff; 1551 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1552 length += sizeof(hdr); 1553 } 1554 } else { 1555 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1556 length = m->m_pkthdr.len; 1557 } 1558 1559 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1560 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1561 1562 /* Transmit */ 1563 err = usbd_transfer(c->axe_xfer); 1564 if (err != USBD_IN_PROGRESS) { 1565 axe_stop(ifp, 0); 1566 return EIO; 1567 } 1568 1569 sc->axe_cdata.axe_tx_cnt++; 1570 1571 return 0; 1572 } 1573 1574 1575 static void 1576 axe_csum_cfg(struct axe_softc *sc) 1577 { 1578 struct ifnet *ifp = &sc->sc_if; 1579 uint16_t csum1, csum2; 1580 1581 if ((sc->axe_flags & AX772B) != 0) { 1582 csum1 = 0; 1583 csum2 = 0; 1584 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1585 csum1 |= AXE_TXCSUM_IP; 1586 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1587 csum1 |= AXE_TXCSUM_TCP; 1588 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1589 csum1 |= AXE_TXCSUM_UDP; 1590 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1591 csum1 |= AXE_TXCSUM_TCPV6; 1592 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1593 csum1 |= AXE_TXCSUM_UDPV6; 1594 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1595 csum1 = 0; 1596 csum2 = 0; 1597 1598 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1599 csum1 |= AXE_RXCSUM_IP; 1600 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1601 csum1 |= AXE_RXCSUM_TCP; 1602 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1603 csum1 |= AXE_RXCSUM_UDP; 1604 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1605 csum1 |= AXE_RXCSUM_TCPV6; 1606 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1607 csum1 |= AXE_RXCSUM_UDPV6; 1608 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1609 } 1610 } 1611 1612 static void 1613 axe_start(struct ifnet *ifp) 1614 { 1615 struct axe_softc *sc; 1616 struct mbuf *m; 1617 1618 sc = ifp->if_softc; 1619 1620 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) 1621 return; 1622 1623 IFQ_POLL(&ifp->if_snd, m); 1624 if (m == NULL) { 1625 return; 1626 } 1627 1628 if (axe_encap(sc, m, 0)) { 1629 ifp->if_flags |= IFF_OACTIVE; 1630 return; 1631 } 1632 IFQ_DEQUEUE(&ifp->if_snd, m); 1633 1634 /* 1635 * If there's a BPF listener, bounce a copy of this frame 1636 * to him. 1637 */ 1638 bpf_mtap(ifp, m); 1639 m_freem(m); 1640 1641 ifp->if_flags |= IFF_OACTIVE; 1642 1643 /* 1644 * Set a timeout in case the chip goes out to lunch. 1645 */ 1646 ifp->if_timer = 5; 1647 1648 return; 1649 } 1650 1651 static int 1652 axe_init(struct ifnet *ifp) 1653 { 1654 AXEHIST_FUNC(); AXEHIST_CALLED(); 1655 struct axe_softc *sc = ifp->if_softc; 1656 struct axe_chain *c; 1657 usbd_status err; 1658 int rxmode; 1659 int i, s; 1660 1661 s = splnet(); 1662 1663 if (ifp->if_flags & IFF_RUNNING) 1664 axe_stop(ifp, 0); 1665 1666 /* 1667 * Cancel pending I/O and free all RX/TX buffers. 1668 */ 1669 axe_reset(sc); 1670 1671 axe_lock_mii(sc); 1672 1673 #if 0 1674 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1675 AX_GPIO_GPO2EN, 5, in_pm); 1676 #endif 1677 /* Set MAC address and transmitter IPG values. */ 1678 if (AXE_IS_178_FAMILY(sc)) { 1679 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1680 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1681 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1682 } else { 1683 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1684 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1685 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1686 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1687 } 1688 if (AXE_IS_178_FAMILY(sc)) { 1689 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1690 if ((sc->axe_flags & AX772B) != 0 && 1691 (ifp->if_capenable & AX_RXCSUM) != 0) { 1692 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1693 sc->axe_flags |= AXCSUM_FRAME; 1694 } else { 1695 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1696 sc->axe_flags |= AXSTD_FRAME; 1697 } 1698 } 1699 1700 /* Configure TX/RX checksum offloading. */ 1701 axe_csum_cfg(sc); 1702 1703 if (sc->axe_flags & AX772B) { 1704 /* AX88772B uses different maximum frame burst configuration. */ 1705 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1706 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1707 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1708 } 1709 /* Enable receiver, set RX mode */ 1710 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1711 if (AXE_IS_178_FAMILY(sc)) { 1712 if (sc->axe_flags & AX772B) { 1713 /* 1714 * Select RX header format type 1. Aligning IP 1715 * header on 4 byte boundary is not needed when 1716 * checksum offloading feature is not used 1717 * because we always copy the received frame in 1718 * RX handler. When RX checksum offloading is 1719 * active, aligning IP header is required to 1720 * reflect actual frame length including RX 1721 * header size. 1722 */ 1723 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1724 if (sc->axe_flags & AXCSUM_FRAME) 1725 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1726 } else { 1727 /* 1728 * Default Rx buffer size is too small to get 1729 * maximum performance. 1730 */ 1731 #if 0 1732 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1733 /* Largest possible USB buffer size for AX88178 */ 1734 #endif 1735 rxmode |= AXE_178_RXCMD_MFB_16384; 1736 } 1737 } else { 1738 rxmode |= AXE_172_RXCMD_UNICAST; 1739 } 1740 1741 1742 /* If we want promiscuous mode, set the allframes bit. */ 1743 if (ifp->if_flags & IFF_PROMISC) 1744 rxmode |= AXE_RXCMD_PROMISC; 1745 1746 if (ifp->if_flags & IFF_BROADCAST) 1747 rxmode |= AXE_RXCMD_BROADCAST; 1748 1749 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1750 1751 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1752 axe_unlock_mii(sc); 1753 1754 /* Load the multicast filter. */ 1755 axe_setmulti(sc); 1756 1757 /* Open RX and TX pipes. */ 1758 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1759 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1760 if (err) { 1761 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1762 usbd_errstr(err)); 1763 splx(s); 1764 return EIO; 1765 } 1766 1767 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1768 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1769 if (err) { 1770 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1771 usbd_errstr(err)); 1772 splx(s); 1773 return EIO; 1774 } 1775 1776 /* Init RX ring. */ 1777 if (axe_rx_list_init(sc) != 0) { 1778 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1779 splx(s); 1780 return ENOBUFS; 1781 } 1782 1783 /* Init TX ring. */ 1784 if (axe_tx_list_init(sc) != 0) { 1785 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1786 splx(s); 1787 return ENOBUFS; 1788 } 1789 1790 /* Start up the receive pipe. */ 1791 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1792 c = &sc->axe_cdata.axe_rx_chain[i]; 1793 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1794 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1795 usbd_transfer(c->axe_xfer); 1796 } 1797 1798 ifp->if_flags |= IFF_RUNNING; 1799 ifp->if_flags &= ~IFF_OACTIVE; 1800 1801 splx(s); 1802 1803 callout_schedule(&sc->axe_stat_ch, hz); 1804 return 0; 1805 } 1806 1807 static int 1808 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1809 { 1810 struct axe_softc *sc = ifp->if_softc; 1811 int s; 1812 int error = 0; 1813 1814 s = splnet(); 1815 1816 switch(cmd) { 1817 case SIOCSIFFLAGS: 1818 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1819 break; 1820 1821 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1822 case IFF_RUNNING: 1823 axe_stop(ifp, 1); 1824 break; 1825 case IFF_UP: 1826 axe_init(ifp); 1827 break; 1828 case IFF_UP | IFF_RUNNING: 1829 if ((ifp->if_flags ^ sc->axe_if_flags) == IFF_PROMISC) 1830 axe_setmulti(sc); 1831 else 1832 axe_init(ifp); 1833 break; 1834 } 1835 sc->axe_if_flags = ifp->if_flags; 1836 break; 1837 1838 default: 1839 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1840 break; 1841 1842 error = 0; 1843 1844 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) 1845 axe_setmulti(sc); 1846 1847 } 1848 splx(s); 1849 1850 return error; 1851 } 1852 1853 static void 1854 axe_watchdog(struct ifnet *ifp) 1855 { 1856 struct axe_softc *sc; 1857 struct axe_chain *c; 1858 usbd_status stat; 1859 int s; 1860 1861 sc = ifp->if_softc; 1862 1863 ifp->if_oerrors++; 1864 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1865 1866 s = splusb(); 1867 c = &sc->axe_cdata.axe_tx_chain[0]; 1868 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1869 axe_txeof(c->axe_xfer, c, stat); 1870 1871 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1872 axe_start(ifp); 1873 splx(s); 1874 } 1875 1876 /* 1877 * Stop the adapter and free any mbufs allocated to the 1878 * RX and TX lists. 1879 */ 1880 static void 1881 axe_stop(struct ifnet *ifp, int disable) 1882 { 1883 struct axe_softc *sc = ifp->if_softc; 1884 usbd_status err; 1885 int i; 1886 1887 ifp->if_timer = 0; 1888 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1889 1890 callout_stop(&sc->axe_stat_ch); 1891 1892 /* Stop transfers. */ 1893 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1894 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1895 if (err) { 1896 aprint_error_dev(sc->axe_dev, 1897 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1898 } 1899 } 1900 1901 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1902 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1903 if (err) { 1904 aprint_error_dev(sc->axe_dev, 1905 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1906 } 1907 } 1908 1909 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1910 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1911 if (err) { 1912 aprint_error_dev(sc->axe_dev, 1913 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1914 } 1915 } 1916 1917 axe_reset(sc); 1918 1919 /* Free RX resources. */ 1920 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1921 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1922 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1923 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1924 } 1925 } 1926 1927 /* Free TX resources. */ 1928 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1929 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1930 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1931 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1932 } 1933 } 1934 1935 /* Close pipes. */ 1936 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1937 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1938 if (err) { 1939 aprint_error_dev(sc->axe_dev, 1940 "close rx pipe failed: %s\n", usbd_errstr(err)); 1941 } 1942 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1943 } 1944 1945 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1946 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1947 if (err) { 1948 aprint_error_dev(sc->axe_dev, 1949 "close tx pipe failed: %s\n", usbd_errstr(err)); 1950 } 1951 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1952 } 1953 1954 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1955 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1956 if (err) { 1957 aprint_error_dev(sc->axe_dev, 1958 "close intr pipe failed: %s\n", usbd_errstr(err)); 1959 } 1960 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1961 } 1962 1963 sc->axe_link = 0; 1964 } 1965 1966 MODULE(MODULE_CLASS_DRIVER, if_axe, "bpf"); 1967 1968 #ifdef _MODULE 1969 #include "ioconf.c" 1970 #endif 1971 1972 static int 1973 if_axe_modcmd(modcmd_t cmd, void *aux) 1974 { 1975 int error = 0; 1976 1977 switch (cmd) { 1978 case MODULE_CMD_INIT: 1979 #ifdef _MODULE 1980 error = config_init_component(cfdriver_ioconf_axe, 1981 cfattach_ioconf_axe, cfdata_ioconf_axe); 1982 #endif 1983 return error; 1984 case MODULE_CMD_FINI: 1985 #ifdef _MODULE 1986 error = config_fini_component(cfdriver_ioconf_axe, 1987 cfattach_ioconf_axe, cfdata_ioconf_axe); 1988 #endif 1989 return error; 1990 default: 1991 return ENOTTY; 1992 } 1993 } 1994
Indexes created Wed Oct 01 18:09:54 GMT 2025