if_axe.c revision 1.88
1 /* $NetBSD: if_axe.c,v 1.88 2018/04/22 20:32:27 christos Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.88 2018/04/22 20:32:27 christos Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 /* 131 * AXE_178_MAX_FRAME_BURST 132 * max frame burst size for Ax88178 and Ax88772 133 * 0 2048 bytes 134 * 1 4096 bytes 135 * 2 8192 bytes 136 * 3 16384 bytes 137 * use the largest your system can handle without USB stalling. 138 * 139 * NB: 88772 parts appear to generate lots of input errors with 140 * a 2K rx buffer and 8K is only slightly faster than 4K on an 141 * EHCI port on a T42 so change at your own risk. 142 */ 143 #define AXE_178_MAX_FRAME_BURST 1 144 145 146 #ifdef USB_DEBUG 147 #ifndef AXE_DEBUG 148 #define axedebug 0 149 #else 150 static int axedebug = 20; 151 152 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 153 { 154 int err; 155 const struct sysctlnode *rnode; 156 const struct sysctlnode *cnode; 157 158 err = sysctl_createv(clog, 0, NULL, &rnode, 159 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 160 SYSCTL_DESCR("axe global controls"), 161 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 162 163 if (err) 164 goto fail; 165 166 /* control debugging printfs */ 167 err = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 169 "debug", SYSCTL_DESCR("Enable debugging output"), 170 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 171 if (err) 172 goto fail; 173 174 return; 175 fail: 176 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 177 } 178 179 #endif /* AXE_DEBUG */ 180 #endif /* USB_DEBUG */ 181 182 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 183 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 184 #define AXEHIST_FUNC() USBHIST_FUNC() 185 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 186 187 /* 188 * Various supported device vendors/products. 189 */ 190 static const struct axe_type axe_devs[] = { 191 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 192 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 193 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 199 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 200 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 201 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 202 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 203 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 204 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 206 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 208 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 209 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 210 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 211 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 212 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 213 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 214 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 215 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 216 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 218 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 219 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 220 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 221 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 222 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 223 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 225 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 226 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 227 }; 228 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 229 230 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 231 { 0x8000, 0x8001, 2048 }, 232 { 0x8100, 0x8147, 4096 }, 233 { 0x8200, 0x81EB, 6144 }, 234 { 0x8300, 0x83D7, 8192 }, 235 { 0x8400, 0x851E, 16384 }, 236 { 0x8500, 0x8666, 20480 }, 237 { 0x8600, 0x87AE, 24576 }, 238 { 0x8700, 0x8A3D, 32768 } 239 }; 240 241 int axe_match(device_t, cfdata_t, void *); 242 void axe_attach(device_t, device_t, void *); 243 int axe_detach(device_t, int); 244 int axe_activate(device_t, devact_t); 245 246 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 247 axe_match, axe_attach, axe_detach, axe_activate); 248 249 static int axe_tx_list_init(struct axe_softc *); 250 static int axe_rx_list_init(struct axe_softc *); 251 static int axe_encap(struct axe_softc *, struct mbuf *, int); 252 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 253 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 254 static void axe_tick(void *); 255 static void axe_tick_task(void *); 256 static void axe_start(struct ifnet *); 257 static int axe_ioctl(struct ifnet *, u_long, void *); 258 static int axe_init(struct ifnet *); 259 static void axe_stop(struct ifnet *, int); 260 static void axe_watchdog(struct ifnet *); 261 static int axe_miibus_readreg_locked(device_t, int, int); 262 static int axe_miibus_readreg(device_t, int, int); 263 static void axe_miibus_writereg_locked(device_t, int, int, int); 264 static void axe_miibus_writereg(device_t, int, int, int); 265 static void axe_miibus_statchg(struct ifnet *); 266 static int axe_cmd(struct axe_softc *, int, int, int, void *); 267 static void axe_reset(struct axe_softc *); 268 269 static void axe_setmulti(struct axe_softc *); 270 static void axe_lock_mii(struct axe_softc *); 271 static void axe_unlock_mii(struct axe_softc *); 272 273 static void axe_ax88178_init(struct axe_softc *); 274 static void axe_ax88772_init(struct axe_softc *); 275 static void axe_ax88772a_init(struct axe_softc *); 276 static void axe_ax88772b_init(struct axe_softc *); 277 278 /* Get exclusive access to the MII registers */ 279 static void 280 axe_lock_mii(struct axe_softc *sc) 281 { 282 283 sc->axe_refcnt++; 284 mutex_enter(&sc->axe_mii_lock); 285 } 286 287 static void 288 axe_unlock_mii(struct axe_softc *sc) 289 { 290 291 mutex_exit(&sc->axe_mii_lock); 292 if (--sc->axe_refcnt < 0) 293 usb_detach_wakeupold((sc->axe_dev)); 294 } 295 296 static int 297 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 298 { 299 AXEHIST_FUNC(); AXEHIST_CALLED(); 300 usb_device_request_t req; 301 usbd_status err; 302 303 KASSERT(mutex_owned(&sc->axe_mii_lock)); 304 305 if (sc->axe_dying) 306 return -1; 307 308 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 309 310 if (AXE_CMD_DIR(cmd)) 311 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 312 else 313 req.bmRequestType = UT_READ_VENDOR_DEVICE; 314 req.bRequest = AXE_CMD_CMD(cmd); 315 USETW(req.wValue, val); 316 USETW(req.wIndex, index); 317 USETW(req.wLength, AXE_CMD_LEN(cmd)); 318 319 err = usbd_do_request(sc->axe_udev, &req, buf); 320 321 if (err) { 322 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 323 return -1; 324 } 325 return 0; 326 } 327 328 static int 329 axe_miibus_readreg_locked(device_t dev, int phy, int reg) 330 { 331 AXEHIST_FUNC(); AXEHIST_CALLED(); 332 struct axe_softc *sc = device_private(dev); 333 usbd_status err; 334 uint16_t val; 335 336 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 337 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 339 340 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 341 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 342 if (err) { 343 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 344 return -1; 345 } 346 347 val = le16toh(val); 348 if (AXE_IS_772(sc) && reg == MII_BMSR) { 349 /* 350 * BMSR of AX88772 indicates that it supports extended 351 * capability but the extended status register is 352 * reserved for embedded ethernet PHY. So clear the 353 * extended capability bit of BMSR. 354 */ 355 val &= ~BMSR_EXTCAP; 356 } 357 358 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, val, 0); 359 360 return val; 361 } 362 363 static int 364 axe_miibus_readreg(device_t dev, int phy, int reg) 365 { 366 struct axe_softc *sc = device_private(dev); 367 int val; 368 369 if (sc->axe_dying) 370 return 0; 371 372 if (sc->axe_phyno != phy) 373 return 0; 374 375 axe_lock_mii(sc); 376 val = axe_miibus_readreg_locked(dev, phy, reg); 377 axe_unlock_mii(sc); 378 379 return val; 380 } 381 382 static void 383 axe_miibus_writereg_locked(device_t dev, int phy, int reg, int aval) 384 { 385 struct axe_softc *sc = device_private(dev); 386 usbd_status err; 387 uint16_t val; 388 389 val = htole16(aval); 390 391 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 392 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 393 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 394 395 if (err) { 396 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 397 return; 398 } 399 } 400 401 static void 402 axe_miibus_writereg(device_t dev, int phy, int reg, int aval) 403 { 404 struct axe_softc *sc = device_private(dev); 405 406 if (sc->axe_dying) 407 return; 408 409 if (sc->axe_phyno != phy) 410 return; 411 412 axe_lock_mii(sc); 413 axe_miibus_writereg_locked(dev, phy, reg, aval); 414 axe_unlock_mii(sc); 415 } 416 417 static void 418 axe_miibus_statchg(struct ifnet *ifp) 419 { 420 AXEHIST_FUNC(); AXEHIST_CALLED(); 421 422 struct axe_softc *sc = ifp->if_softc; 423 struct mii_data *mii = &sc->axe_mii; 424 int val, err; 425 426 val = 0; 427 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 428 val |= AXE_MEDIA_FULL_DUPLEX; 429 if (AXE_IS_178_FAMILY(sc)) { 430 if ((IFM_OPTIONS(mii->mii_media_active) & 431 IFM_ETH_TXPAUSE) != 0) 432 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 433 if ((IFM_OPTIONS(mii->mii_media_active) & 434 IFM_ETH_RXPAUSE) != 0) 435 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 436 } 437 } 438 if (AXE_IS_178_FAMILY(sc)) { 439 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 440 if (sc->axe_flags & AX178) 441 val |= AXE_178_MEDIA_ENCK; 442 switch (IFM_SUBTYPE(mii->mii_media_active)) { 443 case IFM_1000_T: 444 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 445 break; 446 case IFM_100_TX: 447 val |= AXE_178_MEDIA_100TX; 448 break; 449 case IFM_10_T: 450 /* doesn't need to be handled */ 451 break; 452 } 453 } 454 455 DPRINTF("val=0x%jx", val, 0, 0, 0); 456 axe_lock_mii(sc); 457 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 458 axe_unlock_mii(sc); 459 if (err) { 460 aprint_error_dev(sc->axe_dev, "media change failed\n"); 461 return; 462 } 463 } 464 465 static void 466 axe_setmulti(struct axe_softc *sc) 467 { 468 AXEHIST_FUNC(); AXEHIST_CALLED(); 469 struct ifnet *ifp = &sc->sc_if; 470 struct ether_multi *enm; 471 struct ether_multistep step; 472 uint32_t h = 0; 473 uint16_t rxmode; 474 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 475 476 if (sc->axe_dying) 477 return; 478 479 axe_lock_mii(sc); 480 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 481 axe_unlock_mii(sc); 482 aprint_error_dev(sc->axe_dev, "can't read rxmode"); 483 return; 484 } 485 rxmode = le16toh(rxmode); 486 487 rxmode &= 488 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 489 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 490 491 rxmode |= 492 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 493 494 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 495 if (ifp->if_flags & IFF_PROMISC) 496 rxmode |= AXE_RXCMD_PROMISC; 497 goto allmulti; 498 } 499 500 /* Now program new ones */ 501 ETHER_FIRST_MULTI(step, &sc->axe_ec, enm); 502 while (enm != NULL) { 503 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 504 ETHER_ADDR_LEN) != 0) 505 goto allmulti; 506 507 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 508 hashtbl[h >> 3] |= 1U << (h & 7); 509 ETHER_NEXT_MULTI(step, enm); 510 } 511 ifp->if_flags &= ~IFF_ALLMULTI; 512 rxmode |= AXE_RXCMD_MULTICAST; 513 514 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 515 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 516 axe_unlock_mii(sc); 517 return; 518 519 allmulti: 520 ifp->if_flags |= IFF_ALLMULTI; 521 rxmode |= AXE_RXCMD_ALLMULTI; 522 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 523 axe_unlock_mii(sc); 524 } 525 526 static void 527 axe_ax_init(struct axe_softc *sc) 528 { 529 if (sc->axe_flags & AX178) { 530 axe_ax88178_init(sc); 531 } else if (sc->axe_flags & AX772) { 532 axe_ax88772_init(sc); 533 } else if (sc->axe_flags & AX772A) { 534 axe_ax88772a_init(sc); 535 } else if (sc->axe_flags & AX772B) { 536 axe_ax88772b_init(sc); 537 } 538 } 539 540 541 static void 542 axe_reset(struct axe_softc *sc) 543 { 544 545 if (sc->axe_dying) 546 return; 547 548 /* 549 * softnet_lock can be taken when NET_MPAFE is not defined when calling 550 * if_addr_init -> if_init. This doesn't mixe well with the 551 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 552 * can fire during the wait and attempt to take softnet_lock and then 553 * block the softclk thread meaing the wait never ends. 554 */ 555 #ifndef NET_MPSAFE 556 /* XXX What to reset? */ 557 558 /* Wait a little while for the chip to get its brains in order. */ 559 DELAY(1000); 560 #else 561 axe_lock_mii(sc); 562 563 axe_ax_init(sc); 564 565 axe_unlock_mii(sc); 566 #endif 567 } 568 569 static int 570 axe_get_phyno(struct axe_softc *sc, int sel) 571 { 572 int phyno; 573 574 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 575 case PHY_TYPE_100_HOME: 576 /* FALLTHROUGH */ 577 case PHY_TYPE_GIG: 578 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 579 break; 580 case PHY_TYPE_SPECIAL: 581 /* FALLTHROUGH */ 582 case PHY_TYPE_RSVD: 583 /* FALLTHROUGH */ 584 case PHY_TYPE_NON_SUP: 585 /* FALLTHROUGH */ 586 default: 587 phyno = -1; 588 break; 589 } 590 591 return phyno; 592 } 593 594 #define AXE_GPIO_WRITE(x, y) do { \ 595 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 596 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 597 } while (0) 598 599 static void 600 axe_ax88178_init(struct axe_softc *sc) 601 { 602 AXEHIST_FUNC(); AXEHIST_CALLED(); 603 int gpio0, ledmode, phymode; 604 uint16_t eeprom, val; 605 606 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 607 /* XXX magic */ 608 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 609 eeprom = 0xffff; 610 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 611 612 eeprom = le16toh(eeprom); 613 614 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 615 616 /* if EEPROM is invalid we have to use to GPIO0 */ 617 if (eeprom == 0xffff) { 618 phymode = AXE_PHY_MODE_MARVELL; 619 gpio0 = 1; 620 ledmode = 0; 621 } else { 622 phymode = eeprom & 0x7f; 623 gpio0 = (eeprom & 0x80) ? 0 : 1; 624 ledmode = eeprom >> 8; 625 } 626 627 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 628 629 /* Program GPIOs depending on PHY hardware. */ 630 switch (phymode) { 631 case AXE_PHY_MODE_MARVELL: 632 if (gpio0 == 1) { 633 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 634 hz / 32); 635 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 636 hz / 32); 637 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 638 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 639 hz / 32); 640 } else { 641 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 642 AXE_GPIO1_EN, hz / 3); 643 if (ledmode == 1) { 644 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 645 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 646 hz / 3); 647 } else { 648 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 649 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 650 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 651 AXE_GPIO2_EN, hz / 4); 652 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 653 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 654 } 655 } 656 break; 657 case AXE_PHY_MODE_CICADA: 658 case AXE_PHY_MODE_CICADA_V2: 659 case AXE_PHY_MODE_CICADA_V2_ASIX: 660 if (gpio0 == 1) 661 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 662 AXE_GPIO0_EN, hz / 32); 663 else 664 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 665 AXE_GPIO1_EN, hz / 32); 666 break; 667 case AXE_PHY_MODE_AGERE: 668 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 669 AXE_GPIO1_EN, hz / 32); 670 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 671 AXE_GPIO2_EN, hz / 32); 672 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 673 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 674 AXE_GPIO2_EN, hz / 32); 675 break; 676 case AXE_PHY_MODE_REALTEK_8211CL: 677 case AXE_PHY_MODE_REALTEK_8211BN: 678 case AXE_PHY_MODE_REALTEK_8251CL: 679 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 680 AXE_GPIO1 | AXE_GPIO1_EN; 681 AXE_GPIO_WRITE(val, hz / 32); 682 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 683 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 684 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 685 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 686 axe_miibus_writereg_locked(sc->axe_dev, 687 sc->axe_phyno, 0x1F, 0x0005); 688 axe_miibus_writereg_locked(sc->axe_dev, 689 sc->axe_phyno, 0x0C, 0x0000); 690 val = axe_miibus_readreg_locked(sc->axe_dev, 691 sc->axe_phyno, 0x0001); 692 axe_miibus_writereg_locked(sc->axe_dev, 693 sc->axe_phyno, 0x01, val | 0x0080); 694 axe_miibus_writereg_locked(sc->axe_dev, 695 sc->axe_phyno, 0x1F, 0x0000); 696 } 697 break; 698 default: 699 /* Unknown PHY model or no need to program GPIOs. */ 700 break; 701 } 702 703 /* soft reset */ 704 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 705 usbd_delay_ms(sc->axe_udev, 150); 706 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 707 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 708 usbd_delay_ms(sc->axe_udev, 150); 709 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 710 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 711 usbd_delay_ms(sc->axe_udev, 10); 712 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 713 } 714 715 static void 716 axe_ax88772_init(struct axe_softc *sc) 717 { 718 AXEHIST_FUNC(); AXEHIST_CALLED(); 719 720 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 721 usbd_delay_ms(sc->axe_udev, 40); 722 723 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 724 /* ask for the embedded PHY */ 725 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 726 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 727 usbd_delay_ms(sc->axe_udev, 10); 728 729 /* power down and reset state, pin reset state */ 730 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 731 usbd_delay_ms(sc->axe_udev, 60); 732 733 /* power down/reset state, pin operating state */ 734 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 735 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 736 usbd_delay_ms(sc->axe_udev, 150); 737 738 /* power up, reset */ 739 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 740 741 /* power up, operating */ 742 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 743 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 744 } else { 745 /* ask for external PHY */ 746 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 747 NULL); 748 usbd_delay_ms(sc->axe_udev, 10); 749 750 /* power down internal PHY */ 751 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 752 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 753 } 754 755 usbd_delay_ms(sc->axe_udev, 150); 756 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 757 } 758 759 static void 760 axe_ax88772_phywake(struct axe_softc *sc) 761 { 762 AXEHIST_FUNC(); AXEHIST_CALLED(); 763 764 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 765 /* Manually select internal(embedded) PHY - MAC mode. */ 766 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 767 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 768 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 769 } else { 770 /* 771 * Manually select external PHY - MAC mode. 772 * Reverse MII/RMII is for AX88772A PHY mode. 773 */ 774 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 775 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 776 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 777 } 778 779 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 780 AXE_SW_RESET_IPRL, NULL); 781 782 /* T1 = min 500ns everywhere */ 783 usbd_delay_ms(sc->axe_udev, 150); 784 785 /* Take PHY out of power down. */ 786 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 787 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 788 } else { 789 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 790 } 791 792 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 793 usbd_delay_ms(sc->axe_udev, 600); 794 795 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 796 797 /* T3 = 500ns everywhere */ 798 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 799 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 800 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 801 } 802 803 static void 804 axe_ax88772a_init(struct axe_softc *sc) 805 { 806 AXEHIST_FUNC(); AXEHIST_CALLED(); 807 808 /* Reload EEPROM. */ 809 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 810 axe_ax88772_phywake(sc); 811 /* Stop MAC. */ 812 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 813 } 814 815 static void 816 axe_ax88772b_init(struct axe_softc *sc) 817 { 818 AXEHIST_FUNC(); AXEHIST_CALLED(); 819 uint16_t eeprom; 820 int i; 821 822 /* Reload EEPROM. */ 823 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 824 825 /* 826 * Save PHY power saving configuration(high byte) and 827 * clear EEPROM checksum value(low byte). 828 */ 829 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 830 &eeprom)) { 831 aprint_error_dev(sc->axe_dev, "failed to read eeprom\n"); 832 return; 833 } 834 835 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 836 837 /* 838 * Auto-loaded default station address from internal ROM is 839 * 00:00:00:00:00:00 such that an explicit access to EEPROM 840 * is required to get real station address. 841 */ 842 uint8_t *eaddr = sc->axe_enaddr; 843 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 844 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 845 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 846 aprint_error_dev(sc->axe_dev, 847 "failed to read eeprom\n"); 848 eeprom = 0; 849 } 850 eeprom = le16toh(eeprom); 851 *eaddr++ = (uint8_t)(eeprom & 0xFF); 852 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 853 } 854 /* Wakeup PHY. */ 855 axe_ax88772_phywake(sc); 856 /* Stop MAC. */ 857 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 858 } 859 860 #undef AXE_GPIO_WRITE 861 862 /* 863 * Probe for a AX88172 chip. 864 */ 865 int 866 axe_match(device_t parent, cfdata_t match, void *aux) 867 { 868 struct usb_attach_arg *uaa = aux; 869 870 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 871 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 872 } 873 874 /* 875 * Attach the interface. Allocate softc structures, do ifmedia 876 * setup and ethernet/BPF attach. 877 */ 878 void 879 axe_attach(device_t parent, device_t self, void *aux) 880 { 881 AXEHIST_FUNC(); AXEHIST_CALLED(); 882 struct axe_softc *sc = device_private(self); 883 struct usb_attach_arg *uaa = aux; 884 struct usbd_device *dev = uaa->uaa_device; 885 usbd_status err; 886 usb_interface_descriptor_t *id; 887 usb_endpoint_descriptor_t *ed; 888 struct mii_data *mii; 889 char *devinfop; 890 const char *devname = device_xname(self); 891 struct ifnet *ifp; 892 int i, s; 893 894 aprint_naive("\n"); 895 aprint_normal("\n"); 896 897 sc->axe_dev = self; 898 sc->axe_udev = dev; 899 900 devinfop = usbd_devinfo_alloc(dev, 0); 901 aprint_normal_dev(self, "%s\n", devinfop); 902 usbd_devinfo_free(devinfop); 903 904 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 905 if (err) { 906 aprint_error_dev(self, "failed to set configuration" 907 ", err=%s\n", usbd_errstr(err)); 908 return; 909 } 910 911 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 912 913 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 914 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 915 916 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 917 if (err) { 918 aprint_error_dev(self, "getting interface handle failed\n"); 919 return; 920 } 921 922 sc->axe_product = uaa->uaa_product; 923 sc->axe_vendor = uaa->uaa_vendor; 924 925 id = usbd_get_interface_descriptor(sc->axe_iface); 926 927 /* decide on what our bufsize will be */ 928 if (AXE_IS_178_FAMILY(sc)) 929 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 930 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 931 else 932 sc->axe_bufsz = AXE_172_BUFSZ; 933 934 sc->axe_ed[AXE_ENDPT_RX] = -1; 935 sc->axe_ed[AXE_ENDPT_TX] = -1; 936 sc->axe_ed[AXE_ENDPT_INTR] = -1; 937 938 /* Find endpoints. */ 939 for (i = 0; i < id->bNumEndpoints; i++) { 940 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 941 if (ed == NULL) { 942 aprint_error_dev(self, "couldn't get ep %d\n", i); 943 return; 944 } 945 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 946 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 947 948 if (dir == UE_DIR_IN && xt == UE_BULK && 949 sc->axe_ed[AXE_ENDPT_RX] == -1) { 950 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 951 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 952 sc->axe_ed[AXE_ENDPT_TX] == -1) { 953 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 954 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 955 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 956 } 957 } 958 959 s = splnet(); 960 961 /* We need the PHYID for init dance in some cases */ 962 axe_lock_mii(sc); 963 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 964 aprint_error_dev(self, "failed to read phyaddrs\n"); 965 return; 966 } 967 968 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 969 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 970 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 971 if (sc->axe_phyno == -1) 972 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 973 if (sc->axe_phyno == -1) { 974 DPRINTF(" no valid PHY address found, assuming PHY address 0", 975 0, 0, 0, 0); 976 sc->axe_phyno = 0; 977 } 978 979 /* Initialize controller and get station address. */ 980 981 axe_ax_init(sc); 982 983 if ((sc->axe_flags & AX772B) != 0) { 984 if (axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, sc->axe_enaddr)) 985 { 986 aprint_error_dev(self, 987 "failed to read ethernet address\n"); 988 } 989 } 990 991 /* 992 * Fetch IPG values. 993 */ 994 if (sc->axe_flags & (AX772A | AX772B)) { 995 /* Set IPG values. */ 996 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 997 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 998 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 999 } else { 1000 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 1001 aprint_error_dev(self, "failed to read ipg\n"); 1002 return; 1003 } 1004 } 1005 1006 axe_unlock_mii(sc); 1007 1008 /* 1009 * An ASIX chip was detected. Inform the world. 1010 */ 1011 aprint_normal_dev(self, "Ethernet address %s\n", 1012 ether_sprintf(sc->axe_enaddr)); 1013 1014 /* Initialize interface info.*/ 1015 ifp = &sc->sc_if; 1016 ifp->if_softc = sc; 1017 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 1018 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1019 ifp->if_ioctl = axe_ioctl; 1020 ifp->if_start = axe_start; 1021 ifp->if_init = axe_init; 1022 ifp->if_stop = axe_stop; 1023 ifp->if_watchdog = axe_watchdog; 1024 1025 IFQ_SET_READY(&ifp->if_snd); 1026 1027 if (AXE_IS_178_FAMILY(sc)) 1028 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1029 if (sc->axe_flags & AX772B) { 1030 ifp->if_capabilities = 1031 IFCAP_CSUM_IPv4_Rx | 1032 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1033 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1034 /* 1035 * Checksum offloading of AX88772B also works with VLAN 1036 * tagged frames but there is no way to take advantage 1037 * of the feature because vlan(4) assumes 1038 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1039 * support checksum offloading with VLAN. VLAN hardware 1040 * tagging support of AX88772B is very limited so it's 1041 * not possible to announce IFCAP_VLAN_HWTAGGING. 1042 */ 1043 } 1044 u_int adv_pause; 1045 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1046 adv_pause = MIIF_DOPAUSE; 1047 else 1048 adv_pause = 0; 1049 adv_pause = 0; 1050 1051 /* Initialize MII/media info. */ 1052 mii = &sc->axe_mii; 1053 mii->mii_ifp = ifp; 1054 mii->mii_readreg = axe_miibus_readreg; 1055 mii->mii_writereg = axe_miibus_writereg; 1056 mii->mii_statchg = axe_miibus_statchg; 1057 mii->mii_flags = MIIF_AUTOTSLEEP; 1058 1059 sc->axe_ec.ec_mii = mii; 1060 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1061 1062 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1063 adv_pause); 1064 1065 if (LIST_EMPTY(&mii->mii_phys)) { 1066 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1067 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1068 } else 1069 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1070 1071 /* Attach the interface. */ 1072 if_attach(ifp); 1073 ether_ifattach(ifp, sc->axe_enaddr); 1074 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1075 RND_TYPE_NET, RND_FLAG_DEFAULT); 1076 1077 callout_init(&sc->axe_stat_ch, 0); 1078 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1079 1080 sc->axe_attached = true; 1081 splx(s); 1082 1083 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1084 1085 if (!pmf_device_register(self, NULL, NULL)) 1086 aprint_error_dev(self, "couldn't establish power handler\n"); 1087 } 1088 1089 int 1090 axe_detach(device_t self, int flags) 1091 { 1092 AXEHIST_FUNC(); AXEHIST_CALLED(); 1093 struct axe_softc *sc = device_private(self); 1094 int s; 1095 struct ifnet *ifp = &sc->sc_if; 1096 1097 /* Detached before attached finished, so just bail out. */ 1098 if (!sc->axe_attached) 1099 return 0; 1100 1101 pmf_device_deregister(self); 1102 1103 sc->axe_dying = true; 1104 1105 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1106 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1107 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1108 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1109 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1110 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1111 1112 /* 1113 * Remove any pending tasks. They cannot be executing because they run 1114 * in the same thread as detach. 1115 */ 1116 usb_rem_task(sc->axe_udev, &sc->axe_tick_task); 1117 1118 s = splusb(); 1119 1120 if (ifp->if_flags & IFF_RUNNING) 1121 axe_stop(ifp, 1); 1122 1123 1124 if (--sc->axe_refcnt >= 0) { 1125 /* Wait for processes to go away. */ 1126 usb_detach_waitold(sc->axe_dev); 1127 } 1128 1129 callout_destroy(&sc->axe_stat_ch); 1130 mutex_destroy(&sc->axe_mii_lock); 1131 rnd_detach_source(&sc->rnd_source); 1132 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1133 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1134 ether_ifdetach(ifp); 1135 if_detach(ifp); 1136 1137 #ifdef DIAGNOSTIC 1138 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1139 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1140 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1141 aprint_debug_dev(self, "detach has active endpoints\n"); 1142 #endif 1143 1144 sc->axe_attached = false; 1145 1146 splx(s); 1147 1148 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1149 1150 return 0; 1151 } 1152 1153 int 1154 axe_activate(device_t self, devact_t act) 1155 { 1156 AXEHIST_FUNC(); AXEHIST_CALLED(); 1157 struct axe_softc *sc = device_private(self); 1158 1159 switch (act) { 1160 case DVACT_DEACTIVATE: 1161 if_deactivate(&sc->axe_ec.ec_if); 1162 sc->axe_dying = true; 1163 return 0; 1164 default: 1165 return EOPNOTSUPP; 1166 } 1167 } 1168 1169 static int 1170 axe_rx_list_init(struct axe_softc *sc) 1171 { 1172 AXEHIST_FUNC(); AXEHIST_CALLED(); 1173 1174 struct axe_cdata *cd; 1175 struct axe_chain *c; 1176 int i; 1177 1178 cd = &sc->axe_cdata; 1179 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1180 c = &cd->axe_rx_chain[i]; 1181 c->axe_sc = sc; 1182 c->axe_idx = i; 1183 if (c->axe_xfer == NULL) { 1184 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1185 sc->axe_bufsz, 0, 0, &c->axe_xfer); 1186 if (err) 1187 return err; 1188 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1189 } 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int 1196 axe_tx_list_init(struct axe_softc *sc) 1197 { 1198 AXEHIST_FUNC(); AXEHIST_CALLED(); 1199 struct axe_cdata *cd; 1200 struct axe_chain *c; 1201 int i; 1202 1203 cd = &sc->axe_cdata; 1204 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1205 c = &cd->axe_tx_chain[i]; 1206 c->axe_sc = sc; 1207 c->axe_idx = i; 1208 if (c->axe_xfer == NULL) { 1209 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1210 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1211 &c->axe_xfer); 1212 if (err) 1213 return err; 1214 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1215 } 1216 } 1217 1218 return 0; 1219 } 1220 1221 /* 1222 * A frame has been uploaded: pass the resulting mbuf chain up to 1223 * the higher level protocols. 1224 */ 1225 static void 1226 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1227 { 1228 AXEHIST_FUNC(); AXEHIST_CALLED(); 1229 struct axe_softc *sc; 1230 struct axe_chain *c; 1231 struct ifnet *ifp; 1232 uint8_t *buf; 1233 uint32_t total_len; 1234 struct mbuf *m; 1235 int s; 1236 1237 c = (struct axe_chain *)priv; 1238 sc = c->axe_sc; 1239 buf = c->axe_buf; 1240 ifp = &sc->sc_if; 1241 1242 if (sc->axe_dying) 1243 return; 1244 1245 if ((ifp->if_flags & IFF_RUNNING) == 0) 1246 return; 1247 1248 if (status != USBD_NORMAL_COMPLETION) { 1249 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1250 return; 1251 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1252 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1253 usbd_errstr(status)); 1254 } 1255 if (status == USBD_STALLED) 1256 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1257 goto done; 1258 } 1259 1260 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1261 1262 do { 1263 u_int pktlen = 0; 1264 u_int rxlen = 0; 1265 int flags = 0; 1266 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1267 struct axe_sframe_hdr hdr; 1268 1269 if (total_len < sizeof(hdr)) { 1270 ifp->if_ierrors++; 1271 goto done; 1272 } 1273 1274 memcpy(&hdr, buf, sizeof(hdr)); 1275 1276 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1277 total_len, 1278 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1279 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1280 1281 total_len -= sizeof(hdr); 1282 buf += sizeof(hdr); 1283 1284 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1285 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1286 AXE_RH1M_RXLEN_MASK) { 1287 ifp->if_ierrors++; 1288 goto done; 1289 } 1290 1291 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1292 if (total_len < rxlen) { 1293 pktlen = total_len; 1294 total_len = 0; 1295 } else { 1296 pktlen = rxlen; 1297 rxlen = roundup2(rxlen, 2); 1298 total_len -= rxlen; 1299 } 1300 1301 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1302 struct axe_csum_hdr csum_hdr; 1303 1304 if (total_len < sizeof(csum_hdr)) { 1305 ifp->if_ierrors++; 1306 goto done; 1307 } 1308 1309 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1310 1311 csum_hdr.len = le16toh(csum_hdr.len); 1312 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1313 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1314 1315 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1316 " cstatus %#jx", total_len, 1317 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1318 1319 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1320 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1321 sc->sc_lenmask) { 1322 /* we lost sync */ 1323 ifp->if_ierrors++; 1324 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1325 "err", 1326 AXE_CSUM_RXBYTES(csum_hdr.len), 1327 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1328 sc->sc_lenmask, 0); 1329 goto done; 1330 } 1331 /* 1332 * Get total transferred frame length including 1333 * checksum header. The length should be multiple 1334 * of 4. 1335 */ 1336 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1337 u_int len = sizeof(csum_hdr) + pktlen; 1338 len = (len + 3) & ~3; 1339 if (total_len < len) { 1340 DPRINTFN(20, "total_len %#jx < len %#jx", 1341 total_len, len, 0, 0); 1342 /* invalid length */ 1343 ifp->if_ierrors++; 1344 goto done; 1345 } 1346 buf += sizeof(csum_hdr); 1347 1348 const uint16_t cstatus = csum_hdr.cstatus; 1349 1350 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1351 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1352 flags |= M_CSUM_TCP_UDP_BAD; 1353 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1354 flags |= M_CSUM_IPv4_BAD; 1355 1356 const uint16_t l4type = 1357 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1358 1359 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1360 flags |= M_CSUM_TCPv4; 1361 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1362 flags |= M_CSUM_UDPv4; 1363 } 1364 if (total_len < len) { 1365 pktlen = total_len; 1366 total_len = 0; 1367 } else { 1368 total_len -= len; 1369 rxlen = len - sizeof(csum_hdr); 1370 } 1371 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1372 " rxlen %#jx", total_len, len, pktlen, rxlen); 1373 } else { /* AX172 */ 1374 pktlen = rxlen = total_len; 1375 total_len = 0; 1376 } 1377 1378 MGETHDR(m, M_DONTWAIT, MT_DATA); 1379 if (m == NULL) { 1380 ifp->if_ierrors++; 1381 goto done; 1382 } 1383 1384 if (pktlen > MHLEN - ETHER_ALIGN) { 1385 MCLGET(m, M_DONTWAIT); 1386 if ((m->m_flags & M_EXT) == 0) { 1387 m_freem(m); 1388 ifp->if_ierrors++; 1389 goto done; 1390 } 1391 } 1392 m->m_data += ETHER_ALIGN; 1393 1394 m_set_rcvif(m, ifp); 1395 m->m_pkthdr.len = m->m_len = pktlen; 1396 m->m_pkthdr.csum_flags = flags; 1397 1398 memcpy(mtod(m, uint8_t *), buf, pktlen); 1399 buf += rxlen; 1400 1401 DPRINTFN(10, "deliver %jd (%#jx)", m->m_len, m->m_len, 0, 0); 1402 1403 s = splnet(); 1404 1405 if_percpuq_enqueue((ifp)->if_percpuq, (m)); 1406 1407 splx(s); 1408 1409 } while (total_len > 0); 1410 1411 done: 1412 1413 /* Setup new transfer. */ 1414 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1415 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1416 usbd_transfer(xfer); 1417 1418 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1419 } 1420 1421 /* 1422 * A frame was downloaded to the chip. It's safe for us to clean up 1423 * the list buffers. 1424 */ 1425 1426 static void 1427 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1428 { 1429 AXEHIST_FUNC(); AXEHIST_CALLED(); 1430 struct axe_chain *c = priv; 1431 struct axe_softc *sc = c->axe_sc; 1432 struct ifnet *ifp = &sc->sc_if; 1433 int s; 1434 1435 1436 if (sc->axe_dying) 1437 return; 1438 1439 s = splnet(); 1440 1441 ifp->if_timer = 0; 1442 ifp->if_flags &= ~IFF_OACTIVE; 1443 1444 if (status != USBD_NORMAL_COMPLETION) { 1445 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1446 splx(s); 1447 return; 1448 } 1449 ifp->if_oerrors++; 1450 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1451 usbd_errstr(status)); 1452 if (status == USBD_STALLED) 1453 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1454 splx(s); 1455 return; 1456 } 1457 ifp->if_opackets++; 1458 1459 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1460 axe_start(ifp); 1461 1462 splx(s); 1463 } 1464 1465 static void 1466 axe_tick(void *xsc) 1467 { 1468 AXEHIST_FUNC(); AXEHIST_CALLED(); 1469 struct axe_softc *sc = xsc; 1470 1471 if (sc == NULL) 1472 return; 1473 1474 if (sc->axe_dying) 1475 return; 1476 1477 /* Perform periodic stuff in process context */ 1478 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1479 } 1480 1481 static void 1482 axe_tick_task(void *xsc) 1483 { 1484 AXEHIST_FUNC(); AXEHIST_CALLED(); 1485 int s; 1486 struct axe_softc *sc = xsc; 1487 struct ifnet *ifp; 1488 struct mii_data *mii; 1489 1490 if (sc == NULL) 1491 return; 1492 1493 if (sc->axe_dying) 1494 return; 1495 1496 ifp = &sc->sc_if; 1497 mii = &sc->axe_mii; 1498 1499 if (mii == NULL) 1500 return; 1501 1502 s = splnet(); 1503 1504 mii_tick(mii); 1505 if (sc->axe_link == 0 && 1506 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1507 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1508 DPRINTF("got link", 0, 0, 0, 0); 1509 sc->axe_link++; 1510 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1511 axe_start(ifp); 1512 } 1513 1514 callout_schedule(&sc->axe_stat_ch, hz); 1515 1516 splx(s); 1517 } 1518 1519 static int 1520 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1521 { 1522 struct ifnet *ifp = &sc->sc_if; 1523 struct axe_chain *c; 1524 usbd_status err; 1525 int length, boundary; 1526 1527 c = &sc->axe_cdata.axe_tx_chain[idx]; 1528 1529 /* 1530 * Copy the mbuf data into a contiguous buffer, leaving two 1531 * bytes at the beginning to hold the frame length. 1532 */ 1533 if (AXE_IS_178_FAMILY(sc)) { 1534 struct axe_sframe_hdr hdr; 1535 1536 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1537 1538 hdr.len = htole16(m->m_pkthdr.len); 1539 hdr.ilen = ~hdr.len; 1540 1541 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1542 length = sizeof(hdr); 1543 1544 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1545 length += m->m_pkthdr.len; 1546 1547 if ((length % boundary) == 0) { 1548 hdr.len = 0x0000; 1549 hdr.ilen = 0xffff; 1550 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1551 length += sizeof(hdr); 1552 } 1553 } else { 1554 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1555 length = m->m_pkthdr.len; 1556 } 1557 1558 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1559 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1560 1561 /* Transmit */ 1562 err = usbd_transfer(c->axe_xfer); 1563 if (err != USBD_IN_PROGRESS) { 1564 axe_stop(ifp, 0); 1565 return EIO; 1566 } 1567 1568 sc->axe_cdata.axe_tx_cnt++; 1569 1570 return 0; 1571 } 1572 1573 1574 static void 1575 axe_csum_cfg(struct axe_softc *sc) 1576 { 1577 struct ifnet *ifp = &sc->sc_if; 1578 uint16_t csum1, csum2; 1579 1580 if ((sc->axe_flags & AX772B) != 0) { 1581 csum1 = 0; 1582 csum2 = 0; 1583 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1584 csum1 |= AXE_TXCSUM_IP; 1585 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1586 csum1 |= AXE_TXCSUM_TCP; 1587 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1588 csum1 |= AXE_TXCSUM_UDP; 1589 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1590 csum1 |= AXE_TXCSUM_TCPV6; 1591 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1592 csum1 |= AXE_TXCSUM_UDPV6; 1593 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1594 csum1 = 0; 1595 csum2 = 0; 1596 1597 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1598 csum1 |= AXE_RXCSUM_IP; 1599 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1600 csum1 |= AXE_RXCSUM_TCP; 1601 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1602 csum1 |= AXE_RXCSUM_UDP; 1603 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1604 csum1 |= AXE_RXCSUM_TCPV6; 1605 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1606 csum1 |= AXE_RXCSUM_UDPV6; 1607 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1608 } 1609 } 1610 1611 static void 1612 axe_start(struct ifnet *ifp) 1613 { 1614 struct axe_softc *sc; 1615 struct mbuf *m; 1616 1617 sc = ifp->if_softc; 1618 1619 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) 1620 return; 1621 1622 IFQ_POLL(&ifp->if_snd, m); 1623 if (m == NULL) { 1624 return; 1625 } 1626 1627 if (axe_encap(sc, m, 0)) { 1628 ifp->if_flags |= IFF_OACTIVE; 1629 return; 1630 } 1631 IFQ_DEQUEUE(&ifp->if_snd, m); 1632 1633 /* 1634 * If there's a BPF listener, bounce a copy of this frame 1635 * to him. 1636 */ 1637 bpf_mtap(ifp, m); 1638 m_freem(m); 1639 1640 ifp->if_flags |= IFF_OACTIVE; 1641 1642 /* 1643 * Set a timeout in case the chip goes out to lunch. 1644 */ 1645 ifp->if_timer = 5; 1646 1647 return; 1648 } 1649 1650 static int 1651 axe_init(struct ifnet *ifp) 1652 { 1653 AXEHIST_FUNC(); AXEHIST_CALLED(); 1654 struct axe_softc *sc = ifp->if_softc; 1655 struct axe_chain *c; 1656 usbd_status err; 1657 int rxmode; 1658 int i, s; 1659 1660 s = splnet(); 1661 1662 if (ifp->if_flags & IFF_RUNNING) 1663 axe_stop(ifp, 0); 1664 1665 /* 1666 * Cancel pending I/O and free all RX/TX buffers. 1667 */ 1668 axe_reset(sc); 1669 1670 axe_lock_mii(sc); 1671 1672 #if 0 1673 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1674 AX_GPIO_GPO2EN, 5, in_pm); 1675 #endif 1676 /* Set MAC address and transmitter IPG values. */ 1677 if (AXE_IS_178_FAMILY(sc)) { 1678 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1679 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1680 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1681 } else { 1682 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1683 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1684 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1685 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1686 } 1687 if (AXE_IS_178_FAMILY(sc)) { 1688 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1689 if ((sc->axe_flags & AX772B) != 0 && 1690 (ifp->if_capenable & AX_RXCSUM) != 0) { 1691 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1692 sc->axe_flags |= AXCSUM_FRAME; 1693 } else { 1694 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1695 sc->axe_flags |= AXSTD_FRAME; 1696 } 1697 } 1698 1699 /* Configure TX/RX checksum offloading. */ 1700 axe_csum_cfg(sc); 1701 1702 if (sc->axe_flags & AX772B) { 1703 /* AX88772B uses different maximum frame burst configuration. */ 1704 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1705 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1706 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1707 } 1708 /* Enable receiver, set RX mode */ 1709 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1710 if (AXE_IS_178_FAMILY(sc)) { 1711 if (sc->axe_flags & AX772B) { 1712 /* 1713 * Select RX header format type 1. Aligning IP 1714 * header on 4 byte boundary is not needed when 1715 * checksum offloading feature is not used 1716 * because we always copy the received frame in 1717 * RX handler. When RX checksum offloading is 1718 * active, aligning IP header is required to 1719 * reflect actual frame length including RX 1720 * header size. 1721 */ 1722 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1723 if (sc->axe_flags & AXCSUM_FRAME) 1724 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1725 } else { 1726 /* 1727 * Default Rx buffer size is too small to get 1728 * maximum performance. 1729 */ 1730 #if 0 1731 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1732 /* Largest possible USB buffer size for AX88178 */ 1733 #endif 1734 rxmode |= AXE_178_RXCMD_MFB_16384; 1735 } 1736 } else { 1737 rxmode |= AXE_172_RXCMD_UNICAST; 1738 } 1739 1740 1741 /* If we want promiscuous mode, set the allframes bit. */ 1742 if (ifp->if_flags & IFF_PROMISC) 1743 rxmode |= AXE_RXCMD_PROMISC; 1744 1745 if (ifp->if_flags & IFF_BROADCAST) 1746 rxmode |= AXE_RXCMD_BROADCAST; 1747 1748 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1749 1750 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1751 axe_unlock_mii(sc); 1752 1753 /* Load the multicast filter. */ 1754 axe_setmulti(sc); 1755 1756 /* Open RX and TX pipes. */ 1757 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1758 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1759 if (err) { 1760 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1761 usbd_errstr(err)); 1762 splx(s); 1763 return EIO; 1764 } 1765 1766 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1767 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1768 if (err) { 1769 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1770 usbd_errstr(err)); 1771 splx(s); 1772 return EIO; 1773 } 1774 1775 /* Init RX ring. */ 1776 if (axe_rx_list_init(sc) != 0) { 1777 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1778 splx(s); 1779 return ENOBUFS; 1780 } 1781 1782 /* Init TX ring. */ 1783 if (axe_tx_list_init(sc) != 0) { 1784 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1785 splx(s); 1786 return ENOBUFS; 1787 } 1788 1789 /* Start up the receive pipe. */ 1790 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1791 c = &sc->axe_cdata.axe_rx_chain[i]; 1792 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1793 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1794 usbd_transfer(c->axe_xfer); 1795 } 1796 1797 ifp->if_flags |= IFF_RUNNING; 1798 ifp->if_flags &= ~IFF_OACTIVE; 1799 1800 splx(s); 1801 1802 callout_schedule(&sc->axe_stat_ch, hz); 1803 return 0; 1804 } 1805 1806 static int 1807 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1808 { 1809 struct axe_softc *sc = ifp->if_softc; 1810 int s; 1811 int error = 0; 1812 1813 s = splnet(); 1814 1815 switch(cmd) { 1816 case SIOCSIFFLAGS: 1817 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1818 break; 1819 1820 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1821 case IFF_RUNNING: 1822 axe_stop(ifp, 1); 1823 break; 1824 case IFF_UP: 1825 axe_init(ifp); 1826 break; 1827 case IFF_UP | IFF_RUNNING: 1828 if ((ifp->if_flags ^ sc->axe_if_flags) == IFF_PROMISC) 1829 axe_setmulti(sc); 1830 else 1831 axe_init(ifp); 1832 break; 1833 } 1834 sc->axe_if_flags = ifp->if_flags; 1835 break; 1836 1837 default: 1838 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1839 break; 1840 1841 error = 0; 1842 1843 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) 1844 axe_setmulti(sc); 1845 1846 } 1847 splx(s); 1848 1849 return error; 1850 } 1851 1852 static void 1853 axe_watchdog(struct ifnet *ifp) 1854 { 1855 struct axe_softc *sc; 1856 struct axe_chain *c; 1857 usbd_status stat; 1858 int s; 1859 1860 sc = ifp->if_softc; 1861 1862 ifp->if_oerrors++; 1863 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1864 1865 s = splusb(); 1866 c = &sc->axe_cdata.axe_tx_chain[0]; 1867 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1868 axe_txeof(c->axe_xfer, c, stat); 1869 1870 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1871 axe_start(ifp); 1872 splx(s); 1873 } 1874 1875 /* 1876 * Stop the adapter and free any mbufs allocated to the 1877 * RX and TX lists. 1878 */ 1879 static void 1880 axe_stop(struct ifnet *ifp, int disable) 1881 { 1882 struct axe_softc *sc = ifp->if_softc; 1883 usbd_status err; 1884 int i; 1885 1886 ifp->if_timer = 0; 1887 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1888 1889 callout_stop(&sc->axe_stat_ch); 1890 1891 /* Stop transfers. */ 1892 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1893 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1894 if (err) { 1895 aprint_error_dev(sc->axe_dev, 1896 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1897 } 1898 } 1899 1900 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1901 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1902 if (err) { 1903 aprint_error_dev(sc->axe_dev, 1904 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1905 } 1906 } 1907 1908 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1909 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1910 if (err) { 1911 aprint_error_dev(sc->axe_dev, 1912 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1913 } 1914 } 1915 1916 axe_reset(sc); 1917 1918 /* Free RX resources. */ 1919 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1920 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1921 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1922 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1923 } 1924 } 1925 1926 /* Free TX resources. */ 1927 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1928 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1929 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1930 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1931 } 1932 } 1933 1934 /* Close pipes. */ 1935 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1936 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1937 if (err) { 1938 aprint_error_dev(sc->axe_dev, 1939 "close rx pipe failed: %s\n", usbd_errstr(err)); 1940 } 1941 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1942 } 1943 1944 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1945 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1946 if (err) { 1947 aprint_error_dev(sc->axe_dev, 1948 "close tx pipe failed: %s\n", usbd_errstr(err)); 1949 } 1950 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1951 } 1952 1953 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1954 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1955 if (err) { 1956 aprint_error_dev(sc->axe_dev, 1957 "close intr pipe failed: %s\n", usbd_errstr(err)); 1958 } 1959 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1960 } 1961 1962 sc->axe_link = 0; 1963 } 1964 1965 MODULE(MODULE_CLASS_DRIVER, if_axe, "bpf"); 1966 1967 #ifdef _MODULE 1968 #include "ioconf.c" 1969 #endif 1970 1971 static int 1972 if_axe_modcmd(modcmd_t cmd, void *aux) 1973 { 1974 int error = 0; 1975 1976 switch (cmd) { 1977 case MODULE_CMD_INIT: 1978 #ifdef _MODULE 1979 error = config_init_component(cfdriver_ioconf_axe, 1980 cfattach_ioconf_axe, cfdata_ioconf_axe); 1981 #endif 1982 return error; 1983 case MODULE_CMD_FINI: 1984 #ifdef _MODULE 1985 error = config_fini_component(cfdriver_ioconf_axe, 1986 cfattach_ioconf_axe, cfdata_ioconf_axe); 1987 #endif 1988 return error; 1989 default: 1990 return ENOTTY; 1991 } 1992 } 1993
Indexes created Tue Sep 23 14:10:03 GMT 2025