if_axe.c revision 1.90
1 /* $NetBSD: if_axe.c,v 1.90 2018/06/26 06:48:02 msaitoh Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.90 2018/06/26 06:48:02 msaitoh Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 /* 131 * AXE_178_MAX_FRAME_BURST 132 * max frame burst size for Ax88178 and Ax88772 133 * 0 2048 bytes 134 * 1 4096 bytes 135 * 2 8192 bytes 136 * 3 16384 bytes 137 * use the largest your system can handle without USB stalling. 138 * 139 * NB: 88772 parts appear to generate lots of input errors with 140 * a 2K rx buffer and 8K is only slightly faster than 4K on an 141 * EHCI port on a T42 so change at your own risk. 142 */ 143 #define AXE_178_MAX_FRAME_BURST 1 144 145 146 #ifdef USB_DEBUG 147 #ifndef AXE_DEBUG 148 #define axedebug 0 149 #else 150 static int axedebug = 20; 151 152 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 153 { 154 int err; 155 const struct sysctlnode *rnode; 156 const struct sysctlnode *cnode; 157 158 err = sysctl_createv(clog, 0, NULL, &rnode, 159 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 160 SYSCTL_DESCR("axe global controls"), 161 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 162 163 if (err) 164 goto fail; 165 166 /* control debugging printfs */ 167 err = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 169 "debug", SYSCTL_DESCR("Enable debugging output"), 170 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 171 if (err) 172 goto fail; 173 174 return; 175 fail: 176 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 177 } 178 179 #endif /* AXE_DEBUG */ 180 #endif /* USB_DEBUG */ 181 182 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 183 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 184 #define AXEHIST_FUNC() USBHIST_FUNC() 185 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 186 187 /* 188 * Various supported device vendors/products. 189 */ 190 static const struct axe_type axe_devs[] = { 191 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 192 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 193 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 199 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 200 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 201 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 202 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 203 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 204 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 206 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 208 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 209 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 210 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 211 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 212 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 213 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 214 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 215 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 216 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 218 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 219 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 220 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 221 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 222 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 223 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 225 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 226 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 227 }; 228 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 229 230 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 231 { 0x8000, 0x8001, 2048 }, 232 { 0x8100, 0x8147, 4096 }, 233 { 0x8200, 0x81EB, 6144 }, 234 { 0x8300, 0x83D7, 8192 }, 235 { 0x8400, 0x851E, 16384 }, 236 { 0x8500, 0x8666, 20480 }, 237 { 0x8600, 0x87AE, 24576 }, 238 { 0x8700, 0x8A3D, 32768 } 239 }; 240 241 int axe_match(device_t, cfdata_t, void *); 242 void axe_attach(device_t, device_t, void *); 243 int axe_detach(device_t, int); 244 int axe_activate(device_t, devact_t); 245 246 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 247 axe_match, axe_attach, axe_detach, axe_activate); 248 249 static int axe_tx_list_init(struct axe_softc *); 250 static int axe_rx_list_init(struct axe_softc *); 251 static int axe_encap(struct axe_softc *, struct mbuf *, int); 252 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 253 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 254 static void axe_tick(void *); 255 static void axe_tick_task(void *); 256 static void axe_start(struct ifnet *); 257 static int axe_ioctl(struct ifnet *, u_long, void *); 258 static int axe_init(struct ifnet *); 259 static void axe_stop(struct ifnet *, int); 260 static void axe_watchdog(struct ifnet *); 261 static int axe_miibus_readreg_locked(device_t, int, int); 262 static int axe_miibus_readreg(device_t, int, int); 263 static void axe_miibus_writereg_locked(device_t, int, int, int); 264 static void axe_miibus_writereg(device_t, int, int, int); 265 static void axe_miibus_statchg(struct ifnet *); 266 static int axe_cmd(struct axe_softc *, int, int, int, void *); 267 static void axe_reset(struct axe_softc *); 268 269 static void axe_setmulti(struct axe_softc *); 270 static void axe_lock_mii(struct axe_softc *); 271 static void axe_unlock_mii(struct axe_softc *); 272 273 static void axe_ax88178_init(struct axe_softc *); 274 static void axe_ax88772_init(struct axe_softc *); 275 static void axe_ax88772a_init(struct axe_softc *); 276 static void axe_ax88772b_init(struct axe_softc *); 277 278 /* Get exclusive access to the MII registers */ 279 static void 280 axe_lock_mii(struct axe_softc *sc) 281 { 282 283 sc->axe_refcnt++; 284 mutex_enter(&sc->axe_mii_lock); 285 } 286 287 static void 288 axe_unlock_mii(struct axe_softc *sc) 289 { 290 291 mutex_exit(&sc->axe_mii_lock); 292 if (--sc->axe_refcnt < 0) 293 usb_detach_wakeupold((sc->axe_dev)); 294 } 295 296 static int 297 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 298 { 299 AXEHIST_FUNC(); AXEHIST_CALLED(); 300 usb_device_request_t req; 301 usbd_status err; 302 303 KASSERT(mutex_owned(&sc->axe_mii_lock)); 304 305 if (sc->axe_dying) 306 return -1; 307 308 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 309 310 if (AXE_CMD_DIR(cmd)) 311 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 312 else 313 req.bmRequestType = UT_READ_VENDOR_DEVICE; 314 req.bRequest = AXE_CMD_CMD(cmd); 315 USETW(req.wValue, val); 316 USETW(req.wIndex, index); 317 USETW(req.wLength, AXE_CMD_LEN(cmd)); 318 319 err = usbd_do_request(sc->axe_udev, &req, buf); 320 321 if (err) { 322 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 323 return -1; 324 } 325 return 0; 326 } 327 328 static int 329 axe_miibus_readreg_locked(device_t dev, int phy, int reg) 330 { 331 AXEHIST_FUNC(); AXEHIST_CALLED(); 332 struct axe_softc *sc = device_private(dev); 333 usbd_status err; 334 uint16_t val; 335 336 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 337 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 339 340 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 341 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 342 if (err) { 343 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 344 return -1; 345 } 346 347 val = le16toh(val); 348 if (AXE_IS_772(sc) && reg == MII_BMSR) { 349 /* 350 * BMSR of AX88772 indicates that it supports extended 351 * capability but the extended status register is 352 * reserved for embedded ethernet PHY. So clear the 353 * extended capability bit of BMSR. 354 */ 355 val &= ~BMSR_EXTCAP; 356 } 357 358 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, val, 0); 359 360 return val; 361 } 362 363 static int 364 axe_miibus_readreg(device_t dev, int phy, int reg) 365 { 366 struct axe_softc *sc = device_private(dev); 367 int val; 368 369 if (sc->axe_dying) 370 return 0; 371 372 if (sc->axe_phyno != phy) 373 return 0; 374 375 axe_lock_mii(sc); 376 val = axe_miibus_readreg_locked(dev, phy, reg); 377 axe_unlock_mii(sc); 378 379 return val; 380 } 381 382 static void 383 axe_miibus_writereg_locked(device_t dev, int phy, int reg, int aval) 384 { 385 struct axe_softc *sc = device_private(dev); 386 usbd_status err; 387 uint16_t val; 388 389 val = htole16(aval); 390 391 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 392 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 393 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 394 395 if (err) { 396 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 397 return; 398 } 399 } 400 401 static void 402 axe_miibus_writereg(device_t dev, int phy, int reg, int aval) 403 { 404 struct axe_softc *sc = device_private(dev); 405 406 if (sc->axe_dying) 407 return; 408 409 if (sc->axe_phyno != phy) 410 return; 411 412 axe_lock_mii(sc); 413 axe_miibus_writereg_locked(dev, phy, reg, aval); 414 axe_unlock_mii(sc); 415 } 416 417 static void 418 axe_miibus_statchg(struct ifnet *ifp) 419 { 420 AXEHIST_FUNC(); AXEHIST_CALLED(); 421 422 struct axe_softc *sc = ifp->if_softc; 423 struct mii_data *mii = &sc->axe_mii; 424 int val, err; 425 426 val = 0; 427 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 428 val |= AXE_MEDIA_FULL_DUPLEX; 429 if (AXE_IS_178_FAMILY(sc)) { 430 if ((IFM_OPTIONS(mii->mii_media_active) & 431 IFM_ETH_TXPAUSE) != 0) 432 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 433 if ((IFM_OPTIONS(mii->mii_media_active) & 434 IFM_ETH_RXPAUSE) != 0) 435 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 436 } 437 } 438 if (AXE_IS_178_FAMILY(sc)) { 439 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 440 if (sc->axe_flags & AX178) 441 val |= AXE_178_MEDIA_ENCK; 442 switch (IFM_SUBTYPE(mii->mii_media_active)) { 443 case IFM_1000_T: 444 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 445 break; 446 case IFM_100_TX: 447 val |= AXE_178_MEDIA_100TX; 448 break; 449 case IFM_10_T: 450 /* doesn't need to be handled */ 451 break; 452 } 453 } 454 455 DPRINTF("val=0x%jx", val, 0, 0, 0); 456 axe_lock_mii(sc); 457 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 458 axe_unlock_mii(sc); 459 if (err) { 460 aprint_error_dev(sc->axe_dev, "media change failed\n"); 461 return; 462 } 463 } 464 465 static void 466 axe_setmulti(struct axe_softc *sc) 467 { 468 AXEHIST_FUNC(); AXEHIST_CALLED(); 469 struct ifnet *ifp = &sc->sc_if; 470 struct ether_multi *enm; 471 struct ether_multistep step; 472 uint32_t h = 0; 473 uint16_t rxmode; 474 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 475 476 if (sc->axe_dying) 477 return; 478 479 axe_lock_mii(sc); 480 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 481 axe_unlock_mii(sc); 482 aprint_error_dev(sc->axe_dev, "can't read rxmode"); 483 return; 484 } 485 rxmode = le16toh(rxmode); 486 487 rxmode &= 488 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 489 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 490 491 rxmode |= 492 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 493 494 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 495 if (ifp->if_flags & IFF_PROMISC) 496 rxmode |= AXE_RXCMD_PROMISC; 497 goto allmulti; 498 } 499 500 /* Now program new ones */ 501 ETHER_FIRST_MULTI(step, &sc->axe_ec, enm); 502 while (enm != NULL) { 503 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 504 ETHER_ADDR_LEN) != 0) 505 goto allmulti; 506 507 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 508 hashtbl[h >> 3] |= 1U << (h & 7); 509 ETHER_NEXT_MULTI(step, enm); 510 } 511 ifp->if_flags &= ~IFF_ALLMULTI; 512 rxmode |= AXE_RXCMD_MULTICAST; 513 514 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 515 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 516 axe_unlock_mii(sc); 517 return; 518 519 allmulti: 520 ifp->if_flags |= IFF_ALLMULTI; 521 rxmode |= AXE_RXCMD_ALLMULTI; 522 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 523 axe_unlock_mii(sc); 524 } 525 526 static void 527 axe_ax_init(struct axe_softc *sc) 528 { 529 int cmd = AXE_178_CMD_READ_NODEID; 530 531 if (sc->axe_flags & AX178) { 532 axe_ax88178_init(sc); 533 } else if (sc->axe_flags & AX772) { 534 axe_ax88772_init(sc); 535 } else if (sc->axe_flags & AX772A) { 536 axe_ax88772a_init(sc); 537 } else if (sc->axe_flags & AX772B) { 538 axe_ax88772b_init(sc); 539 return; 540 } else { 541 cmd = AXE_172_CMD_READ_NODEID; 542 } 543 544 if (axe_cmd(sc, cmd, 0, 0, sc->axe_enaddr)) { 545 aprint_error_dev(sc->axe_dev, 546 "failed to read ethernet address\n"); 547 } 548 } 549 550 551 static void 552 axe_reset(struct axe_softc *sc) 553 { 554 555 if (sc->axe_dying) 556 return; 557 558 /* 559 * softnet_lock can be taken when NET_MPAFE is not defined when calling 560 * if_addr_init -> if_init. This doesn't mixe well with the 561 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 562 * can fire during the wait and attempt to take softnet_lock and then 563 * block the softclk thread meaing the wait never ends. 564 */ 565 #ifndef NET_MPSAFE 566 /* XXX What to reset? */ 567 568 /* Wait a little while for the chip to get its brains in order. */ 569 DELAY(1000); 570 #else 571 axe_lock_mii(sc); 572 573 axe_ax_init(sc); 574 575 axe_unlock_mii(sc); 576 #endif 577 } 578 579 static int 580 axe_get_phyno(struct axe_softc *sc, int sel) 581 { 582 int phyno; 583 584 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 585 case PHY_TYPE_100_HOME: 586 /* FALLTHROUGH */ 587 case PHY_TYPE_GIG: 588 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 589 break; 590 case PHY_TYPE_SPECIAL: 591 /* FALLTHROUGH */ 592 case PHY_TYPE_RSVD: 593 /* FALLTHROUGH */ 594 case PHY_TYPE_NON_SUP: 595 /* FALLTHROUGH */ 596 default: 597 phyno = -1; 598 break; 599 } 600 601 return phyno; 602 } 603 604 #define AXE_GPIO_WRITE(x, y) do { \ 605 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 606 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 607 } while (0) 608 609 static void 610 axe_ax88178_init(struct axe_softc *sc) 611 { 612 AXEHIST_FUNC(); AXEHIST_CALLED(); 613 int gpio0, ledmode, phymode; 614 uint16_t eeprom, val; 615 616 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 617 /* XXX magic */ 618 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 619 eeprom = 0xffff; 620 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 621 622 eeprom = le16toh(eeprom); 623 624 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 625 626 /* if EEPROM is invalid we have to use to GPIO0 */ 627 if (eeprom == 0xffff) { 628 phymode = AXE_PHY_MODE_MARVELL; 629 gpio0 = 1; 630 ledmode = 0; 631 } else { 632 phymode = eeprom & 0x7f; 633 gpio0 = (eeprom & 0x80) ? 0 : 1; 634 ledmode = eeprom >> 8; 635 } 636 637 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 638 639 /* Program GPIOs depending on PHY hardware. */ 640 switch (phymode) { 641 case AXE_PHY_MODE_MARVELL: 642 if (gpio0 == 1) { 643 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 644 hz / 32); 645 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 646 hz / 32); 647 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 648 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 649 hz / 32); 650 } else { 651 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 652 AXE_GPIO1_EN, hz / 3); 653 if (ledmode == 1) { 654 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 655 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 656 hz / 3); 657 } else { 658 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 659 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 660 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 661 AXE_GPIO2_EN, hz / 4); 662 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 663 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 664 } 665 } 666 break; 667 case AXE_PHY_MODE_CICADA: 668 case AXE_PHY_MODE_CICADA_V2: 669 case AXE_PHY_MODE_CICADA_V2_ASIX: 670 if (gpio0 == 1) 671 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 672 AXE_GPIO0_EN, hz / 32); 673 else 674 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 675 AXE_GPIO1_EN, hz / 32); 676 break; 677 case AXE_PHY_MODE_AGERE: 678 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 679 AXE_GPIO1_EN, hz / 32); 680 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 681 AXE_GPIO2_EN, hz / 32); 682 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 683 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 684 AXE_GPIO2_EN, hz / 32); 685 break; 686 case AXE_PHY_MODE_REALTEK_8211CL: 687 case AXE_PHY_MODE_REALTEK_8211BN: 688 case AXE_PHY_MODE_REALTEK_8251CL: 689 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 690 AXE_GPIO1 | AXE_GPIO1_EN; 691 AXE_GPIO_WRITE(val, hz / 32); 692 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 693 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 694 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 695 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 696 axe_miibus_writereg_locked(sc->axe_dev, 697 sc->axe_phyno, 0x1F, 0x0005); 698 axe_miibus_writereg_locked(sc->axe_dev, 699 sc->axe_phyno, 0x0C, 0x0000); 700 val = axe_miibus_readreg_locked(sc->axe_dev, 701 sc->axe_phyno, 0x0001); 702 axe_miibus_writereg_locked(sc->axe_dev, 703 sc->axe_phyno, 0x01, val | 0x0080); 704 axe_miibus_writereg_locked(sc->axe_dev, 705 sc->axe_phyno, 0x1F, 0x0000); 706 } 707 break; 708 default: 709 /* Unknown PHY model or no need to program GPIOs. */ 710 break; 711 } 712 713 /* soft reset */ 714 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 715 usbd_delay_ms(sc->axe_udev, 150); 716 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 717 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 718 usbd_delay_ms(sc->axe_udev, 150); 719 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 720 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 721 usbd_delay_ms(sc->axe_udev, 10); 722 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 723 } 724 725 static void 726 axe_ax88772_init(struct axe_softc *sc) 727 { 728 AXEHIST_FUNC(); AXEHIST_CALLED(); 729 730 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 731 usbd_delay_ms(sc->axe_udev, 40); 732 733 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 734 /* ask for the embedded PHY */ 735 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 736 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 737 usbd_delay_ms(sc->axe_udev, 10); 738 739 /* power down and reset state, pin reset state */ 740 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 741 usbd_delay_ms(sc->axe_udev, 60); 742 743 /* power down/reset state, pin operating state */ 744 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 745 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 746 usbd_delay_ms(sc->axe_udev, 150); 747 748 /* power up, reset */ 749 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 750 751 /* power up, operating */ 752 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 753 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 754 } else { 755 /* ask for external PHY */ 756 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 757 NULL); 758 usbd_delay_ms(sc->axe_udev, 10); 759 760 /* power down internal PHY */ 761 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 762 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 763 } 764 765 usbd_delay_ms(sc->axe_udev, 150); 766 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 767 } 768 769 static void 770 axe_ax88772_phywake(struct axe_softc *sc) 771 { 772 AXEHIST_FUNC(); AXEHIST_CALLED(); 773 774 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 775 /* Manually select internal(embedded) PHY - MAC mode. */ 776 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 777 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 778 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 779 } else { 780 /* 781 * Manually select external PHY - MAC mode. 782 * Reverse MII/RMII is for AX88772A PHY mode. 783 */ 784 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 785 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 786 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 787 } 788 789 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 790 AXE_SW_RESET_IPRL, NULL); 791 792 /* T1 = min 500ns everywhere */ 793 usbd_delay_ms(sc->axe_udev, 150); 794 795 /* Take PHY out of power down. */ 796 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 797 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 798 } else { 799 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 800 } 801 802 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 803 usbd_delay_ms(sc->axe_udev, 600); 804 805 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 806 807 /* T3 = 500ns everywhere */ 808 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 809 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 810 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 811 } 812 813 static void 814 axe_ax88772a_init(struct axe_softc *sc) 815 { 816 AXEHIST_FUNC(); AXEHIST_CALLED(); 817 818 /* Reload EEPROM. */ 819 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 820 axe_ax88772_phywake(sc); 821 /* Stop MAC. */ 822 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 823 } 824 825 static void 826 axe_ax88772b_init(struct axe_softc *sc) 827 { 828 AXEHIST_FUNC(); AXEHIST_CALLED(); 829 uint16_t eeprom; 830 int i; 831 832 /* Reload EEPROM. */ 833 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 834 835 /* 836 * Save PHY power saving configuration(high byte) and 837 * clear EEPROM checksum value(low byte). 838 */ 839 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 840 &eeprom)) { 841 aprint_error_dev(sc->axe_dev, "failed to read eeprom\n"); 842 return; 843 } 844 845 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 846 847 /* 848 * Auto-loaded default station address from internal ROM is 849 * 00:00:00:00:00:00 such that an explicit access to EEPROM 850 * is required to get real station address. 851 */ 852 uint8_t *eaddr = sc->axe_enaddr; 853 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 854 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 855 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 856 aprint_error_dev(sc->axe_dev, 857 "failed to read eeprom\n"); 858 eeprom = 0; 859 } 860 eeprom = le16toh(eeprom); 861 *eaddr++ = (uint8_t)(eeprom & 0xFF); 862 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 863 } 864 /* Wakeup PHY. */ 865 axe_ax88772_phywake(sc); 866 /* Stop MAC. */ 867 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 868 } 869 870 #undef AXE_GPIO_WRITE 871 872 /* 873 * Probe for a AX88172 chip. 874 */ 875 int 876 axe_match(device_t parent, cfdata_t match, void *aux) 877 { 878 struct usb_attach_arg *uaa = aux; 879 880 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 881 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 882 } 883 884 /* 885 * Attach the interface. Allocate softc structures, do ifmedia 886 * setup and ethernet/BPF attach. 887 */ 888 void 889 axe_attach(device_t parent, device_t self, void *aux) 890 { 891 AXEHIST_FUNC(); AXEHIST_CALLED(); 892 struct axe_softc *sc = device_private(self); 893 struct usb_attach_arg *uaa = aux; 894 struct usbd_device *dev = uaa->uaa_device; 895 usbd_status err; 896 usb_interface_descriptor_t *id; 897 usb_endpoint_descriptor_t *ed; 898 struct mii_data *mii; 899 char *devinfop; 900 const char *devname = device_xname(self); 901 struct ifnet *ifp; 902 int i, s; 903 904 aprint_naive("\n"); 905 aprint_normal("\n"); 906 907 sc->axe_dev = self; 908 sc->axe_udev = dev; 909 910 devinfop = usbd_devinfo_alloc(dev, 0); 911 aprint_normal_dev(self, "%s\n", devinfop); 912 usbd_devinfo_free(devinfop); 913 914 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 915 if (err) { 916 aprint_error_dev(self, "failed to set configuration" 917 ", err=%s\n", usbd_errstr(err)); 918 return; 919 } 920 921 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 922 923 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 924 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 925 926 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 927 if (err) { 928 aprint_error_dev(self, "getting interface handle failed\n"); 929 return; 930 } 931 932 sc->axe_product = uaa->uaa_product; 933 sc->axe_vendor = uaa->uaa_vendor; 934 935 id = usbd_get_interface_descriptor(sc->axe_iface); 936 937 /* decide on what our bufsize will be */ 938 if (AXE_IS_178_FAMILY(sc)) 939 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 940 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 941 else 942 sc->axe_bufsz = AXE_172_BUFSZ; 943 944 sc->axe_ed[AXE_ENDPT_RX] = -1; 945 sc->axe_ed[AXE_ENDPT_TX] = -1; 946 sc->axe_ed[AXE_ENDPT_INTR] = -1; 947 948 /* Find endpoints. */ 949 for (i = 0; i < id->bNumEndpoints; i++) { 950 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 951 if (ed == NULL) { 952 aprint_error_dev(self, "couldn't get ep %d\n", i); 953 return; 954 } 955 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 956 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 957 958 if (dir == UE_DIR_IN && xt == UE_BULK && 959 sc->axe_ed[AXE_ENDPT_RX] == -1) { 960 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 961 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 962 sc->axe_ed[AXE_ENDPT_TX] == -1) { 963 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 964 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 965 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 966 } 967 } 968 969 s = splnet(); 970 971 /* We need the PHYID for init dance in some cases */ 972 axe_lock_mii(sc); 973 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 974 aprint_error_dev(self, "failed to read phyaddrs\n"); 975 return; 976 } 977 978 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 979 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 980 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 981 if (sc->axe_phyno == -1) 982 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 983 if (sc->axe_phyno == -1) { 984 DPRINTF(" no valid PHY address found, assuming PHY address 0", 985 0, 0, 0, 0); 986 sc->axe_phyno = 0; 987 } 988 989 /* Initialize controller and get station address. */ 990 991 axe_ax_init(sc); 992 993 /* 994 * Fetch IPG values. 995 */ 996 if (sc->axe_flags & (AX772A | AX772B)) { 997 /* Set IPG values. */ 998 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 999 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 1000 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1001 } else { 1002 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 1003 aprint_error_dev(self, "failed to read ipg\n"); 1004 return; 1005 } 1006 } 1007 1008 axe_unlock_mii(sc); 1009 1010 /* 1011 * An ASIX chip was detected. Inform the world. 1012 */ 1013 aprint_normal_dev(self, "Ethernet address %s\n", 1014 ether_sprintf(sc->axe_enaddr)); 1015 1016 /* Initialize interface info.*/ 1017 ifp = &sc->sc_if; 1018 ifp->if_softc = sc; 1019 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 1020 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1021 ifp->if_ioctl = axe_ioctl; 1022 ifp->if_start = axe_start; 1023 ifp->if_init = axe_init; 1024 ifp->if_stop = axe_stop; 1025 ifp->if_watchdog = axe_watchdog; 1026 1027 IFQ_SET_READY(&ifp->if_snd); 1028 1029 if (AXE_IS_178_FAMILY(sc)) 1030 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1031 if (sc->axe_flags & AX772B) { 1032 ifp->if_capabilities = 1033 IFCAP_CSUM_IPv4_Rx | 1034 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1035 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1036 /* 1037 * Checksum offloading of AX88772B also works with VLAN 1038 * tagged frames but there is no way to take advantage 1039 * of the feature because vlan(4) assumes 1040 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1041 * support checksum offloading with VLAN. VLAN hardware 1042 * tagging support of AX88772B is very limited so it's 1043 * not possible to announce IFCAP_VLAN_HWTAGGING. 1044 */ 1045 } 1046 u_int adv_pause; 1047 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1048 adv_pause = MIIF_DOPAUSE; 1049 else 1050 adv_pause = 0; 1051 adv_pause = 0; 1052 1053 /* Initialize MII/media info. */ 1054 mii = &sc->axe_mii; 1055 mii->mii_ifp = ifp; 1056 mii->mii_readreg = axe_miibus_readreg; 1057 mii->mii_writereg = axe_miibus_writereg; 1058 mii->mii_statchg = axe_miibus_statchg; 1059 mii->mii_flags = MIIF_AUTOTSLEEP; 1060 1061 sc->axe_ec.ec_mii = mii; 1062 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1063 1064 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1065 adv_pause); 1066 1067 if (LIST_EMPTY(&mii->mii_phys)) { 1068 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1069 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1070 } else 1071 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1072 1073 /* Attach the interface. */ 1074 if_attach(ifp); 1075 ether_ifattach(ifp, sc->axe_enaddr); 1076 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1077 RND_TYPE_NET, RND_FLAG_DEFAULT); 1078 1079 callout_init(&sc->axe_stat_ch, 0); 1080 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1081 1082 sc->axe_attached = true; 1083 splx(s); 1084 1085 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1086 1087 if (!pmf_device_register(self, NULL, NULL)) 1088 aprint_error_dev(self, "couldn't establish power handler\n"); 1089 } 1090 1091 int 1092 axe_detach(device_t self, int flags) 1093 { 1094 AXEHIST_FUNC(); AXEHIST_CALLED(); 1095 struct axe_softc *sc = device_private(self); 1096 int s; 1097 struct ifnet *ifp = &sc->sc_if; 1098 1099 /* Detached before attached finished, so just bail out. */ 1100 if (!sc->axe_attached) 1101 return 0; 1102 1103 pmf_device_deregister(self); 1104 1105 sc->axe_dying = true; 1106 1107 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1108 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1109 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1110 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1111 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1112 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1113 1114 /* 1115 * Remove any pending tasks. They cannot be executing because they run 1116 * in the same thread as detach. 1117 */ 1118 usb_rem_task(sc->axe_udev, &sc->axe_tick_task); 1119 1120 s = splusb(); 1121 1122 if (ifp->if_flags & IFF_RUNNING) 1123 axe_stop(ifp, 1); 1124 1125 1126 if (--sc->axe_refcnt >= 0) { 1127 /* Wait for processes to go away. */ 1128 usb_detach_waitold(sc->axe_dev); 1129 } 1130 1131 callout_destroy(&sc->axe_stat_ch); 1132 mutex_destroy(&sc->axe_mii_lock); 1133 rnd_detach_source(&sc->rnd_source); 1134 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1135 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1136 ether_ifdetach(ifp); 1137 if_detach(ifp); 1138 1139 #ifdef DIAGNOSTIC 1140 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1141 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1142 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1143 aprint_debug_dev(self, "detach has active endpoints\n"); 1144 #endif 1145 1146 sc->axe_attached = false; 1147 1148 splx(s); 1149 1150 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1151 1152 return 0; 1153 } 1154 1155 int 1156 axe_activate(device_t self, devact_t act) 1157 { 1158 AXEHIST_FUNC(); AXEHIST_CALLED(); 1159 struct axe_softc *sc = device_private(self); 1160 1161 switch (act) { 1162 case DVACT_DEACTIVATE: 1163 if_deactivate(&sc->axe_ec.ec_if); 1164 sc->axe_dying = true; 1165 return 0; 1166 default: 1167 return EOPNOTSUPP; 1168 } 1169 } 1170 1171 static int 1172 axe_rx_list_init(struct axe_softc *sc) 1173 { 1174 AXEHIST_FUNC(); AXEHIST_CALLED(); 1175 1176 struct axe_cdata *cd; 1177 struct axe_chain *c; 1178 int i; 1179 1180 cd = &sc->axe_cdata; 1181 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1182 c = &cd->axe_rx_chain[i]; 1183 c->axe_sc = sc; 1184 c->axe_idx = i; 1185 if (c->axe_xfer == NULL) { 1186 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1187 sc->axe_bufsz, 0, 0, &c->axe_xfer); 1188 if (err) 1189 return err; 1190 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1191 } 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int 1198 axe_tx_list_init(struct axe_softc *sc) 1199 { 1200 AXEHIST_FUNC(); AXEHIST_CALLED(); 1201 struct axe_cdata *cd; 1202 struct axe_chain *c; 1203 int i; 1204 1205 cd = &sc->axe_cdata; 1206 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1207 c = &cd->axe_tx_chain[i]; 1208 c->axe_sc = sc; 1209 c->axe_idx = i; 1210 if (c->axe_xfer == NULL) { 1211 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1212 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1213 &c->axe_xfer); 1214 if (err) 1215 return err; 1216 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1217 } 1218 } 1219 1220 return 0; 1221 } 1222 1223 /* 1224 * A frame has been uploaded: pass the resulting mbuf chain up to 1225 * the higher level protocols. 1226 */ 1227 static void 1228 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1229 { 1230 AXEHIST_FUNC(); AXEHIST_CALLED(); 1231 struct axe_softc *sc; 1232 struct axe_chain *c; 1233 struct ifnet *ifp; 1234 uint8_t *buf; 1235 uint32_t total_len; 1236 struct mbuf *m; 1237 int s; 1238 1239 c = (struct axe_chain *)priv; 1240 sc = c->axe_sc; 1241 buf = c->axe_buf; 1242 ifp = &sc->sc_if; 1243 1244 if (sc->axe_dying) 1245 return; 1246 1247 if ((ifp->if_flags & IFF_RUNNING) == 0) 1248 return; 1249 1250 if (status != USBD_NORMAL_COMPLETION) { 1251 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1252 return; 1253 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1254 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1255 usbd_errstr(status)); 1256 } 1257 if (status == USBD_STALLED) 1258 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1259 goto done; 1260 } 1261 1262 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1263 1264 do { 1265 u_int pktlen = 0; 1266 u_int rxlen = 0; 1267 int flags = 0; 1268 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1269 struct axe_sframe_hdr hdr; 1270 1271 if (total_len < sizeof(hdr)) { 1272 ifp->if_ierrors++; 1273 goto done; 1274 } 1275 1276 memcpy(&hdr, buf, sizeof(hdr)); 1277 1278 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1279 total_len, 1280 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1281 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1282 1283 total_len -= sizeof(hdr); 1284 buf += sizeof(hdr); 1285 1286 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1287 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1288 AXE_RH1M_RXLEN_MASK) { 1289 ifp->if_ierrors++; 1290 goto done; 1291 } 1292 1293 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1294 if (total_len < rxlen) { 1295 pktlen = total_len; 1296 total_len = 0; 1297 } else { 1298 pktlen = rxlen; 1299 rxlen = roundup2(rxlen, 2); 1300 total_len -= rxlen; 1301 } 1302 1303 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1304 struct axe_csum_hdr csum_hdr; 1305 1306 if (total_len < sizeof(csum_hdr)) { 1307 ifp->if_ierrors++; 1308 goto done; 1309 } 1310 1311 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1312 1313 csum_hdr.len = le16toh(csum_hdr.len); 1314 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1315 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1316 1317 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1318 " cstatus %#jx", total_len, 1319 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1320 1321 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1322 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1323 sc->sc_lenmask) { 1324 /* we lost sync */ 1325 ifp->if_ierrors++; 1326 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1327 "err", 1328 AXE_CSUM_RXBYTES(csum_hdr.len), 1329 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1330 sc->sc_lenmask, 0); 1331 goto done; 1332 } 1333 /* 1334 * Get total transferred frame length including 1335 * checksum header. The length should be multiple 1336 * of 4. 1337 */ 1338 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1339 u_int len = sizeof(csum_hdr) + pktlen; 1340 len = (len + 3) & ~3; 1341 if (total_len < len) { 1342 DPRINTFN(20, "total_len %#jx < len %#jx", 1343 total_len, len, 0, 0); 1344 /* invalid length */ 1345 ifp->if_ierrors++; 1346 goto done; 1347 } 1348 buf += sizeof(csum_hdr); 1349 1350 const uint16_t cstatus = csum_hdr.cstatus; 1351 1352 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1353 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1354 flags |= M_CSUM_TCP_UDP_BAD; 1355 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1356 flags |= M_CSUM_IPv4_BAD; 1357 1358 const uint16_t l4type = 1359 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1360 1361 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1362 flags |= M_CSUM_TCPv4; 1363 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1364 flags |= M_CSUM_UDPv4; 1365 } 1366 if (total_len < len) { 1367 pktlen = total_len; 1368 total_len = 0; 1369 } else { 1370 total_len -= len; 1371 rxlen = len - sizeof(csum_hdr); 1372 } 1373 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1374 " rxlen %#jx", total_len, len, pktlen, rxlen); 1375 } else { /* AX172 */ 1376 pktlen = rxlen = total_len; 1377 total_len = 0; 1378 } 1379 1380 MGETHDR(m, M_DONTWAIT, MT_DATA); 1381 if (m == NULL) { 1382 ifp->if_ierrors++; 1383 goto done; 1384 } 1385 1386 if (pktlen > MHLEN - ETHER_ALIGN) { 1387 MCLGET(m, M_DONTWAIT); 1388 if ((m->m_flags & M_EXT) == 0) { 1389 m_freem(m); 1390 ifp->if_ierrors++; 1391 goto done; 1392 } 1393 } 1394 m->m_data += ETHER_ALIGN; 1395 1396 m_set_rcvif(m, ifp); 1397 m->m_pkthdr.len = m->m_len = pktlen; 1398 m->m_pkthdr.csum_flags = flags; 1399 1400 memcpy(mtod(m, uint8_t *), buf, pktlen); 1401 buf += rxlen; 1402 1403 DPRINTFN(10, "deliver %jd (%#jx)", m->m_len, m->m_len, 0, 0); 1404 1405 s = splnet(); 1406 1407 if_percpuq_enqueue((ifp)->if_percpuq, (m)); 1408 1409 splx(s); 1410 1411 } while (total_len > 0); 1412 1413 done: 1414 1415 /* Setup new transfer. */ 1416 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1417 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1418 usbd_transfer(xfer); 1419 1420 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1421 } 1422 1423 /* 1424 * A frame was downloaded to the chip. It's safe for us to clean up 1425 * the list buffers. 1426 */ 1427 1428 static void 1429 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1430 { 1431 AXEHIST_FUNC(); AXEHIST_CALLED(); 1432 struct axe_chain *c = priv; 1433 struct axe_softc *sc = c->axe_sc; 1434 struct ifnet *ifp = &sc->sc_if; 1435 int s; 1436 1437 1438 if (sc->axe_dying) 1439 return; 1440 1441 s = splnet(); 1442 1443 ifp->if_timer = 0; 1444 ifp->if_flags &= ~IFF_OACTIVE; 1445 1446 if (status != USBD_NORMAL_COMPLETION) { 1447 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1448 splx(s); 1449 return; 1450 } 1451 ifp->if_oerrors++; 1452 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1453 usbd_errstr(status)); 1454 if (status == USBD_STALLED) 1455 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1456 splx(s); 1457 return; 1458 } 1459 ifp->if_opackets++; 1460 1461 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1462 axe_start(ifp); 1463 1464 splx(s); 1465 } 1466 1467 static void 1468 axe_tick(void *xsc) 1469 { 1470 AXEHIST_FUNC(); AXEHIST_CALLED(); 1471 struct axe_softc *sc = xsc; 1472 1473 if (sc == NULL) 1474 return; 1475 1476 if (sc->axe_dying) 1477 return; 1478 1479 /* Perform periodic stuff in process context */ 1480 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1481 } 1482 1483 static void 1484 axe_tick_task(void *xsc) 1485 { 1486 AXEHIST_FUNC(); AXEHIST_CALLED(); 1487 int s; 1488 struct axe_softc *sc = xsc; 1489 struct ifnet *ifp; 1490 struct mii_data *mii; 1491 1492 if (sc == NULL) 1493 return; 1494 1495 if (sc->axe_dying) 1496 return; 1497 1498 ifp = &sc->sc_if; 1499 mii = &sc->axe_mii; 1500 1501 if (mii == NULL) 1502 return; 1503 1504 s = splnet(); 1505 1506 mii_tick(mii); 1507 if (sc->axe_link == 0 && 1508 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1509 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1510 DPRINTF("got link", 0, 0, 0, 0); 1511 sc->axe_link++; 1512 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1513 axe_start(ifp); 1514 } 1515 1516 callout_schedule(&sc->axe_stat_ch, hz); 1517 1518 splx(s); 1519 } 1520 1521 static int 1522 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1523 { 1524 struct ifnet *ifp = &sc->sc_if; 1525 struct axe_chain *c; 1526 usbd_status err; 1527 int length, boundary; 1528 1529 c = &sc->axe_cdata.axe_tx_chain[idx]; 1530 1531 /* 1532 * Copy the mbuf data into a contiguous buffer, leaving two 1533 * bytes at the beginning to hold the frame length. 1534 */ 1535 if (AXE_IS_178_FAMILY(sc)) { 1536 struct axe_sframe_hdr hdr; 1537 1538 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1539 1540 hdr.len = htole16(m->m_pkthdr.len); 1541 hdr.ilen = ~hdr.len; 1542 1543 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1544 length = sizeof(hdr); 1545 1546 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1547 length += m->m_pkthdr.len; 1548 1549 if ((length % boundary) == 0) { 1550 hdr.len = 0x0000; 1551 hdr.ilen = 0xffff; 1552 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1553 length += sizeof(hdr); 1554 } 1555 } else { 1556 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1557 length = m->m_pkthdr.len; 1558 } 1559 1560 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1561 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1562 1563 /* Transmit */ 1564 err = usbd_transfer(c->axe_xfer); 1565 if (err != USBD_IN_PROGRESS) { 1566 axe_stop(ifp, 0); 1567 return EIO; 1568 } 1569 1570 sc->axe_cdata.axe_tx_cnt++; 1571 1572 return 0; 1573 } 1574 1575 1576 static void 1577 axe_csum_cfg(struct axe_softc *sc) 1578 { 1579 struct ifnet *ifp = &sc->sc_if; 1580 uint16_t csum1, csum2; 1581 1582 if ((sc->axe_flags & AX772B) != 0) { 1583 csum1 = 0; 1584 csum2 = 0; 1585 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1586 csum1 |= AXE_TXCSUM_IP; 1587 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1588 csum1 |= AXE_TXCSUM_TCP; 1589 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1590 csum1 |= AXE_TXCSUM_UDP; 1591 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1592 csum1 |= AXE_TXCSUM_TCPV6; 1593 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1594 csum1 |= AXE_TXCSUM_UDPV6; 1595 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1596 csum1 = 0; 1597 csum2 = 0; 1598 1599 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1600 csum1 |= AXE_RXCSUM_IP; 1601 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1602 csum1 |= AXE_RXCSUM_TCP; 1603 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1604 csum1 |= AXE_RXCSUM_UDP; 1605 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1606 csum1 |= AXE_RXCSUM_TCPV6; 1607 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1608 csum1 |= AXE_RXCSUM_UDPV6; 1609 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1610 } 1611 } 1612 1613 static void 1614 axe_start(struct ifnet *ifp) 1615 { 1616 struct axe_softc *sc; 1617 struct mbuf *m; 1618 1619 sc = ifp->if_softc; 1620 1621 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) 1622 return; 1623 1624 IFQ_POLL(&ifp->if_snd, m); 1625 if (m == NULL) { 1626 return; 1627 } 1628 1629 if (axe_encap(sc, m, 0)) { 1630 ifp->if_flags |= IFF_OACTIVE; 1631 return; 1632 } 1633 IFQ_DEQUEUE(&ifp->if_snd, m); 1634 1635 /* 1636 * If there's a BPF listener, bounce a copy of this frame 1637 * to him. 1638 */ 1639 bpf_mtap(ifp, m, BPF_D_OUT); 1640 m_freem(m); 1641 1642 ifp->if_flags |= IFF_OACTIVE; 1643 1644 /* 1645 * Set a timeout in case the chip goes out to lunch. 1646 */ 1647 ifp->if_timer = 5; 1648 1649 return; 1650 } 1651 1652 static int 1653 axe_init(struct ifnet *ifp) 1654 { 1655 AXEHIST_FUNC(); AXEHIST_CALLED(); 1656 struct axe_softc *sc = ifp->if_softc; 1657 struct axe_chain *c; 1658 usbd_status err; 1659 int rxmode; 1660 int i, s; 1661 1662 s = splnet(); 1663 1664 if (ifp->if_flags & IFF_RUNNING) 1665 axe_stop(ifp, 0); 1666 1667 /* 1668 * Cancel pending I/O and free all RX/TX buffers. 1669 */ 1670 axe_reset(sc); 1671 1672 axe_lock_mii(sc); 1673 1674 #if 0 1675 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1676 AX_GPIO_GPO2EN, 5, in_pm); 1677 #endif 1678 /* Set MAC address and transmitter IPG values. */ 1679 if (AXE_IS_178_FAMILY(sc)) { 1680 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1681 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1682 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1683 } else { 1684 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1685 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1686 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1687 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1688 } 1689 if (AXE_IS_178_FAMILY(sc)) { 1690 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1691 if ((sc->axe_flags & AX772B) != 0 && 1692 (ifp->if_capenable & AX_RXCSUM) != 0) { 1693 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1694 sc->axe_flags |= AXCSUM_FRAME; 1695 } else { 1696 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1697 sc->axe_flags |= AXSTD_FRAME; 1698 } 1699 } 1700 1701 /* Configure TX/RX checksum offloading. */ 1702 axe_csum_cfg(sc); 1703 1704 if (sc->axe_flags & AX772B) { 1705 /* AX88772B uses different maximum frame burst configuration. */ 1706 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1707 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1708 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1709 } 1710 /* Enable receiver, set RX mode */ 1711 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1712 if (AXE_IS_178_FAMILY(sc)) { 1713 if (sc->axe_flags & AX772B) { 1714 /* 1715 * Select RX header format type 1. Aligning IP 1716 * header on 4 byte boundary is not needed when 1717 * checksum offloading feature is not used 1718 * because we always copy the received frame in 1719 * RX handler. When RX checksum offloading is 1720 * active, aligning IP header is required to 1721 * reflect actual frame length including RX 1722 * header size. 1723 */ 1724 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1725 if (sc->axe_flags & AXCSUM_FRAME) 1726 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1727 } else { 1728 /* 1729 * Default Rx buffer size is too small to get 1730 * maximum performance. 1731 */ 1732 #if 0 1733 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1734 /* Largest possible USB buffer size for AX88178 */ 1735 #endif 1736 rxmode |= AXE_178_RXCMD_MFB_16384; 1737 } 1738 } else { 1739 rxmode |= AXE_172_RXCMD_UNICAST; 1740 } 1741 1742 1743 /* If we want promiscuous mode, set the allframes bit. */ 1744 if (ifp->if_flags & IFF_PROMISC) 1745 rxmode |= AXE_RXCMD_PROMISC; 1746 1747 if (ifp->if_flags & IFF_BROADCAST) 1748 rxmode |= AXE_RXCMD_BROADCAST; 1749 1750 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1751 1752 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1753 axe_unlock_mii(sc); 1754 1755 /* Load the multicast filter. */ 1756 axe_setmulti(sc); 1757 1758 /* Open RX and TX pipes. */ 1759 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1760 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1761 if (err) { 1762 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1763 usbd_errstr(err)); 1764 splx(s); 1765 return EIO; 1766 } 1767 1768 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1769 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1770 if (err) { 1771 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1772 usbd_errstr(err)); 1773 splx(s); 1774 return EIO; 1775 } 1776 1777 /* Init RX ring. */ 1778 if (axe_rx_list_init(sc) != 0) { 1779 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1780 splx(s); 1781 return ENOBUFS; 1782 } 1783 1784 /* Init TX ring. */ 1785 if (axe_tx_list_init(sc) != 0) { 1786 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1787 splx(s); 1788 return ENOBUFS; 1789 } 1790 1791 /* Start up the receive pipe. */ 1792 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1793 c = &sc->axe_cdata.axe_rx_chain[i]; 1794 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1795 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1796 usbd_transfer(c->axe_xfer); 1797 } 1798 1799 ifp->if_flags |= IFF_RUNNING; 1800 ifp->if_flags &= ~IFF_OACTIVE; 1801 1802 splx(s); 1803 1804 callout_schedule(&sc->axe_stat_ch, hz); 1805 return 0; 1806 } 1807 1808 static int 1809 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1810 { 1811 struct axe_softc *sc = ifp->if_softc; 1812 int s; 1813 int error = 0; 1814 1815 s = splnet(); 1816 1817 switch(cmd) { 1818 case SIOCSIFFLAGS: 1819 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1820 break; 1821 1822 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1823 case IFF_RUNNING: 1824 axe_stop(ifp, 1); 1825 break; 1826 case IFF_UP: 1827 axe_init(ifp); 1828 break; 1829 case IFF_UP | IFF_RUNNING: 1830 if ((ifp->if_flags ^ sc->axe_if_flags) == IFF_PROMISC) 1831 axe_setmulti(sc); 1832 else 1833 axe_init(ifp); 1834 break; 1835 } 1836 sc->axe_if_flags = ifp->if_flags; 1837 break; 1838 1839 default: 1840 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1841 break; 1842 1843 error = 0; 1844 1845 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) 1846 axe_setmulti(sc); 1847 1848 } 1849 splx(s); 1850 1851 return error; 1852 } 1853 1854 static void 1855 axe_watchdog(struct ifnet *ifp) 1856 { 1857 struct axe_softc *sc; 1858 struct axe_chain *c; 1859 usbd_status stat; 1860 int s; 1861 1862 sc = ifp->if_softc; 1863 1864 ifp->if_oerrors++; 1865 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1866 1867 s = splusb(); 1868 c = &sc->axe_cdata.axe_tx_chain[0]; 1869 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1870 axe_txeof(c->axe_xfer, c, stat); 1871 1872 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1873 axe_start(ifp); 1874 splx(s); 1875 } 1876 1877 /* 1878 * Stop the adapter and free any mbufs allocated to the 1879 * RX and TX lists. 1880 */ 1881 static void 1882 axe_stop(struct ifnet *ifp, int disable) 1883 { 1884 struct axe_softc *sc = ifp->if_softc; 1885 usbd_status err; 1886 int i; 1887 1888 ifp->if_timer = 0; 1889 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1890 1891 callout_stop(&sc->axe_stat_ch); 1892 1893 /* Stop transfers. */ 1894 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1895 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1896 if (err) { 1897 aprint_error_dev(sc->axe_dev, 1898 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1899 } 1900 } 1901 1902 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1903 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1904 if (err) { 1905 aprint_error_dev(sc->axe_dev, 1906 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1907 } 1908 } 1909 1910 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1911 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1912 if (err) { 1913 aprint_error_dev(sc->axe_dev, 1914 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1915 } 1916 } 1917 1918 axe_reset(sc); 1919 1920 /* Free RX resources. */ 1921 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1922 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1923 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1924 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1925 } 1926 } 1927 1928 /* Free TX resources. */ 1929 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1930 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1931 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1932 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1933 } 1934 } 1935 1936 /* Close pipes. */ 1937 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1938 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1939 if (err) { 1940 aprint_error_dev(sc->axe_dev, 1941 "close rx pipe failed: %s\n", usbd_errstr(err)); 1942 } 1943 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1944 } 1945 1946 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1947 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1948 if (err) { 1949 aprint_error_dev(sc->axe_dev, 1950 "close tx pipe failed: %s\n", usbd_errstr(err)); 1951 } 1952 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1953 } 1954 1955 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1956 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1957 if (err) { 1958 aprint_error_dev(sc->axe_dev, 1959 "close intr pipe failed: %s\n", usbd_errstr(err)); 1960 } 1961 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1962 } 1963 1964 sc->axe_link = 0; 1965 } 1966 1967 MODULE(MODULE_CLASS_DRIVER, if_axe, "bpf"); 1968 1969 #ifdef _MODULE 1970 #include "ioconf.c" 1971 #endif 1972 1973 static int 1974 if_axe_modcmd(modcmd_t cmd, void *aux) 1975 { 1976 int error = 0; 1977 1978 switch (cmd) { 1979 case MODULE_CMD_INIT: 1980 #ifdef _MODULE 1981 error = config_init_component(cfdriver_ioconf_axe, 1982 cfattach_ioconf_axe, cfdata_ioconf_axe); 1983 #endif 1984 return error; 1985 case MODULE_CMD_FINI: 1986 #ifdef _MODULE 1987 error = config_fini_component(cfdriver_ioconf_axe, 1988 cfattach_ioconf_axe, cfdata_ioconf_axe); 1989 #endif 1990 return error; 1991 default: 1992 return ENOTTY; 1993 } 1994 } 1995
Indexes created Wed Sep 24 15:09:51 GMT 2025