if_axe.c revision 1.95
1 /* $NetBSD: if_axe.c,v 1.95 2019/01/22 03:42:28 msaitoh Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.95 2019/01/22 03:42:28 msaitoh Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 /* 131 * AXE_178_MAX_FRAME_BURST 132 * max frame burst size for Ax88178 and Ax88772 133 * 0 2048 bytes 134 * 1 4096 bytes 135 * 2 8192 bytes 136 * 3 16384 bytes 137 * use the largest your system can handle without USB stalling. 138 * 139 * NB: 88772 parts appear to generate lots of input errors with 140 * a 2K rx buffer and 8K is only slightly faster than 4K on an 141 * EHCI port on a T42 so change at your own risk. 142 */ 143 #define AXE_178_MAX_FRAME_BURST 1 144 145 146 #ifdef USB_DEBUG 147 #ifndef AXE_DEBUG 148 #define axedebug 0 149 #else 150 static int axedebug = 20; 151 152 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 153 { 154 int err; 155 const struct sysctlnode *rnode; 156 const struct sysctlnode *cnode; 157 158 err = sysctl_createv(clog, 0, NULL, &rnode, 159 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 160 SYSCTL_DESCR("axe global controls"), 161 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 162 163 if (err) 164 goto fail; 165 166 /* control debugging printfs */ 167 err = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 169 "debug", SYSCTL_DESCR("Enable debugging output"), 170 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 171 if (err) 172 goto fail; 173 174 return; 175 fail: 176 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 177 } 178 179 #endif /* AXE_DEBUG */ 180 #endif /* USB_DEBUG */ 181 182 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 183 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 184 #define AXEHIST_FUNC() USBHIST_FUNC() 185 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 186 187 /* 188 * Various supported device vendors/products. 189 */ 190 static const struct axe_type axe_devs[] = { 191 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 192 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 193 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 199 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 200 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 201 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 202 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 203 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 204 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 206 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 208 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 209 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 210 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 211 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 212 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 213 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 214 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 215 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 216 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 218 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 219 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 220 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 221 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 222 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 223 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 225 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 226 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 227 }; 228 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 229 230 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 231 { 0x8000, 0x8001, 2048 }, 232 { 0x8100, 0x8147, 4096 }, 233 { 0x8200, 0x81EB, 6144 }, 234 { 0x8300, 0x83D7, 8192 }, 235 { 0x8400, 0x851E, 16384 }, 236 { 0x8500, 0x8666, 20480 }, 237 { 0x8600, 0x87AE, 24576 }, 238 { 0x8700, 0x8A3D, 32768 } 239 }; 240 241 int axe_match(device_t, cfdata_t, void *); 242 void axe_attach(device_t, device_t, void *); 243 int axe_detach(device_t, int); 244 int axe_activate(device_t, devact_t); 245 246 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 247 axe_match, axe_attach, axe_detach, axe_activate); 248 249 static int axe_tx_list_init(struct axe_softc *); 250 static int axe_rx_list_init(struct axe_softc *); 251 static int axe_encap(struct axe_softc *, struct mbuf *, int); 252 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 253 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 254 static void axe_tick(void *); 255 static void axe_tick_task(void *); 256 static void axe_start(struct ifnet *); 257 static int axe_ioctl(struct ifnet *, u_long, void *); 258 static int axe_init(struct ifnet *); 259 static void axe_stop(struct ifnet *, int); 260 static void axe_watchdog(struct ifnet *); 261 static int axe_miibus_readreg_locked(device_t, int, int, uint16_t *); 262 static int axe_miibus_readreg(device_t, int, int, uint16_t *); 263 static int axe_miibus_writereg_locked(device_t, int, int, uint16_t); 264 static int axe_miibus_writereg(device_t, int, int, uint16_t); 265 static void axe_miibus_statchg(struct ifnet *); 266 static int axe_cmd(struct axe_softc *, int, int, int, void *); 267 static void axe_reset(struct axe_softc *); 268 269 static void axe_setmulti(struct axe_softc *); 270 static void axe_lock_mii(struct axe_softc *); 271 static void axe_unlock_mii(struct axe_softc *); 272 273 static void axe_ax88178_init(struct axe_softc *); 274 static void axe_ax88772_init(struct axe_softc *); 275 static void axe_ax88772a_init(struct axe_softc *); 276 static void axe_ax88772b_init(struct axe_softc *); 277 278 /* Get exclusive access to the MII registers */ 279 static void 280 axe_lock_mii(struct axe_softc *sc) 281 { 282 283 sc->axe_refcnt++; 284 mutex_enter(&sc->axe_mii_lock); 285 } 286 287 static void 288 axe_unlock_mii(struct axe_softc *sc) 289 { 290 291 mutex_exit(&sc->axe_mii_lock); 292 if (--sc->axe_refcnt < 0) 293 usb_detach_wakeupold((sc->axe_dev)); 294 } 295 296 static int 297 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 298 { 299 AXEHIST_FUNC(); AXEHIST_CALLED(); 300 usb_device_request_t req; 301 usbd_status err; 302 303 KASSERT(mutex_owned(&sc->axe_mii_lock)); 304 305 if (sc->axe_dying) 306 return -1; 307 308 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 309 310 if (AXE_CMD_DIR(cmd)) 311 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 312 else 313 req.bmRequestType = UT_READ_VENDOR_DEVICE; 314 req.bRequest = AXE_CMD_CMD(cmd); 315 USETW(req.wValue, val); 316 USETW(req.wIndex, index); 317 USETW(req.wLength, AXE_CMD_LEN(cmd)); 318 319 err = usbd_do_request(sc->axe_udev, &req, buf); 320 321 if (err) { 322 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 323 return -1; 324 } 325 return 0; 326 } 327 328 static int 329 axe_miibus_readreg_locked(device_t dev, int phy, int reg, uint16_t *val) 330 { 331 AXEHIST_FUNC(); AXEHIST_CALLED(); 332 struct axe_softc *sc = device_private(dev); 333 usbd_status err; 334 uint16_t data; 335 336 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 337 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 339 340 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 341 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 342 if (err) { 343 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 344 return err; 345 } 346 347 *val = le16toh(data); 348 if (AXE_IS_772(sc) && reg == MII_BMSR) { 349 /* 350 * BMSR of AX88772 indicates that it supports extended 351 * capability but the extended status register is 352 * reserved for embedded ethernet PHY. So clear the 353 * extended capability bit of BMSR. 354 */ 355 *val &= ~BMSR_EXTCAP; 356 } 357 358 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 359 360 return 0; 361 } 362 363 static int 364 axe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 365 { 366 struct axe_softc *sc = device_private(dev); 367 int rv; 368 369 if (sc->axe_dying) 370 return -1; 371 372 if (sc->axe_phyno != phy) 373 return -1; 374 375 axe_lock_mii(sc); 376 rv = axe_miibus_readreg_locked(dev, phy, reg, val); 377 axe_unlock_mii(sc); 378 379 return rv; 380 } 381 382 static int 383 axe_miibus_writereg_locked(device_t dev, int phy, int reg, uint16_t aval) 384 { 385 struct axe_softc *sc = device_private(dev); 386 usbd_status err; 387 uint16_t val; 388 389 val = htole16(aval); 390 391 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 392 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 393 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 394 395 if (err) { 396 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 397 return err; 398 } 399 400 return 0; 401 } 402 403 static int 404 axe_miibus_writereg(device_t dev, int phy, int reg, uint16_t aval) 405 { 406 struct axe_softc *sc = device_private(dev); 407 int rv; 408 409 if (sc->axe_dying) 410 return -1; 411 412 if (sc->axe_phyno != phy) 413 return -1; 414 415 axe_lock_mii(sc); 416 rv = axe_miibus_writereg_locked(dev, phy, reg, aval); 417 axe_unlock_mii(sc); 418 419 return rv; 420 } 421 422 static void 423 axe_miibus_statchg(struct ifnet *ifp) 424 { 425 AXEHIST_FUNC(); AXEHIST_CALLED(); 426 427 struct axe_softc *sc = ifp->if_softc; 428 struct mii_data *mii = &sc->axe_mii; 429 int val, err; 430 431 val = 0; 432 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 433 val |= AXE_MEDIA_FULL_DUPLEX; 434 if (AXE_IS_178_FAMILY(sc)) { 435 if ((IFM_OPTIONS(mii->mii_media_active) & 436 IFM_ETH_TXPAUSE) != 0) 437 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 438 if ((IFM_OPTIONS(mii->mii_media_active) & 439 IFM_ETH_RXPAUSE) != 0) 440 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 441 } 442 } 443 if (AXE_IS_178_FAMILY(sc)) { 444 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 445 if (sc->axe_flags & AX178) 446 val |= AXE_178_MEDIA_ENCK; 447 switch (IFM_SUBTYPE(mii->mii_media_active)) { 448 case IFM_1000_T: 449 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 450 break; 451 case IFM_100_TX: 452 val |= AXE_178_MEDIA_100TX; 453 break; 454 case IFM_10_T: 455 /* doesn't need to be handled */ 456 break; 457 } 458 } 459 460 DPRINTF("val=0x%jx", val, 0, 0, 0); 461 axe_lock_mii(sc); 462 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 463 axe_unlock_mii(sc); 464 if (err) { 465 aprint_error_dev(sc->axe_dev, "media change failed\n"); 466 return; 467 } 468 } 469 470 static void 471 axe_setmulti(struct axe_softc *sc) 472 { 473 AXEHIST_FUNC(); AXEHIST_CALLED(); 474 struct ifnet *ifp = &sc->sc_if; 475 struct ether_multi *enm; 476 struct ether_multistep step; 477 uint32_t h = 0; 478 uint16_t rxmode; 479 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 480 481 if (sc->axe_dying) 482 return; 483 484 axe_lock_mii(sc); 485 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 486 axe_unlock_mii(sc); 487 aprint_error_dev(sc->axe_dev, "can't read rxmode"); 488 return; 489 } 490 rxmode = le16toh(rxmode); 491 492 rxmode &= 493 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 494 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 495 496 rxmode |= 497 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 498 499 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 500 if (ifp->if_flags & IFF_PROMISC) 501 rxmode |= AXE_RXCMD_PROMISC; 502 goto allmulti; 503 } 504 505 /* Now program new ones */ 506 ETHER_FIRST_MULTI(step, &sc->axe_ec, enm); 507 while (enm != NULL) { 508 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 509 ETHER_ADDR_LEN) != 0) 510 goto allmulti; 511 512 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 513 hashtbl[h >> 3] |= 1U << (h & 7); 514 ETHER_NEXT_MULTI(step, enm); 515 } 516 ifp->if_flags &= ~IFF_ALLMULTI; 517 rxmode |= AXE_RXCMD_MULTICAST; 518 519 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 520 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 521 axe_unlock_mii(sc); 522 return; 523 524 allmulti: 525 ifp->if_flags |= IFF_ALLMULTI; 526 rxmode |= AXE_RXCMD_ALLMULTI; 527 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 528 axe_unlock_mii(sc); 529 } 530 531 static void 532 axe_ax_init(struct axe_softc *sc) 533 { 534 int cmd = AXE_178_CMD_READ_NODEID; 535 536 if (sc->axe_flags & AX178) { 537 axe_ax88178_init(sc); 538 } else if (sc->axe_flags & AX772) { 539 axe_ax88772_init(sc); 540 } else if (sc->axe_flags & AX772A) { 541 axe_ax88772a_init(sc); 542 } else if (sc->axe_flags & AX772B) { 543 axe_ax88772b_init(sc); 544 return; 545 } else { 546 cmd = AXE_172_CMD_READ_NODEID; 547 } 548 549 if (axe_cmd(sc, cmd, 0, 0, sc->axe_enaddr)) { 550 aprint_error_dev(sc->axe_dev, 551 "failed to read ethernet address\n"); 552 } 553 } 554 555 556 static void 557 axe_reset(struct axe_softc *sc) 558 { 559 560 if (sc->axe_dying) 561 return; 562 563 /* 564 * softnet_lock can be taken when NET_MPAFE is not defined when calling 565 * if_addr_init -> if_init. This doesn't mixe well with the 566 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 567 * can fire during the wait and attempt to take softnet_lock and then 568 * block the softclk thread meaing the wait never ends. 569 */ 570 #ifndef NET_MPSAFE 571 /* XXX What to reset? */ 572 573 /* Wait a little while for the chip to get its brains in order. */ 574 DELAY(1000); 575 #else 576 axe_lock_mii(sc); 577 578 axe_ax_init(sc); 579 580 axe_unlock_mii(sc); 581 #endif 582 } 583 584 static int 585 axe_get_phyno(struct axe_softc *sc, int sel) 586 { 587 int phyno; 588 589 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 590 case PHY_TYPE_100_HOME: 591 /* FALLTHROUGH */ 592 case PHY_TYPE_GIG: 593 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 594 break; 595 case PHY_TYPE_SPECIAL: 596 /* FALLTHROUGH */ 597 case PHY_TYPE_RSVD: 598 /* FALLTHROUGH */ 599 case PHY_TYPE_NON_SUP: 600 /* FALLTHROUGH */ 601 default: 602 phyno = -1; 603 break; 604 } 605 606 return phyno; 607 } 608 609 #define AXE_GPIO_WRITE(x, y) do { \ 610 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 611 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 612 } while (0) 613 614 static void 615 axe_ax88178_init(struct axe_softc *sc) 616 { 617 AXEHIST_FUNC(); AXEHIST_CALLED(); 618 int gpio0, ledmode, phymode; 619 uint16_t eeprom, val; 620 621 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 622 /* XXX magic */ 623 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 624 eeprom = 0xffff; 625 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 626 627 eeprom = le16toh(eeprom); 628 629 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 630 631 /* if EEPROM is invalid we have to use to GPIO0 */ 632 if (eeprom == 0xffff) { 633 phymode = AXE_PHY_MODE_MARVELL; 634 gpio0 = 1; 635 ledmode = 0; 636 } else { 637 phymode = eeprom & 0x7f; 638 gpio0 = (eeprom & 0x80) ? 0 : 1; 639 ledmode = eeprom >> 8; 640 } 641 642 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 643 644 /* Program GPIOs depending on PHY hardware. */ 645 switch (phymode) { 646 case AXE_PHY_MODE_MARVELL: 647 if (gpio0 == 1) { 648 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 649 hz / 32); 650 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 651 hz / 32); 652 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 653 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 654 hz / 32); 655 } else { 656 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 657 AXE_GPIO1_EN, hz / 3); 658 if (ledmode == 1) { 659 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 660 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 661 hz / 3); 662 } else { 663 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 664 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 665 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 666 AXE_GPIO2_EN, hz / 4); 667 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 668 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 669 } 670 } 671 break; 672 case AXE_PHY_MODE_CICADA: 673 case AXE_PHY_MODE_CICADA_V2: 674 case AXE_PHY_MODE_CICADA_V2_ASIX: 675 if (gpio0 == 1) 676 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 677 AXE_GPIO0_EN, hz / 32); 678 else 679 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 680 AXE_GPIO1_EN, hz / 32); 681 break; 682 case AXE_PHY_MODE_AGERE: 683 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 684 AXE_GPIO1_EN, hz / 32); 685 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 686 AXE_GPIO2_EN, hz / 32); 687 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 688 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 689 AXE_GPIO2_EN, hz / 32); 690 break; 691 case AXE_PHY_MODE_REALTEK_8211CL: 692 case AXE_PHY_MODE_REALTEK_8211BN: 693 case AXE_PHY_MODE_REALTEK_8251CL: 694 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 695 AXE_GPIO1 | AXE_GPIO1_EN; 696 AXE_GPIO_WRITE(val, hz / 32); 697 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 698 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 699 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 700 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 701 axe_miibus_writereg_locked(sc->axe_dev, 702 sc->axe_phyno, 0x1F, 0x0005); 703 axe_miibus_writereg_locked(sc->axe_dev, 704 sc->axe_phyno, 0x0C, 0x0000); 705 axe_miibus_readreg_locked(sc->axe_dev, 706 sc->axe_phyno, 0x0001, &val); 707 axe_miibus_writereg_locked(sc->axe_dev, 708 sc->axe_phyno, 0x01, val | 0x0080); 709 axe_miibus_writereg_locked(sc->axe_dev, 710 sc->axe_phyno, 0x1F, 0x0000); 711 } 712 break; 713 default: 714 /* Unknown PHY model or no need to program GPIOs. */ 715 break; 716 } 717 718 /* soft reset */ 719 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 720 usbd_delay_ms(sc->axe_udev, 150); 721 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 722 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 723 usbd_delay_ms(sc->axe_udev, 150); 724 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 725 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 726 usbd_delay_ms(sc->axe_udev, 10); 727 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 728 } 729 730 static void 731 axe_ax88772_init(struct axe_softc *sc) 732 { 733 AXEHIST_FUNC(); AXEHIST_CALLED(); 734 735 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 736 usbd_delay_ms(sc->axe_udev, 40); 737 738 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 739 /* ask for the embedded PHY */ 740 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 741 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 742 usbd_delay_ms(sc->axe_udev, 10); 743 744 /* power down and reset state, pin reset state */ 745 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 746 usbd_delay_ms(sc->axe_udev, 60); 747 748 /* power down/reset state, pin operating state */ 749 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 750 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 751 usbd_delay_ms(sc->axe_udev, 150); 752 753 /* power up, reset */ 754 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 755 756 /* power up, operating */ 757 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 758 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 759 } else { 760 /* ask for external PHY */ 761 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 762 NULL); 763 usbd_delay_ms(sc->axe_udev, 10); 764 765 /* power down internal PHY */ 766 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 767 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 768 } 769 770 usbd_delay_ms(sc->axe_udev, 150); 771 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 772 } 773 774 static void 775 axe_ax88772_phywake(struct axe_softc *sc) 776 { 777 AXEHIST_FUNC(); AXEHIST_CALLED(); 778 779 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 780 /* Manually select internal(embedded) PHY - MAC mode. */ 781 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 782 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 783 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 784 } else { 785 /* 786 * Manually select external PHY - MAC mode. 787 * Reverse MII/RMII is for AX88772A PHY mode. 788 */ 789 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 790 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 791 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 792 } 793 794 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 795 AXE_SW_RESET_IPRL, NULL); 796 797 /* T1 = min 500ns everywhere */ 798 usbd_delay_ms(sc->axe_udev, 150); 799 800 /* Take PHY out of power down. */ 801 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 802 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 803 } else { 804 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 805 } 806 807 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 808 usbd_delay_ms(sc->axe_udev, 600); 809 810 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 811 812 /* T3 = 500ns everywhere */ 813 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 814 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 815 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 816 } 817 818 static void 819 axe_ax88772a_init(struct axe_softc *sc) 820 { 821 AXEHIST_FUNC(); AXEHIST_CALLED(); 822 823 /* Reload EEPROM. */ 824 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 825 axe_ax88772_phywake(sc); 826 /* Stop MAC. */ 827 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 828 } 829 830 static void 831 axe_ax88772b_init(struct axe_softc *sc) 832 { 833 AXEHIST_FUNC(); AXEHIST_CALLED(); 834 uint16_t eeprom; 835 int i; 836 837 /* Reload EEPROM. */ 838 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 839 840 /* 841 * Save PHY power saving configuration(high byte) and 842 * clear EEPROM checksum value(low byte). 843 */ 844 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 845 &eeprom)) { 846 aprint_error_dev(sc->axe_dev, "failed to read eeprom\n"); 847 return; 848 } 849 850 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 851 852 /* 853 * Auto-loaded default station address from internal ROM is 854 * 00:00:00:00:00:00 such that an explicit access to EEPROM 855 * is required to get real station address. 856 */ 857 uint8_t *eaddr = sc->axe_enaddr; 858 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 859 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 860 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 861 aprint_error_dev(sc->axe_dev, 862 "failed to read eeprom\n"); 863 eeprom = 0; 864 } 865 eeprom = le16toh(eeprom); 866 *eaddr++ = (uint8_t)(eeprom & 0xFF); 867 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 868 } 869 /* Wakeup PHY. */ 870 axe_ax88772_phywake(sc); 871 /* Stop MAC. */ 872 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 873 } 874 875 #undef AXE_GPIO_WRITE 876 877 /* 878 * Probe for a AX88172 chip. 879 */ 880 int 881 axe_match(device_t parent, cfdata_t match, void *aux) 882 { 883 struct usb_attach_arg *uaa = aux; 884 885 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 886 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 887 } 888 889 /* 890 * Attach the interface. Allocate softc structures, do ifmedia 891 * setup and ethernet/BPF attach. 892 */ 893 void 894 axe_attach(device_t parent, device_t self, void *aux) 895 { 896 AXEHIST_FUNC(); AXEHIST_CALLED(); 897 struct axe_softc *sc = device_private(self); 898 struct usb_attach_arg *uaa = aux; 899 struct usbd_device *dev = uaa->uaa_device; 900 usbd_status err; 901 usb_interface_descriptor_t *id; 902 usb_endpoint_descriptor_t *ed; 903 struct mii_data *mii; 904 char *devinfop; 905 const char *devname = device_xname(self); 906 struct ifnet *ifp; 907 int i, s; 908 909 aprint_naive("\n"); 910 aprint_normal("\n"); 911 912 sc->axe_dev = self; 913 sc->axe_udev = dev; 914 915 devinfop = usbd_devinfo_alloc(dev, 0); 916 aprint_normal_dev(self, "%s\n", devinfop); 917 usbd_devinfo_free(devinfop); 918 919 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 920 if (err) { 921 aprint_error_dev(self, "failed to set configuration" 922 ", err=%s\n", usbd_errstr(err)); 923 return; 924 } 925 926 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 927 928 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 929 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 930 931 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 932 if (err) { 933 aprint_error_dev(self, "getting interface handle failed\n"); 934 return; 935 } 936 937 sc->axe_product = uaa->uaa_product; 938 sc->axe_vendor = uaa->uaa_vendor; 939 940 id = usbd_get_interface_descriptor(sc->axe_iface); 941 942 /* decide on what our bufsize will be */ 943 if (AXE_IS_178_FAMILY(sc)) 944 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 945 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 946 else 947 sc->axe_bufsz = AXE_172_BUFSZ; 948 949 sc->axe_ed[AXE_ENDPT_RX] = -1; 950 sc->axe_ed[AXE_ENDPT_TX] = -1; 951 sc->axe_ed[AXE_ENDPT_INTR] = -1; 952 953 /* Find endpoints. */ 954 for (i = 0; i < id->bNumEndpoints; i++) { 955 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 956 if (ed == NULL) { 957 aprint_error_dev(self, "couldn't get ep %d\n", i); 958 return; 959 } 960 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 961 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 962 963 if (dir == UE_DIR_IN && xt == UE_BULK && 964 sc->axe_ed[AXE_ENDPT_RX] == -1) { 965 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 966 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 967 sc->axe_ed[AXE_ENDPT_TX] == -1) { 968 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 969 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 970 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 971 } 972 } 973 974 s = splnet(); 975 976 /* We need the PHYID for init dance in some cases */ 977 axe_lock_mii(sc); 978 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 979 aprint_error_dev(self, "failed to read phyaddrs\n"); 980 return; 981 } 982 983 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 984 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 985 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 986 if (sc->axe_phyno == -1) 987 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 988 if (sc->axe_phyno == -1) { 989 DPRINTF(" no valid PHY address found, assuming PHY address 0", 990 0, 0, 0, 0); 991 sc->axe_phyno = 0; 992 } 993 994 /* Initialize controller and get station address. */ 995 996 axe_ax_init(sc); 997 998 /* 999 * Fetch IPG values. 1000 */ 1001 if (sc->axe_flags & (AX772A | AX772B)) { 1002 /* Set IPG values. */ 1003 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 1004 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 1005 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1006 } else { 1007 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 1008 aprint_error_dev(self, "failed to read ipg\n"); 1009 return; 1010 } 1011 } 1012 1013 axe_unlock_mii(sc); 1014 1015 /* 1016 * An ASIX chip was detected. Inform the world. 1017 */ 1018 aprint_normal_dev(self, "Ethernet address %s\n", 1019 ether_sprintf(sc->axe_enaddr)); 1020 1021 /* Initialize interface info.*/ 1022 ifp = &sc->sc_if; 1023 ifp->if_softc = sc; 1024 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 1025 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1026 ifp->if_ioctl = axe_ioctl; 1027 ifp->if_start = axe_start; 1028 ifp->if_init = axe_init; 1029 ifp->if_stop = axe_stop; 1030 ifp->if_watchdog = axe_watchdog; 1031 1032 IFQ_SET_READY(&ifp->if_snd); 1033 1034 if (AXE_IS_178_FAMILY(sc)) 1035 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1036 if (sc->axe_flags & AX772B) { 1037 ifp->if_capabilities = 1038 IFCAP_CSUM_IPv4_Rx | 1039 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1040 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1041 /* 1042 * Checksum offloading of AX88772B also works with VLAN 1043 * tagged frames but there is no way to take advantage 1044 * of the feature because vlan(4) assumes 1045 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1046 * support checksum offloading with VLAN. VLAN hardware 1047 * tagging support of AX88772B is very limited so it's 1048 * not possible to announce IFCAP_VLAN_HWTAGGING. 1049 */ 1050 } 1051 u_int adv_pause; 1052 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1053 adv_pause = MIIF_DOPAUSE; 1054 else 1055 adv_pause = 0; 1056 adv_pause = 0; 1057 1058 /* Initialize MII/media info. */ 1059 mii = &sc->axe_mii; 1060 mii->mii_ifp = ifp; 1061 mii->mii_readreg = axe_miibus_readreg; 1062 mii->mii_writereg = axe_miibus_writereg; 1063 mii->mii_statchg = axe_miibus_statchg; 1064 mii->mii_flags = MIIF_AUTOTSLEEP; 1065 1066 sc->axe_ec.ec_mii = mii; 1067 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1068 1069 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1070 adv_pause); 1071 1072 if (LIST_EMPTY(&mii->mii_phys)) { 1073 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1074 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1075 } else 1076 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1077 1078 /* Attach the interface. */ 1079 if_attach(ifp); 1080 ether_ifattach(ifp, sc->axe_enaddr); 1081 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1082 RND_TYPE_NET, RND_FLAG_DEFAULT); 1083 1084 callout_init(&sc->axe_stat_ch, 0); 1085 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1086 1087 sc->axe_attached = true; 1088 splx(s); 1089 1090 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1091 1092 if (!pmf_device_register(self, NULL, NULL)) 1093 aprint_error_dev(self, "couldn't establish power handler\n"); 1094 } 1095 1096 int 1097 axe_detach(device_t self, int flags) 1098 { 1099 AXEHIST_FUNC(); AXEHIST_CALLED(); 1100 struct axe_softc *sc = device_private(self); 1101 int s; 1102 struct ifnet *ifp = &sc->sc_if; 1103 1104 /* Detached before attached finished, so just bail out. */ 1105 if (!sc->axe_attached) 1106 return 0; 1107 1108 pmf_device_deregister(self); 1109 1110 sc->axe_dying = true; 1111 1112 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1113 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1114 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1115 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1116 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1117 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1118 1119 callout_halt(&sc->axe_stat_ch, NULL); 1120 usb_rem_task_wait(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER, 1121 NULL); 1122 1123 s = splusb(); 1124 1125 if (ifp->if_flags & IFF_RUNNING) 1126 axe_stop(ifp, 1); 1127 1128 1129 if (--sc->axe_refcnt >= 0) { 1130 /* Wait for processes to go away. */ 1131 usb_detach_waitold(sc->axe_dev); 1132 } 1133 1134 callout_destroy(&sc->axe_stat_ch); 1135 mutex_destroy(&sc->axe_mii_lock); 1136 rnd_detach_source(&sc->rnd_source); 1137 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1138 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1139 ether_ifdetach(ifp); 1140 if_detach(ifp); 1141 1142 #ifdef DIAGNOSTIC 1143 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1144 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1145 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1146 aprint_debug_dev(self, "detach has active endpoints\n"); 1147 #endif 1148 1149 sc->axe_attached = false; 1150 1151 splx(s); 1152 1153 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1154 1155 return 0; 1156 } 1157 1158 int 1159 axe_activate(device_t self, devact_t act) 1160 { 1161 AXEHIST_FUNC(); AXEHIST_CALLED(); 1162 struct axe_softc *sc = device_private(self); 1163 1164 switch (act) { 1165 case DVACT_DEACTIVATE: 1166 if_deactivate(&sc->axe_ec.ec_if); 1167 sc->axe_dying = true; 1168 return 0; 1169 default: 1170 return EOPNOTSUPP; 1171 } 1172 } 1173 1174 static int 1175 axe_rx_list_init(struct axe_softc *sc) 1176 { 1177 AXEHIST_FUNC(); AXEHIST_CALLED(); 1178 1179 struct axe_cdata *cd; 1180 struct axe_chain *c; 1181 int i; 1182 1183 cd = &sc->axe_cdata; 1184 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1185 c = &cd->axe_rx_chain[i]; 1186 c->axe_sc = sc; 1187 c->axe_idx = i; 1188 if (c->axe_xfer == NULL) { 1189 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1190 sc->axe_bufsz, 0, 0, &c->axe_xfer); 1191 if (err) 1192 return err; 1193 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1194 } 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int 1201 axe_tx_list_init(struct axe_softc *sc) 1202 { 1203 AXEHIST_FUNC(); AXEHIST_CALLED(); 1204 struct axe_cdata *cd; 1205 struct axe_chain *c; 1206 int i; 1207 1208 cd = &sc->axe_cdata; 1209 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1210 c = &cd->axe_tx_chain[i]; 1211 c->axe_sc = sc; 1212 c->axe_idx = i; 1213 if (c->axe_xfer == NULL) { 1214 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1215 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1216 &c->axe_xfer); 1217 if (err) 1218 return err; 1219 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1220 } 1221 } 1222 1223 return 0; 1224 } 1225 1226 /* 1227 * A frame has been uploaded: pass the resulting mbuf chain up to 1228 * the higher level protocols. 1229 */ 1230 static void 1231 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1232 { 1233 AXEHIST_FUNC(); AXEHIST_CALLED(); 1234 struct axe_softc *sc; 1235 struct axe_chain *c; 1236 struct ifnet *ifp; 1237 uint8_t *buf; 1238 uint32_t total_len; 1239 struct mbuf *m; 1240 int s; 1241 1242 c = (struct axe_chain *)priv; 1243 sc = c->axe_sc; 1244 buf = c->axe_buf; 1245 ifp = &sc->sc_if; 1246 1247 if (sc->axe_dying) 1248 return; 1249 1250 if ((ifp->if_flags & IFF_RUNNING) == 0) 1251 return; 1252 1253 if (status != USBD_NORMAL_COMPLETION) { 1254 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1255 return; 1256 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1257 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1258 usbd_errstr(status)); 1259 } 1260 if (status == USBD_STALLED) 1261 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1262 goto done; 1263 } 1264 1265 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1266 1267 do { 1268 u_int pktlen = 0; 1269 u_int rxlen = 0; 1270 int flags = 0; 1271 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1272 struct axe_sframe_hdr hdr; 1273 1274 if (total_len < sizeof(hdr)) { 1275 ifp->if_ierrors++; 1276 goto done; 1277 } 1278 1279 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1280 /* 1281 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1282 * For some architectures, __builtin_memcpy() of 1283 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1284 * at onece, which results in alignment error. 1285 */ 1286 hdr.len = *(uint16_t *)buf; 1287 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1288 #else 1289 memcpy(&hdr, buf, sizeof(hdr)); 1290 #endif 1291 1292 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1293 total_len, 1294 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1295 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1296 1297 total_len -= sizeof(hdr); 1298 buf += sizeof(hdr); 1299 1300 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1301 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1302 AXE_RH1M_RXLEN_MASK) { 1303 ifp->if_ierrors++; 1304 goto done; 1305 } 1306 1307 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1308 if (total_len < rxlen) { 1309 pktlen = total_len; 1310 total_len = 0; 1311 } else { 1312 pktlen = rxlen; 1313 rxlen = roundup2(rxlen, 2); 1314 total_len -= rxlen; 1315 } 1316 1317 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1318 struct axe_csum_hdr csum_hdr; 1319 1320 if (total_len < sizeof(csum_hdr)) { 1321 ifp->if_ierrors++; 1322 goto done; 1323 } 1324 1325 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1326 1327 csum_hdr.len = le16toh(csum_hdr.len); 1328 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1329 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1330 1331 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1332 " cstatus %#jx", total_len, 1333 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1334 1335 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1336 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1337 sc->sc_lenmask) { 1338 /* we lost sync */ 1339 ifp->if_ierrors++; 1340 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1341 "err", 1342 AXE_CSUM_RXBYTES(csum_hdr.len), 1343 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1344 sc->sc_lenmask, 0); 1345 goto done; 1346 } 1347 /* 1348 * Get total transferred frame length including 1349 * checksum header. The length should be multiple 1350 * of 4. 1351 */ 1352 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1353 u_int len = sizeof(csum_hdr) + pktlen; 1354 len = (len + 3) & ~3; 1355 if (total_len < len) { 1356 DPRINTFN(20, "total_len %#jx < len %#jx", 1357 total_len, len, 0, 0); 1358 /* invalid length */ 1359 ifp->if_ierrors++; 1360 goto done; 1361 } 1362 buf += sizeof(csum_hdr); 1363 1364 const uint16_t cstatus = csum_hdr.cstatus; 1365 1366 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1367 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1368 flags |= M_CSUM_TCP_UDP_BAD; 1369 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1370 flags |= M_CSUM_IPv4_BAD; 1371 1372 const uint16_t l4type = 1373 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1374 1375 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1376 flags |= M_CSUM_TCPv4; 1377 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1378 flags |= M_CSUM_UDPv4; 1379 } 1380 if (total_len < len) { 1381 pktlen = total_len; 1382 total_len = 0; 1383 } else { 1384 total_len -= len; 1385 rxlen = len - sizeof(csum_hdr); 1386 } 1387 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1388 " rxlen %#jx", total_len, len, pktlen, rxlen); 1389 } else { /* AX172 */ 1390 pktlen = rxlen = total_len; 1391 total_len = 0; 1392 } 1393 1394 MGETHDR(m, M_DONTWAIT, MT_DATA); 1395 if (m == NULL) { 1396 ifp->if_ierrors++; 1397 goto done; 1398 } 1399 1400 if (pktlen > MHLEN - ETHER_ALIGN) { 1401 MCLGET(m, M_DONTWAIT); 1402 if ((m->m_flags & M_EXT) == 0) { 1403 m_freem(m); 1404 ifp->if_ierrors++; 1405 goto done; 1406 } 1407 } 1408 m->m_data += ETHER_ALIGN; 1409 1410 m_set_rcvif(m, ifp); 1411 m->m_pkthdr.len = m->m_len = pktlen; 1412 m->m_pkthdr.csum_flags = flags; 1413 1414 memcpy(mtod(m, uint8_t *), buf, pktlen); 1415 buf += rxlen; 1416 1417 DPRINTFN(10, "deliver %jd (%#jx)", m->m_len, m->m_len, 0, 0); 1418 1419 s = splnet(); 1420 1421 if_percpuq_enqueue((ifp)->if_percpuq, (m)); 1422 1423 splx(s); 1424 1425 } while (total_len > 0); 1426 1427 done: 1428 1429 /* Setup new transfer. */ 1430 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1431 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1432 usbd_transfer(xfer); 1433 1434 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1435 } 1436 1437 /* 1438 * A frame was downloaded to the chip. It's safe for us to clean up 1439 * the list buffers. 1440 */ 1441 1442 static void 1443 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1444 { 1445 AXEHIST_FUNC(); AXEHIST_CALLED(); 1446 struct axe_chain *c = priv; 1447 struct axe_softc *sc = c->axe_sc; 1448 struct ifnet *ifp = &sc->sc_if; 1449 int s; 1450 1451 1452 if (sc->axe_dying) 1453 return; 1454 1455 s = splnet(); 1456 1457 ifp->if_timer = 0; 1458 ifp->if_flags &= ~IFF_OACTIVE; 1459 1460 if (status != USBD_NORMAL_COMPLETION) { 1461 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1462 splx(s); 1463 return; 1464 } 1465 ifp->if_oerrors++; 1466 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1467 usbd_errstr(status)); 1468 if (status == USBD_STALLED) 1469 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1470 splx(s); 1471 return; 1472 } 1473 ifp->if_opackets++; 1474 1475 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1476 axe_start(ifp); 1477 1478 splx(s); 1479 } 1480 1481 static void 1482 axe_tick(void *xsc) 1483 { 1484 AXEHIST_FUNC(); AXEHIST_CALLED(); 1485 struct axe_softc *sc = xsc; 1486 1487 if (sc == NULL) 1488 return; 1489 1490 if (sc->axe_dying) 1491 return; 1492 1493 /* Perform periodic stuff in process context */ 1494 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1495 } 1496 1497 static void 1498 axe_tick_task(void *xsc) 1499 { 1500 AXEHIST_FUNC(); AXEHIST_CALLED(); 1501 int s; 1502 struct axe_softc *sc = xsc; 1503 struct ifnet *ifp; 1504 struct mii_data *mii; 1505 1506 if (sc == NULL) 1507 return; 1508 1509 if (sc->axe_dying) 1510 return; 1511 1512 ifp = &sc->sc_if; 1513 mii = &sc->axe_mii; 1514 1515 if (mii == NULL) 1516 return; 1517 1518 s = splnet(); 1519 1520 mii_tick(mii); 1521 if (sc->axe_link == 0 && 1522 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1523 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1524 DPRINTF("got link", 0, 0, 0, 0); 1525 sc->axe_link++; 1526 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1527 axe_start(ifp); 1528 } 1529 1530 callout_schedule(&sc->axe_stat_ch, hz); 1531 1532 splx(s); 1533 } 1534 1535 static int 1536 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1537 { 1538 struct ifnet *ifp = &sc->sc_if; 1539 struct axe_chain *c; 1540 usbd_status err; 1541 int length, boundary; 1542 1543 c = &sc->axe_cdata.axe_tx_chain[idx]; 1544 1545 /* 1546 * Copy the mbuf data into a contiguous buffer, leaving two 1547 * bytes at the beginning to hold the frame length. 1548 */ 1549 if (AXE_IS_178_FAMILY(sc)) { 1550 struct axe_sframe_hdr hdr; 1551 1552 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1553 1554 hdr.len = htole16(m->m_pkthdr.len); 1555 hdr.ilen = ~hdr.len; 1556 1557 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1558 length = sizeof(hdr); 1559 1560 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1561 length += m->m_pkthdr.len; 1562 1563 if ((length % boundary) == 0) { 1564 hdr.len = 0x0000; 1565 hdr.ilen = 0xffff; 1566 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1567 length += sizeof(hdr); 1568 } 1569 } else { 1570 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1571 length = m->m_pkthdr.len; 1572 } 1573 1574 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1575 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1576 1577 /* Transmit */ 1578 err = usbd_transfer(c->axe_xfer); 1579 if (err != USBD_IN_PROGRESS) { 1580 axe_stop(ifp, 0); 1581 return EIO; 1582 } 1583 1584 sc->axe_cdata.axe_tx_cnt++; 1585 1586 return 0; 1587 } 1588 1589 1590 static void 1591 axe_csum_cfg(struct axe_softc *sc) 1592 { 1593 struct ifnet *ifp = &sc->sc_if; 1594 uint16_t csum1, csum2; 1595 1596 if ((sc->axe_flags & AX772B) != 0) { 1597 csum1 = 0; 1598 csum2 = 0; 1599 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1600 csum1 |= AXE_TXCSUM_IP; 1601 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1602 csum1 |= AXE_TXCSUM_TCP; 1603 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1604 csum1 |= AXE_TXCSUM_UDP; 1605 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1606 csum1 |= AXE_TXCSUM_TCPV6; 1607 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1608 csum1 |= AXE_TXCSUM_UDPV6; 1609 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1610 csum1 = 0; 1611 csum2 = 0; 1612 1613 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1614 csum1 |= AXE_RXCSUM_IP; 1615 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1616 csum1 |= AXE_RXCSUM_TCP; 1617 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1618 csum1 |= AXE_RXCSUM_UDP; 1619 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1620 csum1 |= AXE_RXCSUM_TCPV6; 1621 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1622 csum1 |= AXE_RXCSUM_UDPV6; 1623 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1624 } 1625 } 1626 1627 static void 1628 axe_start(struct ifnet *ifp) 1629 { 1630 struct axe_softc *sc; 1631 struct mbuf *m; 1632 1633 sc = ifp->if_softc; 1634 1635 if ((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING)) != IFF_RUNNING) 1636 return; 1637 1638 IFQ_POLL(&ifp->if_snd, m); 1639 if (m == NULL) { 1640 return; 1641 } 1642 1643 if (axe_encap(sc, m, 0)) { 1644 ifp->if_flags |= IFF_OACTIVE; 1645 return; 1646 } 1647 IFQ_DEQUEUE(&ifp->if_snd, m); 1648 1649 /* 1650 * If there's a BPF listener, bounce a copy of this frame 1651 * to him. 1652 */ 1653 bpf_mtap(ifp, m, BPF_D_OUT); 1654 m_freem(m); 1655 1656 ifp->if_flags |= IFF_OACTIVE; 1657 1658 /* 1659 * Set a timeout in case the chip goes out to lunch. 1660 */ 1661 ifp->if_timer = 5; 1662 1663 return; 1664 } 1665 1666 static int 1667 axe_init(struct ifnet *ifp) 1668 { 1669 AXEHIST_FUNC(); AXEHIST_CALLED(); 1670 struct axe_softc *sc = ifp->if_softc; 1671 struct axe_chain *c; 1672 usbd_status err; 1673 int rxmode; 1674 int i, s; 1675 1676 s = splnet(); 1677 1678 if (ifp->if_flags & IFF_RUNNING) 1679 axe_stop(ifp, 0); 1680 1681 /* 1682 * Cancel pending I/O and free all RX/TX buffers. 1683 */ 1684 axe_reset(sc); 1685 1686 axe_lock_mii(sc); 1687 1688 #if 0 1689 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1690 AX_GPIO_GPO2EN, 5, in_pm); 1691 #endif 1692 /* Set MAC address and transmitter IPG values. */ 1693 if (AXE_IS_178_FAMILY(sc)) { 1694 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1695 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1696 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1697 } else { 1698 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1699 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1700 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1701 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1702 } 1703 if (AXE_IS_178_FAMILY(sc)) { 1704 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1705 if ((sc->axe_flags & AX772B) != 0 && 1706 (ifp->if_capenable & AX_RXCSUM) != 0) { 1707 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1708 sc->axe_flags |= AXCSUM_FRAME; 1709 } else { 1710 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1711 sc->axe_flags |= AXSTD_FRAME; 1712 } 1713 } 1714 1715 /* Configure TX/RX checksum offloading. */ 1716 axe_csum_cfg(sc); 1717 1718 if (sc->axe_flags & AX772B) { 1719 /* AX88772B uses different maximum frame burst configuration. */ 1720 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1721 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1722 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1723 } 1724 /* Enable receiver, set RX mode */ 1725 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1726 if (AXE_IS_178_FAMILY(sc)) { 1727 if (sc->axe_flags & AX772B) { 1728 /* 1729 * Select RX header format type 1. Aligning IP 1730 * header on 4 byte boundary is not needed when 1731 * checksum offloading feature is not used 1732 * because we always copy the received frame in 1733 * RX handler. When RX checksum offloading is 1734 * active, aligning IP header is required to 1735 * reflect actual frame length including RX 1736 * header size. 1737 */ 1738 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1739 if (sc->axe_flags & AXCSUM_FRAME) 1740 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1741 } else { 1742 /* 1743 * Default Rx buffer size is too small to get 1744 * maximum performance. 1745 */ 1746 #if 0 1747 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1748 /* Largest possible USB buffer size for AX88178 */ 1749 #endif 1750 rxmode |= AXE_178_RXCMD_MFB_16384; 1751 } 1752 } else { 1753 rxmode |= AXE_172_RXCMD_UNICAST; 1754 } 1755 1756 1757 /* If we want promiscuous mode, set the allframes bit. */ 1758 if (ifp->if_flags & IFF_PROMISC) 1759 rxmode |= AXE_RXCMD_PROMISC; 1760 1761 if (ifp->if_flags & IFF_BROADCAST) 1762 rxmode |= AXE_RXCMD_BROADCAST; 1763 1764 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1765 1766 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1767 axe_unlock_mii(sc); 1768 1769 /* Load the multicast filter. */ 1770 axe_setmulti(sc); 1771 1772 /* Open RX and TX pipes. */ 1773 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1774 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1775 if (err) { 1776 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1777 usbd_errstr(err)); 1778 splx(s); 1779 return EIO; 1780 } 1781 1782 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1783 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1784 if (err) { 1785 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1786 usbd_errstr(err)); 1787 splx(s); 1788 return EIO; 1789 } 1790 1791 /* Init RX ring. */ 1792 if (axe_rx_list_init(sc) != 0) { 1793 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1794 splx(s); 1795 return ENOBUFS; 1796 } 1797 1798 /* Init TX ring. */ 1799 if (axe_tx_list_init(sc) != 0) { 1800 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1801 splx(s); 1802 return ENOBUFS; 1803 } 1804 1805 /* Start up the receive pipe. */ 1806 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1807 c = &sc->axe_cdata.axe_rx_chain[i]; 1808 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1809 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1810 usbd_transfer(c->axe_xfer); 1811 } 1812 1813 ifp->if_flags |= IFF_RUNNING; 1814 ifp->if_flags &= ~IFF_OACTIVE; 1815 1816 splx(s); 1817 1818 callout_schedule(&sc->axe_stat_ch, hz); 1819 return 0; 1820 } 1821 1822 static int 1823 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1824 { 1825 struct axe_softc *sc = ifp->if_softc; 1826 int s; 1827 int error = 0; 1828 1829 s = splnet(); 1830 1831 switch(cmd) { 1832 case SIOCSIFFLAGS: 1833 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1834 break; 1835 1836 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1837 case IFF_RUNNING: 1838 axe_stop(ifp, 1); 1839 break; 1840 case IFF_UP: 1841 axe_init(ifp); 1842 break; 1843 case IFF_UP | IFF_RUNNING: 1844 if ((ifp->if_flags ^ sc->axe_if_flags) == IFF_PROMISC) 1845 axe_setmulti(sc); 1846 else 1847 axe_init(ifp); 1848 break; 1849 } 1850 sc->axe_if_flags = ifp->if_flags; 1851 break; 1852 1853 default: 1854 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1855 break; 1856 1857 error = 0; 1858 1859 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) 1860 axe_setmulti(sc); 1861 1862 } 1863 splx(s); 1864 1865 return error; 1866 } 1867 1868 static void 1869 axe_watchdog(struct ifnet *ifp) 1870 { 1871 struct axe_softc *sc; 1872 struct axe_chain *c; 1873 usbd_status stat; 1874 int s; 1875 1876 sc = ifp->if_softc; 1877 1878 ifp->if_oerrors++; 1879 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1880 1881 s = splusb(); 1882 c = &sc->axe_cdata.axe_tx_chain[0]; 1883 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1884 axe_txeof(c->axe_xfer, c, stat); 1885 1886 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1887 axe_start(ifp); 1888 splx(s); 1889 } 1890 1891 /* 1892 * Stop the adapter and free any mbufs allocated to the 1893 * RX and TX lists. 1894 */ 1895 static void 1896 axe_stop(struct ifnet *ifp, int disable) 1897 { 1898 struct axe_softc *sc = ifp->if_softc; 1899 usbd_status err; 1900 int i; 1901 1902 ifp->if_timer = 0; 1903 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1904 1905 callout_stop(&sc->axe_stat_ch); 1906 1907 /* Stop transfers. */ 1908 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1909 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1910 if (err) { 1911 aprint_error_dev(sc->axe_dev, 1912 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1913 } 1914 } 1915 1916 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1917 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1918 if (err) { 1919 aprint_error_dev(sc->axe_dev, 1920 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1921 } 1922 } 1923 1924 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1925 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1926 if (err) { 1927 aprint_error_dev(sc->axe_dev, 1928 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1929 } 1930 } 1931 1932 axe_reset(sc); 1933 1934 /* Free RX resources. */ 1935 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1936 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1937 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1938 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1939 } 1940 } 1941 1942 /* Free TX resources. */ 1943 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1944 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1945 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1946 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1947 } 1948 } 1949 1950 /* Close pipes. */ 1951 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1952 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1953 if (err) { 1954 aprint_error_dev(sc->axe_dev, 1955 "close rx pipe failed: %s\n", usbd_errstr(err)); 1956 } 1957 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1958 } 1959 1960 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1961 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1962 if (err) { 1963 aprint_error_dev(sc->axe_dev, 1964 "close tx pipe failed: %s\n", usbd_errstr(err)); 1965 } 1966 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1967 } 1968 1969 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1970 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1971 if (err) { 1972 aprint_error_dev(sc->axe_dev, 1973 "close intr pipe failed: %s\n", usbd_errstr(err)); 1974 } 1975 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1976 } 1977 1978 sc->axe_link = 0; 1979 } 1980 1981 MODULE(MODULE_CLASS_DRIVER, if_axe, NULL); 1982 1983 #ifdef _MODULE 1984 #include "ioconf.c" 1985 #endif 1986 1987 static int 1988 if_axe_modcmd(modcmd_t cmd, void *aux) 1989 { 1990 int error = 0; 1991 1992 switch (cmd) { 1993 case MODULE_CMD_INIT: 1994 #ifdef _MODULE 1995 error = config_init_component(cfdriver_ioconf_axe, 1996 cfattach_ioconf_axe, cfdata_ioconf_axe); 1997 #endif 1998 return error; 1999 case MODULE_CMD_FINI: 2000 #ifdef _MODULE 2001 error = config_fini_component(cfdriver_ioconf_axe, 2002 cfattach_ioconf_axe, cfdata_ioconf_axe); 2003 #endif 2004 return error; 2005 default: 2006 return ENOTTY; 2007 } 2008 } 2009
Indexes created Tue Sep 23 13:09:54 GMT 2025