if_axe.c revision 1.98
1 /* $NetBSD: if_axe.c,v 1.98 2019/05/28 07:41:50 msaitoh Exp $ */ 2 /* $OpenBSD: if_axe.c,v 1.137 2016/04/13 11:03:37 mpi Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006, 2007 Jonathan Gray <jsg (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Copyright (c) 1997, 1998, 1999, 2000-2003 22 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by Bill Paul. 35 * 4. Neither the name of the author nor the names of any co-contributors 36 * may be used to endorse or promote products derived from this software 37 * without specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 43 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 44 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 45 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 46 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 47 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 48 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 49 * THE POSSIBILITY OF SUCH DAMAGE. 50 */ 51 52 /* 53 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 54 * Used in the LinkSys USB200M and various other adapters. 55 * 56 * Written by Bill Paul <wpaul (at) windriver.com> 57 * Senior Engineer 58 * Wind River Systems 59 */ 60 61 /* 62 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 63 * It uses an external PHY (reference designs use a RealTek chip), 64 * and has a 64-bit multicast hash filter. There is some information 65 * missing from the manual which one needs to know in order to make 66 * the chip function: 67 * 68 * - You must set bit 7 in the RX control register, otherwise the 69 * chip won't receive any packets. 70 * - You must initialize all 3 IPG registers, or you won't be able 71 * to send any packets. 72 * 73 * Note that this device appears to only support loading the station 74 * address via autoload from the EEPROM (i.e. there's no way to manually 75 * set it). 76 * 77 * (Adam Weinberger wanted me to name this driver if_gir.c.) 78 */ 79 80 /* 81 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 82 * 2007/02/12, J.R. Oldroyd, fbsd (at) opal.com 83 * 84 * Manual here: 85 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 86 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 87 */ 88 89 #include <sys/cdefs.h> 90 __KERNEL_RCSID(0, "$NetBSD: if_axe.c,v 1.98 2019/05/28 07:41:50 msaitoh Exp $"); 91 92 #ifdef _KERNEL_OPT 93 #include "opt_inet.h" 94 #include "opt_usb.h" 95 #include "opt_net_mpsafe.h" 96 #endif 97 98 #include <sys/param.h> 99 #include <sys/bus.h> 100 #include <sys/device.h> 101 #include <sys/kernel.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/socket.h> 106 #include <sys/sockio.h> 107 #include <sys/systm.h> 108 109 #include <sys/rndsource.h> 110 111 #include <net/if.h> 112 #include <net/if_dl.h> 113 #include <net/if_ether.h> 114 #include <net/if_media.h> 115 116 #include <net/bpf.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/usb/usb.h> 122 #include <dev/usb/usbhist.h> 123 #include <dev/usb/usbdi.h> 124 #include <dev/usb/usbdi_util.h> 125 #include <dev/usb/usbdivar.h> 126 #include <dev/usb/usbdevs.h> 127 128 #include <dev/usb/if_axereg.h> 129 130 /* 131 * AXE_178_MAX_FRAME_BURST 132 * max frame burst size for Ax88178 and Ax88772 133 * 0 2048 bytes 134 * 1 4096 bytes 135 * 2 8192 bytes 136 * 3 16384 bytes 137 * use the largest your system can handle without USB stalling. 138 * 139 * NB: 88772 parts appear to generate lots of input errors with 140 * a 2K rx buffer and 8K is only slightly faster than 4K on an 141 * EHCI port on a T42 so change at your own risk. 142 */ 143 #define AXE_178_MAX_FRAME_BURST 1 144 145 146 #ifdef USB_DEBUG 147 #ifndef AXE_DEBUG 148 #define axedebug 0 149 #else 150 static int axedebug = 20; 151 152 SYSCTL_SETUP(sysctl_hw_axe_setup, "sysctl hw.axe setup") 153 { 154 int err; 155 const struct sysctlnode *rnode; 156 const struct sysctlnode *cnode; 157 158 err = sysctl_createv(clog, 0, NULL, &rnode, 159 CTLFLAG_PERMANENT, CTLTYPE_NODE, "axe", 160 SYSCTL_DESCR("axe global controls"), 161 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 162 163 if (err) 164 goto fail; 165 166 /* control debugging printfs */ 167 err = sysctl_createv(clog, 0, &rnode, &cnode, 168 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT, 169 "debug", SYSCTL_DESCR("Enable debugging output"), 170 NULL, 0, &axedebug, sizeof(axedebug), CTL_CREATE, CTL_EOL); 171 if (err) 172 goto fail; 173 174 return; 175 fail: 176 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 177 } 178 179 #endif /* AXE_DEBUG */ 180 #endif /* USB_DEBUG */ 181 182 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(axedebug,1,FMT,A,B,C,D) 183 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(axedebug,N,FMT,A,B,C,D) 184 #define AXEHIST_FUNC() USBHIST_FUNC() 185 #define AXEHIST_CALLED(name) USBHIST_CALLED(axedebug) 186 187 /* 188 * Various supported device vendors/products. 189 */ 190 static const struct axe_type axe_devs[] = { 191 { { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_UFE2000}, 0 }, 192 { { USB_VENDOR_ACERCM, USB_PRODUCT_ACERCM_EP1427X2}, 0 }, 193 { { USB_VENDOR_APPLE, USB_PRODUCT_APPLE_ETHERNET }, AX772 }, 194 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88172}, 0 }, 195 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772}, AX772 }, 196 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772A}, AX772 }, 197 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B}, AX772B }, 198 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88772B_1}, AX772B }, 199 { { USB_VENDOR_ASIX, USB_PRODUCT_ASIX_AX88178}, AX178 }, 200 { { USB_VENDOR_ATEN, USB_PRODUCT_ATEN_UC210T}, 0 }, 201 { { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D5055 }, AX178 }, 202 { { USB_VENDOR_BILLIONTON, USB_PRODUCT_BILLIONTON_USB2AR}, 0}, 203 { { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB200MV2}, AX772A }, 204 { { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB2_TX }, 0}, 205 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100}, 0 }, 206 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100B1 }, AX772 }, 207 { { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DUBE100B1 }, AX772 }, 208 { { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DUBE100C1 }, AX772B }, 209 { { USB_VENDOR_GOODWAY, USB_PRODUCT_GOODWAY_GWUSB2E}, 0 }, 210 { { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_ETGUS2 }, AX178 }, 211 { { USB_VENDOR_JVC, USB_PRODUCT_JVC_MP_PRX1}, 0 }, 212 { { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ETHERNET }, AX772B }, 213 { { USB_VENDOR_LINKSYS, USB_PRODUCT_LINKSYS_HG20F9}, AX772B }, 214 { { USB_VENDOR_LINKSYS2, USB_PRODUCT_LINKSYS2_USB200M}, 0 }, 215 { { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_USB1000 }, AX178 }, 216 { { USB_VENDOR_LOGITEC, USB_PRODUCT_LOGITEC_LAN_GTJU2}, AX178 }, 217 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2GT}, AX178 }, 218 { { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAU2KTX}, 0 }, 219 { { USB_VENDOR_MSI, USB_PRODUCT_MSI_AX88772A}, AX772 }, 220 { { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_FA120}, 0 }, 221 { { USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01PLUS }, AX772 }, 222 { { USB_VENDOR_PLANEX3, USB_PRODUCT_PLANEX3_GU1000T }, AX178 }, 223 { { USB_VENDOR_SITECOM, USB_PRODUCT_SITECOM_LN029}, 0 }, 224 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN028 }, AX178 }, 225 { { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN031 }, AX178 }, 226 { { USB_VENDOR_SYSTEMTALKS, USB_PRODUCT_SYSTEMTALKS_SGCX2UL}, 0 }, 227 }; 228 #define axe_lookup(v, p) ((const struct axe_type *)usb_lookup(axe_devs, v, p)) 229 230 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 231 { 0x8000, 0x8001, 2048 }, 232 { 0x8100, 0x8147, 4096 }, 233 { 0x8200, 0x81EB, 6144 }, 234 { 0x8300, 0x83D7, 8192 }, 235 { 0x8400, 0x851E, 16384 }, 236 { 0x8500, 0x8666, 20480 }, 237 { 0x8600, 0x87AE, 24576 }, 238 { 0x8700, 0x8A3D, 32768 } 239 }; 240 241 int axe_match(device_t, cfdata_t, void *); 242 void axe_attach(device_t, device_t, void *); 243 int axe_detach(device_t, int); 244 int axe_activate(device_t, devact_t); 245 246 CFATTACH_DECL_NEW(axe, sizeof(struct axe_softc), 247 axe_match, axe_attach, axe_detach, axe_activate); 248 249 static int axe_tx_list_init(struct axe_softc *); 250 static int axe_rx_list_init(struct axe_softc *); 251 static int axe_encap(struct axe_softc *, struct mbuf *, int); 252 static void axe_rxeof(struct usbd_xfer *, void *, usbd_status); 253 static void axe_txeof(struct usbd_xfer *, void *, usbd_status); 254 static void axe_tick(void *); 255 static void axe_tick_task(void *); 256 static void axe_start(struct ifnet *); 257 static int axe_ioctl(struct ifnet *, u_long, void *); 258 static int axe_init(struct ifnet *); 259 static void axe_stop(struct ifnet *, int); 260 static void axe_watchdog(struct ifnet *); 261 static int axe_miibus_readreg_locked(device_t, int, int, uint16_t *); 262 static int axe_miibus_readreg(device_t, int, int, uint16_t *); 263 static int axe_miibus_writereg_locked(device_t, int, int, uint16_t); 264 static int axe_miibus_writereg(device_t, int, int, uint16_t); 265 static void axe_miibus_statchg(struct ifnet *); 266 static int axe_cmd(struct axe_softc *, int, int, int, void *); 267 static void axe_reset(struct axe_softc *); 268 269 static void axe_setmulti(struct axe_softc *); 270 static void axe_lock_mii(struct axe_softc *); 271 static void axe_unlock_mii(struct axe_softc *); 272 273 static void axe_ax88178_init(struct axe_softc *); 274 static void axe_ax88772_init(struct axe_softc *); 275 static void axe_ax88772a_init(struct axe_softc *); 276 static void axe_ax88772b_init(struct axe_softc *); 277 278 /* Get exclusive access to the MII registers */ 279 static void 280 axe_lock_mii(struct axe_softc *sc) 281 { 282 283 sc->axe_refcnt++; 284 mutex_enter(&sc->axe_mii_lock); 285 } 286 287 static void 288 axe_unlock_mii(struct axe_softc *sc) 289 { 290 291 mutex_exit(&sc->axe_mii_lock); 292 if (--sc->axe_refcnt < 0) 293 usb_detach_wakeupold((sc->axe_dev)); 294 } 295 296 static int 297 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 298 { 299 AXEHIST_FUNC(); AXEHIST_CALLED(); 300 usb_device_request_t req; 301 usbd_status err; 302 303 KASSERT(mutex_owned(&sc->axe_mii_lock)); 304 305 if (sc->axe_dying) 306 return -1; 307 308 DPRINTFN(20, "cmd %#jx index %#jx val %#jx", cmd, index, val, 0); 309 310 if (AXE_CMD_DIR(cmd)) 311 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 312 else 313 req.bmRequestType = UT_READ_VENDOR_DEVICE; 314 req.bRequest = AXE_CMD_CMD(cmd); 315 USETW(req.wValue, val); 316 USETW(req.wIndex, index); 317 USETW(req.wLength, AXE_CMD_LEN(cmd)); 318 319 err = usbd_do_request(sc->axe_udev, &req, buf); 320 321 if (err) { 322 DPRINTF("cmd %jd err %jd", cmd, err, 0, 0); 323 return -1; 324 } 325 return 0; 326 } 327 328 static int 329 axe_miibus_readreg_locked(device_t dev, int phy, int reg, uint16_t *val) 330 { 331 AXEHIST_FUNC(); AXEHIST_CALLED(); 332 struct axe_softc *sc = device_private(dev); 333 usbd_status err; 334 uint16_t data; 335 336 DPRINTFN(30, "phy 0x%jx reg 0x%jx\n", phy, reg, 0, 0); 337 338 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 339 340 err = axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &data); 341 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 342 if (err) { 343 aprint_error_dev(sc->axe_dev, "read PHY failed\n"); 344 return err; 345 } 346 347 *val = le16toh(data); 348 if (AXE_IS_772(sc) && reg == MII_BMSR) { 349 /* 350 * BMSR of AX88772 indicates that it supports extended 351 * capability but the extended status register is 352 * reserved for embedded ethernet PHY. So clear the 353 * extended capability bit of BMSR. 354 */ 355 *val &= ~BMSR_EXTCAP; 356 } 357 358 DPRINTFN(30, "phy 0x%jx reg 0x%jx val %#jx", phy, reg, *val, 0); 359 360 return 0; 361 } 362 363 static int 364 axe_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 365 { 366 struct axe_softc *sc = device_private(dev); 367 int rv; 368 369 if (sc->axe_dying) 370 return -1; 371 372 if (sc->axe_phyno != phy) 373 return -1; 374 375 axe_lock_mii(sc); 376 rv = axe_miibus_readreg_locked(dev, phy, reg, val); 377 axe_unlock_mii(sc); 378 379 return rv; 380 } 381 382 static int 383 axe_miibus_writereg_locked(device_t dev, int phy, int reg, uint16_t aval) 384 { 385 struct axe_softc *sc = device_private(dev); 386 usbd_status err; 387 uint16_t val; 388 389 val = htole16(aval); 390 391 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 392 err = axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 393 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 394 395 if (err) { 396 aprint_error_dev(sc->axe_dev, "write PHY failed\n"); 397 return err; 398 } 399 400 return 0; 401 } 402 403 static int 404 axe_miibus_writereg(device_t dev, int phy, int reg, uint16_t aval) 405 { 406 struct axe_softc *sc = device_private(dev); 407 int rv; 408 409 if (sc->axe_dying) 410 return -1; 411 412 if (sc->axe_phyno != phy) 413 return -1; 414 415 axe_lock_mii(sc); 416 rv = axe_miibus_writereg_locked(dev, phy, reg, aval); 417 axe_unlock_mii(sc); 418 419 return rv; 420 } 421 422 static void 423 axe_miibus_statchg(struct ifnet *ifp) 424 { 425 AXEHIST_FUNC(); AXEHIST_CALLED(); 426 427 struct axe_softc *sc = ifp->if_softc; 428 struct mii_data *mii = &sc->axe_mii; 429 int val, err; 430 431 val = 0; 432 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 433 val |= AXE_MEDIA_FULL_DUPLEX; 434 if (AXE_IS_178_FAMILY(sc)) { 435 if ((IFM_OPTIONS(mii->mii_media_active) & 436 IFM_ETH_TXPAUSE) != 0) 437 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 438 if ((IFM_OPTIONS(mii->mii_media_active) & 439 IFM_ETH_RXPAUSE) != 0) 440 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 441 } 442 } 443 if (AXE_IS_178_FAMILY(sc)) { 444 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 445 if (sc->axe_flags & AX178) 446 val |= AXE_178_MEDIA_ENCK; 447 switch (IFM_SUBTYPE(mii->mii_media_active)) { 448 case IFM_1000_T: 449 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 450 break; 451 case IFM_100_TX: 452 val |= AXE_178_MEDIA_100TX; 453 break; 454 case IFM_10_T: 455 /* doesn't need to be handled */ 456 break; 457 } 458 } 459 460 DPRINTF("val=0x%jx", val, 0, 0, 0); 461 axe_lock_mii(sc); 462 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 463 axe_unlock_mii(sc); 464 if (err) { 465 aprint_error_dev(sc->axe_dev, "media change failed\n"); 466 return; 467 } 468 } 469 470 static void 471 axe_setmulti(struct axe_softc *sc) 472 { 473 AXEHIST_FUNC(); AXEHIST_CALLED(); 474 struct ethercom *ec = &sc->axe_ec; 475 struct ifnet *ifp = &sc->sc_if; 476 struct ether_multi *enm; 477 struct ether_multistep step; 478 uint32_t h = 0; 479 uint16_t rxmode; 480 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 481 482 if (sc->axe_dying) 483 return; 484 485 axe_lock_mii(sc); 486 if (axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode)) { 487 axe_unlock_mii(sc); 488 aprint_error_dev(sc->axe_dev, "can't read rxmode"); 489 return; 490 } 491 rxmode = le16toh(rxmode); 492 493 rxmode &= 494 ~(AXE_RXCMD_ALLMULTI | AXE_RXCMD_PROMISC | 495 AXE_RXCMD_BROADCAST | AXE_RXCMD_MULTICAST); 496 497 rxmode |= 498 (ifp->if_flags & IFF_BROADCAST) ? AXE_RXCMD_BROADCAST : 0; 499 500 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 501 if (ifp->if_flags & IFF_PROMISC) 502 rxmode |= AXE_RXCMD_PROMISC; 503 goto allmulti; 504 } 505 506 /* Now program new ones */ 507 ETHER_LOCK(ec); 508 ETHER_FIRST_MULTI(step, ec, enm); 509 while (enm != NULL) { 510 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 511 ETHER_ADDR_LEN) != 0) { 512 ETHER_UNLOCK(ec); 513 goto allmulti; 514 } 515 516 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26; 517 hashtbl[h >> 3] |= 1U << (h & 7); 518 ETHER_NEXT_MULTI(step, enm); 519 } 520 ETHER_UNLOCK(ec); 521 ifp->if_flags &= ~IFF_ALLMULTI; 522 rxmode |= AXE_RXCMD_MULTICAST; 523 524 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, hashtbl); 525 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 526 axe_unlock_mii(sc); 527 return; 528 529 allmulti: 530 ifp->if_flags |= IFF_ALLMULTI; 531 rxmode |= AXE_RXCMD_ALLMULTI; 532 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 533 axe_unlock_mii(sc); 534 } 535 536 static void 537 axe_ax_init(struct axe_softc *sc) 538 { 539 int cmd = AXE_178_CMD_READ_NODEID; 540 541 if (sc->axe_flags & AX178) { 542 axe_ax88178_init(sc); 543 } else if (sc->axe_flags & AX772) { 544 axe_ax88772_init(sc); 545 } else if (sc->axe_flags & AX772A) { 546 axe_ax88772a_init(sc); 547 } else if (sc->axe_flags & AX772B) { 548 axe_ax88772b_init(sc); 549 return; 550 } else { 551 cmd = AXE_172_CMD_READ_NODEID; 552 } 553 554 if (axe_cmd(sc, cmd, 0, 0, sc->axe_enaddr)) { 555 aprint_error_dev(sc->axe_dev, 556 "failed to read ethernet address\n"); 557 } 558 } 559 560 561 static void 562 axe_reset(struct axe_softc *sc) 563 { 564 565 if (sc->axe_dying) 566 return; 567 568 /* 569 * softnet_lock can be taken when NET_MPAFE is not defined when calling 570 * if_addr_init -> if_init. This doesn't mixe well with the 571 * usbd_delay_ms calls in the init routines as things like nd6_slowtimo 572 * can fire during the wait and attempt to take softnet_lock and then 573 * block the softclk thread meaing the wait never ends. 574 */ 575 #ifndef NET_MPSAFE 576 /* XXX What to reset? */ 577 578 /* Wait a little while for the chip to get its brains in order. */ 579 DELAY(1000); 580 #else 581 axe_lock_mii(sc); 582 583 axe_ax_init(sc); 584 585 axe_unlock_mii(sc); 586 #endif 587 } 588 589 static int 590 axe_get_phyno(struct axe_softc *sc, int sel) 591 { 592 int phyno; 593 594 switch (AXE_PHY_TYPE(sc->axe_phyaddrs[sel])) { 595 case PHY_TYPE_100_HOME: 596 /* FALLTHROUGH */ 597 case PHY_TYPE_GIG: 598 phyno = AXE_PHY_NO(sc->axe_phyaddrs[sel]); 599 break; 600 case PHY_TYPE_SPECIAL: 601 /* FALLTHROUGH */ 602 case PHY_TYPE_RSVD: 603 /* FALLTHROUGH */ 604 case PHY_TYPE_NON_SUP: 605 /* FALLTHROUGH */ 606 default: 607 phyno = -1; 608 break; 609 } 610 611 return phyno; 612 } 613 614 #define AXE_GPIO_WRITE(x, y) do { \ 615 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 616 usbd_delay_ms(sc->axe_udev, hztoms(y)); \ 617 } while (0) 618 619 static void 620 axe_ax88178_init(struct axe_softc *sc) 621 { 622 AXEHIST_FUNC(); AXEHIST_CALLED(); 623 int gpio0, ledmode, phymode; 624 uint16_t eeprom, val; 625 626 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 627 /* XXX magic */ 628 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom) != 0) 629 eeprom = 0xffff; 630 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 631 632 eeprom = le16toh(eeprom); 633 634 DPRINTF("EEPROM is 0x%jx", eeprom, 0, 0, 0); 635 636 /* if EEPROM is invalid we have to use to GPIO0 */ 637 if (eeprom == 0xffff) { 638 phymode = AXE_PHY_MODE_MARVELL; 639 gpio0 = 1; 640 ledmode = 0; 641 } else { 642 phymode = eeprom & 0x7f; 643 gpio0 = (eeprom & 0x80) ? 0 : 1; 644 ledmode = eeprom >> 8; 645 } 646 647 DPRINTF("use gpio0: %jd, phymode %jd", gpio0, phymode, 0, 0); 648 649 /* Program GPIOs depending on PHY hardware. */ 650 switch (phymode) { 651 case AXE_PHY_MODE_MARVELL: 652 if (gpio0 == 1) { 653 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 654 hz / 32); 655 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 656 hz / 32); 657 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 658 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 659 hz / 32); 660 } else { 661 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 662 AXE_GPIO1_EN, hz / 3); 663 if (ledmode == 1) { 664 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 665 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 666 hz / 3); 667 } else { 668 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 669 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 670 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 671 AXE_GPIO2_EN, hz / 4); 672 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 673 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 674 } 675 } 676 break; 677 case AXE_PHY_MODE_CICADA: 678 case AXE_PHY_MODE_CICADA_V2: 679 case AXE_PHY_MODE_CICADA_V2_ASIX: 680 if (gpio0 == 1) 681 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 682 AXE_GPIO0_EN, hz / 32); 683 else 684 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 685 AXE_GPIO1_EN, hz / 32); 686 break; 687 case AXE_PHY_MODE_AGERE: 688 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 689 AXE_GPIO1_EN, hz / 32); 690 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 691 AXE_GPIO2_EN, hz / 32); 692 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 693 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 694 AXE_GPIO2_EN, hz / 32); 695 break; 696 case AXE_PHY_MODE_REALTEK_8211CL: 697 case AXE_PHY_MODE_REALTEK_8211BN: 698 case AXE_PHY_MODE_REALTEK_8251CL: 699 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 700 AXE_GPIO1 | AXE_GPIO1_EN; 701 AXE_GPIO_WRITE(val, hz / 32); 702 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 703 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 704 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 705 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 706 axe_miibus_writereg_locked(sc->axe_dev, 707 sc->axe_phyno, 0x1F, 0x0005); 708 axe_miibus_writereg_locked(sc->axe_dev, 709 sc->axe_phyno, 0x0C, 0x0000); 710 axe_miibus_readreg_locked(sc->axe_dev, 711 sc->axe_phyno, 0x0001, &val); 712 axe_miibus_writereg_locked(sc->axe_dev, 713 sc->axe_phyno, 0x01, val | 0x0080); 714 axe_miibus_writereg_locked(sc->axe_dev, 715 sc->axe_phyno, 0x1F, 0x0000); 716 } 717 break; 718 default: 719 /* Unknown PHY model or no need to program GPIOs. */ 720 break; 721 } 722 723 /* soft reset */ 724 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 725 usbd_delay_ms(sc->axe_udev, 150); 726 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 727 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 728 usbd_delay_ms(sc->axe_udev, 150); 729 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 730 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 731 usbd_delay_ms(sc->axe_udev, 10); 732 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 733 } 734 735 static void 736 axe_ax88772_init(struct axe_softc *sc) 737 { 738 AXEHIST_FUNC(); AXEHIST_CALLED(); 739 740 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 741 usbd_delay_ms(sc->axe_udev, 40); 742 743 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 744 /* ask for the embedded PHY */ 745 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 746 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 747 usbd_delay_ms(sc->axe_udev, 10); 748 749 /* power down and reset state, pin reset state */ 750 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 751 usbd_delay_ms(sc->axe_udev, 60); 752 753 /* power down/reset state, pin operating state */ 754 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 755 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 756 usbd_delay_ms(sc->axe_udev, 150); 757 758 /* power up, reset */ 759 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 760 761 /* power up, operating */ 762 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 763 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 764 } else { 765 /* ask for external PHY */ 766 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_EXT, 767 NULL); 768 usbd_delay_ms(sc->axe_udev, 10); 769 770 /* power down internal PHY */ 771 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 772 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 773 } 774 775 usbd_delay_ms(sc->axe_udev, 150); 776 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 777 } 778 779 static void 780 axe_ax88772_phywake(struct axe_softc *sc) 781 { 782 AXEHIST_FUNC(); AXEHIST_CALLED(); 783 784 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 785 /* Manually select internal(embedded) PHY - MAC mode. */ 786 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 787 AXE_SW_PHY_SELECT_EMBEDDED, NULL); 788 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 789 } else { 790 /* 791 * Manually select external PHY - MAC mode. 792 * Reverse MII/RMII is for AX88772A PHY mode. 793 */ 794 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 795 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 796 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 797 } 798 799 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 800 AXE_SW_RESET_IPRL, NULL); 801 802 /* T1 = min 500ns everywhere */ 803 usbd_delay_ms(sc->axe_udev, 150); 804 805 /* Take PHY out of power down. */ 806 if (sc->axe_phyno == AXE_772_PHY_NO_EPHY) { 807 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 808 } else { 809 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRTE, NULL); 810 } 811 812 /* 772 T2 is 60ms. 772A T2 is 160ms, 772B T2 is 600ms */ 813 usbd_delay_ms(sc->axe_udev, 600); 814 815 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 816 817 /* T3 = 500ns everywhere */ 818 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 819 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 820 usbd_delay_ms(sc->axe_udev, hztoms(hz / 32)); 821 } 822 823 static void 824 axe_ax88772a_init(struct axe_softc *sc) 825 { 826 AXEHIST_FUNC(); AXEHIST_CALLED(); 827 828 /* Reload EEPROM. */ 829 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 830 axe_ax88772_phywake(sc); 831 /* Stop MAC. */ 832 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 833 } 834 835 static void 836 axe_ax88772b_init(struct axe_softc *sc) 837 { 838 AXEHIST_FUNC(); AXEHIST_CALLED(); 839 uint16_t eeprom; 840 int i; 841 842 /* Reload EEPROM. */ 843 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM , hz / 32); 844 845 /* 846 * Save PHY power saving configuration(high byte) and 847 * clear EEPROM checksum value(low byte). 848 */ 849 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, 850 &eeprom)) { 851 aprint_error_dev(sc->axe_dev, "failed to read eeprom\n"); 852 return; 853 } 854 855 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 856 857 /* 858 * Auto-loaded default station address from internal ROM is 859 * 00:00:00:00:00:00 such that an explicit access to EEPROM 860 * is required to get real station address. 861 */ 862 uint8_t *eaddr = sc->axe_enaddr; 863 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 864 if (axe_cmd(sc, AXE_CMD_SROM_READ, 0, 865 AXE_EEPROM_772B_NODE_ID + i, &eeprom)) { 866 aprint_error_dev(sc->axe_dev, 867 "failed to read eeprom\n"); 868 eeprom = 0; 869 } 870 eeprom = le16toh(eeprom); 871 *eaddr++ = (uint8_t)(eeprom & 0xFF); 872 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 873 } 874 /* Wakeup PHY. */ 875 axe_ax88772_phywake(sc); 876 /* Stop MAC. */ 877 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 878 } 879 880 #undef AXE_GPIO_WRITE 881 882 /* 883 * Probe for a AX88172 chip. 884 */ 885 int 886 axe_match(device_t parent, cfdata_t match, void *aux) 887 { 888 struct usb_attach_arg *uaa = aux; 889 890 return axe_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ? 891 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 892 } 893 894 /* 895 * Attach the interface. Allocate softc structures, do ifmedia 896 * setup and ethernet/BPF attach. 897 */ 898 void 899 axe_attach(device_t parent, device_t self, void *aux) 900 { 901 AXEHIST_FUNC(); AXEHIST_CALLED(); 902 struct axe_softc *sc = device_private(self); 903 struct usb_attach_arg *uaa = aux; 904 struct usbd_device *dev = uaa->uaa_device; 905 usbd_status err; 906 usb_interface_descriptor_t *id; 907 usb_endpoint_descriptor_t *ed; 908 struct mii_data *mii; 909 char *devinfop; 910 const char *devname = device_xname(self); 911 struct ifnet *ifp; 912 int i, s; 913 914 aprint_naive("\n"); 915 aprint_normal("\n"); 916 917 sc->axe_dev = self; 918 sc->axe_udev = dev; 919 920 devinfop = usbd_devinfo_alloc(dev, 0); 921 aprint_normal_dev(self, "%s\n", devinfop); 922 usbd_devinfo_free(devinfop); 923 924 err = usbd_set_config_no(dev, AXE_CONFIG_NO, 1); 925 if (err) { 926 aprint_error_dev(self, "failed to set configuration" 927 ", err=%s\n", usbd_errstr(err)); 928 return; 929 } 930 931 sc->axe_flags = axe_lookup(uaa->uaa_vendor, uaa->uaa_product)->axe_flags; 932 933 mutex_init(&sc->axe_mii_lock, MUTEX_DEFAULT, IPL_NONE); 934 usb_init_task(&sc->axe_tick_task, axe_tick_task, sc, 0); 935 936 err = usbd_device2interface_handle(dev, AXE_IFACE_IDX, &sc->axe_iface); 937 if (err) { 938 aprint_error_dev(self, "getting interface handle failed\n"); 939 return; 940 } 941 942 sc->axe_product = uaa->uaa_product; 943 sc->axe_vendor = uaa->uaa_vendor; 944 945 id = usbd_get_interface_descriptor(sc->axe_iface); 946 947 /* decide on what our bufsize will be */ 948 if (AXE_IS_178_FAMILY(sc)) 949 sc->axe_bufsz = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 950 AXE_178_MAX_BUFSZ : AXE_178_MIN_BUFSZ; 951 else 952 sc->axe_bufsz = AXE_172_BUFSZ; 953 954 sc->axe_ed[AXE_ENDPT_RX] = -1; 955 sc->axe_ed[AXE_ENDPT_TX] = -1; 956 sc->axe_ed[AXE_ENDPT_INTR] = -1; 957 958 /* Find endpoints. */ 959 for (i = 0; i < id->bNumEndpoints; i++) { 960 ed = usbd_interface2endpoint_descriptor(sc->axe_iface, i); 961 if (ed == NULL) { 962 aprint_error_dev(self, "couldn't get ep %d\n", i); 963 return; 964 } 965 const uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 966 const uint8_t dir = UE_GET_DIR(ed->bEndpointAddress); 967 968 if (dir == UE_DIR_IN && xt == UE_BULK && 969 sc->axe_ed[AXE_ENDPT_RX] == -1) { 970 sc->axe_ed[AXE_ENDPT_RX] = ed->bEndpointAddress; 971 } else if (dir == UE_DIR_OUT && xt == UE_BULK && 972 sc->axe_ed[AXE_ENDPT_TX] == -1) { 973 sc->axe_ed[AXE_ENDPT_TX] = ed->bEndpointAddress; 974 } else if (dir == UE_DIR_IN && xt == UE_INTERRUPT) { 975 sc->axe_ed[AXE_ENDPT_INTR] = ed->bEndpointAddress; 976 } 977 } 978 979 s = splnet(); 980 981 /* We need the PHYID for init dance in some cases */ 982 axe_lock_mii(sc); 983 if (axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, &sc->axe_phyaddrs)) { 984 aprint_error_dev(self, "failed to read phyaddrs\n"); 985 return; 986 } 987 988 DPRINTF(" phyaddrs[0]: %jx phyaddrs[1]: %jx", 989 sc->axe_phyaddrs[0], sc->axe_phyaddrs[1], 0, 0); 990 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 991 if (sc->axe_phyno == -1) 992 sc->axe_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 993 if (sc->axe_phyno == -1) { 994 DPRINTF(" no valid PHY address found, assuming PHY address 0", 995 0, 0, 0, 0); 996 sc->axe_phyno = 0; 997 } 998 999 /* Initialize controller and get station address. */ 1000 1001 axe_ax_init(sc); 1002 1003 /* 1004 * Fetch IPG values. 1005 */ 1006 if (sc->axe_flags & (AX772A | AX772B)) { 1007 /* Set IPG values. */ 1008 sc->axe_ipgs[0] = AXE_IPG0_DEFAULT; 1009 sc->axe_ipgs[1] = AXE_IPG1_DEFAULT; 1010 sc->axe_ipgs[2] = AXE_IPG2_DEFAULT; 1011 } else { 1012 if (axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->axe_ipgs)) { 1013 aprint_error_dev(self, "failed to read ipg\n"); 1014 return; 1015 } 1016 } 1017 1018 axe_unlock_mii(sc); 1019 1020 /* 1021 * An ASIX chip was detected. Inform the world. 1022 */ 1023 aprint_normal_dev(self, "Ethernet address %s\n", 1024 ether_sprintf(sc->axe_enaddr)); 1025 1026 /* Initialize interface info.*/ 1027 ifp = &sc->sc_if; 1028 ifp->if_softc = sc; 1029 strlcpy(ifp->if_xname, devname, IFNAMSIZ); 1030 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1031 ifp->if_ioctl = axe_ioctl; 1032 ifp->if_start = axe_start; 1033 ifp->if_init = axe_init; 1034 ifp->if_stop = axe_stop; 1035 ifp->if_watchdog = axe_watchdog; 1036 1037 IFQ_SET_READY(&ifp->if_snd); 1038 1039 if (AXE_IS_178_FAMILY(sc)) 1040 sc->axe_ec.ec_capabilities = ETHERCAP_VLAN_MTU; 1041 if (sc->axe_flags & AX772B) { 1042 ifp->if_capabilities = 1043 IFCAP_CSUM_IPv4_Rx | 1044 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 1045 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 1046 /* 1047 * Checksum offloading of AX88772B also works with VLAN 1048 * tagged frames but there is no way to take advantage 1049 * of the feature because vlan(4) assumes 1050 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 1051 * support checksum offloading with VLAN. VLAN hardware 1052 * tagging support of AX88772B is very limited so it's 1053 * not possible to announce IFCAP_VLAN_HWTAGGING. 1054 */ 1055 } 1056 u_int adv_pause; 1057 if (sc->axe_flags & (AX772A | AX772B | AX178)) 1058 adv_pause = MIIF_DOPAUSE; 1059 else 1060 adv_pause = 0; 1061 adv_pause = 0; 1062 1063 /* Initialize MII/media info. */ 1064 mii = &sc->axe_mii; 1065 mii->mii_ifp = ifp; 1066 mii->mii_readreg = axe_miibus_readreg; 1067 mii->mii_writereg = axe_miibus_writereg; 1068 mii->mii_statchg = axe_miibus_statchg; 1069 mii->mii_flags = MIIF_AUTOTSLEEP; 1070 1071 sc->axe_ec.ec_mii = mii; 1072 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 1073 1074 mii_attach(sc->axe_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 1075 adv_pause); 1076 1077 if (LIST_EMPTY(&mii->mii_phys)) { 1078 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1079 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1080 } else 1081 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1082 1083 /* Attach the interface. */ 1084 if_attach(ifp); 1085 ether_ifattach(ifp, sc->axe_enaddr); 1086 rnd_attach_source(&sc->rnd_source, device_xname(sc->axe_dev), 1087 RND_TYPE_NET, RND_FLAG_DEFAULT); 1088 1089 callout_init(&sc->axe_stat_ch, 0); 1090 callout_setfunc(&sc->axe_stat_ch, axe_tick, sc); 1091 1092 sc->axe_attached = true; 1093 splx(s); 1094 1095 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->axe_udev, sc->axe_dev); 1096 1097 if (!pmf_device_register(self, NULL, NULL)) 1098 aprint_error_dev(self, "couldn't establish power handler\n"); 1099 } 1100 1101 int 1102 axe_detach(device_t self, int flags) 1103 { 1104 AXEHIST_FUNC(); AXEHIST_CALLED(); 1105 struct axe_softc *sc = device_private(self); 1106 int s; 1107 struct ifnet *ifp = &sc->sc_if; 1108 1109 /* Detached before attached finished, so just bail out. */ 1110 if (!sc->axe_attached) 1111 return 0; 1112 1113 pmf_device_deregister(self); 1114 1115 sc->axe_dying = true; 1116 1117 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) 1118 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1119 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) 1120 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1121 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1122 usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1123 1124 callout_halt(&sc->axe_stat_ch, NULL); 1125 usb_rem_task_wait(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER, 1126 NULL); 1127 1128 s = splusb(); 1129 1130 if (ifp->if_flags & IFF_RUNNING) 1131 axe_stop(ifp, 1); 1132 1133 1134 if (--sc->axe_refcnt >= 0) { 1135 /* Wait for processes to go away. */ 1136 usb_detach_waitold(sc->axe_dev); 1137 } 1138 1139 callout_destroy(&sc->axe_stat_ch); 1140 mutex_destroy(&sc->axe_mii_lock); 1141 rnd_detach_source(&sc->rnd_source); 1142 mii_detach(&sc->axe_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1143 ifmedia_delete_instance(&sc->axe_mii.mii_media, IFM_INST_ANY); 1144 ether_ifdetach(ifp); 1145 if_detach(ifp); 1146 1147 #ifdef DIAGNOSTIC 1148 if (sc->axe_ep[AXE_ENDPT_TX] != NULL || 1149 sc->axe_ep[AXE_ENDPT_RX] != NULL || 1150 sc->axe_ep[AXE_ENDPT_INTR] != NULL) 1151 aprint_debug_dev(self, "detach has active endpoints\n"); 1152 #endif 1153 1154 sc->axe_attached = false; 1155 1156 splx(s); 1157 1158 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->axe_udev, sc->axe_dev); 1159 1160 return 0; 1161 } 1162 1163 int 1164 axe_activate(device_t self, devact_t act) 1165 { 1166 AXEHIST_FUNC(); AXEHIST_CALLED(); 1167 struct axe_softc *sc = device_private(self); 1168 1169 switch (act) { 1170 case DVACT_DEACTIVATE: 1171 if_deactivate(&sc->axe_ec.ec_if); 1172 sc->axe_dying = true; 1173 return 0; 1174 default: 1175 return EOPNOTSUPP; 1176 } 1177 } 1178 1179 static int 1180 axe_rx_list_init(struct axe_softc *sc) 1181 { 1182 AXEHIST_FUNC(); AXEHIST_CALLED(); 1183 1184 struct axe_cdata *cd; 1185 struct axe_chain *c; 1186 int i; 1187 1188 cd = &sc->axe_cdata; 1189 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1190 c = &cd->axe_rx_chain[i]; 1191 c->axe_sc = sc; 1192 c->axe_idx = i; 1193 if (c->axe_xfer == NULL) { 1194 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_RX], 1195 sc->axe_bufsz, 0, 0, &c->axe_xfer); 1196 if (err) 1197 return err; 1198 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1199 } 1200 } 1201 1202 return 0; 1203 } 1204 1205 static int 1206 axe_tx_list_init(struct axe_softc *sc) 1207 { 1208 AXEHIST_FUNC(); AXEHIST_CALLED(); 1209 struct axe_cdata *cd; 1210 struct axe_chain *c; 1211 int i; 1212 1213 cd = &sc->axe_cdata; 1214 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1215 c = &cd->axe_tx_chain[i]; 1216 c->axe_sc = sc; 1217 c->axe_idx = i; 1218 if (c->axe_xfer == NULL) { 1219 int err = usbd_create_xfer(sc->axe_ep[AXE_ENDPT_TX], 1220 sc->axe_bufsz, USBD_FORCE_SHORT_XFER, 0, 1221 &c->axe_xfer); 1222 if (err) 1223 return err; 1224 c->axe_buf = usbd_get_buffer(c->axe_xfer); 1225 } 1226 } 1227 1228 return 0; 1229 } 1230 1231 /* 1232 * A frame has been uploaded: pass the resulting mbuf chain up to 1233 * the higher level protocols. 1234 */ 1235 static void 1236 axe_rxeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1237 { 1238 AXEHIST_FUNC(); AXEHIST_CALLED(); 1239 struct axe_softc *sc; 1240 struct axe_chain *c; 1241 struct ifnet *ifp; 1242 uint8_t *buf; 1243 uint32_t total_len; 1244 struct mbuf *m; 1245 int s; 1246 1247 c = (struct axe_chain *)priv; 1248 sc = c->axe_sc; 1249 buf = c->axe_buf; 1250 ifp = &sc->sc_if; 1251 1252 if (sc->axe_dying) 1253 return; 1254 1255 if ((ifp->if_flags & IFF_RUNNING) == 0) 1256 return; 1257 1258 if (status != USBD_NORMAL_COMPLETION) { 1259 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1260 return; 1261 if (usbd_ratecheck(&sc->axe_rx_notice)) { 1262 aprint_error_dev(sc->axe_dev, "usb errors on rx: %s\n", 1263 usbd_errstr(status)); 1264 } 1265 if (status == USBD_STALLED) 1266 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_RX]); 1267 goto done; 1268 } 1269 1270 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1271 1272 do { 1273 u_int pktlen = 0; 1274 u_int rxlen = 0; 1275 int flags = 0; 1276 if ((sc->axe_flags & AXSTD_FRAME) != 0) { 1277 struct axe_sframe_hdr hdr; 1278 1279 if (total_len < sizeof(hdr)) { 1280 ifp->if_ierrors++; 1281 goto done; 1282 } 1283 1284 #if !defined(__NO_STRICT_ALIGNMENT) && __GNUC_PREREQ__(6, 1) 1285 /* 1286 * XXX hdr is 2-byte aligned in buf, not 4-byte. 1287 * For some architectures, __builtin_memcpy() of 1288 * GCC 6 attempts to copy sizeof(hdr) = 4 bytes 1289 * at onece, which results in alignment error. 1290 */ 1291 hdr.len = *(uint16_t *)buf; 1292 hdr.ilen = *(uint16_t *)(buf + sizeof(uint16_t)); 1293 #else 1294 memcpy(&hdr, buf, sizeof(hdr)); 1295 #endif 1296 1297 DPRINTFN(20, "total_len %#jx len %jx ilen %#jx", 1298 total_len, 1299 (le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK), 1300 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK), 0); 1301 1302 total_len -= sizeof(hdr); 1303 buf += sizeof(hdr); 1304 1305 if (((le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK) ^ 1306 (le16toh(hdr.ilen) & AXE_RH1M_RXLEN_MASK)) != 1307 AXE_RH1M_RXLEN_MASK) { 1308 ifp->if_ierrors++; 1309 goto done; 1310 } 1311 1312 rxlen = le16toh(hdr.len) & AXE_RH1M_RXLEN_MASK; 1313 if (total_len < rxlen) { 1314 pktlen = total_len; 1315 total_len = 0; 1316 } else { 1317 pktlen = rxlen; 1318 rxlen = roundup2(rxlen, 2); 1319 total_len -= rxlen; 1320 } 1321 1322 } else if ((sc->axe_flags & AXCSUM_FRAME) != 0) { 1323 struct axe_csum_hdr csum_hdr; 1324 1325 if (total_len < sizeof(csum_hdr)) { 1326 ifp->if_ierrors++; 1327 goto done; 1328 } 1329 1330 memcpy(&csum_hdr, buf, sizeof(csum_hdr)); 1331 1332 csum_hdr.len = le16toh(csum_hdr.len); 1333 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1334 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1335 1336 DPRINTFN(20, "total_len %#jx len %#jx ilen %#jx" 1337 " cstatus %#jx", total_len, 1338 csum_hdr.len, csum_hdr.ilen, csum_hdr.cstatus); 1339 1340 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1341 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1342 sc->sc_lenmask) { 1343 /* we lost sync */ 1344 ifp->if_ierrors++; 1345 DPRINTFN(20, "len %#jx ilen %#jx lenmask %#jx " 1346 "err", 1347 AXE_CSUM_RXBYTES(csum_hdr.len), 1348 AXE_CSUM_RXBYTES(csum_hdr.ilen), 1349 sc->sc_lenmask, 0); 1350 goto done; 1351 } 1352 /* 1353 * Get total transferred frame length including 1354 * checksum header. The length should be multiple 1355 * of 4. 1356 */ 1357 pktlen = AXE_CSUM_RXBYTES(csum_hdr.len); 1358 u_int len = sizeof(csum_hdr) + pktlen; 1359 len = (len + 3) & ~3; 1360 if (total_len < len) { 1361 DPRINTFN(20, "total_len %#jx < len %#jx", 1362 total_len, len, 0, 0); 1363 /* invalid length */ 1364 ifp->if_ierrors++; 1365 goto done; 1366 } 1367 buf += sizeof(csum_hdr); 1368 1369 const uint16_t cstatus = csum_hdr.cstatus; 1370 1371 if (cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1372 if (cstatus & AXE_CSUM_HDR_L4_CSUM_ERR) 1373 flags |= M_CSUM_TCP_UDP_BAD; 1374 if (cstatus & AXE_CSUM_HDR_L3_CSUM_ERR) 1375 flags |= M_CSUM_IPv4_BAD; 1376 1377 const uint16_t l4type = 1378 cstatus & AXE_CSUM_HDR_L4_TYPE_MASK; 1379 1380 if (l4type == AXE_CSUM_HDR_L4_TYPE_TCP) 1381 flags |= M_CSUM_TCPv4; 1382 if (l4type == AXE_CSUM_HDR_L4_TYPE_UDP) 1383 flags |= M_CSUM_UDPv4; 1384 } 1385 if (total_len < len) { 1386 pktlen = total_len; 1387 total_len = 0; 1388 } else { 1389 total_len -= len; 1390 rxlen = len - sizeof(csum_hdr); 1391 } 1392 DPRINTFN(20, "total_len %#jx len %#jx pktlen %#jx" 1393 " rxlen %#jx", total_len, len, pktlen, rxlen); 1394 } else { /* AX172 */ 1395 pktlen = rxlen = total_len; 1396 total_len = 0; 1397 } 1398 1399 MGETHDR(m, M_DONTWAIT, MT_DATA); 1400 if (m == NULL) { 1401 ifp->if_ierrors++; 1402 goto done; 1403 } 1404 1405 if (pktlen > MHLEN - ETHER_ALIGN) { 1406 MCLGET(m, M_DONTWAIT); 1407 if ((m->m_flags & M_EXT) == 0) { 1408 m_freem(m); 1409 ifp->if_ierrors++; 1410 goto done; 1411 } 1412 } 1413 m->m_data += ETHER_ALIGN; 1414 1415 m_set_rcvif(m, ifp); 1416 m->m_pkthdr.len = m->m_len = pktlen; 1417 m->m_pkthdr.csum_flags = flags; 1418 1419 memcpy(mtod(m, uint8_t *), buf, pktlen); 1420 buf += rxlen; 1421 1422 DPRINTFN(10, "deliver %jd (%#jx)", m->m_len, m->m_len, 0, 0); 1423 1424 s = splnet(); 1425 1426 if_percpuq_enqueue((ifp)->if_percpuq, (m)); 1427 1428 splx(s); 1429 1430 } while (total_len > 0); 1431 1432 done: 1433 1434 /* Setup new transfer. */ 1435 usbd_setup_xfer(xfer, c, c->axe_buf, sc->axe_bufsz, 1436 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1437 usbd_transfer(xfer); 1438 1439 DPRINTFN(10, "start rx", 0, 0, 0, 0); 1440 } 1441 1442 /* 1443 * A frame was downloaded to the chip. It's safe for us to clean up 1444 * the list buffers. 1445 */ 1446 1447 static void 1448 axe_txeof(struct usbd_xfer *xfer, void * priv, usbd_status status) 1449 { 1450 AXEHIST_FUNC(); AXEHIST_CALLED(); 1451 struct axe_chain *c = priv; 1452 struct axe_softc *sc = c->axe_sc; 1453 struct ifnet *ifp = &sc->sc_if; 1454 int s; 1455 1456 1457 if (sc->axe_dying) 1458 return; 1459 1460 s = splnet(); 1461 1462 ifp->if_timer = 0; 1463 ifp->if_flags &= ~IFF_OACTIVE; 1464 1465 if (status != USBD_NORMAL_COMPLETION) { 1466 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1467 splx(s); 1468 return; 1469 } 1470 ifp->if_oerrors++; 1471 aprint_error_dev(sc->axe_dev, "usb error on tx: %s\n", 1472 usbd_errstr(status)); 1473 if (status == USBD_STALLED) 1474 usbd_clear_endpoint_stall_async(sc->axe_ep[AXE_ENDPT_TX]); 1475 splx(s); 1476 return; 1477 } 1478 ifp->if_opackets++; 1479 1480 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1481 axe_start(ifp); 1482 1483 splx(s); 1484 } 1485 1486 static void 1487 axe_tick(void *xsc) 1488 { 1489 AXEHIST_FUNC(); AXEHIST_CALLED(); 1490 struct axe_softc *sc = xsc; 1491 1492 if (sc == NULL) 1493 return; 1494 1495 if (sc->axe_dying) 1496 return; 1497 1498 /* Perform periodic stuff in process context */ 1499 usb_add_task(sc->axe_udev, &sc->axe_tick_task, USB_TASKQ_DRIVER); 1500 } 1501 1502 static void 1503 axe_tick_task(void *xsc) 1504 { 1505 AXEHIST_FUNC(); AXEHIST_CALLED(); 1506 int s; 1507 struct axe_softc *sc = xsc; 1508 struct ifnet *ifp; 1509 struct mii_data *mii; 1510 1511 if (sc == NULL) 1512 return; 1513 1514 if (sc->axe_dying) 1515 return; 1516 1517 ifp = &sc->sc_if; 1518 mii = &sc->axe_mii; 1519 1520 if (mii == NULL) 1521 return; 1522 1523 s = splnet(); 1524 1525 mii_tick(mii); 1526 if (sc->axe_link == 0 && 1527 (mii->mii_media_status & IFM_ACTIVE) != 0 && 1528 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1529 DPRINTF("got link", 0, 0, 0, 0); 1530 sc->axe_link++; 1531 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1532 axe_start(ifp); 1533 } 1534 1535 callout_schedule(&sc->axe_stat_ch, hz); 1536 1537 splx(s); 1538 } 1539 1540 static int 1541 axe_encap(struct axe_softc *sc, struct mbuf *m, int idx) 1542 { 1543 struct ifnet *ifp = &sc->sc_if; 1544 struct axe_chain *c; 1545 usbd_status err; 1546 int length, boundary; 1547 1548 c = &sc->axe_cdata.axe_tx_chain[idx]; 1549 1550 /* 1551 * Copy the mbuf data into a contiguous buffer, leaving two 1552 * bytes at the beginning to hold the frame length. 1553 */ 1554 if (AXE_IS_178_FAMILY(sc)) { 1555 struct axe_sframe_hdr hdr; 1556 1557 boundary = (sc->axe_udev->ud_speed == USB_SPEED_HIGH) ? 512 : 64; 1558 1559 hdr.len = htole16(m->m_pkthdr.len); 1560 hdr.ilen = ~hdr.len; 1561 1562 memcpy(c->axe_buf, &hdr, sizeof(hdr)); 1563 length = sizeof(hdr); 1564 1565 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf + length); 1566 length += m->m_pkthdr.len; 1567 1568 if ((length % boundary) == 0) { 1569 hdr.len = 0x0000; 1570 hdr.ilen = 0xffff; 1571 memcpy(c->axe_buf + length, &hdr, sizeof(hdr)); 1572 length += sizeof(hdr); 1573 } 1574 } else { 1575 m_copydata(m, 0, m->m_pkthdr.len, c->axe_buf); 1576 length = m->m_pkthdr.len; 1577 } 1578 1579 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, length, 1580 USBD_FORCE_SHORT_XFER, 10000, axe_txeof); 1581 1582 /* Transmit */ 1583 err = usbd_transfer(c->axe_xfer); 1584 if (err != USBD_IN_PROGRESS) { 1585 axe_stop(ifp, 0); 1586 return EIO; 1587 } 1588 1589 sc->axe_cdata.axe_tx_cnt++; 1590 1591 return 0; 1592 } 1593 1594 1595 static void 1596 axe_csum_cfg(struct axe_softc *sc) 1597 { 1598 struct ifnet *ifp = &sc->sc_if; 1599 uint16_t csum1, csum2; 1600 1601 if ((sc->axe_flags & AX772B) != 0) { 1602 csum1 = 0; 1603 csum2 = 0; 1604 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) != 0) 1605 csum1 |= AXE_TXCSUM_IP; 1606 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx) != 0) 1607 csum1 |= AXE_TXCSUM_TCP; 1608 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx) != 0) 1609 csum1 |= AXE_TXCSUM_UDP; 1610 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Tx) != 0) 1611 csum1 |= AXE_TXCSUM_TCPV6; 1612 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Tx) != 0) 1613 csum1 |= AXE_TXCSUM_UDPV6; 1614 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1615 csum1 = 0; 1616 csum2 = 0; 1617 1618 if ((ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) != 0) 1619 csum1 |= AXE_RXCSUM_IP; 1620 if ((ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx) != 0) 1621 csum1 |= AXE_RXCSUM_TCP; 1622 if ((ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx) != 0) 1623 csum1 |= AXE_RXCSUM_UDP; 1624 if ((ifp->if_capenable & IFCAP_CSUM_TCPv6_Rx) != 0) 1625 csum1 |= AXE_RXCSUM_TCPV6; 1626 if ((ifp->if_capenable & IFCAP_CSUM_UDPv6_Rx) != 0) 1627 csum1 |= AXE_RXCSUM_UDPV6; 1628 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1629 } 1630 } 1631 1632 static void 1633 axe_start(struct ifnet *ifp) 1634 { 1635 struct axe_softc *sc; 1636 struct mbuf *m; 1637 1638 sc = ifp->if_softc; 1639 1640 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING) 1641 return; 1642 1643 IFQ_POLL(&ifp->if_snd, m); 1644 if (m == NULL) { 1645 return; 1646 } 1647 1648 if (axe_encap(sc, m, 0)) { 1649 ifp->if_flags |= IFF_OACTIVE; 1650 return; 1651 } 1652 IFQ_DEQUEUE(&ifp->if_snd, m); 1653 1654 /* 1655 * If there's a BPF listener, bounce a copy of this frame 1656 * to him. 1657 */ 1658 bpf_mtap(ifp, m, BPF_D_OUT); 1659 m_freem(m); 1660 1661 ifp->if_flags |= IFF_OACTIVE; 1662 1663 /* 1664 * Set a timeout in case the chip goes out to lunch. 1665 */ 1666 ifp->if_timer = 5; 1667 1668 return; 1669 } 1670 1671 static int 1672 axe_init(struct ifnet *ifp) 1673 { 1674 AXEHIST_FUNC(); AXEHIST_CALLED(); 1675 struct axe_softc *sc = ifp->if_softc; 1676 struct axe_chain *c; 1677 usbd_status err; 1678 int rxmode; 1679 int i, s; 1680 1681 s = splnet(); 1682 1683 if (ifp->if_flags & IFF_RUNNING) 1684 axe_stop(ifp, 0); 1685 1686 /* 1687 * Cancel pending I/O and free all RX/TX buffers. 1688 */ 1689 axe_reset(sc); 1690 1691 axe_lock_mii(sc); 1692 1693 #if 0 1694 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 | 1695 AX_GPIO_GPO2EN, 5, in_pm); 1696 #endif 1697 /* Set MAC address and transmitter IPG values. */ 1698 if (AXE_IS_178_FAMILY(sc)) { 1699 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1700 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->axe_ipgs[2], 1701 (sc->axe_ipgs[1] << 8) | (sc->axe_ipgs[0]), NULL); 1702 } else { 1703 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, sc->axe_enaddr); 1704 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->axe_ipgs[0], NULL); 1705 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->axe_ipgs[1], NULL); 1706 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->axe_ipgs[2], NULL); 1707 } 1708 if (AXE_IS_178_FAMILY(sc)) { 1709 sc->axe_flags &= ~(AXSTD_FRAME | AXCSUM_FRAME); 1710 if ((sc->axe_flags & AX772B) != 0 && 1711 (ifp->if_capenable & AX_RXCSUM) != 0) { 1712 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1713 sc->axe_flags |= AXCSUM_FRAME; 1714 } else { 1715 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1716 sc->axe_flags |= AXSTD_FRAME; 1717 } 1718 } 1719 1720 /* Configure TX/RX checksum offloading. */ 1721 axe_csum_cfg(sc); 1722 1723 if (sc->axe_flags & AX772B) { 1724 /* AX88772B uses different maximum frame burst configuration. */ 1725 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1726 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1727 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1728 } 1729 /* Enable receiver, set RX mode */ 1730 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1731 if (AXE_IS_178_FAMILY(sc)) { 1732 if (sc->axe_flags & AX772B) { 1733 /* 1734 * Select RX header format type 1. Aligning IP 1735 * header on 4 byte boundary is not needed when 1736 * checksum offloading feature is not used 1737 * because we always copy the received frame in 1738 * RX handler. When RX checksum offloading is 1739 * active, aligning IP header is required to 1740 * reflect actual frame length including RX 1741 * header size. 1742 */ 1743 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1744 if (sc->axe_flags & AXCSUM_FRAME) 1745 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1746 } else { 1747 /* 1748 * Default Rx buffer size is too small to get 1749 * maximum performance. 1750 */ 1751 #if 0 1752 if (sc->axe_udev->ud_speed == USB_SPEED_HIGH) { 1753 /* Largest possible USB buffer size for AX88178 */ 1754 #endif 1755 rxmode |= AXE_178_RXCMD_MFB_16384; 1756 } 1757 } else { 1758 rxmode |= AXE_172_RXCMD_UNICAST; 1759 } 1760 1761 1762 /* If we want promiscuous mode, set the allframes bit. */ 1763 if (ifp->if_flags & IFF_PROMISC) 1764 rxmode |= AXE_RXCMD_PROMISC; 1765 1766 if (ifp->if_flags & IFF_BROADCAST) 1767 rxmode |= AXE_RXCMD_BROADCAST; 1768 1769 DPRINTF("rxmode 0x%#jx", rxmode, 0, 0, 0); 1770 1771 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1772 axe_unlock_mii(sc); 1773 1774 /* Load the multicast filter. */ 1775 axe_setmulti(sc); 1776 1777 /* Open RX and TX pipes. */ 1778 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_RX], 1779 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_RX]); 1780 if (err) { 1781 aprint_error_dev(sc->axe_dev, "open rx pipe failed: %s\n", 1782 usbd_errstr(err)); 1783 splx(s); 1784 return EIO; 1785 } 1786 1787 err = usbd_open_pipe(sc->axe_iface, sc->axe_ed[AXE_ENDPT_TX], 1788 USBD_EXCLUSIVE_USE, &sc->axe_ep[AXE_ENDPT_TX]); 1789 if (err) { 1790 aprint_error_dev(sc->axe_dev, "open tx pipe failed: %s\n", 1791 usbd_errstr(err)); 1792 splx(s); 1793 return EIO; 1794 } 1795 1796 /* Init RX ring. */ 1797 if (axe_rx_list_init(sc) != 0) { 1798 aprint_error_dev(sc->axe_dev, "rx list init failed\n"); 1799 splx(s); 1800 return ENOBUFS; 1801 } 1802 1803 /* Init TX ring. */ 1804 if (axe_tx_list_init(sc) != 0) { 1805 aprint_error_dev(sc->axe_dev, "tx list init failed\n"); 1806 splx(s); 1807 return ENOBUFS; 1808 } 1809 1810 /* Start up the receive pipe. */ 1811 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1812 c = &sc->axe_cdata.axe_rx_chain[i]; 1813 usbd_setup_xfer(c->axe_xfer, c, c->axe_buf, sc->axe_bufsz, 1814 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, axe_rxeof); 1815 usbd_transfer(c->axe_xfer); 1816 } 1817 1818 ifp->if_flags |= IFF_RUNNING; 1819 ifp->if_flags &= ~IFF_OACTIVE; 1820 1821 splx(s); 1822 1823 callout_schedule(&sc->axe_stat_ch, hz); 1824 return 0; 1825 } 1826 1827 static int 1828 axe_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1829 { 1830 struct axe_softc *sc = ifp->if_softc; 1831 int s; 1832 int error = 0; 1833 1834 s = splnet(); 1835 1836 switch (cmd) { 1837 case SIOCSIFFLAGS: 1838 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1839 break; 1840 1841 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1842 case IFF_RUNNING: 1843 axe_stop(ifp, 1); 1844 break; 1845 case IFF_UP: 1846 axe_init(ifp); 1847 break; 1848 case IFF_UP | IFF_RUNNING: 1849 if ((ifp->if_flags ^ sc->axe_if_flags) == IFF_PROMISC) 1850 axe_setmulti(sc); 1851 else 1852 axe_init(ifp); 1853 break; 1854 } 1855 sc->axe_if_flags = ifp->if_flags; 1856 break; 1857 1858 default: 1859 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1860 break; 1861 1862 error = 0; 1863 1864 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI) 1865 axe_setmulti(sc); 1866 1867 } 1868 splx(s); 1869 1870 return error; 1871 } 1872 1873 static void 1874 axe_watchdog(struct ifnet *ifp) 1875 { 1876 struct axe_softc *sc; 1877 struct axe_chain *c; 1878 usbd_status stat; 1879 int s; 1880 1881 sc = ifp->if_softc; 1882 1883 ifp->if_oerrors++; 1884 aprint_error_dev(sc->axe_dev, "watchdog timeout\n"); 1885 1886 s = splusb(); 1887 c = &sc->axe_cdata.axe_tx_chain[0]; 1888 usbd_get_xfer_status(c->axe_xfer, NULL, NULL, NULL, &stat); 1889 axe_txeof(c->axe_xfer, c, stat); 1890 1891 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1892 axe_start(ifp); 1893 splx(s); 1894 } 1895 1896 /* 1897 * Stop the adapter and free any mbufs allocated to the 1898 * RX and TX lists. 1899 */ 1900 static void 1901 axe_stop(struct ifnet *ifp, int disable) 1902 { 1903 struct axe_softc *sc = ifp->if_softc; 1904 usbd_status err; 1905 int i; 1906 1907 ifp->if_timer = 0; 1908 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1909 1910 callout_stop(&sc->axe_stat_ch); 1911 1912 /* Stop transfers. */ 1913 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1914 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1915 if (err) { 1916 aprint_error_dev(sc->axe_dev, 1917 "abort rx pipe failed: %s\n", usbd_errstr(err)); 1918 } 1919 } 1920 1921 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1922 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1923 if (err) { 1924 aprint_error_dev(sc->axe_dev, 1925 "abort tx pipe failed: %s\n", usbd_errstr(err)); 1926 } 1927 } 1928 1929 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1930 err = usbd_abort_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1931 if (err) { 1932 aprint_error_dev(sc->axe_dev, 1933 "abort intr pipe failed: %s\n", usbd_errstr(err)); 1934 } 1935 } 1936 1937 axe_reset(sc); 1938 1939 /* Free RX resources. */ 1940 for (i = 0; i < AXE_RX_LIST_CNT; i++) { 1941 if (sc->axe_cdata.axe_rx_chain[i].axe_xfer != NULL) { 1942 usbd_destroy_xfer(sc->axe_cdata.axe_rx_chain[i].axe_xfer); 1943 sc->axe_cdata.axe_rx_chain[i].axe_xfer = NULL; 1944 } 1945 } 1946 1947 /* Free TX resources. */ 1948 for (i = 0; i < AXE_TX_LIST_CNT; i++) { 1949 if (sc->axe_cdata.axe_tx_chain[i].axe_xfer != NULL) { 1950 usbd_destroy_xfer(sc->axe_cdata.axe_tx_chain[i].axe_xfer); 1951 sc->axe_cdata.axe_tx_chain[i].axe_xfer = NULL; 1952 } 1953 } 1954 1955 /* Close pipes. */ 1956 if (sc->axe_ep[AXE_ENDPT_RX] != NULL) { 1957 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_RX]); 1958 if (err) { 1959 aprint_error_dev(sc->axe_dev, 1960 "close rx pipe failed: %s\n", usbd_errstr(err)); 1961 } 1962 sc->axe_ep[AXE_ENDPT_RX] = NULL; 1963 } 1964 1965 if (sc->axe_ep[AXE_ENDPT_TX] != NULL) { 1966 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_TX]); 1967 if (err) { 1968 aprint_error_dev(sc->axe_dev, 1969 "close tx pipe failed: %s\n", usbd_errstr(err)); 1970 } 1971 sc->axe_ep[AXE_ENDPT_TX] = NULL; 1972 } 1973 1974 if (sc->axe_ep[AXE_ENDPT_INTR] != NULL) { 1975 err = usbd_close_pipe(sc->axe_ep[AXE_ENDPT_INTR]); 1976 if (err) { 1977 aprint_error_dev(sc->axe_dev, 1978 "close intr pipe failed: %s\n", usbd_errstr(err)); 1979 } 1980 sc->axe_ep[AXE_ENDPT_INTR] = NULL; 1981 } 1982 1983 sc->axe_link = 0; 1984 } 1985 1986 MODULE(MODULE_CLASS_DRIVER, if_axe, NULL); 1987 1988 #ifdef _MODULE 1989 #include "ioconf.c" 1990 #endif 1991 1992 static int 1993 if_axe_modcmd(modcmd_t cmd, void *aux) 1994 { 1995 int error = 0; 1996 1997 switch (cmd) { 1998 case MODULE_CMD_INIT: 1999 #ifdef _MODULE 2000 error = config_init_component(cfdriver_ioconf_axe, 2001 cfattach_ioconf_axe, cfdata_ioconf_axe); 2002 #endif 2003 return error; 2004 case MODULE_CMD_FINI: 2005 #ifdef _MODULE 2006 error = config_fini_component(cfdriver_ioconf_axe, 2007 cfattach_ioconf_axe, cfdata_ioconf_axe); 2008 #endif 2009 return error; 2010 default: 2011 return ENOTTY; 2012 } 2013 } 2014
Indexes created Fri Sep 26 08:10:20 GMT 2025