if_axereg.h revision 1.16
1 /* $NetBSD: if_axereg.h,v 1.16 2013/11/08 17:46:35 roy Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/usb/if_axereg.h,v 1.2 2003/06/15 21:45:43 wpaul Exp $ 35 */ 36 37 /* 38 * Definitions for the ASIX Electronics AX88172 to ethernet controller. 39 */ 40 41 42 /* 43 * Vendor specific commands 44 * ASIX conveniently doesn't document the 'set NODEID' command in their 45 * datasheet (thanks a lot guys). 46 * To make handling these commands easier, I added some extra data 47 * which is decided by the axe_cmd() routine. Commands are encoded 48 * in 16 bites, with the format: LDCC. L and D are both nibbles in 49 * the high byte. L represents the data length (0 to 15) and D 50 * represents the direction (0 for vendor read, 1 for vendor write). 51 * CC is the command byte, as specified in the manual. 52 */ 53 54 #define AXE_CMD_DIR(x) (((x) & 0x0F00) >> 8) 55 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 56 #define AXE_CMD_CMD(x) ((x) & 0x00FF) 57 58 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002 59 #define AXE_182_CMD_READ_RXTX_SRAM 0x6002 60 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103 61 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104 62 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 63 #define AXE_CMD_MII_OPMODE_SW 0x0106 64 #define AXE_CMD_MII_READ_REG 0x2007 65 #define AXE_CMD_MII_WRITE_REG 0x2108 66 #define AXE_CMD_MII_READ_OPMODE 0x1009 67 #define AXE_CMD_MII_OPMODE_HW 0x010A 68 #define AXE_CMD_SROM_READ 0x200B 69 #define AXE_CMD_SROM_WRITE 0x010C 70 #define AXE_CMD_SROM_WR_ENABLE 0x010D 71 #define AXE_CMD_SROM_WR_DISABLE 0x010E 72 #define AXE_CMD_RXCTL_READ 0x200F 73 #define AXE_CMD_RXCTL_WRITE 0x0110 74 #define AXE_CMD_READ_IPG012 0x3011 75 #define AXE_172_CMD_WRITE_IPG0 0x0112 76 #define AXE_172_CMD_WRITE_IPG1 0x0113 77 #define AXE_172_CMD_WRITE_IPG2 0x0114 78 #define AXE_178_CMD_WRITE_IPG012 0x0112 79 #define AXE_CMD_READ_MCAST 0x8015 80 #define AXE_CMD_WRITE_MCAST 0x8116 81 #define AXE_172_CMD_READ_NODEID 0x6017 82 #define AXE_172_CMD_WRITE_NODEID 0x6118 83 #define AXE_178_CMD_READ_NODEID 0x6013 84 #define AXE_178_CMD_WRITE_NODEID 0x6114 85 #define AXE_CMD_READ_PHYID 0x2019 86 #define AXE_172_CMD_READ_MEDIA 0x101A 87 #define AXE_178_CMD_READ_MEDIA 0x201A 88 #define AXE_CMD_WRITE_MEDIA 0x011B 89 #define AXE_CMD_READ_MONITOR_MODE 0x101C 90 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D 91 #define AXE_CMD_READ_GPIO 0x101E 92 #define AXE_CMD_WRITE_GPIO 0x011F 93 #define AXE_CMD_SW_RESET_REG 0x0120 94 #define AXE_CMD_SW_PHY_STATUS 0x0021 95 #define AXE_CMD_SW_PHY_SELECT 0x0122 96 97 #define AXE_SW_RESET_CLEAR 0x00 98 #define AXE_SW_RESET_RR 0x01 99 #define AXE_SW_RESET_RT 0x02 100 #define AXE_SW_RESET_PRTE 0x04 101 #define AXE_SW_RESET_PRL 0x08 102 #define AXE_SW_RESET_BZ 0x10 103 #define AXE_SW_RESET_IPRL 0x20 104 #define AXE_SW_RESET_IPPD 0x40 105 106 /* AX88178 documentation says to always write this bit... */ 107 #define AXE_178_RESET_MAGIC 0x40 108 109 #define AXE_178_MEDIA_GMII 0x0001 110 #define AXE_MEDIA_FULL_DUPLEX 0x0002 111 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 112 /* AX88178 documentation says to always write 1 to reserved bit... */ 113 #define AXE_178_MEDIA_MAGIC 0x0004 114 #define AXE_178_MEDIA_ENCK 0x0008 115 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 116 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 117 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 118 #define AXE_178_MEDIA_JUMBO_EN 0x0040 119 #define AXE_178_MEDIA_LTPF_ONLY 0x0080 120 #define AXE_178_MEDIA_RX_EN 0x0100 121 #define AXE_178_MEDIA_100TX 0x0200 122 #define AXE_178_MEDIA_SBP 0x0800 123 #define AXE_178_MEDIA_SUPERMAC 0x1000 124 125 #define AXE_PHY_SEL_PRI 1 126 #define AXE_PHY_SEL_SEC 0 127 #define AXE_PHY_TYPE_MASK 0xE0 128 #define AXE_PHY_TYPE_SHIFT 5 129 #define AXE_PHY_TYPE(x) \ 130 (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 131 132 #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 133 #define PHY_TYPE_GIG 1 /* Gigabit PHY */ 134 #define PHY_TYPE_SPECIAL 4 /* Special case */ 135 #define PHY_TYPE_RSVD 5 /* Reserved */ 136 #define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 137 138 #define AXE_PHY_NO_MASK 0x1F 139 #define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 140 141 #define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 142 143 #define AXE_GPIO0_EN 0x01 144 #define AXE_GPIO0 0x02 145 #define AXE_GPIO1_EN 0x04 146 #define AXE_GPIO1 0x08 147 #define AXE_GPIO2_EN 0x10 148 #define AXE_GPIO2 0x20 149 #define AXE_GPIO_RELOAD_EEPROM 0x80 150 151 #define AXE_PHY_MODE_MARVELL 0x00 152 #define AXE_PHY_MODE_CICADA 0x01 153 #define AXE_PHY_MODE_AGERE 0x02 154 #define AXE_PHY_MODE_CICADA_V2 0x05 155 #define AXE_PHY_MODE_AGERE_GMII 0x06 156 #define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 157 #define AXE_PHY_MODE_REALTEK_8211CL 0x0C 158 #define AXE_PHY_MODE_REALTEK_8211BN 0x0D 159 #define AXE_PHY_MODE_REALTEK_8251CL 0x0E 160 #define AXE_PHY_MODE_ATTANSIC 0x40 161 162 #define AXE_RXCMD_PROMISC 0x0001 163 #define AXE_RXCMD_ALLMULTI 0x0002 164 #define AXE_172_RXCMD_UNICAST 0x0004 165 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 166 #define AXE_RXCMD_BROADCAST 0x0008 167 #define AXE_RXCMD_MULTICAST 0x0010 168 #define AXE_RXCMD_ENABLE 0x0080 169 #define AXE_178_RXCMD_MFB 0x0300 170 171 #define AXE_NOPHY 0xE0 172 #define AXE_INTPHY 0x10 173 174 #define AXE_772B_RXCMD_RH1M 0x0100 175 #define AXE_772B_RXCMD_RH2M 0x0200 176 #define AXE_772B_RXCMD_RH3M 0x0400 177 178 #define AXE_RH1M_RXLEN_MASK 0x07ff 179 180 #define AXE_TIMEOUT 1000 181 182 #define AXE_172_BUFSZ 1536 183 #define AXE_178_MIN_BUFSZ 2048 184 #define AXE_178_MAX_BUFSZ 16384 185 186 #define AXE_MIN_FRAMELEN 60 187 #define AXE_RX_FRAMES 1 188 #define AXE_TX_FRAMES 1 189 190 #define AXE_RX_LIST_CNT 1 191 #define AXE_TX_LIST_CNT 1 192 193 #define AXE_CTL_READ 0x01 194 #define AXE_CTL_WRITE 0x02 195 196 #define AXE_CONFIG_NO 1 197 #define AXE_IFACE_IDX 0 198 199 /* 200 * The interrupt endpoint is currently unused 201 * by the ASIX part. 202 */ 203 #define AXE_ENDPT_RX 0x0 204 #define AXE_ENDPT_TX 0x1 205 #define AXE_ENDPT_INTR 0x2 206 #define AXE_ENDPT_MAX 0x3 207 208 struct axe_type { 209 struct usb_devno axe_dev; 210 uint16_t axe_flags; 211 #define AX178 0x0001 /* AX88178 */ 212 #define AX772 0x0002 /* AX88772 */ 213 #define AX772B 0x0004 /* AX88772B */ 214 #define AXE_ANY_PHY 0x1000 /* Chip lies about valid phys */ 215 #define AXE_MII 0x2000 /* Chip-specific MII handling */ 216 }; 217 218 struct axe_softc; 219 220 struct axe_chain { 221 struct axe_softc *axe_sc; 222 usbd_xfer_handle axe_xfer; 223 uint8_t *axe_buf; 224 int axe_accum; 225 int axe_idx; 226 }; 227 228 struct axe_cdata { 229 struct axe_chain axe_tx_chain[AXE_TX_LIST_CNT]; 230 struct axe_chain axe_rx_chain[AXE_RX_LIST_CNT]; 231 int axe_tx_prod; 232 int axe_tx_cons; 233 int axe_tx_cnt; 234 int axe_rx_prod; 235 }; 236 237 struct axe_sframe_hdr { 238 uint16_t len; 239 uint16_t ilen; 240 } __packed; 241 242 struct axe_softc { 243 device_t axe_dev; 244 struct ethercom axe_ec; 245 struct mii_data axe_mii; 246 krndsource_t rnd_source; 247 usbd_device_handle axe_udev; 248 usbd_interface_handle axe_iface; 249 250 uint16_t axe_vendor; 251 uint16_t axe_product; 252 uint16_t axe_flags; 253 254 int axe_ed[AXE_ENDPT_MAX]; 255 usbd_pipe_handle axe_ep[AXE_ENDPT_MAX]; 256 int axe_if_flags; 257 struct axe_cdata axe_cdata; 258 struct callout axe_stat_ch; 259 260 int axe_refcnt; 261 bool axe_dying; 262 bool axe_attached; 263 264 struct usb_task axe_tick_task; 265 266 kmutex_t axe_mii_lock; 267 268 int axe_link; 269 270 uint8_t axe_ipgs[3]; 271 uint8_t axe_phyaddrs[2]; 272 int axe_phyno; 273 struct timeval axe_rx_notice; 274 int axe_bufsz; 275 276 #define sc_if axe_ec.ec_if 277 }; 278 279 #define ETHER_ALIGN 2 280
Indexes created Fri Sep 26 08:10:20 GMT 2025