if_mue.c revision 1.44 1 1.44 msaitoh /* $NetBSD: if_mue.c,v 1.44 2019/05/23 10:57:29 msaitoh Exp $ */
2 1.1 rin /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3 1.1 rin
4 1.1 rin /*
5 1.1 rin * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 1.1 rin *
7 1.1 rin * Permission to use, copy, modify, and distribute this software for any
8 1.1 rin * purpose with or without fee is hereby granted, provided that the above
9 1.1 rin * copyright notice and this permission notice appear in all copies.
10 1.1 rin *
11 1.1 rin * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 1.1 rin * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 1.1 rin * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 1.1 rin * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 1.1 rin * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 1.1 rin * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 1.1 rin * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 1.1 rin */
19 1.1 rin
20 1.1 rin /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21 1.1 rin
22 1.1 rin #include <sys/cdefs.h>
23 1.44 msaitoh __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.44 2019/05/23 10:57:29 msaitoh Exp $");
24 1.1 rin
25 1.1 rin #ifdef _KERNEL_OPT
26 1.1 rin #include "opt_usb.h"
27 1.1 rin #include "opt_inet.h"
28 1.1 rin #endif
29 1.1 rin
30 1.1 rin #include <sys/param.h>
31 1.1 rin #include <sys/bus.h>
32 1.1 rin #include <sys/systm.h>
33 1.1 rin #include <sys/sockio.h>
34 1.1 rin #include <sys/mbuf.h>
35 1.1 rin #include <sys/mutex.h>
36 1.1 rin #include <sys/kernel.h>
37 1.1 rin #include <sys/proc.h>
38 1.1 rin #include <sys/socket.h>
39 1.1 rin
40 1.1 rin #include <sys/device.h>
41 1.1 rin
42 1.1 rin #include <sys/rndsource.h>
43 1.1 rin
44 1.1 rin #include <net/if.h>
45 1.1 rin #include <net/if_dl.h>
46 1.1 rin #include <net/if_media.h>
47 1.1 rin #include <net/if_ether.h>
48 1.1 rin
49 1.1 rin #include <net/bpf.h>
50 1.1 rin
51 1.3 rin #include <netinet/if_inarp.h>
52 1.1 rin #include <netinet/in.h>
53 1.3 rin #include <netinet/ip.h> /* XXX for struct ip */
54 1.3 rin #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
55 1.1 rin
56 1.1 rin #include <dev/mii/mii.h>
57 1.1 rin #include <dev/mii/miivar.h>
58 1.1 rin
59 1.1 rin #include <dev/usb/usb.h>
60 1.1 rin #include <dev/usb/usbdi.h>
61 1.1 rin #include <dev/usb/usbdi_util.h>
62 1.1 rin #include <dev/usb/usbdivar.h>
63 1.1 rin #include <dev/usb/usbdevs.h>
64 1.1 rin
65 1.1 rin #include <dev/usb/if_muereg.h>
66 1.1 rin #include <dev/usb/if_muevar.h>
67 1.1 rin
68 1.1 rin #define MUE_PRINTF(sc, fmt, args...) \
69 1.1 rin device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
70 1.1 rin
71 1.1 rin #ifdef USB_DEBUG
72 1.1 rin int muedebug = 0;
73 1.1 rin #define DPRINTF(sc, fmt, args...) \
74 1.1 rin do { \
75 1.1 rin if (muedebug) \
76 1.1 rin MUE_PRINTF(sc, fmt, ##args); \
77 1.1 rin } while (0 /* CONSTCOND */)
78 1.1 rin #else
79 1.26 rin #define DPRINTF(sc, fmt, args...) __nothing
80 1.1 rin #endif
81 1.1 rin
82 1.1 rin /*
83 1.1 rin * Various supported device vendors/products.
84 1.1 rin */
85 1.1 rin struct mue_type {
86 1.1 rin struct usb_devno mue_dev;
87 1.1 rin uint16_t mue_flags;
88 1.1 rin #define LAN7500 0x0001 /* LAN7500 */
89 1.1 rin };
90 1.1 rin
91 1.1 rin const struct mue_type mue_devs[] = {
92 1.1 rin { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
93 1.1 rin { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
94 1.1 rin { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
95 1.1 rin { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
96 1.1 rin { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
97 1.1 rin };
98 1.1 rin
99 1.1 rin #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
100 1.1 rin uaa->uaa_vendor, uaa->uaa_product))
101 1.1 rin
102 1.1 rin #define MUE_ENADDR_LO(enaddr) \
103 1.1 rin ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
104 1.1 rin #define MUE_ENADDR_HI(enaddr) \
105 1.1 rin ((enaddr[5] << 8) | enaddr[4])
106 1.1 rin
107 1.1 rin static int mue_match(device_t, cfdata_t, void *);
108 1.1 rin static void mue_attach(device_t, device_t, void *);
109 1.1 rin static int mue_detach(device_t, int);
110 1.1 rin static int mue_activate(device_t, enum devact);
111 1.1 rin
112 1.1 rin static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
113 1.1 rin static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
114 1.1 rin static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
115 1.1 rin uint32_t, uint32_t);
116 1.1 rin
117 1.1 rin static void mue_lock_mii(struct mue_softc *);
118 1.1 rin static void mue_unlock_mii(struct mue_softc *);
119 1.1 rin
120 1.28 msaitoh static int mue_miibus_readreg(device_t, int, int, uint16_t *);
121 1.28 msaitoh static int mue_miibus_writereg(device_t, int, int, uint16_t);
122 1.1 rin static void mue_miibus_statchg(struct ifnet *);
123 1.1 rin static int mue_ifmedia_upd(struct ifnet *);
124 1.1 rin static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125 1.1 rin
126 1.1 rin static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
127 1.1 rin static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
128 1.1 rin static bool mue_eeprom_present(struct mue_softc *sc);
129 1.1 rin
130 1.1 rin static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
131 1.1 rin static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
132 1.1 rin
133 1.1 rin static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
134 1.1 rin uint32_t, uint32_t *);
135 1.1 rin
136 1.1 rin static void mue_init_ltm(struct mue_softc *);
137 1.1 rin
138 1.1 rin static int mue_chip_init(struct mue_softc *);
139 1.1 rin
140 1.1 rin static void mue_set_macaddr(struct mue_softc *);
141 1.1 rin static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
142 1.1 rin
143 1.1 rin static int mue_rx_list_init(struct mue_softc *);
144 1.1 rin static int mue_tx_list_init(struct mue_softc *);
145 1.1 rin static int mue_open_pipes(struct mue_softc *);
146 1.18 rin static void mue_startup_rx_pipes(struct mue_softc *);
147 1.1 rin
148 1.1 rin static int mue_encap(struct mue_softc *, struct mbuf *, int);
149 1.37 rin static int mue_prepare_tso(struct mue_softc *, struct mbuf *);
150 1.1 rin
151 1.1 rin static void mue_setmulti(struct mue_softc *);
152 1.1 rin static void mue_sethwcsum(struct mue_softc *);
153 1.22 rin static void mue_setmtu(struct mue_softc *);
154 1.1 rin
155 1.1 rin static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
156 1.1 rin static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
157 1.1 rin
158 1.1 rin static int mue_init(struct ifnet *);
159 1.1 rin static int mue_ioctl(struct ifnet *, u_long, void *);
160 1.1 rin static void mue_watchdog(struct ifnet *);
161 1.1 rin static void mue_reset(struct mue_softc *);
162 1.1 rin static void mue_start(struct ifnet *);
163 1.1 rin static void mue_stop(struct ifnet *, int);
164 1.1 rin static void mue_tick(void *);
165 1.1 rin static void mue_tick_task(void *);
166 1.1 rin
167 1.1 rin static struct mbuf *mue_newbuf(void);
168 1.1 rin
169 1.1 rin #define MUE_SETBIT(sc, reg, x) \
170 1.1 rin mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
171 1.1 rin
172 1.1 rin #define MUE_CLRBIT(sc, reg, x) \
173 1.1 rin mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
174 1.1 rin
175 1.1 rin #define MUE_WAIT_SET(sc, reg, set, fail) \
176 1.1 rin mue_wait_for_bits(sc, reg, set, ~0, fail)
177 1.1 rin
178 1.1 rin #define MUE_WAIT_CLR(sc, reg, clear, fail) \
179 1.1 rin mue_wait_for_bits(sc, reg, 0, clear, fail)
180 1.1 rin
181 1.1 rin #define ETHER_IS_VALID(addr) \
182 1.1 rin (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
183 1.1 rin
184 1.1 rin #define ETHER_IS_ZERO(addr) \
185 1.1 rin (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
186 1.1 rin
187 1.1 rin CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
188 1.1 rin mue_detach, mue_activate);
189 1.1 rin
190 1.1 rin static uint32_t
191 1.1 rin mue_csr_read(struct mue_softc *sc, uint32_t reg)
192 1.1 rin {
193 1.1 rin usb_device_request_t req;
194 1.1 rin usbd_status err;
195 1.1 rin uDWord val;
196 1.1 rin
197 1.1 rin if (sc->mue_dying)
198 1.1 rin return 0;
199 1.1 rin
200 1.1 rin USETDW(val, 0);
201 1.1 rin req.bmRequestType = UT_READ_VENDOR_DEVICE;
202 1.1 rin req.bRequest = MUE_UR_READREG;
203 1.1 rin USETW(req.wValue, 0);
204 1.1 rin USETW(req.wIndex, reg);
205 1.1 rin USETW(req.wLength, 4);
206 1.1 rin
207 1.1 rin err = usbd_do_request(sc->mue_udev, &req, &val);
208 1.1 rin if (err) {
209 1.1 rin MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
210 1.1 rin return 0;
211 1.1 rin }
212 1.1 rin
213 1.1 rin return UGETDW(val);
214 1.1 rin }
215 1.1 rin
216 1.1 rin static int
217 1.1 rin mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
218 1.1 rin {
219 1.1 rin usb_device_request_t req;
220 1.1 rin usbd_status err;
221 1.1 rin uDWord val;
222 1.1 rin
223 1.1 rin if (sc->mue_dying)
224 1.1 rin return 0;
225 1.1 rin
226 1.1 rin USETDW(val, aval);
227 1.1 rin req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
228 1.1 rin req.bRequest = MUE_UR_WRITEREG;
229 1.1 rin USETW(req.wValue, 0);
230 1.1 rin USETW(req.wIndex, reg);
231 1.1 rin USETW(req.wLength, 4);
232 1.1 rin
233 1.1 rin err = usbd_do_request(sc->mue_udev, &req, &val);
234 1.1 rin if (err) {
235 1.1 rin MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
236 1.1 rin return -1;
237 1.1 rin }
238 1.1 rin
239 1.1 rin return 0;
240 1.1 rin }
241 1.1 rin
242 1.1 rin static int
243 1.1 rin mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
244 1.1 rin uint32_t set, uint32_t clear, uint32_t fail)
245 1.1 rin {
246 1.1 rin uint32_t val;
247 1.1 rin int ntries;
248 1.1 rin
249 1.1 rin for (ntries = 0; ntries < 1000; ntries++) {
250 1.1 rin val = mue_csr_read(sc, reg);
251 1.1 rin if ((val & set) || !(val & clear))
252 1.1 rin return 0;
253 1.1 rin if (val & fail)
254 1.1 rin return 1;
255 1.1 rin usbd_delay_ms(sc->mue_udev, 1);
256 1.1 rin }
257 1.1 rin
258 1.1 rin return 1;
259 1.1 rin }
260 1.1 rin
261 1.1 rin /*
262 1.1 rin * Get exclusive access to the MII registers.
263 1.1 rin */
264 1.1 rin static void
265 1.1 rin mue_lock_mii(struct mue_softc *sc)
266 1.1 rin {
267 1.1 rin sc->mue_refcnt++;
268 1.1 rin mutex_enter(&sc->mue_mii_lock);
269 1.1 rin }
270 1.1 rin
271 1.1 rin static void
272 1.1 rin mue_unlock_mii(struct mue_softc *sc)
273 1.1 rin {
274 1.1 rin mutex_exit(&sc->mue_mii_lock);
275 1.1 rin if (--sc->mue_refcnt < 0)
276 1.1 rin usb_detach_wakeupold(sc->mue_dev);
277 1.1 rin }
278 1.1 rin
279 1.1 rin static int
280 1.28 msaitoh mue_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
281 1.1 rin {
282 1.1 rin struct mue_softc *sc = device_private(dev);
283 1.28 msaitoh uint32_t data;
284 1.28 msaitoh int rv = 0;
285 1.1 rin
286 1.1 rin if (sc->mue_dying) {
287 1.1 rin DPRINTF(sc, "dying\n");
288 1.28 msaitoh return -1;
289 1.1 rin }
290 1.1 rin
291 1.1 rin if (sc->mue_phyno != phy)
292 1.28 msaitoh return -1;
293 1.1 rin
294 1.1 rin mue_lock_mii(sc);
295 1.1 rin if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
296 1.1 rin mue_unlock_mii(sc);
297 1.1 rin MUE_PRINTF(sc, "not ready\n");
298 1.1 rin return -1;
299 1.1 rin }
300 1.1 rin
301 1.1 rin mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
302 1.1 rin MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
303 1.1 rin MUE_MII_ACCESS_PHYADDR(phy));
304 1.1 rin
305 1.1 rin if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
306 1.1 rin MUE_PRINTF(sc, "timed out\n");
307 1.28 msaitoh rv = ETIMEDOUT;
308 1.28 msaitoh goto out;
309 1.1 rin }
310 1.1 rin
311 1.28 msaitoh data = mue_csr_read(sc, MUE_MII_DATA);
312 1.28 msaitoh *val = data & 0xffff;
313 1.28 msaitoh
314 1.28 msaitoh out:
315 1.1 rin mue_unlock_mii(sc);
316 1.28 msaitoh return rv;
317 1.1 rin }
318 1.1 rin
319 1.28 msaitoh static int
320 1.28 msaitoh mue_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
321 1.1 rin {
322 1.1 rin struct mue_softc *sc = device_private(dev);
323 1.28 msaitoh int rv = 0;
324 1.1 rin
325 1.1 rin if (sc->mue_dying) {
326 1.1 rin DPRINTF(sc, "dying\n");
327 1.28 msaitoh return -1;
328 1.1 rin }
329 1.1 rin
330 1.1 rin if (sc->mue_phyno != phy) {
331 1.1 rin DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
332 1.1 rin sc->mue_phyno, phy);
333 1.28 msaitoh return -1;
334 1.1 rin }
335 1.1 rin
336 1.1 rin mue_lock_mii(sc);
337 1.1 rin if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
338 1.1 rin MUE_PRINTF(sc, "not ready\n");
339 1.28 msaitoh rv = EBUSY;
340 1.28 msaitoh goto out;
341 1.1 rin }
342 1.1 rin
343 1.28 msaitoh mue_csr_write(sc, MUE_MII_DATA, val);
344 1.1 rin mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
345 1.1 rin MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
346 1.1 rin MUE_MII_ACCESS_PHYADDR(phy));
347 1.1 rin
348 1.28 msaitoh if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
349 1.1 rin MUE_PRINTF(sc, "timed out\n");
350 1.28 msaitoh rv = ETIMEDOUT;
351 1.28 msaitoh }
352 1.28 msaitoh out:
353 1.1 rin mue_unlock_mii(sc);
354 1.28 msaitoh return rv;
355 1.1 rin }
356 1.1 rin
357 1.1 rin static void
358 1.1 rin mue_miibus_statchg(struct ifnet *ifp)
359 1.1 rin {
360 1.34 rin struct mue_softc *sc;
361 1.34 rin struct mii_data *mii;
362 1.1 rin uint32_t flow, threshold;
363 1.1 rin
364 1.34 rin if (ifp == NULL) {
365 1.40 rin printf("%s: ifp not ready\n", __func__);
366 1.34 rin return;
367 1.34 rin }
368 1.34 rin
369 1.40 rin sc = ifp->if_softc;
370 1.40 rin mii = GET_MII(sc);
371 1.40 rin
372 1.34 rin if ((ifp->if_flags & IFF_RUNNING) == 0) {
373 1.34 rin DPRINTF(sc, "not running\n");
374 1.34 rin return;
375 1.34 rin }
376 1.34 rin
377 1.34 rin if (mii == NULL) {
378 1.34 rin DPRINTF(sc, "mii not ready\n");
379 1.1 rin return;
380 1.1 rin }
381 1.1 rin
382 1.1 rin sc->mue_link = 0;
383 1.1 rin if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
384 1.1 rin (IFM_ACTIVE | IFM_AVALID)) {
385 1.1 rin switch (IFM_SUBTYPE(mii->mii_media_active)) {
386 1.1 rin case IFM_10_T:
387 1.1 rin case IFM_100_TX:
388 1.1 rin case IFM_1000_T:
389 1.1 rin sc->mue_link++;
390 1.1 rin break;
391 1.1 rin default:
392 1.1 rin break;
393 1.1 rin }
394 1.1 rin }
395 1.1 rin
396 1.1 rin /* Lost link, do nothing. */
397 1.1 rin if (sc->mue_link == 0) {
398 1.1 rin DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
399 1.1 rin return;
400 1.1 rin }
401 1.1 rin
402 1.1 rin if (!(sc->mue_flags & LAN7500)) {
403 1.1 rin if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
404 1.1 rin if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
405 1.1 rin /* Disable U2 and enable U1. */
406 1.1 rin MUE_CLRBIT(sc, MUE_USB_CFG1,
407 1.1 rin MUE_USB_CFG1_DEV_U2_INIT_EN);
408 1.1 rin MUE_SETBIT(sc, MUE_USB_CFG1,
409 1.1 rin MUE_USB_CFG1_DEV_U1_INIT_EN);
410 1.1 rin } else {
411 1.1 rin /* Enable U1 and U2. */
412 1.1 rin MUE_SETBIT(sc, MUE_USB_CFG1,
413 1.1 rin MUE_USB_CFG1_DEV_U1_INIT_EN |
414 1.1 rin MUE_USB_CFG1_DEV_U2_INIT_EN);
415 1.1 rin }
416 1.1 rin }
417 1.1 rin }
418 1.1 rin
419 1.1 rin flow = 0;
420 1.1 rin /* XXX Linux does not check IFM_FDX flag for 7800. */
421 1.1 rin if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
422 1.1 rin if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
423 1.1 rin flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
424 1.1 rin if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
425 1.1 rin flow |= MUE_FLOW_RX_FCEN;
426 1.1 rin }
427 1.1 rin
428 1.1 rin /* XXX Magic numbers taken from Linux driver. */
429 1.1 rin if (sc->mue_flags & LAN7500)
430 1.1 rin threshold = 0x820;
431 1.1 rin else
432 1.1 rin switch (sc->mue_udev->ud_speed) {
433 1.1 rin case USB_SPEED_SUPER:
434 1.1 rin threshold = 0x817;
435 1.1 rin break;
436 1.1 rin case USB_SPEED_HIGH:
437 1.1 rin threshold = 0x211;
438 1.1 rin break;
439 1.1 rin default:
440 1.1 rin threshold = 0;
441 1.1 rin break;
442 1.1 rin }
443 1.1 rin
444 1.1 rin /* Threshold value should be set before enabling flow. */
445 1.1 rin mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
446 1.1 rin MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
447 1.1 rin mue_csr_write(sc, MUE_FLOW, flow);
448 1.1 rin
449 1.1 rin DPRINTF(sc, "done\n");
450 1.1 rin }
451 1.1 rin
452 1.1 rin /*
453 1.1 rin * Set media options.
454 1.1 rin */
455 1.1 rin static int
456 1.1 rin mue_ifmedia_upd(struct ifnet *ifp)
457 1.1 rin {
458 1.1 rin struct mue_softc *sc = ifp->if_softc;
459 1.1 rin struct mii_data *mii = GET_MII(sc);
460 1.1 rin
461 1.1 rin sc->mue_link = 0; /* XXX */
462 1.1 rin
463 1.1 rin if (mii->mii_instance) {
464 1.1 rin struct mii_softc *miisc;
465 1.1 rin LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
466 1.1 rin mii_phy_reset(miisc);
467 1.1 rin }
468 1.1 rin return mii_mediachg(mii);
469 1.1 rin }
470 1.1 rin
471 1.1 rin /*
472 1.1 rin * Report current media status.
473 1.1 rin */
474 1.1 rin static void
475 1.1 rin mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
476 1.1 rin {
477 1.1 rin struct mue_softc *sc = ifp->if_softc;
478 1.1 rin struct mii_data *mii = GET_MII(sc);
479 1.1 rin
480 1.1 rin mii_pollstat(mii);
481 1.1 rin ifmr->ifm_active = mii->mii_media_active;
482 1.1 rin ifmr->ifm_status = mii->mii_media_status;
483 1.1 rin }
484 1.1 rin
485 1.1 rin static uint8_t
486 1.1 rin mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
487 1.1 rin {
488 1.1 rin uint32_t val;
489 1.1 rin
490 1.1 rin if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
491 1.1 rin MUE_PRINTF(sc, "not ready\n");
492 1.1 rin return ETIMEDOUT;
493 1.1 rin }
494 1.1 rin
495 1.17 rin KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
496 1.1 rin mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
497 1.17 rin off);
498 1.1 rin
499 1.1 rin if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
500 1.1 rin MUE_E2P_CMD_TIMEOUT)) {
501 1.1 rin MUE_PRINTF(sc, "timed out\n");
502 1.1 rin return ETIMEDOUT;
503 1.1 rin }
504 1.1 rin
505 1.1 rin val = mue_csr_read(sc, MUE_E2P_DATA);
506 1.1 rin *dest = val & 0xff;
507 1.1 rin
508 1.1 rin return 0;
509 1.1 rin }
510 1.1 rin
511 1.1 rin static int
512 1.1 rin mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
513 1.1 rin {
514 1.1 rin uint32_t val = 0; /* XXX gcc */
515 1.1 rin uint8_t byte;
516 1.42 martin int i, err = 0;
517 1.1 rin
518 1.1 rin /*
519 1.1 rin * EEPROM pins are muxed with the LED function on LAN7800 device.
520 1.1 rin */
521 1.1 rin if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
522 1.1 rin val = mue_csr_read(sc, MUE_HW_CFG);
523 1.1 rin mue_csr_write(sc, MUE_HW_CFG,
524 1.1 rin val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
525 1.1 rin }
526 1.1 rin
527 1.1 rin for (i = 0; i < cnt; i++) {
528 1.1 rin err = mue_eeprom_getbyte(sc, off + i, &byte);
529 1.1 rin if (err)
530 1.1 rin break;
531 1.1 rin *(dest + i) = byte;
532 1.1 rin }
533 1.1 rin
534 1.1 rin if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
535 1.1 rin mue_csr_write(sc, MUE_HW_CFG, val);
536 1.1 rin
537 1.1 rin return err ? 1 : 0;
538 1.1 rin }
539 1.1 rin
540 1.1 rin static bool
541 1.1 rin mue_eeprom_present(struct mue_softc *sc)
542 1.1 rin {
543 1.1 rin uint32_t val;
544 1.1 rin uint8_t sig;
545 1.1 rin int ret;
546 1.1 rin
547 1.1 rin if (sc->mue_flags & LAN7500) {
548 1.1 rin val = mue_csr_read(sc, MUE_E2P_CMD);
549 1.1 rin return val & MUE_E2P_CMD_LOADED;
550 1.1 rin } else {
551 1.1 rin ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
552 1.1 rin return (ret == 0) && (sig == MUE_E2P_IND);
553 1.1 rin }
554 1.1 rin }
555 1.1 rin
556 1.1 rin static int
557 1.1 rin mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
558 1.1 rin {
559 1.1 rin uint32_t val;
560 1.1 rin int i, err;
561 1.1 rin
562 1.1 rin val = mue_csr_read(sc, MUE_OTP_PWR_DN);
563 1.1 rin
564 1.1 rin /* Checking if bit is set. */
565 1.1 rin if (val & MUE_OTP_PWR_DN_PWRDN_N) {
566 1.1 rin /* Clear it, then wait for it to be cleared. */
567 1.1 rin mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
568 1.1 rin err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
569 1.1 rin 0);
570 1.1 rin if (err) {
571 1.1 rin MUE_PRINTF(sc, "not ready\n");
572 1.1 rin return 1;
573 1.1 rin }
574 1.1 rin }
575 1.1 rin
576 1.1 rin /* Start reading the bytes, one at a time. */
577 1.1 rin for (i = 0; i < cnt; i++) {
578 1.1 rin mue_csr_write(sc, MUE_OTP_ADDR1,
579 1.1 rin ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
580 1.1 rin mue_csr_write(sc, MUE_OTP_ADDR2,
581 1.1 rin ((off + i) & MUE_OTP_ADDR2_MASK));
582 1.1 rin mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
583 1.1 rin mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
584 1.1 rin
585 1.1 rin err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
586 1.1 rin if (err) {
587 1.1 rin MUE_PRINTF(sc, "timed out\n");
588 1.1 rin return 1;
589 1.1 rin }
590 1.1 rin val = mue_csr_read(sc, MUE_OTP_RD_DATA);
591 1.1 rin *(dest + i) = (uint8_t)(val & 0xff);
592 1.1 rin }
593 1.1 rin
594 1.1 rin return 0;
595 1.1 rin }
596 1.1 rin
597 1.1 rin static int
598 1.1 rin mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
599 1.1 rin {
600 1.1 rin uint8_t sig;
601 1.1 rin int err;
602 1.1 rin
603 1.1 rin if (sc->mue_flags & LAN7500)
604 1.1 rin return 1;
605 1.1 rin
606 1.1 rin err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
607 1.1 rin if (err)
608 1.1 rin return 1;
609 1.1 rin switch (sig) {
610 1.1 rin case MUE_OTP_IND_1:
611 1.1 rin break;
612 1.1 rin case MUE_OTP_IND_2:
613 1.1 rin off += 0x100;
614 1.1 rin break;
615 1.1 rin default:
616 1.1 rin DPRINTF(sc, "OTP not found\n");
617 1.1 rin return 1;
618 1.1 rin }
619 1.1 rin err = mue_read_otp_raw(sc, dest, off, cnt);
620 1.1 rin return err;
621 1.1 rin }
622 1.1 rin
623 1.1 rin static void
624 1.1 rin mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
625 1.1 rin uint32_t cnt, uint32_t *data)
626 1.1 rin {
627 1.1 rin uint32_t i;
628 1.1 rin
629 1.1 rin if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
630 1.1 rin MUE_PRINTF(sc, "not ready\n");
631 1.1 rin return;
632 1.1 rin }
633 1.1 rin
634 1.1 rin mue_csr_write(sc, MUE_DP_SEL,
635 1.1 rin (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
636 1.1 rin
637 1.1 rin for (i = 0; i < cnt; i++) {
638 1.1 rin mue_csr_write(sc, MUE_DP_ADDR, addr + i);
639 1.1 rin mue_csr_write(sc, MUE_DP_DATA, data[i]);
640 1.1 rin mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
641 1.1 rin if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
642 1.1 rin MUE_PRINTF(sc, "timed out\n");
643 1.1 rin return;
644 1.1 rin }
645 1.1 rin }
646 1.1 rin }
647 1.1 rin
648 1.1 rin static void
649 1.1 rin mue_init_ltm(struct mue_softc *sc)
650 1.1 rin {
651 1.1 rin uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
652 1.1 rin uint8_t temp[2];
653 1.1 rin size_t i;
654 1.1 rin
655 1.1 rin if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
656 1.1 rin if (mue_eeprom_present(sc) &&
657 1.1 rin (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
658 1.1 rin if (temp[0] != sizeof(idx)) {
659 1.1 rin DPRINTF(sc, "EEPROM: unexpected size\n");
660 1.1 rin goto done;
661 1.1 rin }
662 1.1 rin if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
663 1.1 rin sizeof(idx))) {
664 1.9 rin DPRINTF(sc, "EEPROM: failed to read\n");
665 1.1 rin goto done;
666 1.1 rin }
667 1.1 rin DPRINTF(sc, "success\n");
668 1.1 rin } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
669 1.1 rin if (temp[0] != sizeof(idx)) {
670 1.1 rin DPRINTF(sc, "OTP: unexpected size\n");
671 1.1 rin goto done;
672 1.1 rin }
673 1.1 rin if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
674 1.1 rin sizeof(idx))) {
675 1.9 rin DPRINTF(sc, "OTP: failed to read\n");
676 1.1 rin goto done;
677 1.1 rin }
678 1.1 rin DPRINTF(sc, "success\n");
679 1.26 rin } else
680 1.1 rin DPRINTF(sc, "nothing to do\n");
681 1.26 rin } else
682 1.1 rin DPRINTF(sc, "nothing to do\n");
683 1.1 rin done:
684 1.1 rin for (i = 0; i < __arraycount(idx); i++)
685 1.1 rin mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
686 1.1 rin }
687 1.1 rin
688 1.1 rin static int
689 1.1 rin mue_chip_init(struct mue_softc *sc)
690 1.1 rin {
691 1.1 rin uint32_t val;
692 1.1 rin
693 1.1 rin if ((sc->mue_flags & LAN7500) &&
694 1.1 rin MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
695 1.1 rin MUE_PRINTF(sc, "not ready\n");
696 1.1 rin return ETIMEDOUT;
697 1.1 rin }
698 1.1 rin
699 1.1 rin MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
700 1.1 rin if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
701 1.1 rin MUE_PRINTF(sc, "timed out\n");
702 1.1 rin return ETIMEDOUT;
703 1.1 rin }
704 1.1 rin
705 1.1 rin /* Respond to the IN token with a NAK. */
706 1.1 rin if (sc->mue_flags & LAN7500)
707 1.1 rin MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
708 1.1 rin else
709 1.1 rin MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
710 1.1 rin
711 1.1 rin if (sc->mue_flags & LAN7500) {
712 1.1 rin if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
713 1.3 rin val = MUE_7500_HS_RX_BUFSIZE /
714 1.1 rin MUE_HS_USB_PKT_SIZE;
715 1.1 rin else
716 1.3 rin val = MUE_7500_FS_RX_BUFSIZE /
717 1.1 rin MUE_FS_USB_PKT_SIZE;
718 1.1 rin mue_csr_write(sc, MUE_7500_BURST_CAP, val);
719 1.1 rin mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
720 1.1 rin MUE_7500_DEFAULT_BULKIN_DELAY);
721 1.1 rin
722 1.1 rin MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
723 1.1 rin
724 1.1 rin /* Set FIFO sizes. */
725 1.1 rin val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
726 1.1 rin mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
727 1.1 rin val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
728 1.1 rin mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
729 1.1 rin } else {
730 1.1 rin /* Init LTM. */
731 1.1 rin mue_init_ltm(sc);
732 1.1 rin
733 1.3 rin val = MUE_7800_RX_BUFSIZE;
734 1.1 rin switch (sc->mue_udev->ud_speed) {
735 1.1 rin case USB_SPEED_SUPER:
736 1.1 rin val /= MUE_SS_USB_PKT_SIZE;
737 1.1 rin break;
738 1.1 rin case USB_SPEED_HIGH:
739 1.1 rin val /= MUE_HS_USB_PKT_SIZE;
740 1.1 rin break;
741 1.1 rin default:
742 1.1 rin val /= MUE_FS_USB_PKT_SIZE;
743 1.1 rin break;
744 1.1 rin }
745 1.1 rin mue_csr_write(sc, MUE_7800_BURST_CAP, val);
746 1.1 rin mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
747 1.1 rin MUE_7800_DEFAULT_BULKIN_DELAY);
748 1.1 rin
749 1.1 rin MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
750 1.1 rin MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
751 1.1 rin
752 1.1 rin /*
753 1.1 rin * Set FCL's RX and TX FIFO sizes: according to data sheet this
754 1.1 rin * is already the default value. But we initialize it to the
755 1.1 rin * same value anyways, as that's what the Linux driver does.
756 1.1 rin */
757 1.1 rin val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
758 1.1 rin mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
759 1.1 rin val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
760 1.1 rin mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
761 1.1 rin }
762 1.1 rin
763 1.1 rin /* Enabling interrupts. */
764 1.1 rin mue_csr_write(sc, MUE_INT_STATUS, ~0);
765 1.1 rin
766 1.1 rin mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
767 1.1 rin MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
768 1.1 rin mue_csr_write(sc, MUE_FLOW, 0);
769 1.44 msaitoh
770 1.1 rin /* Reset PHY. */
771 1.1 rin MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
772 1.1 rin if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
773 1.1 rin MUE_PRINTF(sc, "PHY not ready\n");
774 1.1 rin return ETIMEDOUT;
775 1.1 rin }
776 1.1 rin
777 1.1 rin /* LAN7801 only has RGMII mode. */
778 1.1 rin if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
779 1.1 rin MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
780 1.1 rin
781 1.1 rin if ((sc->mue_flags & LAN7500) ||
782 1.1 rin (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
783 1.1 rin !mue_eeprom_present(sc))) {
784 1.1 rin /* Allow MAC to detect speed and duplex from PHY. */
785 1.1 rin MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
786 1.1 rin MUE_MAC_CR_AUTO_DUPLEX);
787 1.1 rin }
788 1.1 rin
789 1.1 rin MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
790 1.1 rin MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
791 1.1 rin MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
792 1.1 rin
793 1.1 rin MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
794 1.1 rin MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
795 1.1 rin
796 1.1 rin /* Set default GPIO/LED settings only if no EEPROM is detected. */
797 1.1 rin if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
798 1.1 rin MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
799 1.1 rin MUE_SETBIT(sc, MUE_LED_CFG,
800 1.1 rin MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
801 1.1 rin }
802 1.1 rin
803 1.1 rin /* XXX We assume two LEDs at least when EEPROM is missing. */
804 1.1 rin if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
805 1.1 rin !mue_eeprom_present(sc))
806 1.1 rin MUE_SETBIT(sc, MUE_HW_CFG,
807 1.1 rin MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
808 1.1 rin
809 1.1 rin return 0;
810 1.1 rin }
811 1.1 rin
812 1.1 rin static void
813 1.1 rin mue_set_macaddr(struct mue_softc *sc)
814 1.1 rin {
815 1.1 rin struct ifnet *ifp = GET_IFP(sc);
816 1.1 rin const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
817 1.1 rin uint32_t lo, hi;
818 1.1 rin
819 1.1 rin lo = MUE_ENADDR_LO(enaddr);
820 1.1 rin hi = MUE_ENADDR_HI(enaddr);
821 1.1 rin
822 1.1 rin mue_csr_write(sc, MUE_RX_ADDRL, lo);
823 1.1 rin mue_csr_write(sc, MUE_RX_ADDRH, hi);
824 1.1 rin }
825 1.1 rin
826 1.1 rin static int
827 1.1 rin mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
828 1.1 rin {
829 1.1 rin prop_data_t eaprop;
830 1.1 rin uint32_t low, high;
831 1.1 rin
832 1.1 rin if (!(sc->mue_flags & LAN7500)) {
833 1.1 rin low = mue_csr_read(sc, MUE_RX_ADDRL);
834 1.1 rin high = mue_csr_read(sc, MUE_RX_ADDRH);
835 1.1 rin sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
836 1.1 rin sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
837 1.1 rin sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
838 1.1 rin sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
839 1.1 rin sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
840 1.1 rin sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
841 1.1 rin if (ETHER_IS_VALID(sc->mue_enaddr))
842 1.1 rin return 0;
843 1.26 rin else
844 1.1 rin DPRINTF(sc, "registers: %s\n",
845 1.1 rin ether_sprintf(sc->mue_enaddr));
846 1.1 rin }
847 1.1 rin
848 1.1 rin if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
849 1.1 rin MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
850 1.1 rin if (ETHER_IS_VALID(sc->mue_enaddr))
851 1.1 rin return 0;
852 1.26 rin else
853 1.1 rin DPRINTF(sc, "EEPROM: %s\n",
854 1.1 rin ether_sprintf(sc->mue_enaddr));
855 1.1 rin }
856 1.1 rin
857 1.1 rin if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
858 1.1 rin ETHER_ADDR_LEN) == 0) {
859 1.1 rin if (ETHER_IS_VALID(sc->mue_enaddr))
860 1.1 rin return 0;
861 1.26 rin else
862 1.1 rin DPRINTF(sc, "OTP: %s\n",
863 1.1 rin ether_sprintf(sc->mue_enaddr));
864 1.1 rin }
865 1.1 rin
866 1.1 rin /*
867 1.1 rin * Other MD methods. This should be tried only if other methods fail.
868 1.1 rin * Otherwise, MAC address for internal device can be assinged to
869 1.1 rin * external devices on Raspberry Pi, for example.
870 1.1 rin */
871 1.1 rin eaprop = prop_dictionary_get(dict, "mac-address");
872 1.1 rin if (eaprop != NULL) {
873 1.1 rin KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
874 1.1 rin KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
875 1.1 rin memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
876 1.1 rin ETHER_ADDR_LEN);
877 1.1 rin if (ETHER_IS_VALID(sc->mue_enaddr))
878 1.1 rin return 0;
879 1.26 rin else
880 1.1 rin DPRINTF(sc, "prop_dictionary_get: %s\n",
881 1.1 rin ether_sprintf(sc->mue_enaddr));
882 1.1 rin }
883 1.1 rin
884 1.1 rin return 1;
885 1.1 rin }
886 1.1 rin
887 1.1 rin
888 1.1 rin /*
889 1.1 rin * Probe for a Microchip chip. */
890 1.1 rin static int
891 1.1 rin mue_match(device_t parent, cfdata_t match, void *aux)
892 1.1 rin {
893 1.1 rin struct usb_attach_arg *uaa = aux;
894 1.1 rin
895 1.1 rin return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
896 1.1 rin }
897 1.1 rin
898 1.1 rin static void
899 1.1 rin mue_attach(device_t parent, device_t self, void *aux)
900 1.1 rin {
901 1.1 rin struct mue_softc *sc = device_private(self);
902 1.1 rin prop_dictionary_t dict = device_properties(self);
903 1.1 rin struct usb_attach_arg *uaa = aux;
904 1.1 rin struct usbd_device *dev = uaa->uaa_device;
905 1.1 rin usb_interface_descriptor_t *id;
906 1.1 rin usb_endpoint_descriptor_t *ed;
907 1.1 rin char *devinfop;
908 1.1 rin struct mii_data *mii;
909 1.1 rin struct ifnet *ifp;
910 1.1 rin usbd_status err;
911 1.31 mlelstv const char *descr;
912 1.8 rin uint8_t i;
913 1.8 rin int s;
914 1.1 rin
915 1.1 rin aprint_naive("\n");
916 1.1 rin aprint_normal("\n");
917 1.1 rin
918 1.1 rin sc->mue_dev = self;
919 1.1 rin sc->mue_udev = dev;
920 1.1 rin
921 1.1 rin devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
922 1.1 rin aprint_normal_dev(self, "%s\n", devinfop);
923 1.1 rin usbd_devinfo_free(devinfop);
924 1.1 rin
925 1.1 rin #define MUE_CONFIG_NO 1
926 1.1 rin err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
927 1.1 rin if (err) {
928 1.1 rin aprint_error_dev(self, "failed to set configuration: %s\n",
929 1.1 rin usbd_errstr(err));
930 1.1 rin return;
931 1.1 rin }
932 1.1 rin
933 1.1 rin usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
934 1.1 rin
935 1.1 rin #define MUE_IFACE_IDX 0
936 1.1 rin err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
937 1.1 rin if (err) {
938 1.1 rin aprint_error_dev(self, "failed to get interface handle: %s\n",
939 1.1 rin usbd_errstr(err));
940 1.1 rin return;
941 1.1 rin }
942 1.1 rin
943 1.1 rin sc->mue_product = uaa->uaa_product;
944 1.1 rin sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
945 1.1 rin
946 1.31 mlelstv sc->mue_id_rev = mue_csr_read(sc, MUE_ID_REV);
947 1.31 mlelstv
948 1.1 rin /* Decide on what our bufsize will be. */
949 1.31 mlelstv if (sc->mue_flags & LAN7500) {
950 1.3 rin sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
951 1.3 rin MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
952 1.31 mlelstv sc->mue_rx_list_cnt = 1;
953 1.31 mlelstv sc->mue_tx_list_cnt = 1;
954 1.31 mlelstv } else {
955 1.3 rin sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
956 1.31 mlelstv sc->mue_rx_list_cnt = MUE_RX_LIST_CNT;
957 1.31 mlelstv sc->mue_tx_list_cnt = MUE_TX_LIST_CNT;
958 1.31 mlelstv }
959 1.3 rin sc->mue_txbufsz = MUE_TX_BUFSIZE;
960 1.1 rin
961 1.1 rin /* Find endpoints. */
962 1.1 rin id = usbd_get_interface_descriptor(sc->mue_iface);
963 1.1 rin for (i = 0; i < id->bNumEndpoints; i++) {
964 1.1 rin ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
965 1.1 rin if (ed == NULL) {
966 1.8 rin aprint_error_dev(self, "failed to get ep %hhd\n", i);
967 1.1 rin return;
968 1.1 rin }
969 1.1 rin if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
970 1.1 rin UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
971 1.1 rin sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
972 1.1 rin } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
973 1.1 rin UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
974 1.1 rin sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
975 1.1 rin } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
976 1.1 rin UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
977 1.1 rin sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
978 1.1 rin }
979 1.1 rin }
980 1.1 rin KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
981 1.1 rin KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
982 1.1 rin KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
983 1.1 rin
984 1.1 rin s = splnet();
985 1.1 rin
986 1.1 rin sc->mue_phyno = 1;
987 1.1 rin
988 1.1 rin if (mue_chip_init(sc)) {
989 1.9 rin aprint_error_dev(self, "failed to initialize chip\n");
990 1.1 rin splx(s);
991 1.1 rin return;
992 1.1 rin }
993 1.1 rin
994 1.1 rin /* A Microchip chip was detected. Inform the world. */
995 1.31 mlelstv descr = (sc->mue_flags & LAN7500) ? "LAN7500" : "LAN7800";
996 1.31 mlelstv aprint_normal_dev(self, "%s id 0x%x rev 0x%x\n", descr,
997 1.31 mlelstv (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_ID),
998 1.31 mlelstv (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_REV));
999 1.1 rin
1000 1.1 rin if (mue_get_macaddr(sc, dict)) {
1001 1.21 rin aprint_error_dev(self, "failed to read MAC address\n");
1002 1.21 rin splx(s);
1003 1.21 rin return;
1004 1.1 rin }
1005 1.1 rin
1006 1.1 rin aprint_normal_dev(self, "Ethernet address %s\n",
1007 1.1 rin ether_sprintf(sc->mue_enaddr));
1008 1.1 rin
1009 1.1 rin /* Initialize interface info.*/
1010 1.1 rin ifp = GET_IFP(sc);
1011 1.1 rin ifp->if_softc = sc;
1012 1.1 rin strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
1013 1.1 rin ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1014 1.1 rin ifp->if_init = mue_init;
1015 1.1 rin ifp->if_ioctl = mue_ioctl;
1016 1.1 rin ifp->if_start = mue_start;
1017 1.1 rin ifp->if_stop = mue_stop;
1018 1.1 rin ifp->if_watchdog = mue_watchdog;
1019 1.1 rin
1020 1.1 rin IFQ_SET_READY(&ifp->if_snd);
1021 1.1 rin
1022 1.20 rin ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
1023 1.44 msaitoh IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1024 1.20 rin IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1025 1.20 rin IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1026 1.20 rin IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
1027 1.20 rin IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
1028 1.3 rin
1029 1.1 rin sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1030 1.22 rin #if 0 /* XXX not yet */
1031 1.22 rin sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
1032 1.22 rin #endif
1033 1.1 rin
1034 1.1 rin /* Initialize MII/media info. */
1035 1.1 rin mii = GET_MII(sc);
1036 1.1 rin mii->mii_ifp = ifp;
1037 1.1 rin mii->mii_readreg = mue_miibus_readreg;
1038 1.1 rin mii->mii_writereg = mue_miibus_writereg;
1039 1.1 rin mii->mii_statchg = mue_miibus_statchg;
1040 1.1 rin mii->mii_flags = MIIF_AUTOTSLEEP;
1041 1.1 rin
1042 1.1 rin sc->mue_ec.ec_mii = mii;
1043 1.1 rin ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1044 1.1 rin mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1045 1.1 rin
1046 1.1 rin if (LIST_FIRST(&mii->mii_phys) == NULL) {
1047 1.1 rin ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1048 1.1 rin ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1049 1.1 rin } else
1050 1.1 rin ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1051 1.1 rin
1052 1.1 rin /* Attach the interface. */
1053 1.1 rin if_attach(ifp);
1054 1.1 rin ether_ifattach(ifp, sc->mue_enaddr);
1055 1.1 rin
1056 1.1 rin rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1057 1.1 rin RND_TYPE_NET, RND_FLAG_DEFAULT);
1058 1.1 rin
1059 1.1 rin callout_init(&sc->mue_stat_ch, 0);
1060 1.1 rin
1061 1.1 rin splx(s);
1062 1.1 rin
1063 1.21 rin mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
1064 1.21 rin
1065 1.1 rin usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1066 1.1 rin }
1067 1.1 rin
1068 1.1 rin static int
1069 1.1 rin mue_detach(device_t self, int flags)
1070 1.1 rin {
1071 1.1 rin struct mue_softc *sc = device_private(self);
1072 1.1 rin struct ifnet *ifp = GET_IFP(sc);
1073 1.1 rin size_t i;
1074 1.1 rin int s;
1075 1.1 rin
1076 1.1 rin sc->mue_dying = true;
1077 1.1 rin
1078 1.1 rin callout_halt(&sc->mue_stat_ch, NULL);
1079 1.1 rin
1080 1.1 rin for (i = 0; i < __arraycount(sc->mue_ep); i++)
1081 1.1 rin if (sc->mue_ep[i] != NULL)
1082 1.1 rin usbd_abort_pipe(sc->mue_ep[i]);
1083 1.1 rin
1084 1.1 rin /*
1085 1.7 rin * Remove any pending tasks. They cannot be executing because they run
1086 1.1 rin * in the same thread as detach.
1087 1.1 rin */
1088 1.1 rin usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1089 1.1 rin NULL);
1090 1.1 rin
1091 1.1 rin s = splusb();
1092 1.1 rin
1093 1.1 rin if (ifp->if_flags & IFF_RUNNING)
1094 1.1 rin mue_stop(ifp, 1);
1095 1.1 rin
1096 1.30 rin callout_destroy(&sc->mue_stat_ch);
1097 1.1 rin rnd_detach_source(&sc->mue_rnd_source);
1098 1.1 rin mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1099 1.1 rin ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1100 1.1 rin if (ifp->if_softc != NULL) {
1101 1.1 rin ether_ifdetach(ifp);
1102 1.1 rin if_detach(ifp);
1103 1.1 rin }
1104 1.1 rin
1105 1.1 rin if (--sc->mue_refcnt >= 0) {
1106 1.1 rin /* Wait for processes to go away. */
1107 1.1 rin usb_detach_waitold(sc->mue_dev);
1108 1.1 rin }
1109 1.1 rin splx(s);
1110 1.1 rin
1111 1.1 rin usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1112 1.44 msaitoh
1113 1.1 rin mutex_destroy(&sc->mue_mii_lock);
1114 1.1 rin
1115 1.1 rin return 0;
1116 1.1 rin }
1117 1.1 rin
1118 1.1 rin static int
1119 1.1 rin mue_activate(device_t self, enum devact act)
1120 1.1 rin {
1121 1.1 rin struct mue_softc *sc = device_private(self);
1122 1.1 rin struct ifnet *ifp = GET_IFP(sc);
1123 1.1 rin
1124 1.1 rin switch (act) {
1125 1.1 rin case DVACT_DEACTIVATE:
1126 1.1 rin if_deactivate(ifp);
1127 1.1 rin sc->mue_dying = true;
1128 1.1 rin return 0;
1129 1.1 rin default:
1130 1.1 rin return EOPNOTSUPP;
1131 1.1 rin }
1132 1.1 rin return 0;
1133 1.1 rin }
1134 1.1 rin
1135 1.1 rin static int
1136 1.1 rin mue_rx_list_init(struct mue_softc *sc)
1137 1.1 rin {
1138 1.1 rin struct mue_cdata *cd;
1139 1.1 rin struct mue_chain *c;
1140 1.1 rin size_t i;
1141 1.1 rin int err;
1142 1.1 rin
1143 1.1 rin cd = &sc->mue_cdata;
1144 1.31 mlelstv for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1145 1.1 rin c = &cd->mue_rx_chain[i];
1146 1.1 rin c->mue_sc = sc;
1147 1.1 rin if (c->mue_xfer == NULL) {
1148 1.1 rin err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1149 1.3 rin sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1150 1.1 rin if (err)
1151 1.1 rin return err;
1152 1.1 rin c->mue_buf = usbd_get_buffer(c->mue_xfer);
1153 1.1 rin }
1154 1.1 rin }
1155 1.1 rin
1156 1.1 rin return 0;
1157 1.1 rin }
1158 1.1 rin
1159 1.1 rin static int
1160 1.1 rin mue_tx_list_init(struct mue_softc *sc)
1161 1.1 rin {
1162 1.1 rin struct mue_cdata *cd;
1163 1.1 rin struct mue_chain *c;
1164 1.1 rin size_t i;
1165 1.1 rin int err;
1166 1.1 rin
1167 1.1 rin cd = &sc->mue_cdata;
1168 1.31 mlelstv for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1169 1.1 rin c = &cd->mue_tx_chain[i];
1170 1.1 rin c->mue_sc = sc;
1171 1.1 rin if (c->mue_xfer == NULL) {
1172 1.1 rin err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1173 1.3 rin sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1174 1.1 rin &c->mue_xfer);
1175 1.1 rin if (err)
1176 1.1 rin return err;
1177 1.1 rin c->mue_buf = usbd_get_buffer(c->mue_xfer);
1178 1.1 rin }
1179 1.1 rin }
1180 1.1 rin
1181 1.27 mlelstv cd->mue_tx_prod = 0;
1182 1.27 mlelstv cd->mue_tx_cnt = 0;
1183 1.27 mlelstv
1184 1.1 rin return 0;
1185 1.1 rin }
1186 1.1 rin
1187 1.1 rin static int
1188 1.1 rin mue_open_pipes(struct mue_softc *sc)
1189 1.1 rin {
1190 1.1 rin usbd_status err;
1191 1.1 rin
1192 1.1 rin /* Open RX and TX pipes. */
1193 1.1 rin err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1194 1.1 rin USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1195 1.1 rin if (err) {
1196 1.1 rin MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1197 1.1 rin return EIO;
1198 1.1 rin }
1199 1.1 rin err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1200 1.1 rin USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1201 1.1 rin if (err) {
1202 1.1 rin MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1203 1.1 rin return EIO;
1204 1.1 rin }
1205 1.1 rin return 0;
1206 1.1 rin }
1207 1.1 rin
1208 1.1 rin static void
1209 1.18 rin mue_startup_rx_pipes(struct mue_softc *sc)
1210 1.1 rin {
1211 1.1 rin struct mue_chain *c;
1212 1.1 rin size_t i;
1213 1.1 rin
1214 1.1 rin /* Start up the receive pipe. */
1215 1.31 mlelstv for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1216 1.1 rin c = &sc->mue_cdata.mue_rx_chain[i];
1217 1.3 rin usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1218 1.1 rin USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1219 1.1 rin usbd_transfer(c->mue_xfer);
1220 1.1 rin }
1221 1.1 rin }
1222 1.1 rin
1223 1.1 rin static int
1224 1.1 rin mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1225 1.1 rin {
1226 1.1 rin struct ifnet *ifp = GET_IFP(sc);
1227 1.1 rin struct mue_chain *c;
1228 1.1 rin usbd_status err;
1229 1.1 rin struct mue_txbuf_hdr hdr;
1230 1.12 rin uint32_t tx_cmd_a, tx_cmd_b;
1231 1.37 rin int csum, len, rv;
1232 1.20 rin bool tso, ipe, tpe;
1233 1.12 rin
1234 1.20 rin csum = m->m_pkthdr.csum_flags;
1235 1.20 rin tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
1236 1.20 rin ipe = csum & M_CSUM_IPv4;
1237 1.20 rin tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
1238 1.20 rin M_CSUM_TCPv6 | M_CSUM_UDPv6);
1239 1.12 rin
1240 1.12 rin len = m->m_pkthdr.len;
1241 1.41 rin if (__predict_false((!tso && len > (int)MUE_FRAME_LEN(ifp->if_mtu)) ||
1242 1.22 rin ( tso && len > MUE_TSO_FRAME_LEN))) {
1243 1.12 rin MUE_PRINTF(sc, "packet length %d\n too long", len);
1244 1.12 rin return EINVAL;
1245 1.12 rin }
1246 1.1 rin
1247 1.1 rin c = &sc->mue_cdata.mue_tx_chain[idx];
1248 1.1 rin
1249 1.12 rin KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
1250 1.12 rin tx_cmd_a = len | MUE_TX_CMD_A_FCS;
1251 1.3 rin
1252 1.12 rin if (tso) {
1253 1.12 rin tx_cmd_a |= MUE_TX_CMD_A_LSO;
1254 1.3 rin if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1255 1.12 rin tx_cmd_b = m->m_pkthdr.segsz;
1256 1.3 rin else
1257 1.12 rin tx_cmd_b = MUE_TX_MSS_MIN;
1258 1.12 rin tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
1259 1.12 rin KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
1260 1.37 rin rv = mue_prepare_tso(sc, m);
1261 1.37 rin if (__predict_false(rv))
1262 1.37 rin return rv;
1263 1.20 rin } else {
1264 1.20 rin if (ipe)
1265 1.20 rin tx_cmd_a |= MUE_TX_CMD_A_IPE;
1266 1.20 rin if (tpe)
1267 1.20 rin tx_cmd_a |= MUE_TX_CMD_A_TPE;
1268 1.12 rin tx_cmd_b = 0;
1269 1.20 rin }
1270 1.12 rin
1271 1.12 rin hdr.tx_cmd_a = htole32(tx_cmd_a);
1272 1.12 rin hdr.tx_cmd_b = htole32(tx_cmd_b);
1273 1.3 rin
1274 1.44 msaitoh memcpy(c->mue_buf, &hdr, sizeof(hdr));
1275 1.12 rin m_copydata(m, 0, len, c->mue_buf + sizeof(hdr));
1276 1.1 rin
1277 1.32 rin if (__predict_false(c->mue_xfer == NULL))
1278 1.32 rin return EIO; /* XXX plugged out or down */
1279 1.32 rin
1280 1.12 rin usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr),
1281 1.1 rin USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1282 1.1 rin
1283 1.1 rin /* Transmit */
1284 1.1 rin err = usbd_transfer(c->mue_xfer);
1285 1.1 rin if (__predict_false(err != USBD_IN_PROGRESS)) {
1286 1.12 rin MUE_PRINTF(sc, "%s\n", usbd_errstr(err));
1287 1.1 rin mue_stop(ifp, 0);
1288 1.1 rin return EIO;
1289 1.1 rin }
1290 1.1 rin
1291 1.1 rin return 0;
1292 1.1 rin }
1293 1.1 rin
1294 1.37 rin /*
1295 1.37 rin * L3 length field should be cleared.
1296 1.37 rin */
1297 1.37 rin static int
1298 1.37 rin mue_prepare_tso(struct mue_softc *sc, struct mbuf *m)
1299 1.3 rin {
1300 1.3 rin struct ether_header *eh;
1301 1.3 rin struct ip *ip;
1302 1.3 rin struct ip6_hdr *ip6;
1303 1.37 rin uint16_t type, len = 0;
1304 1.18 rin int off;
1305 1.3 rin
1306 1.41 rin if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
1307 1.37 rin eh = mtod(m, struct ether_header *);
1308 1.37 rin type = eh->ether_type;
1309 1.37 rin } else
1310 1.37 rin m_copydata(m, offsetof(struct ether_header, ether_type),
1311 1.37 rin sizeof(type), &type);
1312 1.37 rin switch (type = htons(type)) {
1313 1.3 rin case ETHERTYPE_IP:
1314 1.3 rin case ETHERTYPE_IPV6:
1315 1.18 rin off = ETHER_HDR_LEN;
1316 1.3 rin break;
1317 1.3 rin case ETHERTYPE_VLAN:
1318 1.18 rin off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1319 1.3 rin break;
1320 1.3 rin default:
1321 1.37 rin if (usbd_ratecheck(&sc->mue_tx_notice))
1322 1.37 rin MUE_PRINTF(sc, "dropping invalid frame "
1323 1.44 msaitoh "type 0x%04hx csum_flags 0x%08x\n",
1324 1.37 rin type, m->m_pkthdr.csum_flags);
1325 1.37 rin return EINVAL;
1326 1.3 rin }
1327 1.3 rin
1328 1.13 rin if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1329 1.41 rin if (__predict_true(m->m_len >= off + (int)sizeof(*ip))) {
1330 1.37 rin ip = (void *)(mtod(m, char *) + off);
1331 1.37 rin ip->ip_len = 0;
1332 1.37 rin } else
1333 1.37 rin m_copyback(m, off + offsetof(struct ip, ip_len),
1334 1.37 rin sizeof(len), &len);
1335 1.3 rin } else {
1336 1.41 rin if (__predict_true(m->m_len >= off + (int)sizeof(*ip6))) {
1337 1.37 rin ip6 = (void *)(mtod(m, char *) + off);
1338 1.37 rin ip6->ip6_plen = 0;
1339 1.37 rin } else
1340 1.37 rin m_copyback(m, off + offsetof(struct ip6_hdr, ip6_plen),
1341 1.37 rin sizeof(len), &len);
1342 1.3 rin }
1343 1.37 rin return 0;
1344 1.3 rin }
1345 1.3 rin
1346 1.3 rin static void
1347 1.1 rin mue_setmulti(struct mue_softc *sc)
1348 1.1 rin {
1349 1.1 rin struct ifnet *ifp = GET_IFP(sc);
1350 1.1 rin const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1351 1.1 rin struct ether_multi *enm;
1352 1.1 rin struct ether_multistep step;
1353 1.1 rin uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1354 1.1 rin uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1355 1.1 rin uint32_t reg, rxfilt, h, hireg, loreg;
1356 1.8 rin size_t i;
1357 1.1 rin
1358 1.1 rin if (sc->mue_dying)
1359 1.1 rin return;
1360 1.1 rin
1361 1.1 rin /* Clear perfect filter and hash tables. */
1362 1.1 rin memset(pfiltbl, 0, sizeof(pfiltbl));
1363 1.1 rin memset(hashtbl, 0, sizeof(hashtbl));
1364 1.1 rin
1365 1.1 rin reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1366 1.1 rin rxfilt = mue_csr_read(sc, reg);
1367 1.1 rin rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1368 1.1 rin MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1369 1.1 rin
1370 1.1 rin /* Always accept broadcast frames. */
1371 1.1 rin rxfilt |= MUE_RFE_CTL_BROADCAST;
1372 1.1 rin
1373 1.25 rin if (ifp->if_flags & IFF_PROMISC) {
1374 1.25 rin rxfilt |= MUE_RFE_CTL_UNICAST;
1375 1.25 rin allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1376 1.25 rin ifp->if_flags |= IFF_ALLMULTI;
1377 1.26 rin if (ifp->if_flags & IFF_PROMISC)
1378 1.1 rin DPRINTF(sc, "promisc\n");
1379 1.26 rin else
1380 1.1 rin DPRINTF(sc, "allmulti\n");
1381 1.1 rin } else {
1382 1.1 rin /* Now program new ones. */
1383 1.1 rin pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1384 1.1 rin pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1385 1.1 rin i = 1;
1386 1.1 rin ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1387 1.1 rin while (enm != NULL) {
1388 1.1 rin if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1389 1.1 rin ETHER_ADDR_LEN)) {
1390 1.1 rin memset(pfiltbl, 0, sizeof(pfiltbl));
1391 1.1 rin memset(hashtbl, 0, sizeof(hashtbl));
1392 1.1 rin rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1393 1.1 rin goto allmulti;
1394 1.1 rin }
1395 1.1 rin if (i < MUE_NUM_ADDR_FILTX) {
1396 1.1 rin /* Use perfect address table if possible. */
1397 1.1 rin pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1398 1.1 rin MUE_ADDR_FILTX_VALID;
1399 1.1 rin pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1400 1.1 rin } else {
1401 1.1 rin /* Otherwise, use hash table. */
1402 1.1 rin rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1403 1.1 rin h = (ether_crc32_be(enm->enm_addrlo,
1404 1.1 rin ETHER_ADDR_LEN) >> 23) & 0x1ff;
1405 1.44 msaitoh hashtbl[h / 32] |= 1 << (h % 32);
1406 1.1 rin }
1407 1.1 rin i++;
1408 1.1 rin ETHER_NEXT_MULTI(step, enm);
1409 1.1 rin }
1410 1.1 rin rxfilt |= MUE_RFE_CTL_PERFECT;
1411 1.25 rin ifp->if_flags &= ~IFF_ALLMULTI;
1412 1.26 rin if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH)
1413 1.1 rin DPRINTF(sc, "perfect filter and hash tables\n");
1414 1.26 rin else
1415 1.1 rin DPRINTF(sc, "perfect filter\n");
1416 1.1 rin }
1417 1.1 rin
1418 1.1 rin for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1419 1.1 rin hireg = (sc->mue_flags & LAN7500) ?
1420 1.1 rin MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1421 1.1 rin loreg = hireg + 4;
1422 1.1 rin mue_csr_write(sc, hireg, 0);
1423 1.1 rin mue_csr_write(sc, loreg, pfiltbl[i][1]);
1424 1.1 rin mue_csr_write(sc, hireg, pfiltbl[i][0]);
1425 1.1 rin }
1426 1.1 rin
1427 1.1 rin mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1428 1.1 rin MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1429 1.1 rin
1430 1.1 rin mue_csr_write(sc, reg, rxfilt);
1431 1.1 rin }
1432 1.1 rin
1433 1.1 rin static void
1434 1.1 rin mue_sethwcsum(struct mue_softc *sc)
1435 1.1 rin {
1436 1.1 rin struct ifnet *ifp = GET_IFP(sc);
1437 1.1 rin uint32_t reg, val;
1438 1.1 rin
1439 1.1 rin reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1440 1.1 rin val = mue_csr_read(sc, reg);
1441 1.1 rin
1442 1.29 rin if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) {
1443 1.29 rin DPRINTF(sc, "RX IPv4 hwcsum enabled\n");
1444 1.29 rin val |= MUE_RFE_CTL_IP_COE;
1445 1.1 rin } else {
1446 1.29 rin DPRINTF(sc, "RX IPv4 hwcsum disabled\n");
1447 1.29 rin val &= ~MUE_RFE_CTL_IP_COE;
1448 1.29 rin }
1449 1.29 rin
1450 1.29 rin if (ifp->if_capenable &
1451 1.29 rin (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
1452 1.29 rin IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) {
1453 1.29 rin DPRINTF(sc, "RX L4 hwcsum enabled\n");
1454 1.29 rin val |= MUE_RFE_CTL_TCPUDP_COE;
1455 1.29 rin } else {
1456 1.29 rin DPRINTF(sc, "RX L4 hwcsum disabled\n");
1457 1.29 rin val &= ~MUE_RFE_CTL_TCPUDP_COE;
1458 1.29 rin }
1459 1.1 rin
1460 1.1 rin val &= ~MUE_RFE_CTL_VLAN_FILTER;
1461 1.1 rin
1462 1.1 rin mue_csr_write(sc, reg, val);
1463 1.1 rin }
1464 1.1 rin
1465 1.22 rin static void
1466 1.22 rin mue_setmtu(struct mue_softc *sc)
1467 1.22 rin {
1468 1.22 rin struct ifnet *ifp = GET_IFP(sc);
1469 1.22 rin uint32_t val;
1470 1.22 rin
1471 1.22 rin /* Set the maximum frame size. */
1472 1.22 rin MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1473 1.22 rin val = mue_csr_read(sc, MUE_MAC_RX);
1474 1.22 rin val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1475 1.22 rin val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1476 1.22 rin mue_csr_write(sc, MUE_MAC_RX, val);
1477 1.22 rin MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1478 1.22 rin }
1479 1.1 rin
1480 1.1 rin static void
1481 1.1 rin mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1482 1.1 rin {
1483 1.1 rin struct mue_chain *c = (struct mue_chain *)priv;
1484 1.1 rin struct mue_softc *sc = c->mue_sc;
1485 1.1 rin struct ifnet *ifp = GET_IFP(sc);
1486 1.1 rin struct mbuf *m;
1487 1.1 rin struct mue_rxbuf_hdr *hdrp;
1488 1.15 rin uint32_t rx_cmd_a, totlen;
1489 1.1 rin uint16_t pktlen;
1490 1.1 rin int s;
1491 1.20 rin int csum;
1492 1.1 rin char *buf = c->mue_buf;
1493 1.20 rin bool v6;
1494 1.1 rin
1495 1.1 rin if (__predict_false(sc->mue_dying)) {
1496 1.1 rin DPRINTF(sc, "dying\n");
1497 1.1 rin return;
1498 1.1 rin }
1499 1.1 rin
1500 1.1 rin if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1501 1.1 rin DPRINTF(sc, "%s\n", usbd_errstr(status));
1502 1.32 rin if (status == USBD_INVAL)
1503 1.32 rin return; /* XXX plugged out or down */
1504 1.1 rin if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1505 1.1 rin return;
1506 1.1 rin if (usbd_ratecheck(&sc->mue_rx_notice))
1507 1.1 rin MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1508 1.1 rin if (status == USBD_STALLED)
1509 1.1 rin usbd_clear_endpoint_stall_async(
1510 1.1 rin sc->mue_ep[MUE_ENDPT_RX]);
1511 1.1 rin goto done;
1512 1.1 rin }
1513 1.1 rin
1514 1.15 rin usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL);
1515 1.1 rin
1516 1.16 rin KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u",
1517 1.15 rin totlen, sc->mue_rxbufsz);
1518 1.1 rin
1519 1.1 rin do {
1520 1.15 rin if (__predict_false(totlen < sizeof(*hdrp))) {
1521 1.15 rin MUE_PRINTF(sc, "packet length %u too short\n", totlen);
1522 1.1 rin ifp->if_ierrors++;
1523 1.1 rin goto done;
1524 1.1 rin }
1525 1.1 rin
1526 1.1 rin hdrp = (struct mue_rxbuf_hdr *)buf;
1527 1.1 rin rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1528 1.1 rin
1529 1.20 rin if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1530 1.20 rin /*
1531 1.20 rin * We cannot use MUE_RX_CMD_A_RED bit here;
1532 1.20 rin * it is turned on in the cases of L3/L4
1533 1.20 rin * checksum errors which we handle below.
1534 1.20 rin */
1535 1.9 rin MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1536 1.1 rin ifp->if_ierrors++;
1537 1.1 rin goto done;
1538 1.1 rin }
1539 1.1 rin
1540 1.1 rin pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1541 1.1 rin if (sc->mue_flags & LAN7500)
1542 1.1 rin pktlen -= 2;
1543 1.1 rin
1544 1.10 rin if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1545 1.22 rin pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1546 1.15 rin pktlen + sizeof(*hdrp) > totlen)) {
1547 1.9 rin MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1548 1.1 rin ifp->if_ierrors++;
1549 1.1 rin goto done;
1550 1.1 rin }
1551 1.1 rin
1552 1.1 rin m = mue_newbuf();
1553 1.1 rin if (__predict_false(m == NULL)) {
1554 1.9 rin MUE_PRINTF(sc, "failed to allocate mbuf\n");
1555 1.1 rin ifp->if_ierrors++;
1556 1.1 rin goto done;
1557 1.1 rin }
1558 1.1 rin
1559 1.1 rin m_set_rcvif(m, ifp);
1560 1.1 rin m->m_pkthdr.len = m->m_len = pktlen;
1561 1.1 rin m->m_flags |= M_HASFCS;
1562 1.20 rin
1563 1.20 rin if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1564 1.20 rin csum = 0;
1565 1.20 rin } else {
1566 1.20 rin v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1567 1.20 rin switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1568 1.20 rin case MUE_RX_CMD_A_PID_TCP:
1569 1.20 rin csum = v6 ?
1570 1.20 rin M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1571 1.20 rin break;
1572 1.20 rin case MUE_RX_CMD_A_PID_UDP:
1573 1.20 rin csum = v6 ?
1574 1.20 rin M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1575 1.20 rin break;
1576 1.20 rin case MUE_RX_CMD_A_PID_IP:
1577 1.20 rin csum = v6 ? 0 : M_CSUM_IPv4;
1578 1.20 rin break;
1579 1.20 rin default:
1580 1.20 rin csum = 0;
1581 1.20 rin break;
1582 1.20 rin }
1583 1.20 rin csum &= ifp->if_csum_flags_rx;
1584 1.20 rin if (__predict_false((csum & M_CSUM_IPv4) &&
1585 1.20 rin (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1586 1.20 rin csum |= M_CSUM_IPv4_BAD;
1587 1.20 rin if (__predict_false((csum & ~M_CSUM_IPv4) &&
1588 1.20 rin (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1589 1.20 rin csum |= M_CSUM_TCP_UDP_BAD;
1590 1.20 rin }
1591 1.20 rin m->m_pkthdr.csum_flags = csum;
1592 1.1 rin memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1593 1.1 rin
1594 1.1 rin /* Attention: sizeof(hdr) = 10 */
1595 1.1 rin pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1596 1.15 rin if (pktlen > totlen)
1597 1.15 rin pktlen = totlen;
1598 1.15 rin totlen -= pktlen;
1599 1.1 rin buf += pktlen;
1600 1.1 rin
1601 1.1 rin s = splnet();
1602 1.1 rin if_percpuq_enqueue(ifp->if_percpuq, m);
1603 1.1 rin splx(s);
1604 1.15 rin } while (totlen > 0);
1605 1.1 rin
1606 1.1 rin done:
1607 1.1 rin /* Setup new transfer. */
1608 1.3 rin usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1609 1.1 rin USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1610 1.1 rin usbd_transfer(xfer);
1611 1.1 rin }
1612 1.1 rin
1613 1.1 rin static void
1614 1.1 rin mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1615 1.1 rin {
1616 1.1 rin struct mue_chain *c = priv;
1617 1.1 rin struct mue_softc *sc = c->mue_sc;
1618 1.27 mlelstv struct mue_cdata *cd = &sc->mue_cdata;
1619 1.1 rin struct ifnet *ifp = GET_IFP(sc);
1620 1.1 rin int s;
1621 1.1 rin
1622 1.1 rin if (__predict_false(sc->mue_dying))
1623 1.1 rin return;
1624 1.1 rin
1625 1.1 rin s = splnet();
1626 1.27 mlelstv KASSERT(cd->mue_tx_cnt > 0);
1627 1.27 mlelstv cd->mue_tx_cnt--;
1628 1.1 rin if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1629 1.1 rin if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1630 1.1 rin splx(s);
1631 1.1 rin return;
1632 1.1 rin }
1633 1.1 rin ifp->if_oerrors++;
1634 1.38 rin if (usbd_ratecheck(&sc->mue_tx_notice))
1635 1.38 rin MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1636 1.1 rin if (status == USBD_STALLED)
1637 1.1 rin usbd_clear_endpoint_stall_async(
1638 1.1 rin sc->mue_ep[MUE_ENDPT_TX]);
1639 1.1 rin splx(s);
1640 1.1 rin return;
1641 1.1 rin }
1642 1.1 rin
1643 1.1 rin ifp->if_timer = 0;
1644 1.1 rin ifp->if_flags &= ~IFF_OACTIVE;
1645 1.1 rin
1646 1.1 rin if (!IFQ_IS_EMPTY(&ifp->if_snd))
1647 1.1 rin mue_start(ifp);
1648 1.1 rin
1649 1.1 rin ifp->if_opackets++;
1650 1.1 rin splx(s);
1651 1.1 rin }
1652 1.1 rin
1653 1.1 rin static int
1654 1.1 rin mue_init(struct ifnet *ifp)
1655 1.1 rin {
1656 1.44 msaitoh struct mue_softc *sc = ifp->if_softc;
1657 1.1 rin int s;
1658 1.1 rin
1659 1.1 rin if (sc->mue_dying) {
1660 1.1 rin DPRINTF(sc, "dying\n");
1661 1.1 rin return EIO;
1662 1.1 rin }
1663 1.1 rin
1664 1.1 rin s = splnet();
1665 1.1 rin
1666 1.1 rin /* Cancel pending I/O and free all TX/RX buffers. */
1667 1.1 rin if (ifp->if_flags & IFF_RUNNING)
1668 1.1 rin mue_stop(ifp, 1);
1669 1.1 rin
1670 1.1 rin mue_reset(sc);
1671 1.1 rin
1672 1.1 rin /* Set MAC address. */
1673 1.1 rin mue_set_macaddr(sc);
1674 1.1 rin
1675 1.1 rin /* Load the multicast filter. */
1676 1.1 rin mue_setmulti(sc);
1677 1.1 rin
1678 1.1 rin /* TCP/UDP checksum offload engines. */
1679 1.1 rin mue_sethwcsum(sc);
1680 1.1 rin
1681 1.22 rin /* Set MTU. */
1682 1.22 rin mue_setmtu(sc);
1683 1.22 rin
1684 1.1 rin if (mue_open_pipes(sc)) {
1685 1.1 rin splx(s);
1686 1.1 rin return EIO;
1687 1.1 rin }
1688 1.1 rin
1689 1.1 rin /* Init RX ring. */
1690 1.1 rin if (mue_rx_list_init(sc)) {
1691 1.9 rin MUE_PRINTF(sc, "failed to init rx list\n");
1692 1.1 rin splx(s);
1693 1.1 rin return ENOBUFS;
1694 1.1 rin }
1695 1.1 rin
1696 1.1 rin /* Init TX ring. */
1697 1.1 rin if (mue_tx_list_init(sc)) {
1698 1.9 rin MUE_PRINTF(sc, "failed to init tx list\n");
1699 1.1 rin splx(s);
1700 1.1 rin return ENOBUFS;
1701 1.1 rin }
1702 1.1 rin
1703 1.18 rin mue_startup_rx_pipes(sc);
1704 1.1 rin
1705 1.1 rin ifp->if_flags |= IFF_RUNNING;
1706 1.1 rin ifp->if_flags &= ~IFF_OACTIVE;
1707 1.1 rin
1708 1.1 rin splx(s);
1709 1.1 rin
1710 1.1 rin callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1711 1.1 rin
1712 1.1 rin return 0;
1713 1.1 rin }
1714 1.1 rin
1715 1.1 rin static int
1716 1.1 rin mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1717 1.1 rin {
1718 1.1 rin struct mue_softc *sc = ifp->if_softc;
1719 1.1 rin int s, error = 0;
1720 1.1 rin
1721 1.1 rin s = splnet();
1722 1.1 rin
1723 1.22 rin switch (cmd) {
1724 1.1 rin case SIOCSIFFLAGS:
1725 1.1 rin if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1726 1.1 rin break;
1727 1.1 rin
1728 1.1 rin switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1729 1.1 rin case IFF_RUNNING:
1730 1.1 rin mue_stop(ifp, 1);
1731 1.1 rin break;
1732 1.1 rin case IFF_UP:
1733 1.1 rin mue_init(ifp);
1734 1.1 rin break;
1735 1.1 rin case IFF_UP | IFF_RUNNING:
1736 1.1 rin if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1737 1.1 rin mue_setmulti(sc);
1738 1.1 rin else
1739 1.1 rin mue_init(ifp);
1740 1.1 rin break;
1741 1.1 rin }
1742 1.1 rin sc->mue_if_flags = ifp->if_flags;
1743 1.1 rin break;
1744 1.1 rin default:
1745 1.1 rin if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1746 1.1 rin break;
1747 1.1 rin error = 0;
1748 1.22 rin switch (cmd) {
1749 1.22 rin case SIOCADDMULTI:
1750 1.22 rin case SIOCDELMULTI:
1751 1.22 rin mue_setmulti(sc);
1752 1.22 rin break;
1753 1.22 rin case SIOCSIFCAP:
1754 1.20 rin mue_sethwcsum(sc);
1755 1.22 rin break;
1756 1.22 rin case SIOCSIFMTU:
1757 1.22 rin mue_setmtu(sc);
1758 1.22 rin break;
1759 1.22 rin default:
1760 1.22 rin break;
1761 1.22 rin }
1762 1.1 rin break;
1763 1.1 rin }
1764 1.1 rin splx(s);
1765 1.1 rin
1766 1.1 rin return error;
1767 1.1 rin }
1768 1.1 rin
1769 1.1 rin static void
1770 1.1 rin mue_watchdog(struct ifnet *ifp)
1771 1.1 rin {
1772 1.1 rin struct mue_softc *sc = ifp->if_softc;
1773 1.1 rin struct mue_chain *c;
1774 1.1 rin usbd_status stat;
1775 1.1 rin int s;
1776 1.1 rin
1777 1.1 rin ifp->if_oerrors++;
1778 1.1 rin MUE_PRINTF(sc, "timed out\n");
1779 1.1 rin
1780 1.1 rin s = splusb();
1781 1.1 rin c = &sc->mue_cdata.mue_tx_chain[0];
1782 1.1 rin usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1783 1.1 rin mue_txeof(c->mue_xfer, c, stat);
1784 1.1 rin
1785 1.1 rin if (!IFQ_IS_EMPTY(&ifp->if_snd))
1786 1.1 rin mue_start(ifp);
1787 1.1 rin splx(s);
1788 1.1 rin }
1789 1.1 rin
1790 1.1 rin static void
1791 1.1 rin mue_reset(struct mue_softc *sc)
1792 1.1 rin {
1793 1.1 rin if (sc->mue_dying)
1794 1.1 rin return;
1795 1.1 rin
1796 1.1 rin /* Wait a little while for the chip to get its brains in order. */
1797 1.1 rin usbd_delay_ms(sc->mue_udev, 1);
1798 1.1 rin
1799 1.1 rin // mue_chip_init(sc); /* XXX */
1800 1.1 rin }
1801 1.1 rin
1802 1.1 rin static void
1803 1.1 rin mue_start(struct ifnet *ifp)
1804 1.1 rin {
1805 1.1 rin struct mue_softc *sc = ifp->if_softc;
1806 1.1 rin struct mbuf *m;
1807 1.27 mlelstv struct mue_cdata *cd = &sc->mue_cdata;
1808 1.27 mlelstv int idx;
1809 1.1 rin
1810 1.1 rin if (__predict_false(!sc->mue_link)) {
1811 1.1 rin DPRINTF(sc, "no link\n");
1812 1.1 rin return;
1813 1.1 rin }
1814 1.1 rin
1815 1.44 msaitoh if (__predict_false((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING))
1816 1.1 rin != IFF_RUNNING)) {
1817 1.1 rin DPRINTF(sc, "not ready\n");
1818 1.1 rin return;
1819 1.1 rin }
1820 1.1 rin
1821 1.27 mlelstv idx = cd->mue_tx_prod;
1822 1.41 rin while (cd->mue_tx_cnt < (int)sc->mue_tx_list_cnt) {
1823 1.27 mlelstv IFQ_POLL(&ifp->if_snd, m);
1824 1.27 mlelstv if (m == NULL)
1825 1.27 mlelstv break;
1826 1.27 mlelstv
1827 1.27 mlelstv if (__predict_false(mue_encap(sc, m, idx))) {
1828 1.27 mlelstv ifp->if_oerrors++;
1829 1.27 mlelstv break;
1830 1.27 mlelstv }
1831 1.27 mlelstv IFQ_DEQUEUE(&ifp->if_snd, m);
1832 1.27 mlelstv
1833 1.27 mlelstv bpf_mtap(ifp, m, BPF_D_OUT);
1834 1.27 mlelstv m_freem(m);
1835 1.27 mlelstv
1836 1.31 mlelstv idx = (idx + 1) % sc->mue_tx_list_cnt;
1837 1.27 mlelstv cd->mue_tx_cnt++;
1838 1.1 rin
1839 1.1 rin }
1840 1.27 mlelstv cd->mue_tx_prod = idx;
1841 1.1 rin
1842 1.41 rin if (cd->mue_tx_cnt >= (int)sc->mue_tx_list_cnt)
1843 1.27 mlelstv ifp->if_flags |= IFF_OACTIVE;
1844 1.1 rin
1845 1.1 rin /* Set a timeout in case the chip goes out to lunch. */
1846 1.1 rin ifp->if_timer = 5;
1847 1.1 rin }
1848 1.1 rin
1849 1.1 rin static void
1850 1.1 rin mue_stop(struct ifnet *ifp, int disable __unused)
1851 1.1 rin {
1852 1.1 rin struct mue_softc *sc = ifp->if_softc;
1853 1.33 rin struct mue_chain *c;
1854 1.1 rin usbd_status err;
1855 1.1 rin size_t i;
1856 1.1 rin
1857 1.1 rin mue_reset(sc);
1858 1.1 rin
1859 1.1 rin ifp->if_timer = 0;
1860 1.1 rin ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1861 1.1 rin
1862 1.1 rin callout_stop(&sc->mue_stat_ch);
1863 1.32 rin sc->mue_link = 0;
1864 1.1 rin
1865 1.1 rin /* Stop transfers. */
1866 1.1 rin for (i = 0; i < __arraycount(sc->mue_ep); i++)
1867 1.1 rin if (sc->mue_ep[i] != NULL) {
1868 1.1 rin err = usbd_abort_pipe(sc->mue_ep[i]);
1869 1.1 rin if (err)
1870 1.1 rin MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1871 1.1 rin i, usbd_errstr(err));
1872 1.1 rin }
1873 1.1 rin
1874 1.1 rin /* Free RX resources. */
1875 1.33 rin for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1876 1.33 rin c = &sc->mue_cdata.mue_rx_chain[i];
1877 1.33 rin if (c->mue_xfer != NULL) {
1878 1.33 rin usbd_destroy_xfer(c->mue_xfer);
1879 1.33 rin c->mue_xfer = NULL;
1880 1.1 rin }
1881 1.33 rin }
1882 1.1 rin
1883 1.1 rin /* Free TX resources. */
1884 1.33 rin for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1885 1.33 rin c = &sc->mue_cdata.mue_tx_chain[i];
1886 1.33 rin if (c->mue_xfer != NULL) {
1887 1.33 rin usbd_destroy_xfer(c->mue_xfer);
1888 1.33 rin c->mue_xfer = NULL;
1889 1.1 rin }
1890 1.33 rin }
1891 1.1 rin
1892 1.1 rin /* Close pipes */
1893 1.1 rin for (i = 0; i < __arraycount(sc->mue_ep); i++)
1894 1.1 rin if (sc->mue_ep[i] != NULL) {
1895 1.1 rin err = usbd_close_pipe(sc->mue_ep[i]);
1896 1.1 rin if (err)
1897 1.1 rin MUE_PRINTF(sc, "close pipe %zu: %s\n",
1898 1.1 rin i, usbd_errstr(err));
1899 1.1 rin sc->mue_ep[i] = NULL;
1900 1.1 rin }
1901 1.1 rin
1902 1.1 rin DPRINTF(sc, "done\n");
1903 1.1 rin }
1904 1.1 rin
1905 1.1 rin static void
1906 1.1 rin mue_tick(void *xsc)
1907 1.1 rin {
1908 1.1 rin struct mue_softc *sc = xsc;
1909 1.1 rin
1910 1.1 rin if (sc == NULL)
1911 1.1 rin return;
1912 1.1 rin
1913 1.1 rin if (sc->mue_dying)
1914 1.1 rin return;
1915 1.1 rin
1916 1.1 rin /* Perform periodic stuff in process context. */
1917 1.1 rin usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1918 1.1 rin }
1919 1.1 rin
1920 1.1 rin static void
1921 1.1 rin mue_tick_task(void *xsc)
1922 1.1 rin {
1923 1.1 rin struct mue_softc *sc = xsc;
1924 1.34 rin struct ifnet *ifp;
1925 1.34 rin struct mii_data *mii;
1926 1.1 rin int s;
1927 1.1 rin
1928 1.1 rin if (sc == NULL)
1929 1.1 rin return;
1930 1.1 rin
1931 1.1 rin if (sc->mue_dying)
1932 1.1 rin return;
1933 1.1 rin
1934 1.34 rin ifp = GET_IFP(sc);
1935 1.34 rin mii = GET_MII(sc);
1936 1.34 rin
1937 1.1 rin s = splnet();
1938 1.1 rin mii_tick(mii);
1939 1.1 rin if (sc->mue_link == 0)
1940 1.1 rin mue_miibus_statchg(ifp);
1941 1.1 rin callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1942 1.1 rin splx(s);
1943 1.1 rin }
1944 1.1 rin
1945 1.1 rin static struct mbuf *
1946 1.1 rin mue_newbuf(void)
1947 1.1 rin {
1948 1.1 rin struct mbuf *m;
1949 1.1 rin
1950 1.1 rin MGETHDR(m, M_DONTWAIT, MT_DATA);
1951 1.1 rin if (__predict_false(m == NULL))
1952 1.1 rin return NULL;
1953 1.1 rin
1954 1.1 rin MCLGET(m, M_DONTWAIT);
1955 1.1 rin if (__predict_false(!(m->m_flags & M_EXT))) {
1956 1.1 rin m_freem(m);
1957 1.1 rin return NULL;
1958 1.1 rin }
1959 1.1 rin
1960 1.1 rin m_adj(m, ETHER_ALIGN);
1961 1.1 rin
1962 1.1 rin return m;
1963 1.1 rin }
1964