if_mue.c revision 1.81 1 1.81 riastrad /* $NetBSD: if_mue.c,v 1.81 2022/03/03 05:56:28 riastradh Exp $ */
2 1.1 rin /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3 1.1 rin
4 1.1 rin /*
5 1.1 rin * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 1.1 rin *
7 1.1 rin * Permission to use, copy, modify, and distribute this software for any
8 1.1 rin * purpose with or without fee is hereby granted, provided that the above
9 1.1 rin * copyright notice and this permission notice appear in all copies.
10 1.1 rin *
11 1.1 rin * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 1.1 rin * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 1.1 rin * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 1.1 rin * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 1.1 rin * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 1.1 rin * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 1.1 rin * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 1.1 rin */
19 1.1 rin
20 1.1 rin /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21 1.1 rin
22 1.1 rin #include <sys/cdefs.h>
23 1.81 riastrad __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.81 2022/03/03 05:56:28 riastradh Exp $");
24 1.1 rin
25 1.1 rin #ifdef _KERNEL_OPT
26 1.1 rin #include "opt_usb.h"
27 1.1 rin #include "opt_inet.h"
28 1.1 rin #endif
29 1.1 rin
30 1.1 rin #include <sys/param.h>
31 1.52 mrg
32 1.52 mrg #include <dev/usb/usbnet.h>
33 1.1 rin
34 1.1 rin #include <dev/usb/if_muereg.h>
35 1.1 rin #include <dev/usb/if_muevar.h>
36 1.1 rin
37 1.52 mrg #define MUE_PRINTF(un, fmt, args...) \
38 1.52 mrg device_printf((un)->un_dev, "%s: " fmt, __func__, ##args);
39 1.1 rin
40 1.1 rin #ifdef USB_DEBUG
41 1.1 rin int muedebug = 0;
42 1.52 mrg #define DPRINTF(un, fmt, args...) \
43 1.45 msaitoh do { \
44 1.1 rin if (muedebug) \
45 1.52 mrg MUE_PRINTF(un, fmt, ##args); \
46 1.1 rin } while (0 /* CONSTCOND */)
47 1.1 rin #else
48 1.52 mrg #define DPRINTF(un, fmt, args...) __nothing
49 1.1 rin #endif
50 1.1 rin
51 1.1 rin /*
52 1.1 rin * Various supported device vendors/products.
53 1.1 rin */
54 1.1 rin struct mue_type {
55 1.1 rin struct usb_devno mue_dev;
56 1.1 rin uint16_t mue_flags;
57 1.1 rin #define LAN7500 0x0001 /* LAN7500 */
58 1.52 mrg #define LAN7800 0x0002 /* LAN7800 */
59 1.52 mrg #define LAN7801 0x0004 /* LAN7801 */
60 1.52 mrg #define LAN7850 0x0008 /* LAN7850 */
61 1.1 rin };
62 1.1 rin
63 1.56 maxv static const struct mue_type mue_devs[] = {
64 1.1 rin { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
65 1.1 rin { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
66 1.52 mrg { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, LAN7800 },
67 1.52 mrg { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, LAN7801 },
68 1.52 mrg { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, LAN7850 }
69 1.1 rin };
70 1.1 rin
71 1.1 rin #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
72 1.1 rin uaa->uaa_vendor, uaa->uaa_product))
73 1.1 rin
74 1.1 rin #define MUE_ENADDR_LO(enaddr) \
75 1.1 rin ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
76 1.1 rin #define MUE_ENADDR_HI(enaddr) \
77 1.1 rin ((enaddr[5] << 8) | enaddr[4])
78 1.1 rin
79 1.1 rin static int mue_match(device_t, cfdata_t, void *);
80 1.1 rin static void mue_attach(device_t, device_t, void *);
81 1.1 rin
82 1.52 mrg static uint32_t mue_csr_read(struct usbnet *, uint32_t);
83 1.52 mrg static int mue_csr_write(struct usbnet *, uint32_t, uint32_t);
84 1.52 mrg static int mue_wait_for_bits(struct usbnet *, uint32_t, uint32_t,
85 1.1 rin uint32_t, uint32_t);
86 1.52 mrg static uint8_t mue_eeprom_getbyte(struct usbnet *, int, uint8_t *);
87 1.52 mrg static bool mue_eeprom_present(struct usbnet *);
88 1.52 mrg static void mue_dataport_write(struct usbnet *, uint32_t, uint32_t,
89 1.1 rin uint32_t, uint32_t *);
90 1.52 mrg static void mue_init_ltm(struct usbnet *);
91 1.52 mrg static int mue_chip_init(struct usbnet *);
92 1.52 mrg static void mue_set_macaddr(struct usbnet *);
93 1.52 mrg static int mue_get_macaddr(struct usbnet *, prop_dictionary_t);
94 1.52 mrg static int mue_prepare_tso(struct usbnet *, struct mbuf *);
95 1.72 riastrad static void mue_uno_mcast(struct ifnet *);
96 1.59 thorpej static void mue_sethwcsum_locked(struct usbnet *);
97 1.59 thorpej static void mue_setmtu_locked(struct usbnet *);
98 1.52 mrg static void mue_reset(struct usbnet *);
99 1.52 mrg
100 1.59 thorpej static void mue_uno_stop(struct ifnet *, int);
101 1.62 nisimura static int mue_uno_ioctl(struct ifnet *, u_long, void *);
102 1.59 thorpej static int mue_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *);
103 1.59 thorpej static int mue_uno_mii_write_reg(struct usbnet *, int, int, uint16_t);
104 1.59 thorpej static void mue_uno_mii_statchg(struct ifnet *);
105 1.59 thorpej static void mue_uno_rx_loop(struct usbnet *, struct usbnet_chain *,
106 1.59 thorpej uint32_t);
107 1.59 thorpej static unsigned mue_uno_tx_prepare(struct usbnet *, struct mbuf *,
108 1.59 thorpej struct usbnet_chain *);
109 1.59 thorpej static int mue_uno_init(struct ifnet *);
110 1.1 rin
111 1.56 maxv static const struct usbnet_ops mue_ops = {
112 1.59 thorpej .uno_stop = mue_uno_stop,
113 1.62 nisimura .uno_ioctl = mue_uno_ioctl,
114 1.66 riastrad .uno_mcast = mue_uno_mcast,
115 1.59 thorpej .uno_read_reg = mue_uno_mii_read_reg,
116 1.59 thorpej .uno_write_reg = mue_uno_mii_write_reg,
117 1.59 thorpej .uno_statchg = mue_uno_mii_statchg,
118 1.59 thorpej .uno_tx_prepare = mue_uno_tx_prepare,
119 1.59 thorpej .uno_rx_loop = mue_uno_rx_loop,
120 1.59 thorpej .uno_init = mue_uno_init,
121 1.52 mrg };
122 1.1 rin
123 1.52 mrg #define MUE_SETBIT(un, reg, x) \
124 1.52 mrg mue_csr_write(un, reg, mue_csr_read(un, reg) | (x))
125 1.1 rin
126 1.52 mrg #define MUE_CLRBIT(un, reg, x) \
127 1.52 mrg mue_csr_write(un, reg, mue_csr_read(un, reg) & ~(x))
128 1.1 rin
129 1.52 mrg #define MUE_WAIT_SET(un, reg, set, fail) \
130 1.52 mrg mue_wait_for_bits(un, reg, set, ~0, fail)
131 1.1 rin
132 1.52 mrg #define MUE_WAIT_CLR(un, reg, clear, fail) \
133 1.52 mrg mue_wait_for_bits(un, reg, 0, clear, fail)
134 1.1 rin
135 1.1 rin #define ETHER_IS_VALID(addr) \
136 1.1 rin (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
137 1.1 rin
138 1.1 rin #define ETHER_IS_ZERO(addr) \
139 1.1 rin (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
140 1.1 rin
141 1.62 nisimura CFATTACH_DECL_NEW(mue, sizeof(struct usbnet), mue_match, mue_attach,
142 1.52 mrg usbnet_detach, usbnet_activate);
143 1.1 rin
144 1.1 rin static uint32_t
145 1.52 mrg mue_csr_read(struct usbnet *un, uint32_t reg)
146 1.1 rin {
147 1.1 rin usb_device_request_t req;
148 1.1 rin usbd_status err;
149 1.1 rin uDWord val;
150 1.1 rin
151 1.52 mrg if (usbnet_isdying(un))
152 1.1 rin return 0;
153 1.1 rin
154 1.1 rin USETDW(val, 0);
155 1.1 rin req.bmRequestType = UT_READ_VENDOR_DEVICE;
156 1.1 rin req.bRequest = MUE_UR_READREG;
157 1.1 rin USETW(req.wValue, 0);
158 1.1 rin USETW(req.wIndex, reg);
159 1.1 rin USETW(req.wLength, 4);
160 1.1 rin
161 1.52 mrg err = usbd_do_request(un->un_udev, &req, &val);
162 1.1 rin if (err) {
163 1.58 christos MUE_PRINTF(un, "reg = %#x: %s\n", reg, usbd_errstr(err));
164 1.1 rin return 0;
165 1.1 rin }
166 1.1 rin
167 1.1 rin return UGETDW(val);
168 1.1 rin }
169 1.1 rin
170 1.1 rin static int
171 1.52 mrg mue_csr_write(struct usbnet *un, uint32_t reg, uint32_t aval)
172 1.1 rin {
173 1.1 rin usb_device_request_t req;
174 1.1 rin usbd_status err;
175 1.1 rin uDWord val;
176 1.1 rin
177 1.52 mrg if (usbnet_isdying(un))
178 1.1 rin return 0;
179 1.1 rin
180 1.1 rin USETDW(val, aval);
181 1.1 rin req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
182 1.1 rin req.bRequest = MUE_UR_WRITEREG;
183 1.1 rin USETW(req.wValue, 0);
184 1.1 rin USETW(req.wIndex, reg);
185 1.1 rin USETW(req.wLength, 4);
186 1.1 rin
187 1.52 mrg err = usbd_do_request(un->un_udev, &req, &val);
188 1.1 rin if (err) {
189 1.58 christos MUE_PRINTF(un, "reg = %#x: %s\n", reg, usbd_errstr(err));
190 1.1 rin return -1;
191 1.1 rin }
192 1.1 rin
193 1.1 rin return 0;
194 1.1 rin }
195 1.1 rin
196 1.1 rin static int
197 1.52 mrg mue_wait_for_bits(struct usbnet *un, uint32_t reg,
198 1.1 rin uint32_t set, uint32_t clear, uint32_t fail)
199 1.1 rin {
200 1.1 rin uint32_t val;
201 1.1 rin int ntries;
202 1.1 rin
203 1.1 rin for (ntries = 0; ntries < 1000; ntries++) {
204 1.65 riastrad if (usbnet_isdying(un))
205 1.65 riastrad return 1;
206 1.52 mrg val = mue_csr_read(un, reg);
207 1.1 rin if ((val & set) || !(val & clear))
208 1.1 rin return 0;
209 1.1 rin if (val & fail)
210 1.1 rin return 1;
211 1.52 mrg usbd_delay_ms(un->un_udev, 1);
212 1.1 rin }
213 1.1 rin
214 1.1 rin return 1;
215 1.1 rin }
216 1.1 rin
217 1.54 mrg static int
218 1.59 thorpej mue_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val)
219 1.1 rin {
220 1.28 msaitoh uint32_t data;
221 1.1 rin
222 1.76 riastrad if (un->un_phyno != phy) {
223 1.76 riastrad *val = 0;
224 1.54 mrg return EINVAL;
225 1.76 riastrad }
226 1.53 mrg
227 1.52 mrg if (MUE_WAIT_CLR(un, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
228 1.52 mrg MUE_PRINTF(un, "not ready\n");
229 1.76 riastrad *val = 0;
230 1.54 mrg return EBUSY;
231 1.1 rin }
232 1.1 rin
233 1.52 mrg mue_csr_write(un, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
234 1.1 rin MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
235 1.1 rin MUE_MII_ACCESS_PHYADDR(phy));
236 1.1 rin
237 1.52 mrg if (MUE_WAIT_CLR(un, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
238 1.52 mrg MUE_PRINTF(un, "timed out\n");
239 1.76 riastrad *val = 0;
240 1.54 mrg return ETIMEDOUT;
241 1.1 rin }
242 1.1 rin
243 1.52 mrg data = mue_csr_read(un, MUE_MII_DATA);
244 1.28 msaitoh *val = data & 0xffff;
245 1.28 msaitoh
246 1.54 mrg return 0;
247 1.1 rin }
248 1.1 rin
249 1.54 mrg static int
250 1.59 thorpej mue_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val)
251 1.1 rin {
252 1.1 rin
253 1.53 mrg if (un->un_phyno != phy)
254 1.54 mrg return EINVAL;
255 1.53 mrg
256 1.52 mrg if (MUE_WAIT_CLR(un, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
257 1.52 mrg MUE_PRINTF(un, "not ready\n");
258 1.54 mrg return EBUSY;
259 1.1 rin }
260 1.1 rin
261 1.52 mrg mue_csr_write(un, MUE_MII_DATA, val);
262 1.52 mrg mue_csr_write(un, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
263 1.1 rin MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
264 1.1 rin MUE_MII_ACCESS_PHYADDR(phy));
265 1.1 rin
266 1.52 mrg if (MUE_WAIT_CLR(un, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
267 1.52 mrg MUE_PRINTF(un, "timed out\n");
268 1.54 mrg return ETIMEDOUT;
269 1.28 msaitoh }
270 1.52 mrg
271 1.54 mrg return 0;
272 1.1 rin }
273 1.1 rin
274 1.1 rin static void
275 1.59 thorpej mue_uno_mii_statchg(struct ifnet *ifp)
276 1.1 rin {
277 1.52 mrg struct usbnet * const un = ifp->if_softc;
278 1.52 mrg struct mii_data * const mii = usbnet_mii(un);
279 1.1 rin uint32_t flow, threshold;
280 1.1 rin
281 1.52 mrg if (usbnet_isdying(un))
282 1.34 rin return;
283 1.34 rin
284 1.1 rin if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
285 1.1 rin (IFM_ACTIVE | IFM_AVALID)) {
286 1.1 rin switch (IFM_SUBTYPE(mii->mii_media_active)) {
287 1.1 rin case IFM_10_T:
288 1.1 rin case IFM_100_TX:
289 1.1 rin case IFM_1000_T:
290 1.52 mrg usbnet_set_link(un, true);
291 1.1 rin break;
292 1.1 rin default:
293 1.1 rin break;
294 1.1 rin }
295 1.1 rin }
296 1.1 rin
297 1.1 rin /* Lost link, do nothing. */
298 1.52 mrg if (!usbnet_havelink(un)) {
299 1.58 christos DPRINTF(un, "mii_media_status = %#x\n", mii->mii_media_status);
300 1.1 rin return;
301 1.1 rin }
302 1.1 rin
303 1.52 mrg if (!(un->un_flags & LAN7500)) {
304 1.52 mrg if (un->un_udev->ud_speed == USB_SPEED_SUPER) {
305 1.1 rin if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
306 1.1 rin /* Disable U2 and enable U1. */
307 1.52 mrg MUE_CLRBIT(un, MUE_USB_CFG1,
308 1.1 rin MUE_USB_CFG1_DEV_U2_INIT_EN);
309 1.52 mrg MUE_SETBIT(un, MUE_USB_CFG1,
310 1.1 rin MUE_USB_CFG1_DEV_U1_INIT_EN);
311 1.1 rin } else {
312 1.1 rin /* Enable U1 and U2. */
313 1.52 mrg MUE_SETBIT(un, MUE_USB_CFG1,
314 1.1 rin MUE_USB_CFG1_DEV_U1_INIT_EN |
315 1.1 rin MUE_USB_CFG1_DEV_U2_INIT_EN);
316 1.1 rin }
317 1.1 rin }
318 1.1 rin }
319 1.1 rin
320 1.1 rin flow = 0;
321 1.1 rin /* XXX Linux does not check IFM_FDX flag for 7800. */
322 1.1 rin if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
323 1.1 rin if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
324 1.1 rin flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
325 1.1 rin if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
326 1.1 rin flow |= MUE_FLOW_RX_FCEN;
327 1.1 rin }
328 1.1 rin
329 1.1 rin /* XXX Magic numbers taken from Linux driver. */
330 1.52 mrg if (un->un_flags & LAN7500)
331 1.1 rin threshold = 0x820;
332 1.1 rin else
333 1.52 mrg switch (un->un_udev->ud_speed) {
334 1.1 rin case USB_SPEED_SUPER:
335 1.1 rin threshold = 0x817;
336 1.1 rin break;
337 1.1 rin case USB_SPEED_HIGH:
338 1.1 rin threshold = 0x211;
339 1.1 rin break;
340 1.1 rin default:
341 1.1 rin threshold = 0;
342 1.1 rin break;
343 1.1 rin }
344 1.1 rin
345 1.1 rin /* Threshold value should be set before enabling flow. */
346 1.52 mrg mue_csr_write(un, (un->un_flags & LAN7500) ?
347 1.1 rin MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
348 1.52 mrg mue_csr_write(un, MUE_FLOW, flow);
349 1.1 rin
350 1.52 mrg DPRINTF(un, "done\n");
351 1.1 rin }
352 1.1 rin
353 1.1 rin static uint8_t
354 1.52 mrg mue_eeprom_getbyte(struct usbnet *un, int off, uint8_t *dest)
355 1.1 rin {
356 1.1 rin uint32_t val;
357 1.1 rin
358 1.52 mrg if (MUE_WAIT_CLR(un, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
359 1.52 mrg MUE_PRINTF(un, "not ready\n");
360 1.1 rin return ETIMEDOUT;
361 1.1 rin }
362 1.1 rin
363 1.17 rin KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
364 1.52 mrg mue_csr_write(un, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
365 1.17 rin off);
366 1.1 rin
367 1.52 mrg if (MUE_WAIT_CLR(un, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
368 1.1 rin MUE_E2P_CMD_TIMEOUT)) {
369 1.52 mrg MUE_PRINTF(un, "timed out\n");
370 1.1 rin return ETIMEDOUT;
371 1.1 rin }
372 1.1 rin
373 1.52 mrg val = mue_csr_read(un, MUE_E2P_DATA);
374 1.1 rin *dest = val & 0xff;
375 1.1 rin
376 1.1 rin return 0;
377 1.1 rin }
378 1.1 rin
379 1.1 rin static int
380 1.52 mrg mue_read_eeprom(struct usbnet *un, uint8_t *dest, int off, int cnt)
381 1.1 rin {
382 1.1 rin uint32_t val = 0; /* XXX gcc */
383 1.1 rin uint8_t byte;
384 1.42 martin int i, err = 0;
385 1.1 rin
386 1.1 rin /*
387 1.1 rin * EEPROM pins are muxed with the LED function on LAN7800 device.
388 1.1 rin */
389 1.52 mrg if (un->un_flags & LAN7800) {
390 1.52 mrg val = mue_csr_read(un, MUE_HW_CFG);
391 1.52 mrg mue_csr_write(un, MUE_HW_CFG,
392 1.1 rin val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
393 1.1 rin }
394 1.1 rin
395 1.1 rin for (i = 0; i < cnt; i++) {
396 1.52 mrg err = mue_eeprom_getbyte(un, off + i, &byte);
397 1.1 rin if (err)
398 1.1 rin break;
399 1.1 rin *(dest + i) = byte;
400 1.1 rin }
401 1.1 rin
402 1.52 mrg if (un->un_flags & LAN7800)
403 1.52 mrg mue_csr_write(un, MUE_HW_CFG, val);
404 1.1 rin
405 1.1 rin return err ? 1 : 0;
406 1.1 rin }
407 1.1 rin
408 1.1 rin static bool
409 1.52 mrg mue_eeprom_present(struct usbnet *un)
410 1.1 rin {
411 1.1 rin uint32_t val;
412 1.1 rin uint8_t sig;
413 1.1 rin int ret;
414 1.1 rin
415 1.52 mrg if (un->un_flags & LAN7500) {
416 1.52 mrg val = mue_csr_read(un, MUE_E2P_CMD);
417 1.1 rin return val & MUE_E2P_CMD_LOADED;
418 1.1 rin } else {
419 1.52 mrg ret = mue_read_eeprom(un, &sig, MUE_E2P_IND_OFFSET, 1);
420 1.1 rin return (ret == 0) && (sig == MUE_E2P_IND);
421 1.1 rin }
422 1.1 rin }
423 1.1 rin
424 1.1 rin static int
425 1.52 mrg mue_read_otp_raw(struct usbnet *un, uint8_t *dest, int off, int cnt)
426 1.1 rin {
427 1.1 rin uint32_t val;
428 1.1 rin int i, err;
429 1.1 rin
430 1.52 mrg val = mue_csr_read(un, MUE_OTP_PWR_DN);
431 1.1 rin
432 1.1 rin /* Checking if bit is set. */
433 1.1 rin if (val & MUE_OTP_PWR_DN_PWRDN_N) {
434 1.1 rin /* Clear it, then wait for it to be cleared. */
435 1.52 mrg mue_csr_write(un, MUE_OTP_PWR_DN, 0);
436 1.52 mrg err = MUE_WAIT_CLR(un, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
437 1.1 rin 0);
438 1.1 rin if (err) {
439 1.52 mrg MUE_PRINTF(un, "not ready\n");
440 1.1 rin return 1;
441 1.1 rin }
442 1.1 rin }
443 1.1 rin
444 1.1 rin /* Start reading the bytes, one at a time. */
445 1.1 rin for (i = 0; i < cnt; i++) {
446 1.52 mrg mue_csr_write(un, MUE_OTP_ADDR1,
447 1.1 rin ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
448 1.52 mrg mue_csr_write(un, MUE_OTP_ADDR2,
449 1.1 rin ((off + i) & MUE_OTP_ADDR2_MASK));
450 1.52 mrg mue_csr_write(un, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
451 1.52 mrg mue_csr_write(un, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
452 1.1 rin
453 1.52 mrg err = MUE_WAIT_CLR(un, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
454 1.1 rin if (err) {
455 1.52 mrg MUE_PRINTF(un, "timed out\n");
456 1.1 rin return 1;
457 1.1 rin }
458 1.52 mrg val = mue_csr_read(un, MUE_OTP_RD_DATA);
459 1.1 rin *(dest + i) = (uint8_t)(val & 0xff);
460 1.1 rin }
461 1.1 rin
462 1.1 rin return 0;
463 1.1 rin }
464 1.1 rin
465 1.1 rin static int
466 1.52 mrg mue_read_otp(struct usbnet *un, uint8_t *dest, int off, int cnt)
467 1.1 rin {
468 1.1 rin uint8_t sig;
469 1.1 rin int err;
470 1.1 rin
471 1.52 mrg if (un->un_flags & LAN7500)
472 1.1 rin return 1;
473 1.1 rin
474 1.52 mrg err = mue_read_otp_raw(un, &sig, MUE_OTP_IND_OFFSET, 1);
475 1.1 rin if (err)
476 1.1 rin return 1;
477 1.1 rin switch (sig) {
478 1.1 rin case MUE_OTP_IND_1:
479 1.1 rin break;
480 1.1 rin case MUE_OTP_IND_2:
481 1.1 rin off += 0x100;
482 1.1 rin break;
483 1.1 rin default:
484 1.52 mrg DPRINTF(un, "OTP not found\n");
485 1.1 rin return 1;
486 1.1 rin }
487 1.52 mrg err = mue_read_otp_raw(un, dest, off, cnt);
488 1.1 rin return err;
489 1.1 rin }
490 1.1 rin
491 1.1 rin static void
492 1.52 mrg mue_dataport_write(struct usbnet *un, uint32_t sel, uint32_t addr,
493 1.1 rin uint32_t cnt, uint32_t *data)
494 1.1 rin {
495 1.1 rin uint32_t i;
496 1.1 rin
497 1.52 mrg if (MUE_WAIT_SET(un, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
498 1.52 mrg MUE_PRINTF(un, "not ready\n");
499 1.1 rin return;
500 1.1 rin }
501 1.1 rin
502 1.52 mrg mue_csr_write(un, MUE_DP_SEL,
503 1.52 mrg (mue_csr_read(un, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
504 1.1 rin
505 1.1 rin for (i = 0; i < cnt; i++) {
506 1.52 mrg mue_csr_write(un, MUE_DP_ADDR, addr + i);
507 1.52 mrg mue_csr_write(un, MUE_DP_DATA, data[i]);
508 1.52 mrg mue_csr_write(un, MUE_DP_CMD, MUE_DP_CMD_WRITE);
509 1.52 mrg if (MUE_WAIT_SET(un, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
510 1.52 mrg MUE_PRINTF(un, "timed out\n");
511 1.1 rin return;
512 1.1 rin }
513 1.1 rin }
514 1.1 rin }
515 1.1 rin
516 1.1 rin static void
517 1.52 mrg mue_init_ltm(struct usbnet *un)
518 1.1 rin {
519 1.1 rin uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
520 1.1 rin uint8_t temp[2];
521 1.1 rin size_t i;
522 1.1 rin
523 1.52 mrg if (mue_csr_read(un, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
524 1.52 mrg if (mue_eeprom_present(un) &&
525 1.52 mrg (mue_read_eeprom(un, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
526 1.1 rin if (temp[0] != sizeof(idx)) {
527 1.52 mrg DPRINTF(un, "EEPROM: unexpected size\n");
528 1.1 rin goto done;
529 1.1 rin }
530 1.52 mrg if (mue_read_eeprom(un, (uint8_t *)idx, temp[1] << 1,
531 1.1 rin sizeof(idx))) {
532 1.52 mrg DPRINTF(un, "EEPROM: failed to read\n");
533 1.1 rin goto done;
534 1.1 rin }
535 1.52 mrg DPRINTF(un, "success\n");
536 1.52 mrg } else if (mue_read_otp(un, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
537 1.1 rin if (temp[0] != sizeof(idx)) {
538 1.52 mrg DPRINTF(un, "OTP: unexpected size\n");
539 1.1 rin goto done;
540 1.1 rin }
541 1.52 mrg if (mue_read_otp(un, (uint8_t *)idx, temp[1] << 1,
542 1.1 rin sizeof(idx))) {
543 1.52 mrg DPRINTF(un, "OTP: failed to read\n");
544 1.1 rin goto done;
545 1.1 rin }
546 1.52 mrg DPRINTF(un, "success\n");
547 1.26 rin } else
548 1.52 mrg DPRINTF(un, "nothing to do\n");
549 1.26 rin } else
550 1.52 mrg DPRINTF(un, "nothing to do\n");
551 1.1 rin done:
552 1.1 rin for (i = 0; i < __arraycount(idx); i++)
553 1.52 mrg mue_csr_write(un, MUE_LTM_INDEX(i), idx[i]);
554 1.1 rin }
555 1.1 rin
556 1.1 rin static int
557 1.52 mrg mue_chip_init(struct usbnet *un)
558 1.1 rin {
559 1.1 rin uint32_t val;
560 1.1 rin
561 1.52 mrg if ((un->un_flags & LAN7500) &&
562 1.52 mrg MUE_WAIT_SET(un, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
563 1.52 mrg MUE_PRINTF(un, "not ready\n");
564 1.1 rin return ETIMEDOUT;
565 1.1 rin }
566 1.1 rin
567 1.52 mrg MUE_SETBIT(un, MUE_HW_CFG, MUE_HW_CFG_LRST);
568 1.52 mrg if (MUE_WAIT_CLR(un, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
569 1.52 mrg MUE_PRINTF(un, "timed out\n");
570 1.1 rin return ETIMEDOUT;
571 1.1 rin }
572 1.1 rin
573 1.1 rin /* Respond to the IN token with a NAK. */
574 1.52 mrg if (un->un_flags & LAN7500)
575 1.52 mrg MUE_SETBIT(un, MUE_HW_CFG, MUE_HW_CFG_BIR);
576 1.1 rin else
577 1.52 mrg MUE_SETBIT(un, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
578 1.1 rin
579 1.52 mrg if (un->un_flags & LAN7500) {
580 1.52 mrg if (un->un_udev->ud_speed == USB_SPEED_HIGH)
581 1.3 rin val = MUE_7500_HS_RX_BUFSIZE /
582 1.1 rin MUE_HS_USB_PKT_SIZE;
583 1.1 rin else
584 1.3 rin val = MUE_7500_FS_RX_BUFSIZE /
585 1.1 rin MUE_FS_USB_PKT_SIZE;
586 1.52 mrg mue_csr_write(un, MUE_7500_BURST_CAP, val);
587 1.52 mrg mue_csr_write(un, MUE_7500_BULKIN_DELAY,
588 1.1 rin MUE_7500_DEFAULT_BULKIN_DELAY);
589 1.1 rin
590 1.52 mrg MUE_SETBIT(un, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
591 1.1 rin
592 1.1 rin /* Set FIFO sizes. */
593 1.1 rin val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
594 1.52 mrg mue_csr_write(un, MUE_7500_FCT_RX_FIFO_END, val);
595 1.1 rin val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
596 1.52 mrg mue_csr_write(un, MUE_7500_FCT_TX_FIFO_END, val);
597 1.1 rin } else {
598 1.1 rin /* Init LTM. */
599 1.52 mrg mue_init_ltm(un);
600 1.1 rin
601 1.3 rin val = MUE_7800_RX_BUFSIZE;
602 1.52 mrg switch (un->un_udev->ud_speed) {
603 1.1 rin case USB_SPEED_SUPER:
604 1.1 rin val /= MUE_SS_USB_PKT_SIZE;
605 1.1 rin break;
606 1.1 rin case USB_SPEED_HIGH:
607 1.1 rin val /= MUE_HS_USB_PKT_SIZE;
608 1.1 rin break;
609 1.1 rin default:
610 1.1 rin val /= MUE_FS_USB_PKT_SIZE;
611 1.1 rin break;
612 1.1 rin }
613 1.52 mrg mue_csr_write(un, MUE_7800_BURST_CAP, val);
614 1.52 mrg mue_csr_write(un, MUE_7800_BULKIN_DELAY,
615 1.1 rin MUE_7800_DEFAULT_BULKIN_DELAY);
616 1.1 rin
617 1.52 mrg MUE_SETBIT(un, MUE_HW_CFG, MUE_HW_CFG_MEF);
618 1.52 mrg MUE_SETBIT(un, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
619 1.1 rin
620 1.1 rin /*
621 1.1 rin * Set FCL's RX and TX FIFO sizes: according to data sheet this
622 1.1 rin * is already the default value. But we initialize it to the
623 1.1 rin * same value anyways, as that's what the Linux driver does.
624 1.1 rin */
625 1.1 rin val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
626 1.52 mrg mue_csr_write(un, MUE_7800_FCT_RX_FIFO_END, val);
627 1.1 rin val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
628 1.52 mrg mue_csr_write(un, MUE_7800_FCT_TX_FIFO_END, val);
629 1.1 rin }
630 1.1 rin
631 1.1 rin /* Enabling interrupts. */
632 1.52 mrg mue_csr_write(un, MUE_INT_STATUS, ~0);
633 1.1 rin
634 1.52 mrg mue_csr_write(un, (un->un_flags & LAN7500) ?
635 1.1 rin MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
636 1.52 mrg mue_csr_write(un, MUE_FLOW, 0);
637 1.44 msaitoh
638 1.1 rin /* Reset PHY. */
639 1.52 mrg MUE_SETBIT(un, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
640 1.52 mrg if (MUE_WAIT_CLR(un, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
641 1.52 mrg MUE_PRINTF(un, "PHY not ready\n");
642 1.1 rin return ETIMEDOUT;
643 1.1 rin }
644 1.1 rin
645 1.1 rin /* LAN7801 only has RGMII mode. */
646 1.52 mrg if (un->un_flags & LAN7801)
647 1.52 mrg MUE_CLRBIT(un, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
648 1.1 rin
649 1.52 mrg if ((un->un_flags & (LAN7500 | LAN7800)) ||
650 1.52 mrg !mue_eeprom_present(un)) {
651 1.1 rin /* Allow MAC to detect speed and duplex from PHY. */
652 1.52 mrg MUE_SETBIT(un, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
653 1.1 rin MUE_MAC_CR_AUTO_DUPLEX);
654 1.1 rin }
655 1.1 rin
656 1.52 mrg MUE_SETBIT(un, MUE_MAC_TX, MUE_MAC_TX_TXEN);
657 1.52 mrg MUE_SETBIT(un, (un->un_flags & LAN7500) ?
658 1.1 rin MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
659 1.1 rin
660 1.52 mrg MUE_SETBIT(un, (un->un_flags & LAN7500) ?
661 1.1 rin MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
662 1.1 rin
663 1.1 rin /* Set default GPIO/LED settings only if no EEPROM is detected. */
664 1.52 mrg if ((un->un_flags & LAN7500) && !mue_eeprom_present(un)) {
665 1.52 mrg MUE_CLRBIT(un, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
666 1.52 mrg MUE_SETBIT(un, MUE_LED_CFG,
667 1.1 rin MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
668 1.1 rin }
669 1.1 rin
670 1.1 rin /* XXX We assume two LEDs at least when EEPROM is missing. */
671 1.52 mrg if (un->un_flags & LAN7800 &&
672 1.52 mrg !mue_eeprom_present(un))
673 1.52 mrg MUE_SETBIT(un, MUE_HW_CFG,
674 1.1 rin MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
675 1.1 rin
676 1.1 rin return 0;
677 1.1 rin }
678 1.1 rin
679 1.1 rin static void
680 1.52 mrg mue_set_macaddr(struct usbnet *un)
681 1.1 rin {
682 1.52 mrg struct ifnet * const ifp = usbnet_ifp(un);
683 1.1 rin const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
684 1.1 rin uint32_t lo, hi;
685 1.1 rin
686 1.1 rin lo = MUE_ENADDR_LO(enaddr);
687 1.1 rin hi = MUE_ENADDR_HI(enaddr);
688 1.1 rin
689 1.52 mrg mue_csr_write(un, MUE_RX_ADDRL, lo);
690 1.52 mrg mue_csr_write(un, MUE_RX_ADDRH, hi);
691 1.1 rin }
692 1.1 rin
693 1.1 rin static int
694 1.52 mrg mue_get_macaddr(struct usbnet *un, prop_dictionary_t dict)
695 1.1 rin {
696 1.1 rin prop_data_t eaprop;
697 1.1 rin uint32_t low, high;
698 1.1 rin
699 1.52 mrg if (!(un->un_flags & LAN7500)) {
700 1.52 mrg low = mue_csr_read(un, MUE_RX_ADDRL);
701 1.52 mrg high = mue_csr_read(un, MUE_RX_ADDRH);
702 1.52 mrg un->un_eaddr[5] = (uint8_t)((high >> 8) & 0xff);
703 1.52 mrg un->un_eaddr[4] = (uint8_t)((high) & 0xff);
704 1.52 mrg un->un_eaddr[3] = (uint8_t)((low >> 24) & 0xff);
705 1.52 mrg un->un_eaddr[2] = (uint8_t)((low >> 16) & 0xff);
706 1.52 mrg un->un_eaddr[1] = (uint8_t)((low >> 8) & 0xff);
707 1.52 mrg un->un_eaddr[0] = (uint8_t)((low) & 0xff);
708 1.52 mrg if (ETHER_IS_VALID(un->un_eaddr))
709 1.1 rin return 0;
710 1.26 rin else
711 1.52 mrg DPRINTF(un, "registers: %s\n",
712 1.52 mrg ether_sprintf(un->un_eaddr));
713 1.1 rin }
714 1.1 rin
715 1.52 mrg if (mue_eeprom_present(un) && !mue_read_eeprom(un, un->un_eaddr,
716 1.1 rin MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
717 1.52 mrg if (ETHER_IS_VALID(un->un_eaddr))
718 1.1 rin return 0;
719 1.26 rin else
720 1.52 mrg DPRINTF(un, "EEPROM: %s\n",
721 1.52 mrg ether_sprintf(un->un_eaddr));
722 1.1 rin }
723 1.1 rin
724 1.52 mrg if (mue_read_otp(un, un->un_eaddr, MUE_OTP_MAC_OFFSET,
725 1.1 rin ETHER_ADDR_LEN) == 0) {
726 1.52 mrg if (ETHER_IS_VALID(un->un_eaddr))
727 1.1 rin return 0;
728 1.26 rin else
729 1.52 mrg DPRINTF(un, "OTP: %s\n",
730 1.52 mrg ether_sprintf(un->un_eaddr));
731 1.1 rin }
732 1.1 rin
733 1.1 rin /*
734 1.1 rin * Other MD methods. This should be tried only if other methods fail.
735 1.1 rin * Otherwise, MAC address for internal device can be assinged to
736 1.1 rin * external devices on Raspberry Pi, for example.
737 1.1 rin */
738 1.1 rin eaprop = prop_dictionary_get(dict, "mac-address");
739 1.1 rin if (eaprop != NULL) {
740 1.1 rin KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
741 1.1 rin KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
742 1.60 jmcneill memcpy(un->un_eaddr, prop_data_value(eaprop),
743 1.1 rin ETHER_ADDR_LEN);
744 1.52 mrg if (ETHER_IS_VALID(un->un_eaddr))
745 1.1 rin return 0;
746 1.26 rin else
747 1.52 mrg DPRINTF(un, "prop_dictionary_get: %s\n",
748 1.52 mrg ether_sprintf(un->un_eaddr));
749 1.1 rin }
750 1.1 rin
751 1.1 rin return 1;
752 1.1 rin }
753 1.1 rin
754 1.1 rin
755 1.1 rin /*
756 1.45 msaitoh * Probe for a Microchip chip.
757 1.45 msaitoh */
758 1.1 rin static int
759 1.1 rin mue_match(device_t parent, cfdata_t match, void *aux)
760 1.1 rin {
761 1.1 rin struct usb_attach_arg *uaa = aux;
762 1.1 rin
763 1.1 rin return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
764 1.1 rin }
765 1.1 rin
766 1.1 rin static void
767 1.1 rin mue_attach(device_t parent, device_t self, void *aux)
768 1.1 rin {
769 1.55 mrg USBNET_MII_DECL_DEFAULT(unm);
770 1.62 nisimura struct usbnet * const un = device_private(self);
771 1.1 rin prop_dictionary_t dict = device_properties(self);
772 1.1 rin struct usb_attach_arg *uaa = aux;
773 1.1 rin struct usbd_device *dev = uaa->uaa_device;
774 1.1 rin usb_interface_descriptor_t *id;
775 1.1 rin usb_endpoint_descriptor_t *ed;
776 1.62 nisimura char *devinfop;
777 1.61 nisimura usbd_status err;
778 1.31 mlelstv const char *descr;
779 1.52 mrg uint32_t id_rev;
780 1.8 rin uint8_t i;
781 1.52 mrg unsigned rx_list_cnt, tx_list_cnt;
782 1.52 mrg unsigned rx_bufsz;
783 1.1 rin
784 1.1 rin aprint_naive("\n");
785 1.1 rin aprint_normal("\n");
786 1.52 mrg devinfop = usbd_devinfo_alloc(dev, 0);
787 1.1 rin aprint_normal_dev(self, "%s\n", devinfop);
788 1.1 rin usbd_devinfo_free(devinfop);
789 1.1 rin
790 1.52 mrg un->un_dev = self;
791 1.52 mrg un->un_udev = dev;
792 1.62 nisimura un->un_sc = un;
793 1.52 mrg un->un_ops = &mue_ops;
794 1.52 mrg un->un_rx_xfer_flags = USBD_SHORT_XFER_OK;
795 1.52 mrg un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER;
796 1.49 mlelstv
797 1.1 rin #define MUE_CONFIG_NO 1
798 1.1 rin err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
799 1.1 rin if (err) {
800 1.1 rin aprint_error_dev(self, "failed to set configuration: %s\n",
801 1.1 rin usbd_errstr(err));
802 1.1 rin return;
803 1.1 rin }
804 1.1 rin
805 1.1 rin #define MUE_IFACE_IDX 0
806 1.52 mrg err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &un->un_iface);
807 1.1 rin if (err) {
808 1.1 rin aprint_error_dev(self, "failed to get interface handle: %s\n",
809 1.1 rin usbd_errstr(err));
810 1.1 rin return;
811 1.1 rin }
812 1.1 rin
813 1.52 mrg un->un_flags = MUE_LOOKUP(uaa)->mue_flags;
814 1.31 mlelstv
815 1.1 rin /* Decide on what our bufsize will be. */
816 1.52 mrg if (un->un_flags & LAN7500) {
817 1.52 mrg rx_bufsz = (un->un_udev->ud_speed == USB_SPEED_HIGH) ?
818 1.3 rin MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
819 1.52 mrg rx_list_cnt = 1;
820 1.52 mrg tx_list_cnt = 1;
821 1.31 mlelstv } else {
822 1.52 mrg rx_bufsz = MUE_7800_RX_BUFSIZE;
823 1.52 mrg rx_list_cnt = MUE_RX_LIST_CNT;
824 1.52 mrg tx_list_cnt = MUE_TX_LIST_CNT;
825 1.31 mlelstv }
826 1.52 mrg
827 1.52 mrg un->un_rx_list_cnt = rx_list_cnt;
828 1.52 mrg un->un_tx_list_cnt = tx_list_cnt;
829 1.52 mrg un->un_rx_bufsz = rx_bufsz;
830 1.52 mrg un->un_tx_bufsz = MUE_TX_BUFSIZE;
831 1.1 rin
832 1.1 rin /* Find endpoints. */
833 1.52 mrg id = usbd_get_interface_descriptor(un->un_iface);
834 1.1 rin for (i = 0; i < id->bNumEndpoints; i++) {
835 1.52 mrg ed = usbd_interface2endpoint_descriptor(un->un_iface, i);
836 1.1 rin if (ed == NULL) {
837 1.8 rin aprint_error_dev(self, "failed to get ep %hhd\n", i);
838 1.1 rin return;
839 1.1 rin }
840 1.1 rin if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
841 1.1 rin UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
842 1.52 mrg un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress;
843 1.1 rin } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
844 1.1 rin UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
845 1.52 mrg un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress;
846 1.1 rin } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
847 1.1 rin UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
848 1.52 mrg un->un_ed[USBNET_ENDPT_INTR] = ed->bEndpointAddress;
849 1.1 rin }
850 1.1 rin }
851 1.52 mrg if (un->un_ed[USBNET_ENDPT_RX] == 0 ||
852 1.52 mrg un->un_ed[USBNET_ENDPT_TX] == 0 ||
853 1.52 mrg un->un_ed[USBNET_ENDPT_INTR] == 0) {
854 1.52 mrg aprint_error_dev(self, "failed to find endpoints\n");
855 1.52 mrg return;
856 1.52 mrg }
857 1.1 rin
858 1.52 mrg /* Set these up now for mue_cmd(). */
859 1.81 riastrad usbnet_attach(un);
860 1.1 rin
861 1.52 mrg un->un_phyno = 1;
862 1.1 rin
863 1.52 mrg if (mue_chip_init(un)) {
864 1.9 rin aprint_error_dev(self, "failed to initialize chip\n");
865 1.1 rin return;
866 1.1 rin }
867 1.1 rin
868 1.1 rin /* A Microchip chip was detected. Inform the world. */
869 1.52 mrg id_rev = mue_csr_read(un, MUE_ID_REV);
870 1.52 mrg descr = (un->un_flags & LAN7500) ? "LAN7500" : "LAN7800";
871 1.58 christos aprint_normal_dev(self, "%s id %#x rev %#x\n", descr,
872 1.52 mrg (unsigned)__SHIFTOUT(id_rev, MUE_ID_REV_ID),
873 1.52 mrg (unsigned)__SHIFTOUT(id_rev, MUE_ID_REV_REV));
874 1.1 rin
875 1.52 mrg if (mue_get_macaddr(un, dict)) {
876 1.21 rin aprint_error_dev(self, "failed to read MAC address\n");
877 1.21 rin return;
878 1.1 rin }
879 1.1 rin
880 1.52 mrg struct ifnet *ifp = usbnet_ifp(un);
881 1.20 rin ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
882 1.44 msaitoh IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
883 1.20 rin IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
884 1.20 rin IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
885 1.20 rin IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
886 1.20 rin IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
887 1.3 rin
888 1.52 mrg struct ethercom *ec = usbnet_ec(un);
889 1.52 mrg ec->ec_capabilities = ETHERCAP_VLAN_MTU;
890 1.22 rin #if 0 /* XXX not yet */
891 1.52 mrg ec->ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
892 1.22 rin #endif
893 1.1 rin
894 1.54 mrg usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST,
895 1.54 mrg 0, &unm);
896 1.1 rin }
897 1.1 rin
898 1.52 mrg static unsigned
899 1.59 thorpej mue_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c)
900 1.1 rin {
901 1.52 mrg struct ifnet * const ifp = usbnet_ifp(un);
902 1.1 rin struct mue_txbuf_hdr hdr;
903 1.12 rin uint32_t tx_cmd_a, tx_cmd_b;
904 1.37 rin int csum, len, rv;
905 1.20 rin bool tso, ipe, tpe;
906 1.12 rin
907 1.52 mrg if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(hdr))
908 1.52 mrg return 0;
909 1.52 mrg
910 1.20 rin csum = m->m_pkthdr.csum_flags;
911 1.20 rin tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
912 1.20 rin ipe = csum & M_CSUM_IPv4;
913 1.20 rin tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
914 1.20 rin M_CSUM_TCPv6 | M_CSUM_UDPv6);
915 1.12 rin
916 1.12 rin len = m->m_pkthdr.len;
917 1.41 rin if (__predict_false((!tso && len > (int)MUE_FRAME_LEN(ifp->if_mtu)) ||
918 1.22 rin ( tso && len > MUE_TSO_FRAME_LEN))) {
919 1.52 mrg MUE_PRINTF(un, "packet length %d\n too long", len);
920 1.52 mrg return 0;
921 1.12 rin }
922 1.1 rin
923 1.12 rin KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
924 1.12 rin tx_cmd_a = len | MUE_TX_CMD_A_FCS;
925 1.3 rin
926 1.12 rin if (tso) {
927 1.12 rin tx_cmd_a |= MUE_TX_CMD_A_LSO;
928 1.3 rin if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
929 1.12 rin tx_cmd_b = m->m_pkthdr.segsz;
930 1.3 rin else
931 1.12 rin tx_cmd_b = MUE_TX_MSS_MIN;
932 1.12 rin tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
933 1.12 rin KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
934 1.52 mrg rv = mue_prepare_tso(un, m);
935 1.37 rin if (__predict_false(rv))
936 1.52 mrg return 0;
937 1.20 rin } else {
938 1.20 rin if (ipe)
939 1.20 rin tx_cmd_a |= MUE_TX_CMD_A_IPE;
940 1.20 rin if (tpe)
941 1.20 rin tx_cmd_a |= MUE_TX_CMD_A_TPE;
942 1.12 rin tx_cmd_b = 0;
943 1.20 rin }
944 1.12 rin
945 1.12 rin hdr.tx_cmd_a = htole32(tx_cmd_a);
946 1.12 rin hdr.tx_cmd_b = htole32(tx_cmd_b);
947 1.3 rin
948 1.52 mrg memcpy(c->unc_buf, &hdr, sizeof(hdr));
949 1.52 mrg m_copydata(m, 0, len, c->unc_buf + sizeof(hdr));
950 1.32 rin
951 1.52 mrg return len + sizeof(hdr);
952 1.1 rin }
953 1.1 rin
954 1.37 rin /*
955 1.37 rin * L3 length field should be cleared.
956 1.37 rin */
957 1.37 rin static int
958 1.52 mrg mue_prepare_tso(struct usbnet *un, struct mbuf *m)
959 1.3 rin {
960 1.3 rin struct ether_header *eh;
961 1.3 rin struct ip *ip;
962 1.3 rin struct ip6_hdr *ip6;
963 1.37 rin uint16_t type, len = 0;
964 1.18 rin int off;
965 1.3 rin
966 1.41 rin if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
967 1.37 rin eh = mtod(m, struct ether_header *);
968 1.37 rin type = eh->ether_type;
969 1.37 rin } else
970 1.37 rin m_copydata(m, offsetof(struct ether_header, ether_type),
971 1.37 rin sizeof(type), &type);
972 1.37 rin switch (type = htons(type)) {
973 1.3 rin case ETHERTYPE_IP:
974 1.3 rin case ETHERTYPE_IPV6:
975 1.18 rin off = ETHER_HDR_LEN;
976 1.3 rin break;
977 1.3 rin case ETHERTYPE_VLAN:
978 1.18 rin off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
979 1.3 rin break;
980 1.3 rin default:
981 1.37 rin return EINVAL;
982 1.3 rin }
983 1.3 rin
984 1.13 rin if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
985 1.41 rin if (__predict_true(m->m_len >= off + (int)sizeof(*ip))) {
986 1.37 rin ip = (void *)(mtod(m, char *) + off);
987 1.37 rin ip->ip_len = 0;
988 1.37 rin } else
989 1.37 rin m_copyback(m, off + offsetof(struct ip, ip_len),
990 1.37 rin sizeof(len), &len);
991 1.3 rin } else {
992 1.41 rin if (__predict_true(m->m_len >= off + (int)sizeof(*ip6))) {
993 1.37 rin ip6 = (void *)(mtod(m, char *) + off);
994 1.37 rin ip6->ip6_plen = 0;
995 1.37 rin } else
996 1.37 rin m_copyback(m, off + offsetof(struct ip6_hdr, ip6_plen),
997 1.37 rin sizeof(len), &len);
998 1.3 rin }
999 1.37 rin return 0;
1000 1.3 rin }
1001 1.3 rin
1002 1.3 rin static void
1003 1.72 riastrad mue_uno_mcast(struct ifnet *ifp)
1004 1.1 rin {
1005 1.72 riastrad struct usbnet *un = ifp->if_softc;
1006 1.52 mrg struct ethercom *ec = usbnet_ec(un);
1007 1.62 nisimura const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1008 1.62 nisimura struct ether_multi *enm;
1009 1.61 nisimura struct ether_multistep step;
1010 1.62 nisimura uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1011 1.62 nisimura uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1012 1.62 nisimura uint32_t reg, rxfilt, h, hireg, loreg;
1013 1.8 rin size_t i;
1014 1.1 rin
1015 1.52 mrg if (usbnet_isdying(un))
1016 1.1 rin return;
1017 1.1 rin
1018 1.62 nisimura /* Clear perfect filter and hash tables. */
1019 1.62 nisimura memset(pfiltbl, 0, sizeof(pfiltbl));
1020 1.62 nisimura memset(hashtbl, 0, sizeof(hashtbl));
1021 1.1 rin
1022 1.62 nisimura reg = (un->un_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1023 1.62 nisimura rxfilt = mue_csr_read(un, reg);
1024 1.62 nisimura rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1025 1.1 rin MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1026 1.1 rin
1027 1.62 nisimura /* Always accept broadcast frames. */
1028 1.62 nisimura rxfilt |= MUE_RFE_CTL_BROADCAST;
1029 1.62 nisimura
1030 1.73 riastrad ETHER_LOCK(ec);
1031 1.25 rin if (ifp->if_flags & IFF_PROMISC) {
1032 1.62 nisimura rxfilt |= MUE_RFE_CTL_UNICAST;
1033 1.62 nisimura allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1034 1.73 riastrad ec->ec_flags |= ETHER_F_ALLMULTI;
1035 1.62 nisimura if (ifp->if_flags & IFF_PROMISC)
1036 1.62 nisimura DPRINTF(un, "promisc\n");
1037 1.62 nisimura else
1038 1.62 nisimura DPRINTF(un, "allmulti\n");
1039 1.62 nisimura } else {
1040 1.62 nisimura /* Now program new ones. */
1041 1.62 nisimura pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1042 1.62 nisimura pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1043 1.62 nisimura i = 1;
1044 1.62 nisimura ETHER_FIRST_MULTI(step, ec, enm);
1045 1.62 nisimura while (enm != NULL) {
1046 1.62 nisimura if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1047 1.62 nisimura ETHER_ADDR_LEN)) {
1048 1.62 nisimura memset(pfiltbl, 0, sizeof(pfiltbl));
1049 1.62 nisimura memset(hashtbl, 0, sizeof(hashtbl));
1050 1.62 nisimura rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1051 1.62 nisimura goto allmulti;
1052 1.62 nisimura }
1053 1.62 nisimura if (i < MUE_NUM_ADDR_FILTX) {
1054 1.62 nisimura /* Use perfect address table if possible. */
1055 1.62 nisimura pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1056 1.62 nisimura MUE_ADDR_FILTX_VALID;
1057 1.62 nisimura pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1058 1.62 nisimura } else {
1059 1.62 nisimura /* Otherwise, use hash table. */
1060 1.62 nisimura rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1061 1.62 nisimura h = (ether_crc32_be(enm->enm_addrlo,
1062 1.62 nisimura ETHER_ADDR_LEN) >> 23) & 0x1ff;
1063 1.62 nisimura hashtbl[h / 32] |= 1 << (h % 32);
1064 1.61 nisimura }
1065 1.62 nisimura i++;
1066 1.62 nisimura ETHER_NEXT_MULTI(step, enm);
1067 1.61 nisimura }
1068 1.73 riastrad ec->ec_flags &= ~ETHER_F_ALLMULTI;
1069 1.62 nisimura rxfilt |= MUE_RFE_CTL_PERFECT;
1070 1.62 nisimura if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH)
1071 1.62 nisimura DPRINTF(un, "perfect filter and hash tables\n");
1072 1.62 nisimura else
1073 1.62 nisimura DPRINTF(un, "perfect filter\n");
1074 1.62 nisimura }
1075 1.73 riastrad ETHER_UNLOCK(ec);
1076 1.62 nisimura
1077 1.62 nisimura for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1078 1.62 nisimura hireg = (un->un_flags & LAN7500) ?
1079 1.62 nisimura MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1080 1.62 nisimura loreg = hireg + 4;
1081 1.62 nisimura mue_csr_write(un, hireg, 0);
1082 1.62 nisimura mue_csr_write(un, loreg, pfiltbl[i][1]);
1083 1.62 nisimura mue_csr_write(un, hireg, pfiltbl[i][0]);
1084 1.1 rin }
1085 1.62 nisimura
1086 1.52 mrg mue_dataport_write(un, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1087 1.62 nisimura MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1088 1.62 nisimura
1089 1.62 nisimura mue_csr_write(un, reg, rxfilt);
1090 1.1 rin }
1091 1.1 rin
1092 1.1 rin static void
1093 1.59 thorpej mue_sethwcsum_locked(struct usbnet *un)
1094 1.1 rin {
1095 1.52 mrg struct ifnet * const ifp = usbnet_ifp(un);
1096 1.1 rin uint32_t reg, val;
1097 1.1 rin
1098 1.75 riastrad KASSERT(IFNET_LOCKED(ifp));
1099 1.75 riastrad
1100 1.52 mrg reg = (un->un_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1101 1.52 mrg val = mue_csr_read(un, reg);
1102 1.1 rin
1103 1.29 rin if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) {
1104 1.52 mrg DPRINTF(un, "RX IPv4 hwcsum enabled\n");
1105 1.29 rin val |= MUE_RFE_CTL_IP_COE;
1106 1.1 rin } else {
1107 1.52 mrg DPRINTF(un, "RX IPv4 hwcsum disabled\n");
1108 1.29 rin val &= ~MUE_RFE_CTL_IP_COE;
1109 1.29 rin }
1110 1.29 rin
1111 1.29 rin if (ifp->if_capenable &
1112 1.29 rin (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
1113 1.29 rin IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) {
1114 1.52 mrg DPRINTF(un, "RX L4 hwcsum enabled\n");
1115 1.29 rin val |= MUE_RFE_CTL_TCPUDP_COE;
1116 1.29 rin } else {
1117 1.52 mrg DPRINTF(un, "RX L4 hwcsum disabled\n");
1118 1.29 rin val &= ~MUE_RFE_CTL_TCPUDP_COE;
1119 1.29 rin }
1120 1.1 rin
1121 1.1 rin val &= ~MUE_RFE_CTL_VLAN_FILTER;
1122 1.1 rin
1123 1.52 mrg mue_csr_write(un, reg, val);
1124 1.1 rin }
1125 1.1 rin
1126 1.22 rin static void
1127 1.59 thorpej mue_setmtu_locked(struct usbnet *un)
1128 1.22 rin {
1129 1.52 mrg struct ifnet * const ifp = usbnet_ifp(un);
1130 1.22 rin uint32_t val;
1131 1.22 rin
1132 1.75 riastrad KASSERT(IFNET_LOCKED(ifp));
1133 1.75 riastrad
1134 1.22 rin /* Set the maximum frame size. */
1135 1.52 mrg MUE_CLRBIT(un, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1136 1.52 mrg val = mue_csr_read(un, MUE_MAC_RX);
1137 1.22 rin val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1138 1.22 rin val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1139 1.52 mrg mue_csr_write(un, MUE_MAC_RX, val);
1140 1.52 mrg MUE_SETBIT(un, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1141 1.22 rin }
1142 1.1 rin
1143 1.1 rin static void
1144 1.59 thorpej mue_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len)
1145 1.1 rin {
1146 1.52 mrg struct ifnet * const ifp = usbnet_ifp(un);
1147 1.1 rin struct mue_rxbuf_hdr *hdrp;
1148 1.52 mrg uint32_t rx_cmd_a;
1149 1.1 rin uint16_t pktlen;
1150 1.20 rin int csum;
1151 1.52 mrg uint8_t *buf = c->unc_buf;
1152 1.20 rin bool v6;
1153 1.1 rin
1154 1.52 mrg KASSERTMSG(total_len <= un->un_rx_bufsz, "%u vs %u",
1155 1.52 mrg total_len, un->un_rx_bufsz);
1156 1.1 rin
1157 1.1 rin do {
1158 1.52 mrg if (__predict_false(total_len < sizeof(*hdrp))) {
1159 1.52 mrg MUE_PRINTF(un, "packet length %u too short\n", total_len);
1160 1.57 thorpej if_statinc(ifp, if_ierrors);
1161 1.52 mrg return;
1162 1.1 rin }
1163 1.1 rin
1164 1.1 rin hdrp = (struct mue_rxbuf_hdr *)buf;
1165 1.1 rin rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1166 1.1 rin
1167 1.20 rin if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1168 1.20 rin /*
1169 1.20 rin * We cannot use MUE_RX_CMD_A_RED bit here;
1170 1.20 rin * it is turned on in the cases of L3/L4
1171 1.20 rin * checksum errors which we handle below.
1172 1.20 rin */
1173 1.58 christos MUE_PRINTF(un, "rx_cmd_a: %#x\n", rx_cmd_a);
1174 1.57 thorpej if_statinc(ifp, if_ierrors);
1175 1.52 mrg return;
1176 1.1 rin }
1177 1.1 rin
1178 1.1 rin pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1179 1.52 mrg if (un->un_flags & LAN7500)
1180 1.1 rin pktlen -= 2;
1181 1.1 rin
1182 1.10 rin if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1183 1.22 rin pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1184 1.52 mrg pktlen + sizeof(*hdrp) > total_len)) {
1185 1.52 mrg MUE_PRINTF(un, "invalid packet length %d\n", pktlen);
1186 1.57 thorpej if_statinc(ifp, if_ierrors);
1187 1.52 mrg return;
1188 1.1 rin }
1189 1.1 rin
1190 1.20 rin if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1191 1.20 rin csum = 0;
1192 1.20 rin } else {
1193 1.20 rin v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1194 1.20 rin switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1195 1.20 rin case MUE_RX_CMD_A_PID_TCP:
1196 1.20 rin csum = v6 ?
1197 1.20 rin M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1198 1.20 rin break;
1199 1.20 rin case MUE_RX_CMD_A_PID_UDP:
1200 1.20 rin csum = v6 ?
1201 1.20 rin M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1202 1.20 rin break;
1203 1.20 rin case MUE_RX_CMD_A_PID_IP:
1204 1.20 rin csum = v6 ? 0 : M_CSUM_IPv4;
1205 1.20 rin break;
1206 1.20 rin default:
1207 1.20 rin csum = 0;
1208 1.20 rin break;
1209 1.20 rin }
1210 1.20 rin csum &= ifp->if_csum_flags_rx;
1211 1.20 rin if (__predict_false((csum & M_CSUM_IPv4) &&
1212 1.20 rin (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1213 1.20 rin csum |= M_CSUM_IPv4_BAD;
1214 1.20 rin if (__predict_false((csum & ~M_CSUM_IPv4) &&
1215 1.20 rin (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1216 1.20 rin csum |= M_CSUM_TCP_UDP_BAD;
1217 1.20 rin }
1218 1.52 mrg
1219 1.52 mrg usbnet_enqueue(un, buf + sizeof(*hdrp), pktlen, csum,
1220 1.52 mrg 0, M_HASFCS);
1221 1.1 rin
1222 1.1 rin /* Attention: sizeof(hdr) = 10 */
1223 1.1 rin pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1224 1.52 mrg if (pktlen > total_len)
1225 1.52 mrg pktlen = total_len;
1226 1.52 mrg total_len -= pktlen;
1227 1.1 rin buf += pktlen;
1228 1.52 mrg } while (total_len > 0);
1229 1.1 rin }
1230 1.1 rin
1231 1.1 rin static int
1232 1.70 riastrad mue_uno_init(struct ifnet *ifp)
1233 1.1 rin {
1234 1.52 mrg struct usbnet * const un = ifp->if_softc;
1235 1.1 rin
1236 1.52 mrg mue_reset(un);
1237 1.1 rin
1238 1.1 rin /* Set MAC address. */
1239 1.52 mrg mue_set_macaddr(un);
1240 1.1 rin
1241 1.1 rin /* TCP/UDP checksum offload engines. */
1242 1.59 thorpej mue_sethwcsum_locked(un);
1243 1.1 rin
1244 1.22 rin /* Set MTU. */
1245 1.59 thorpej mue_setmtu_locked(un);
1246 1.22 rin
1247 1.80 riastrad return 0;
1248 1.52 mrg }
1249 1.1 rin
1250 1.52 mrg static int
1251 1.62 nisimura mue_uno_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1252 1.1 rin {
1253 1.52 mrg struct usbnet * const un = ifp->if_softc;
1254 1.1 rin
1255 1.22 rin switch (cmd) {
1256 1.52 mrg case SIOCSIFCAP:
1257 1.59 thorpej mue_sethwcsum_locked(un);
1258 1.52 mrg break;
1259 1.52 mrg case SIOCSIFMTU:
1260 1.59 thorpej mue_setmtu_locked(un);
1261 1.1 rin break;
1262 1.1 rin default:
1263 1.1 rin break;
1264 1.1 rin }
1265 1.1 rin
1266 1.52 mrg return 0;
1267 1.1 rin }
1268 1.1 rin
1269 1.1 rin static void
1270 1.52 mrg mue_reset(struct usbnet *un)
1271 1.1 rin {
1272 1.52 mrg if (usbnet_isdying(un))
1273 1.1 rin return;
1274 1.1 rin
1275 1.1 rin /* Wait a little while for the chip to get its brains in order. */
1276 1.52 mrg usbd_delay_ms(un->un_udev, 1);
1277 1.1 rin
1278 1.52 mrg // mue_chip_init(un); /* XXX */
1279 1.1 rin }
1280 1.1 rin
1281 1.1 rin static void
1282 1.59 thorpej mue_uno_stop(struct ifnet *ifp, int disable)
1283 1.1 rin {
1284 1.52 mrg struct usbnet * const un = ifp->if_softc;
1285 1.27 mlelstv
1286 1.52 mrg mue_reset(un);
1287 1.1 rin }
1288 1.1 rin
1289 1.52 mrg #ifdef _MODULE
1290 1.52 mrg #include "ioconf.c"
1291 1.52 mrg #endif
1292 1.1 rin
1293 1.52 mrg USBNET_MODULE(mue)
1294