if_mue.c revision 1.1 1 /* $NetBSD: if_mue.c,v 1.1 2018/08/25 20:12:22 rin Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.1 2018/08/25 20:12:22 rin Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/cprng.h>
32 #include <sys/bus.h>
33 #include <sys/systm.h>
34 #include <sys/sockio.h>
35 #include <sys/mbuf.h>
36 #include <sys/mutex.h>
37 #include <sys/kernel.h>
38 #include <sys/proc.h>
39 #include <sys/socket.h>
40
41 #include <sys/device.h>
42
43 #include <sys/rndsource.h>
44
45 #include <net/if.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
48 #include <net/if_ether.h>
49
50 #include <net/bpf.h>
51
52 #include <netinet/in.h>
53 #include <netinet/if_inarp.h>
54
55 #include <dev/mii/mii.h>
56 #include <dev/mii/miivar.h>
57
58 #include <dev/usb/usb.h>
59 #include <dev/usb/usbdi.h>
60 #include <dev/usb/usbdi_util.h>
61 #include <dev/usb/usbdivar.h>
62 #include <dev/usb/usbdevs.h>
63
64 #include <dev/usb/if_muereg.h>
65 #include <dev/usb/if_muevar.h>
66
67 #define MUE_PRINTF(sc, fmt, args...) \
68 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
69
70 #ifdef USB_DEBUG
71 int muedebug = 0;
72 #define DPRINTF(sc, fmt, args...) \
73 do { \
74 if (muedebug) \
75 MUE_PRINTF(sc, fmt, ##args); \
76 } while (0 /* CONSTCOND */)
77 #else
78 #define DPRINTF(sc, fmt, args...) /* nothing */
79 #endif
80
81 /*
82 * Various supported device vendors/products.
83 */
84 struct mue_type {
85 struct usb_devno mue_dev;
86 uint16_t mue_flags;
87 #define LAN7500 0x0001 /* LAN7500 */
88 };
89
90 const struct mue_type mue_devs[] = {
91 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
96 };
97
98 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
99 uaa->uaa_vendor, uaa->uaa_product))
100
101 #define MUE_ENADDR_LO(enaddr) \
102 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
103 #define MUE_ENADDR_HI(enaddr) \
104 ((enaddr[5] << 8) | enaddr[4])
105
106 static int mue_match(device_t, cfdata_t, void *);
107 static void mue_attach(device_t, device_t, void *);
108 static int mue_detach(device_t, int);
109 static int mue_activate(device_t, enum devact);
110
111 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
112 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
113 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
114 uint32_t, uint32_t);
115
116 static void mue_lock_mii(struct mue_softc *);
117 static void mue_unlock_mii(struct mue_softc *);
118
119 static int mue_miibus_readreg(device_t, int, int);
120 static void mue_miibus_writereg(device_t, int, int, int);
121 static void mue_miibus_statchg(struct ifnet *);
122 static int mue_ifmedia_upd(struct ifnet *);
123 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
124
125 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
126 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
127 static bool mue_eeprom_present(struct mue_softc *sc);
128
129 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
130 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
131
132 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
133 uint32_t, uint32_t *);
134
135 static void mue_init_ltm(struct mue_softc *);
136
137 static int mue_chip_init(struct mue_softc *);
138
139 static void mue_set_macaddr(struct mue_softc *);
140 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
141
142 static int mue_rx_list_init(struct mue_softc *);
143 static int mue_tx_list_init(struct mue_softc *);
144 static int mue_open_pipes(struct mue_softc *);
145 static void mue_start_rx(struct mue_softc *);
146
147 static int mue_encap(struct mue_softc *, struct mbuf *, int);
148
149 static void mue_setmulti(struct mue_softc *);
150 static void mue_sethwcsum(struct mue_softc *);
151
152 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
153 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
154
155 static int mue_init(struct ifnet *);
156 static int mue_ioctl(struct ifnet *, u_long, void *);
157 static void mue_watchdog(struct ifnet *);
158 static void mue_reset(struct mue_softc *);
159 static void mue_start(struct ifnet *);
160 static void mue_stop(struct ifnet *, int);
161 static void mue_tick(void *);
162 static void mue_tick_task(void *);
163
164 static struct mbuf *mue_newbuf(void);
165
166 #define MUE_SETBIT(sc, reg, x) \
167 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
168
169 #define MUE_CLRBIT(sc, reg, x) \
170 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
171
172 #define MUE_WAIT_SET(sc, reg, set, fail) \
173 mue_wait_for_bits(sc, reg, set, ~0, fail)
174
175 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
176 mue_wait_for_bits(sc, reg, 0, clear, fail)
177
178 #define ETHER_IS_VALID(addr) \
179 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
180
181 #define ETHER_IS_ZERO(addr) \
182 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
183
184 #define ETHER_ALIGN 2
185
186 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
187 mue_detach, mue_activate);
188
189 static uint32_t
190 mue_csr_read(struct mue_softc *sc, uint32_t reg)
191 {
192 usb_device_request_t req;
193 usbd_status err;
194 uDWord val;
195
196 if (sc->mue_dying)
197 return 0;
198
199 USETDW(val, 0);
200 req.bmRequestType = UT_READ_VENDOR_DEVICE;
201 req.bRequest = MUE_UR_READREG;
202 USETW(req.wValue, 0);
203 USETW(req.wIndex, reg);
204 USETW(req.wLength, 4);
205
206 err = usbd_do_request(sc->mue_udev, &req, &val);
207 if (err) {
208 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
209 return 0;
210 }
211
212 return UGETDW(val);
213 }
214
215 static int
216 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
217 {
218 usb_device_request_t req;
219 usbd_status err;
220 uDWord val;
221
222 if (sc->mue_dying)
223 return 0;
224
225 USETDW(val, aval);
226 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
227 req.bRequest = MUE_UR_WRITEREG;
228 USETW(req.wValue, 0);
229 USETW(req.wIndex, reg);
230 USETW(req.wLength, 4);
231
232 err = usbd_do_request(sc->mue_udev, &req, &val);
233 if (err) {
234 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
235 return -1;
236 }
237
238 return 0;
239 }
240
241 static int
242 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
243 uint32_t set, uint32_t clear, uint32_t fail)
244 {
245 uint32_t val;
246 int ntries;
247
248 for (ntries = 0; ntries < 1000; ntries++) {
249 val = mue_csr_read(sc, reg);
250 if ((val & set) || !(val & clear))
251 return 0;
252 if (val & fail)
253 return 1;
254 usbd_delay_ms(sc->mue_udev, 1);
255 }
256
257 return 1;
258 }
259
260 /*
261 * Get exclusive access to the MII registers.
262 */
263 static void
264 mue_lock_mii(struct mue_softc *sc)
265 {
266 sc->mue_refcnt++;
267 mutex_enter(&sc->mue_mii_lock);
268 }
269
270 static void
271 mue_unlock_mii(struct mue_softc *sc)
272 {
273 mutex_exit(&sc->mue_mii_lock);
274 if (--sc->mue_refcnt < 0)
275 usb_detach_wakeupold(sc->mue_dev);
276 }
277
278 static int
279 mue_miibus_readreg(device_t dev, int phy, int reg)
280 {
281 struct mue_softc *sc = device_private(dev);
282 uint32_t val;
283
284 if (sc->mue_dying) {
285 DPRINTF(sc, "dying\n");
286 return 0;
287 }
288
289 if (sc->mue_phyno != phy)
290 return 0;
291
292 mue_lock_mii(sc);
293 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
294 mue_unlock_mii(sc);
295 MUE_PRINTF(sc, "not ready\n");
296 return -1;
297 }
298
299 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
300 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
301 MUE_MII_ACCESS_PHYADDR(phy));
302
303 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
304 mue_unlock_mii(sc);
305 MUE_PRINTF(sc, "timed out\n");
306 return -1;
307 }
308
309 val = mue_csr_read(sc, MUE_MII_DATA);
310 mue_unlock_mii(sc);
311 return val & 0xffff;
312 }
313
314 static void
315 mue_miibus_writereg(device_t dev, int phy, int reg, int data)
316 {
317 struct mue_softc *sc = device_private(dev);
318
319 if (sc->mue_dying) {
320 DPRINTF(sc, "dying\n");
321 return;
322 }
323
324 if (sc->mue_phyno != phy) {
325 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
326 sc->mue_phyno, phy);
327 return;
328 }
329
330 mue_lock_mii(sc);
331 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
332 mue_unlock_mii(sc);
333 MUE_PRINTF(sc, "not ready\n");
334 return;
335 }
336
337 mue_csr_write(sc, MUE_MII_DATA, data);
338 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
339 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
340 MUE_MII_ACCESS_PHYADDR(phy));
341
342 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0))
343 MUE_PRINTF(sc, "timed out\n");
344
345 mue_unlock_mii(sc);
346 }
347
348 static void
349 mue_miibus_statchg(struct ifnet *ifp)
350 {
351 struct mue_softc *sc = ifp->if_softc;
352 struct mii_data *mii = GET_MII(sc);
353 uint32_t flow, threshold;
354
355 if (mii == NULL || ifp == NULL || (ifp->if_flags & IFF_RUNNING) == 0) {
356 DPRINTF(sc, "not ready\n");
357 return;
358 }
359
360 sc->mue_link = 0;
361 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
362 (IFM_ACTIVE | IFM_AVALID)) {
363 switch (IFM_SUBTYPE(mii->mii_media_active)) {
364 case IFM_10_T:
365 case IFM_100_TX:
366 case IFM_1000_T:
367 sc->mue_link++;
368 break;
369 default:
370 break;
371 }
372 }
373
374 /* Lost link, do nothing. */
375 if (sc->mue_link == 0) {
376 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
377 return;
378 }
379
380 if (!(sc->mue_flags & LAN7500)) {
381 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
382 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
383 /* Disable U2 and enable U1. */
384 MUE_CLRBIT(sc, MUE_USB_CFG1,
385 MUE_USB_CFG1_DEV_U2_INIT_EN);
386 MUE_SETBIT(sc, MUE_USB_CFG1,
387 MUE_USB_CFG1_DEV_U1_INIT_EN);
388 } else {
389 /* Enable U1 and U2. */
390 MUE_SETBIT(sc, MUE_USB_CFG1,
391 MUE_USB_CFG1_DEV_U1_INIT_EN |
392 MUE_USB_CFG1_DEV_U2_INIT_EN);
393 }
394 }
395 }
396
397 flow = 0;
398 /* XXX Linux does not check IFM_FDX flag for 7800. */
399 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
400 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
401 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
402 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
403 flow |= MUE_FLOW_RX_FCEN;
404 }
405
406 /* XXX Magic numbers taken from Linux driver. */
407 if (sc->mue_flags & LAN7500)
408 threshold = 0x820;
409 else
410 switch (sc->mue_udev->ud_speed) {
411 case USB_SPEED_SUPER:
412 threshold = 0x817;
413 break;
414 case USB_SPEED_HIGH:
415 threshold = 0x211;
416 break;
417 default:
418 threshold = 0;
419 break;
420 }
421
422 /* Threshold value should be set before enabling flow. */
423 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
424 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
425 mue_csr_write(sc, MUE_FLOW, flow);
426
427 DPRINTF(sc, "done\n");
428 }
429
430 /*
431 * Set media options.
432 */
433 static int
434 mue_ifmedia_upd(struct ifnet *ifp)
435 {
436 struct mue_softc *sc = ifp->if_softc;
437 struct mii_data *mii = GET_MII(sc);
438
439 sc->mue_link = 0; /* XXX */
440
441 if (mii->mii_instance) {
442 struct mii_softc *miisc;
443 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
444 mii_phy_reset(miisc);
445 }
446 return mii_mediachg(mii);
447 }
448
449 /*
450 * Report current media status.
451 */
452 static void
453 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
454 {
455 struct mue_softc *sc = ifp->if_softc;
456 struct mii_data *mii = GET_MII(sc);
457
458 mii_pollstat(mii);
459 ifmr->ifm_active = mii->mii_media_active;
460 ifmr->ifm_status = mii->mii_media_status;
461 }
462
463 static uint8_t
464 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
465 {
466 uint32_t val;
467
468 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
469 MUE_PRINTF(sc, "not ready\n");
470 return ETIMEDOUT;
471 }
472
473 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
474 (off & MUE_E2P_CMD_ADDR_MASK));
475
476 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
477 MUE_E2P_CMD_TIMEOUT)) {
478 MUE_PRINTF(sc, "timed out\n");
479 return ETIMEDOUT;
480 }
481
482 val = mue_csr_read(sc, MUE_E2P_DATA);
483 *dest = val & 0xff;
484
485 return 0;
486 }
487
488 static int
489 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
490 {
491 uint32_t val = 0; /* XXX gcc */
492 uint8_t byte;
493 int i, err;
494
495 /*
496 * EEPROM pins are muxed with the LED function on LAN7800 device.
497 */
498 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
499 val = mue_csr_read(sc, MUE_HW_CFG);
500 mue_csr_write(sc, MUE_HW_CFG,
501 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
502 }
503
504 for (i = 0; i < cnt; i++) {
505 err = mue_eeprom_getbyte(sc, off + i, &byte);
506 if (err)
507 break;
508 *(dest + i) = byte;
509 }
510
511 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
512 mue_csr_write(sc, MUE_HW_CFG, val);
513
514 return err ? 1 : 0;
515 }
516
517 static bool
518 mue_eeprom_present(struct mue_softc *sc)
519 {
520 uint32_t val;
521 uint8_t sig;
522 int ret;
523
524 if (sc->mue_flags & LAN7500) {
525 val = mue_csr_read(sc, MUE_E2P_CMD);
526 return val & MUE_E2P_CMD_LOADED;
527 } else {
528 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
529 return (ret == 0) && (sig == MUE_E2P_IND);
530 }
531 }
532
533 static int
534 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
535 {
536 uint32_t val;
537 int i, err;
538
539 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
540
541 /* Checking if bit is set. */
542 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
543 /* Clear it, then wait for it to be cleared. */
544 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
545 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
546 0);
547 if (err) {
548 MUE_PRINTF(sc, "not ready\n");
549 return 1;
550 }
551 }
552
553 /* Start reading the bytes, one at a time. */
554 for (i = 0; i < cnt; i++) {
555 mue_csr_write(sc, MUE_OTP_ADDR1,
556 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
557 mue_csr_write(sc, MUE_OTP_ADDR2,
558 ((off + i) & MUE_OTP_ADDR2_MASK));
559 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
560 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
561
562 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
563 if (err) {
564 MUE_PRINTF(sc, "timed out\n");
565 return 1;
566 }
567 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
568 *(dest + i) = (uint8_t)(val & 0xff);
569 }
570
571 return 0;
572 }
573
574 static int
575 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
576 {
577 uint8_t sig;
578 int err;
579
580 if (sc->mue_flags & LAN7500)
581 return 1;
582
583 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
584 if (err)
585 return 1;
586 switch (sig) {
587 case MUE_OTP_IND_1:
588 break;
589 case MUE_OTP_IND_2:
590 off += 0x100;
591 break;
592 default:
593 DPRINTF(sc, "OTP not found\n");
594 return 1;
595 }
596 err = mue_read_otp_raw(sc, dest, off, cnt);
597 return err;
598 }
599
600 static void
601 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
602 uint32_t cnt, uint32_t *data)
603 {
604 uint32_t i;
605
606 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
607 MUE_PRINTF(sc, "not ready\n");
608 return;
609 }
610
611 mue_csr_write(sc, MUE_DP_SEL,
612 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
613
614 for (i = 0; i < cnt; i++) {
615 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
616 mue_csr_write(sc, MUE_DP_DATA, data[i]);
617 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
618 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
619 MUE_PRINTF(sc, "timed out\n");
620 return;
621 }
622 }
623 }
624
625 static void
626 mue_init_ltm(struct mue_softc *sc)
627 {
628 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
629 uint8_t temp[2];
630 size_t i;
631
632 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
633 if (mue_eeprom_present(sc) &&
634 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
635 if (temp[0] != sizeof(idx)) {
636 DPRINTF(sc, "EEPROM: unexpected size\n");
637 goto done;
638 }
639 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
640 sizeof(idx))) {
641 DPRINTF(sc, "EEPROM read failed\n");
642 goto done;
643 }
644 DPRINTF(sc, "success\n");
645 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
646 if (temp[0] != sizeof(idx)) {
647 DPRINTF(sc, "OTP: unexpected size\n");
648 goto done;
649 }
650 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
651 sizeof(idx))) {
652 DPRINTF(sc, "OTP read failed\n");
653 goto done;
654 }
655 DPRINTF(sc, "success\n");
656 } else {
657 DPRINTF(sc, "nothing to do\n");
658 }
659 } else {
660 DPRINTF(sc, "nothing to do\n");
661 }
662 done:
663 for (i = 0; i < __arraycount(idx); i++)
664 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
665 }
666
667 static int
668 mue_chip_init(struct mue_softc *sc)
669 {
670 uint32_t val;
671
672 if ((sc->mue_flags & LAN7500) &&
673 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
674 MUE_PRINTF(sc, "not ready\n");
675 return ETIMEDOUT;
676 }
677
678 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
679 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
680 MUE_PRINTF(sc, "timed out\n");
681 return ETIMEDOUT;
682 }
683
684 /* Respond to the IN token with a NAK. */
685 if (sc->mue_flags & LAN7500)
686 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
687 else
688 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
689
690 if (sc->mue_flags & LAN7500) {
691 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
692 val = MUE_7500_HS_BUFSIZE /
693 MUE_HS_USB_PKT_SIZE;
694 else
695 val = MUE_7500_FS_BUFSIZE /
696 MUE_FS_USB_PKT_SIZE;
697 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
698 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
699 MUE_7500_DEFAULT_BULKIN_DELAY);
700
701 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
702
703 /* Set FIFO sizes. */
704 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
705 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
706 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
707 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
708 } else {
709 /* Init LTM. */
710 mue_init_ltm(sc);
711
712 val = MUE_7800_BUFSIZE;
713 switch (sc->mue_udev->ud_speed) {
714 case USB_SPEED_SUPER:
715 val /= MUE_SS_USB_PKT_SIZE;
716 break;
717 case USB_SPEED_HIGH:
718 val /= MUE_HS_USB_PKT_SIZE;
719 break;
720 default:
721 val /= MUE_FS_USB_PKT_SIZE;
722 break;
723 }
724 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
725 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
726 MUE_7800_DEFAULT_BULKIN_DELAY);
727
728 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
729 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
730
731 /*
732 * Set FCL's RX and TX FIFO sizes: according to data sheet this
733 * is already the default value. But we initialize it to the
734 * same value anyways, as that's what the Linux driver does.
735 */
736 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
737 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
738 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
739 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
740 }
741
742 /* Enabling interrupts. */
743 mue_csr_write(sc, MUE_INT_STATUS, ~0);
744
745 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
746 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
747 mue_csr_write(sc, MUE_FLOW, 0);
748
749 /* Reset PHY. */
750 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
751 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
752 MUE_PRINTF(sc, "PHY not ready\n");
753 return ETIMEDOUT;
754 }
755
756 /* LAN7801 only has RGMII mode. */
757 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
758 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
759
760 if ((sc->mue_flags & LAN7500) ||
761 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
762 !mue_eeprom_present(sc))) {
763 /* Allow MAC to detect speed and duplex from PHY. */
764 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
765 MUE_MAC_CR_AUTO_DUPLEX);
766 }
767
768 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
769 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
770 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
771
772 /* Set the maximum frame size. */
773 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
774 val = mue_csr_read(sc, MUE_MAC_RX);
775 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
776 val |= MUE_MAC_RX_MAX_LEN(ETHER_MAX_LEN);
777 mue_csr_write(sc, MUE_MAC_RX, val);
778 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
779
780 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
781 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
782
783 /* Set default GPIO/LED settings only if no EEPROM is detected. */
784 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
785 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
786 MUE_SETBIT(sc, MUE_LED_CFG,
787 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
788 }
789
790 /* XXX We assume two LEDs at least when EEPROM is missing. */
791 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
792 !mue_eeprom_present(sc))
793 MUE_SETBIT(sc, MUE_HW_CFG,
794 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
795
796 return 0;
797 }
798
799 static void
800 mue_set_macaddr(struct mue_softc *sc)
801 {
802 struct ifnet *ifp = GET_IFP(sc);
803 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
804 uint32_t lo, hi;
805
806 lo = MUE_ENADDR_LO(enaddr);
807 hi = MUE_ENADDR_HI(enaddr);
808
809 mue_csr_write(sc, MUE_RX_ADDRL, lo);
810 mue_csr_write(sc, MUE_RX_ADDRH, hi);
811 }
812
813 static int
814 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
815 {
816 prop_data_t eaprop;
817 uint32_t low, high;
818
819 if (!(sc->mue_flags & LAN7500)) {
820 low = mue_csr_read(sc, MUE_RX_ADDRL);
821 high = mue_csr_read(sc, MUE_RX_ADDRH);
822 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
823 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
824 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
825 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
826 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
827 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
828 if (ETHER_IS_VALID(sc->mue_enaddr))
829 return 0;
830 else {
831 DPRINTF(sc, "registers: %s\n",
832 ether_sprintf(sc->mue_enaddr));
833 }
834 }
835
836 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
837 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
838 if (ETHER_IS_VALID(sc->mue_enaddr))
839 return 0;
840 else {
841 DPRINTF(sc, "EEPROM: %s\n",
842 ether_sprintf(sc->mue_enaddr));
843 }
844 }
845
846 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
847 ETHER_ADDR_LEN) == 0) {
848 if (ETHER_IS_VALID(sc->mue_enaddr))
849 return 0;
850 else {
851 DPRINTF(sc, "OTP: %s\n",
852 ether_sprintf(sc->mue_enaddr));
853 }
854 }
855
856 /*
857 * Other MD methods. This should be tried only if other methods fail.
858 * Otherwise, MAC address for internal device can be assinged to
859 * external devices on Raspberry Pi, for example.
860 */
861 eaprop = prop_dictionary_get(dict, "mac-address");
862 if (eaprop != NULL) {
863 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
864 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
865 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
866 ETHER_ADDR_LEN);
867 if (ETHER_IS_VALID(sc->mue_enaddr))
868 return 0;
869 else {
870 DPRINTF(sc, "prop_dictionary_get: %s\n",
871 ether_sprintf(sc->mue_enaddr));
872 }
873 }
874
875 return 1;
876 }
877
878
879 /*
880 * Probe for a Microchip chip. */
881 static int
882 mue_match(device_t parent, cfdata_t match, void *aux)
883 {
884 struct usb_attach_arg *uaa = aux;
885
886 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
887 }
888
889 static void
890 mue_attach(device_t parent, device_t self, void *aux)
891 {
892 struct mue_softc *sc = device_private(self);
893 prop_dictionary_t dict = device_properties(self);
894 struct usb_attach_arg *uaa = aux;
895 struct usbd_device *dev = uaa->uaa_device;
896 usb_interface_descriptor_t *id;
897 usb_endpoint_descriptor_t *ed;
898 char *devinfop;
899 struct mii_data *mii;
900 struct ifnet *ifp;
901 usbd_status err;
902 int i, s;
903
904 aprint_naive("\n");
905 aprint_normal("\n");
906
907 sc->mue_dev = self;
908 sc->mue_udev = dev;
909
910 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
911 aprint_normal_dev(self, "%s\n", devinfop);
912 usbd_devinfo_free(devinfop);
913
914 #define MUE_CONFIG_NO 1
915 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
916 if (err) {
917 aprint_error_dev(self, "failed to set configuration: %s\n",
918 usbd_errstr(err));
919 return;
920 }
921
922 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
923 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
924 usb_init_task(&sc->mue_stop_task, (void (*)(void *))mue_stop, sc, 0);
925
926 #define MUE_IFACE_IDX 0
927 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
928 if (err) {
929 aprint_error_dev(self, "failed to get interface handle: %s\n",
930 usbd_errstr(err));
931 return;
932 }
933
934 sc->mue_product = uaa->uaa_product;
935 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
936
937 /* Decide on what our bufsize will be. */
938 if (sc->mue_flags & LAN7500)
939 sc->mue_bufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
940 MUE_7500_HS_BUFSIZE : MUE_7500_FS_BUFSIZE;
941 else
942 sc->mue_bufsz = MUE_7800_BUFSIZE;
943
944 /* Find endpoints. */
945 id = usbd_get_interface_descriptor(sc->mue_iface);
946 for (i = 0; i < id->bNumEndpoints; i++) {
947 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
948 if (ed == NULL) {
949 aprint_error_dev(self, "couldn't get ep %d\n", i);
950 return;
951 }
952 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
953 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
954 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
955 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
956 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
957 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
958 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
959 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
960 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
961 }
962 }
963 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
964 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
965 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
966
967 s = splnet();
968
969 sc->mue_phyno = 1;
970
971 if (mue_chip_init(sc)) {
972 aprint_error_dev(self, "chip initialization failed\n");
973 splx(s);
974 return;
975 }
976
977 /* A Microchip chip was detected. Inform the world. */
978 if (sc->mue_flags & LAN7500)
979 aprint_normal_dev(self, "LAN7500\n");
980 else
981 aprint_normal_dev(self, "LAN7800\n");
982
983 if (mue_get_macaddr(sc, dict)) {
984 aprint_error_dev(self, "Ethernet address assigned randomly\n");
985 cprng_fast(sc->mue_enaddr, ETHER_ADDR_LEN);
986 sc->mue_enaddr[0] &= ~0x01; /* unicast */
987 sc->mue_enaddr[0] |= 0x02; /* locally administered */
988 }
989
990 aprint_normal_dev(self, "Ethernet address %s\n",
991 ether_sprintf(sc->mue_enaddr));
992
993 /* Initialize interface info.*/
994 ifp = GET_IFP(sc);
995 ifp->if_softc = sc;
996 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
997 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
998 ifp->if_init = mue_init;
999 ifp->if_ioctl = mue_ioctl;
1000 ifp->if_start = mue_start;
1001 ifp->if_stop = mue_stop;
1002 ifp->if_watchdog = mue_watchdog;
1003
1004 IFQ_SET_READY(&ifp->if_snd);
1005
1006 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1007
1008 /* Initialize MII/media info. */
1009 mii = GET_MII(sc);
1010 mii->mii_ifp = ifp;
1011 mii->mii_readreg = mue_miibus_readreg;
1012 mii->mii_writereg = mue_miibus_writereg;
1013 mii->mii_statchg = mue_miibus_statchg;
1014 mii->mii_flags = MIIF_AUTOTSLEEP;
1015
1016 sc->mue_ec.ec_mii = mii;
1017 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1018 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1019
1020 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1021 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1022 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1023 } else
1024 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1025
1026 /* Attach the interface. */
1027 if_attach(ifp);
1028 ether_ifattach(ifp, sc->mue_enaddr);
1029
1030 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1031 RND_TYPE_NET, RND_FLAG_DEFAULT);
1032
1033 callout_init(&sc->mue_stat_ch, 0);
1034
1035 splx(s);
1036
1037 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1038 }
1039
1040 static int
1041 mue_detach(device_t self, int flags)
1042 {
1043 struct mue_softc *sc = device_private(self);
1044 struct ifnet *ifp = GET_IFP(sc);
1045 size_t i;
1046 int s;
1047
1048 sc->mue_dying = true;
1049
1050 callout_halt(&sc->mue_stat_ch, NULL);
1051
1052 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1053 if (sc->mue_ep[i] != NULL)
1054 usbd_abort_pipe(sc->mue_ep[i]);
1055
1056 /*
1057 * Remove any pending tasks. They cannot be executing because they run
1058 * in the same thread as detach.
1059 */
1060 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1061 NULL);
1062 usb_rem_task_wait(sc->mue_udev, &sc->mue_stop_task, USB_TASKQ_DRIVER,
1063 NULL);
1064
1065 s = splusb();
1066
1067 if (ifp->if_flags & IFF_RUNNING)
1068 mue_stop(ifp, 1);
1069
1070 rnd_detach_source(&sc->mue_rnd_source);
1071 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1072 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1073 if (ifp->if_softc != NULL) {
1074 ether_ifdetach(ifp);
1075 if_detach(ifp);
1076 }
1077
1078 if (--sc->mue_refcnt >= 0) {
1079 /* Wait for processes to go away. */
1080 usb_detach_waitold(sc->mue_dev);
1081 }
1082 splx(s);
1083
1084 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1085
1086 mutex_destroy(&sc->mue_mii_lock);
1087
1088 return 0;
1089 }
1090
1091 static int
1092 mue_activate(device_t self, enum devact act)
1093 {
1094 struct mue_softc *sc = device_private(self);
1095 struct ifnet *ifp = GET_IFP(sc);
1096
1097 switch (act) {
1098 case DVACT_DEACTIVATE:
1099 if_deactivate(ifp);
1100 sc->mue_dying = true;
1101 return 0;
1102 default:
1103 return EOPNOTSUPP;
1104 }
1105 return 0;
1106 }
1107
1108 static int
1109 mue_rx_list_init(struct mue_softc *sc)
1110 {
1111 struct mue_cdata *cd;
1112 struct mue_chain *c;
1113 size_t i;
1114 int err;
1115
1116 cd = &sc->mue_cdata;
1117 for (i = 0; i < __arraycount(cd->mue_rx_chain); i++) {
1118 c = &cd->mue_rx_chain[i];
1119 c->mue_sc = sc;
1120 c->mue_idx = i;
1121 if (c->mue_xfer == NULL) {
1122 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1123 sc->mue_bufsz, 0, 0, &c->mue_xfer);
1124 if (err)
1125 return err;
1126 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1127 }
1128 }
1129
1130 return 0;
1131 }
1132
1133 static int
1134 mue_tx_list_init(struct mue_softc *sc)
1135 {
1136 struct mue_cdata *cd;
1137 struct mue_chain *c;
1138 size_t i;
1139 int err;
1140
1141 cd = &sc->mue_cdata;
1142 for (i = 0; i < __arraycount(cd->mue_tx_chain); i++) {
1143 c = &cd->mue_tx_chain[i];
1144 c->mue_sc = sc;
1145 c->mue_idx = i;
1146 if (c->mue_xfer == NULL) {
1147 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1148 sc->mue_bufsz, USBD_FORCE_SHORT_XFER, 0,
1149 &c->mue_xfer);
1150 if (err)
1151 return err;
1152 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1153 }
1154 }
1155
1156 return 0;
1157 }
1158
1159 static int
1160 mue_open_pipes(struct mue_softc *sc)
1161 {
1162 usbd_status err;
1163
1164 /* Open RX and TX pipes. */
1165 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1166 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1167 if (err) {
1168 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1169 return EIO;
1170 }
1171 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1172 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1173 if (err) {
1174 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1175 return EIO;
1176 }
1177 return 0;
1178 }
1179
1180 static void
1181 mue_start_rx(struct mue_softc *sc)
1182 {
1183 struct mue_chain *c;
1184 size_t i;
1185
1186 /* Start up the receive pipe. */
1187 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++) {
1188 c = &sc->mue_cdata.mue_rx_chain[i];
1189 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_bufsz,
1190 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1191 usbd_transfer(c->mue_xfer);
1192 }
1193 }
1194
1195 static int
1196 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1197 {
1198 struct ifnet *ifp = GET_IFP(sc);
1199 struct mue_chain *c;
1200 usbd_status err;
1201 struct mue_txbuf_hdr hdr;
1202 int len;
1203
1204 c = &sc->mue_cdata.mue_tx_chain[idx];
1205
1206 hdr.tx_cmd_a = htole32((m->m_pkthdr.len & MUE_TX_CMD_A_LEN_MASK) |
1207 MUE_TX_CMD_A_FCS);
1208 /* Disable segmentation offload. */
1209 hdr.tx_cmd_b = htole32(0);
1210 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1211 len = sizeof(hdr);
1212
1213 m_copydata(m, 0, m->m_pkthdr.len, c->mue_buf + len);
1214 len += m->m_pkthdr.len;
1215
1216 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len,
1217 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1218
1219 /* Transmit */
1220 err = usbd_transfer(c->mue_xfer);
1221 if (__predict_false(err != USBD_IN_PROGRESS)) {
1222 DPRINTF(sc, "%s\n", usbd_errstr(err));
1223 mue_stop(ifp, 0);
1224 return EIO;
1225 }
1226
1227 sc->mue_cdata.mue_tx_cnt++;
1228
1229 return 0;
1230 }
1231
1232 static void
1233 mue_setmulti(struct mue_softc *sc)
1234 {
1235 struct ifnet *ifp = GET_IFP(sc);
1236 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1237 struct ether_multi *enm;
1238 struct ether_multistep step;
1239 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1240 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1241 uint32_t reg, rxfilt, h, hireg, loreg;
1242 int i;
1243
1244 if (sc->mue_dying)
1245 return;
1246
1247 /* Clear perfect filter and hash tables. */
1248 memset(pfiltbl, 0, sizeof(pfiltbl));
1249 memset(hashtbl, 0, sizeof(hashtbl));
1250
1251 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1252 rxfilt = mue_csr_read(sc, reg);
1253 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1254 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1255
1256 /* Always accept broadcast frames. */
1257 rxfilt |= MUE_RFE_CTL_BROADCAST;
1258
1259 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1260 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1261 if (ifp->if_flags & IFF_PROMISC) {
1262 rxfilt |= MUE_RFE_CTL_UNICAST;
1263 DPRINTF(sc, "promisc\n");
1264 } else {
1265 DPRINTF(sc, "allmulti\n");
1266 }
1267 } else {
1268 /* Now program new ones. */
1269 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1270 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1271 i = 1;
1272 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1273 while (enm != NULL) {
1274 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1275 ETHER_ADDR_LEN)) {
1276 memset(pfiltbl, 0, sizeof(pfiltbl));
1277 memset(hashtbl, 0, sizeof(hashtbl));
1278 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1279 goto allmulti;
1280 }
1281 if (i < MUE_NUM_ADDR_FILTX) {
1282 /* Use perfect address table if possible. */
1283 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1284 MUE_ADDR_FILTX_VALID;
1285 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1286 } else {
1287 /* Otherwise, use hash table. */
1288 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1289 h = (ether_crc32_be(enm->enm_addrlo,
1290 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1291 hashtbl[h / 32] |= 1 << (h % 32);
1292 }
1293 i++;
1294 ETHER_NEXT_MULTI(step, enm);
1295 }
1296 rxfilt |= MUE_RFE_CTL_PERFECT;
1297 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH) {
1298 DPRINTF(sc, "perfect filter and hash tables\n");
1299 } else {
1300 DPRINTF(sc, "perfect filter\n");
1301 }
1302 }
1303
1304 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1305 hireg = (sc->mue_flags & LAN7500) ?
1306 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1307 loreg = hireg + 4;
1308 mue_csr_write(sc, hireg, 0);
1309 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1310 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1311 }
1312
1313 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1314 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1315
1316 mue_csr_write(sc, reg, rxfilt);
1317 }
1318
1319 static void
1320 mue_sethwcsum(struct mue_softc *sc)
1321 {
1322 struct ifnet *ifp = GET_IFP(sc);
1323 uint32_t reg, val;
1324
1325 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1326 val = mue_csr_read(sc, reg);
1327
1328 if (ifp->if_capabilities & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) {
1329 DPRINTF(sc, "enabled\n");;
1330 val |= MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE;
1331 val |= MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE;
1332 } else {
1333 DPRINTF(sc, "disabled\n");;
1334 val &=
1335 ~(MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE);
1336 val &=
1337 ~(MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE);
1338 }
1339
1340 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1341
1342 mue_csr_write(sc, reg, val);
1343 }
1344
1345
1346 static void
1347 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1348 {
1349 struct mue_chain *c = (struct mue_chain *)priv;
1350 struct mue_softc *sc = c->mue_sc;
1351 struct ifnet *ifp = GET_IFP(sc);
1352 struct mbuf *m;
1353 struct mue_rxbuf_hdr *hdrp;
1354 uint32_t rx_cmd_a, total_len;
1355 uint16_t pktlen;
1356 int s;
1357 char *buf = c->mue_buf;
1358
1359 if (__predict_false(sc->mue_dying)) {
1360 DPRINTF(sc, "dying\n");
1361 return;
1362 }
1363
1364 if (__predict_false(!(ifp->if_flags & IFF_RUNNING))) {
1365 DPRINTF(sc, "not running\n");
1366 return;
1367 }
1368
1369 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1370 DPRINTF(sc, "%s\n", usbd_errstr(status));
1371 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1372 return;
1373 if (usbd_ratecheck(&sc->mue_rx_notice))
1374 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1375 if (status == USBD_STALLED)
1376 usbd_clear_endpoint_stall_async(
1377 sc->mue_ep[MUE_ENDPT_RX]);
1378 goto done;
1379 }
1380
1381 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
1382
1383 if (__predict_false(total_len > sc->mue_bufsz)) {
1384 DPRINTF(sc, "too large transfer\n");
1385 goto done;
1386 }
1387
1388 do {
1389 if (__predict_false(total_len < sizeof(*hdrp))) {
1390 DPRINTF(sc, "too short transfer\n");
1391 ifp->if_ierrors++;
1392 goto done;
1393 }
1394
1395 hdrp = (struct mue_rxbuf_hdr *)buf;
1396 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1397
1398 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_RED)) {
1399 DPRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1400 ifp->if_ierrors++;
1401 goto done;
1402 }
1403
1404 /* XXX not yet */
1405 KASSERT((rx_cmd_a & MUE_RX_CMD_A_ICSM) == 0);
1406
1407 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1408 if (sc->mue_flags & LAN7500)
1409 pktlen -= 2;
1410
1411 if (__predict_false(pktlen < ETHER_HDR_LEN ||
1412 pktlen > MCLBYTES - ETHER_ALIGN ||
1413 pktlen + sizeof(*hdrp) > total_len)) {
1414 DPRINTF(sc, "bad pktlen\n");
1415 ifp->if_ierrors++;
1416 goto done;
1417 }
1418
1419 m = mue_newbuf();
1420 if (__predict_false(m == NULL)) {
1421 DPRINTF(sc, "mbuf allocation failed\n");
1422 ifp->if_ierrors++;
1423 goto done;
1424 }
1425
1426 m_set_rcvif(m, ifp);
1427 m->m_pkthdr.len = m->m_len = pktlen;
1428 m->m_flags |= M_HASFCS;
1429 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1430
1431 /* Attention: sizeof(hdr) = 10 */
1432 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1433 if (pktlen > total_len)
1434 pktlen = total_len;
1435 total_len -= pktlen;
1436 buf += pktlen;
1437
1438 s = splnet();
1439 if_percpuq_enqueue(ifp->if_percpuq, m);
1440 splx(s);
1441 } while (total_len > 0);
1442
1443 done:
1444 /* Setup new transfer. */
1445 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_bufsz,
1446 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1447 usbd_transfer(xfer);
1448 }
1449
1450 static void
1451 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1452 {
1453 struct mue_chain *c = priv;
1454 struct mue_softc *sc = c->mue_sc;
1455 struct ifnet *ifp = GET_IFP(sc);
1456 int s;
1457
1458 if (__predict_false(sc->mue_dying))
1459 return;
1460
1461 s = splnet();
1462
1463
1464 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1465 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1466 splx(s);
1467 return;
1468 }
1469 ifp->if_oerrors++;
1470 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1471 if (status == USBD_STALLED)
1472 usbd_clear_endpoint_stall_async(
1473 sc->mue_ep[MUE_ENDPT_TX]);
1474 splx(s);
1475 return;
1476 }
1477
1478 ifp->if_timer = 0;
1479 ifp->if_flags &= ~IFF_OACTIVE;
1480
1481 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1482 mue_start(ifp);
1483
1484 ifp->if_opackets++;
1485 splx(s);
1486 }
1487
1488 static int
1489 mue_init(struct ifnet *ifp)
1490 {
1491 struct mue_softc *sc = ifp->if_softc;
1492 int s;
1493
1494 if (sc->mue_dying) {
1495 DPRINTF(sc, "dying\n");
1496 return EIO;
1497 }
1498
1499 s = splnet();
1500
1501 /* Cancel pending I/O and free all TX/RX buffers. */
1502 if (ifp->if_flags & IFF_RUNNING)
1503 mue_stop(ifp, 1);
1504
1505 mue_reset(sc);
1506
1507 /* Set MAC address. */
1508 mue_set_macaddr(sc);
1509
1510 /* Load the multicast filter. */
1511 mue_setmulti(sc);
1512
1513 /* TCP/UDP checksum offload engines. */
1514 mue_sethwcsum(sc);
1515
1516 if (mue_open_pipes(sc)) {
1517 splx(s);
1518 return EIO;
1519 }
1520
1521 /* Init RX ring. */
1522 if (mue_rx_list_init(sc)) {
1523 MUE_PRINTF(sc, "rx list init failed\n");
1524 splx(s);
1525 return ENOBUFS;
1526 }
1527
1528 /* Init TX ring. */
1529 if (mue_tx_list_init(sc)) {
1530 MUE_PRINTF(sc, "tx list init failed\n");
1531 splx(s);
1532 return ENOBUFS;
1533 }
1534
1535 mue_start_rx(sc);
1536
1537 ifp->if_flags |= IFF_RUNNING;
1538 ifp->if_flags &= ~IFF_OACTIVE;
1539
1540 splx(s);
1541
1542 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1543
1544 return 0;
1545 }
1546
1547 static int
1548 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1549 {
1550 struct mue_softc *sc = ifp->if_softc;
1551 struct ifreq /*const*/ *ifr = data;
1552 int s, error = 0;
1553
1554 s = splnet();
1555
1556 switch(cmd) {
1557 case SIOCSIFFLAGS:
1558 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1559 break;
1560
1561 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1562 case IFF_RUNNING:
1563 mue_stop(ifp, 1);
1564 break;
1565 case IFF_UP:
1566 mue_init(ifp);
1567 break;
1568 case IFF_UP | IFF_RUNNING:
1569 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1570 mue_setmulti(sc);
1571 else
1572 mue_init(ifp);
1573 break;
1574 }
1575 sc->mue_if_flags = ifp->if_flags;
1576 break;
1577 case SIOCGIFMEDIA:
1578 case SIOCSIFMEDIA:
1579 error = ifmedia_ioctl(ifp, ifr, &sc->mue_mii.mii_media, cmd);
1580 break;
1581 default:
1582 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1583 break;
1584 error = 0;
1585 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI)
1586 mue_setmulti(sc);
1587 break;
1588 }
1589 splx(s);
1590
1591 return error;
1592 }
1593
1594 static void
1595 mue_watchdog(struct ifnet *ifp)
1596 {
1597 struct mue_softc *sc = ifp->if_softc;
1598 struct mue_chain *c;
1599 usbd_status stat;
1600 int s;
1601
1602 ifp->if_oerrors++;
1603 MUE_PRINTF(sc, "timed out\n");
1604
1605 s = splusb();
1606 c = &sc->mue_cdata.mue_tx_chain[0];
1607 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1608 mue_txeof(c->mue_xfer, c, stat);
1609
1610 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1611 mue_start(ifp);
1612 splx(s);
1613 }
1614
1615 static void
1616 mue_reset(struct mue_softc *sc)
1617 {
1618 if (sc->mue_dying)
1619 return;
1620
1621 /* Wait a little while for the chip to get its brains in order. */
1622 usbd_delay_ms(sc->mue_udev, 1);
1623
1624 // mue_chip_init(sc); /* XXX */
1625 }
1626
1627 static void
1628 mue_start(struct ifnet *ifp)
1629 {
1630 struct mue_softc *sc = ifp->if_softc;
1631 struct mbuf *m;
1632
1633 if (__predict_false(!sc->mue_link)) {
1634 DPRINTF(sc, "no link\n");
1635 return;
1636 }
1637
1638 if (__predict_false((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING))
1639 != IFF_RUNNING)) {
1640 DPRINTF(sc, "not ready\n");
1641 return;
1642 }
1643
1644 IFQ_POLL(&ifp->if_snd, m);
1645 if (m == NULL)
1646 return;
1647
1648 if (__predict_false(mue_encap(sc, m, 0))) {
1649 DPRINTF(sc, "encap failed\n");
1650 ifp->if_flags |= IFF_OACTIVE;
1651 return;
1652 }
1653 IFQ_DEQUEUE(&ifp->if_snd, m);
1654
1655 bpf_mtap(ifp, m, BPF_D_OUT);
1656 m_freem(m);
1657
1658 ifp->if_flags |= IFF_OACTIVE;
1659
1660 /* Set a timeout in case the chip goes out to lunch. */
1661 ifp->if_timer = 5;
1662 }
1663
1664 static void
1665 mue_stop(struct ifnet *ifp, int disable __unused)
1666 {
1667 struct mue_softc *sc = ifp->if_softc;
1668 usbd_status err;
1669 size_t i;
1670
1671 mue_reset(sc);
1672
1673 ifp->if_timer = 0;
1674 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1675
1676 callout_stop(&sc->mue_stat_ch);
1677
1678 /* Stop transfers. */
1679 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1680 if (sc->mue_ep[i] != NULL) {
1681 err = usbd_abort_pipe(sc->mue_ep[i]);
1682 if (err)
1683 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1684 i, usbd_errstr(err));
1685 }
1686
1687 /* Free RX resources. */
1688 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++)
1689 if (sc->mue_cdata.mue_rx_chain[i].mue_xfer != NULL) {
1690 usbd_destroy_xfer(
1691 sc->mue_cdata.mue_rx_chain[i].mue_xfer);
1692 sc->mue_cdata.mue_rx_chain[i].mue_xfer = NULL;
1693 }
1694
1695 /* Free TX resources. */
1696 for (i = 0; i < __arraycount(sc->mue_cdata.mue_tx_chain); i++)
1697 if (sc->mue_cdata.mue_tx_chain[i].mue_xfer != NULL) {
1698 usbd_destroy_xfer(
1699 sc->mue_cdata.mue_tx_chain[i].mue_xfer);
1700 sc->mue_cdata.mue_tx_chain[i].mue_xfer = NULL;
1701 }
1702
1703 /* Close pipes */
1704 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1705 if (sc->mue_ep[i] != NULL) {
1706 err = usbd_close_pipe(sc->mue_ep[i]);
1707 if (err)
1708 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1709 i, usbd_errstr(err));
1710 sc->mue_ep[i] = NULL;
1711 }
1712
1713 sc->mue_link = 0; /* XXX */
1714
1715 DPRINTF(sc, "done\n");
1716 }
1717
1718 static void
1719 mue_tick(void *xsc)
1720 {
1721 struct mue_softc *sc = xsc;
1722
1723 if (sc == NULL)
1724 return;
1725
1726 if (sc->mue_dying)
1727 return;
1728
1729 /* Perform periodic stuff in process context. */
1730 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1731 }
1732
1733 static void
1734 mue_tick_task(void *xsc)
1735 {
1736 struct mue_softc *sc = xsc;
1737 struct ifnet *ifp = GET_IFP(sc);
1738 struct mii_data *mii = GET_MII(sc);
1739 int s;
1740
1741 if (sc == NULL)
1742 return;
1743
1744 if (sc->mue_dying)
1745 return;
1746
1747 s = splnet();
1748 mii_tick(mii);
1749 if (sc->mue_link == 0)
1750 mue_miibus_statchg(ifp);
1751 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1752 splx(s);
1753 }
1754
1755 static struct mbuf *
1756 mue_newbuf(void)
1757 {
1758 struct mbuf *m;
1759
1760 MGETHDR(m, M_DONTWAIT, MT_DATA);
1761 if (__predict_false(m == NULL))
1762 return NULL;
1763
1764 MCLGET(m, M_DONTWAIT);
1765 if (__predict_false(!(m->m_flags & M_EXT))) {
1766 m_freem(m);
1767 return NULL;
1768 }
1769
1770 m_adj(m, ETHER_ALIGN);
1771
1772 return m;
1773 }
1774