if_mue.c revision 1.10 1 /* $NetBSD: if_mue.c,v 1.10 2018/09/16 01:13:26 rin Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.10 2018/09/16 01:13:26 rin Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/cprng.h>
32 #include <sys/bus.h>
33 #include <sys/systm.h>
34 #include <sys/sockio.h>
35 #include <sys/mbuf.h>
36 #include <sys/mutex.h>
37 #include <sys/kernel.h>
38 #include <sys/proc.h>
39 #include <sys/socket.h>
40
41 #include <sys/device.h>
42
43 #include <sys/rndsource.h>
44
45 #include <net/if.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
48 #include <net/if_ether.h>
49
50 #include <net/bpf.h>
51
52 #include <netinet/if_inarp.h>
53 #include <netinet/in.h>
54 #include <netinet/ip.h> /* XXX for struct ip */
55 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
56 #include <netinet/tcp.h> /* XXX for struct tcphdr */
57
58 #include <dev/mii/mii.h>
59 #include <dev/mii/miivar.h>
60
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
63 #include <dev/usb/usbdi_util.h>
64 #include <dev/usb/usbdivar.h>
65 #include <dev/usb/usbdevs.h>
66
67 #include <dev/usb/if_muereg.h>
68 #include <dev/usb/if_muevar.h>
69
70 #define MUE_PRINTF(sc, fmt, args...) \
71 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
72
73 #ifdef USB_DEBUG
74 int muedebug = 0;
75 #define DPRINTF(sc, fmt, args...) \
76 do { \
77 if (muedebug) \
78 MUE_PRINTF(sc, fmt, ##args); \
79 } while (0 /* CONSTCOND */)
80 #else
81 #define DPRINTF(sc, fmt, args...) /* nothing */
82 #endif
83
84 /*
85 * Various supported device vendors/products.
86 */
87 struct mue_type {
88 struct usb_devno mue_dev;
89 uint16_t mue_flags;
90 #define LAN7500 0x0001 /* LAN7500 */
91 };
92
93 const struct mue_type mue_devs[] = {
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
97 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
98 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
99 };
100
101 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
102 uaa->uaa_vendor, uaa->uaa_product))
103
104 #define MUE_ENADDR_LO(enaddr) \
105 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
106 #define MUE_ENADDR_HI(enaddr) \
107 ((enaddr[5] << 8) | enaddr[4])
108
109 static int mue_match(device_t, cfdata_t, void *);
110 static void mue_attach(device_t, device_t, void *);
111 static int mue_detach(device_t, int);
112 static int mue_activate(device_t, enum devact);
113
114 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
115 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
116 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
117 uint32_t, uint32_t);
118
119 static void mue_lock_mii(struct mue_softc *);
120 static void mue_unlock_mii(struct mue_softc *);
121
122 static int mue_miibus_readreg(device_t, int, int);
123 static void mue_miibus_writereg(device_t, int, int, int);
124 static void mue_miibus_statchg(struct ifnet *);
125 static int mue_ifmedia_upd(struct ifnet *);
126 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
127
128 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
129 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
130 static bool mue_eeprom_present(struct mue_softc *sc);
131
132 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
133 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
134
135 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
136 uint32_t, uint32_t *);
137
138 static void mue_init_ltm(struct mue_softc *);
139
140 static int mue_chip_init(struct mue_softc *);
141
142 static void mue_set_macaddr(struct mue_softc *);
143 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
144
145 static int mue_rx_list_init(struct mue_softc *);
146 static int mue_tx_list_init(struct mue_softc *);
147 static int mue_open_pipes(struct mue_softc *);
148 static void mue_start_rx(struct mue_softc *);
149
150 static int mue_encap(struct mue_softc *, struct mbuf *, int);
151 static void mue_tx_offload(struct mue_softc *, struct mbuf *);
152
153 static void mue_setmulti(struct mue_softc *);
154 static void mue_sethwcsum(struct mue_softc *);
155
156 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
157 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
158
159 static int mue_init(struct ifnet *);
160 static int mue_ioctl(struct ifnet *, u_long, void *);
161 static void mue_watchdog(struct ifnet *);
162 static void mue_reset(struct mue_softc *);
163 static void mue_start(struct ifnet *);
164 static void mue_stop(struct ifnet *, int);
165 static void mue_tick(void *);
166 static void mue_tick_task(void *);
167
168 static struct mbuf *mue_newbuf(void);
169
170 #define MUE_SETBIT(sc, reg, x) \
171 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
172
173 #define MUE_CLRBIT(sc, reg, x) \
174 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
175
176 #define MUE_WAIT_SET(sc, reg, set, fail) \
177 mue_wait_for_bits(sc, reg, set, ~0, fail)
178
179 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
180 mue_wait_for_bits(sc, reg, 0, clear, fail)
181
182 #define ETHER_IS_VALID(addr) \
183 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
184
185 #define ETHER_IS_ZERO(addr) \
186 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
187
188 #define ETHER_ALIGN 2
189
190 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
191 mue_detach, mue_activate);
192
193 static uint32_t
194 mue_csr_read(struct mue_softc *sc, uint32_t reg)
195 {
196 usb_device_request_t req;
197 usbd_status err;
198 uDWord val;
199
200 if (sc->mue_dying)
201 return 0;
202
203 USETDW(val, 0);
204 req.bmRequestType = UT_READ_VENDOR_DEVICE;
205 req.bRequest = MUE_UR_READREG;
206 USETW(req.wValue, 0);
207 USETW(req.wIndex, reg);
208 USETW(req.wLength, 4);
209
210 err = usbd_do_request(sc->mue_udev, &req, &val);
211 if (err) {
212 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
213 return 0;
214 }
215
216 return UGETDW(val);
217 }
218
219 static int
220 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
221 {
222 usb_device_request_t req;
223 usbd_status err;
224 uDWord val;
225
226 if (sc->mue_dying)
227 return 0;
228
229 USETDW(val, aval);
230 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
231 req.bRequest = MUE_UR_WRITEREG;
232 USETW(req.wValue, 0);
233 USETW(req.wIndex, reg);
234 USETW(req.wLength, 4);
235
236 err = usbd_do_request(sc->mue_udev, &req, &val);
237 if (err) {
238 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
239 return -1;
240 }
241
242 return 0;
243 }
244
245 static int
246 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
247 uint32_t set, uint32_t clear, uint32_t fail)
248 {
249 uint32_t val;
250 int ntries;
251
252 for (ntries = 0; ntries < 1000; ntries++) {
253 val = mue_csr_read(sc, reg);
254 if ((val & set) || !(val & clear))
255 return 0;
256 if (val & fail)
257 return 1;
258 usbd_delay_ms(sc->mue_udev, 1);
259 }
260
261 return 1;
262 }
263
264 /*
265 * Get exclusive access to the MII registers.
266 */
267 static void
268 mue_lock_mii(struct mue_softc *sc)
269 {
270 sc->mue_refcnt++;
271 mutex_enter(&sc->mue_mii_lock);
272 }
273
274 static void
275 mue_unlock_mii(struct mue_softc *sc)
276 {
277 mutex_exit(&sc->mue_mii_lock);
278 if (--sc->mue_refcnt < 0)
279 usb_detach_wakeupold(sc->mue_dev);
280 }
281
282 static int
283 mue_miibus_readreg(device_t dev, int phy, int reg)
284 {
285 struct mue_softc *sc = device_private(dev);
286 uint32_t val;
287
288 if (sc->mue_dying) {
289 DPRINTF(sc, "dying\n");
290 return 0;
291 }
292
293 if (sc->mue_phyno != phy)
294 return 0;
295
296 mue_lock_mii(sc);
297 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
298 mue_unlock_mii(sc);
299 MUE_PRINTF(sc, "not ready\n");
300 return -1;
301 }
302
303 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
304 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
305 MUE_MII_ACCESS_PHYADDR(phy));
306
307 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
308 mue_unlock_mii(sc);
309 MUE_PRINTF(sc, "timed out\n");
310 return -1;
311 }
312
313 val = mue_csr_read(sc, MUE_MII_DATA);
314 mue_unlock_mii(sc);
315 return val & 0xffff;
316 }
317
318 static void
319 mue_miibus_writereg(device_t dev, int phy, int reg, int data)
320 {
321 struct mue_softc *sc = device_private(dev);
322
323 if (sc->mue_dying) {
324 DPRINTF(sc, "dying\n");
325 return;
326 }
327
328 if (sc->mue_phyno != phy) {
329 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
330 sc->mue_phyno, phy);
331 return;
332 }
333
334 mue_lock_mii(sc);
335 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
336 mue_unlock_mii(sc);
337 MUE_PRINTF(sc, "not ready\n");
338 return;
339 }
340
341 mue_csr_write(sc, MUE_MII_DATA, data);
342 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
343 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
344 MUE_MII_ACCESS_PHYADDR(phy));
345
346 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0))
347 MUE_PRINTF(sc, "timed out\n");
348
349 mue_unlock_mii(sc);
350 }
351
352 static void
353 mue_miibus_statchg(struct ifnet *ifp)
354 {
355 struct mue_softc *sc = ifp->if_softc;
356 struct mii_data *mii = GET_MII(sc);
357 uint32_t flow, threshold;
358
359 if (mii == NULL || ifp == NULL || (ifp->if_flags & IFF_RUNNING) == 0) {
360 DPRINTF(sc, "not ready\n");
361 return;
362 }
363
364 sc->mue_link = 0;
365 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
366 (IFM_ACTIVE | IFM_AVALID)) {
367 switch (IFM_SUBTYPE(mii->mii_media_active)) {
368 case IFM_10_T:
369 case IFM_100_TX:
370 case IFM_1000_T:
371 sc->mue_link++;
372 break;
373 default:
374 break;
375 }
376 }
377
378 /* Lost link, do nothing. */
379 if (sc->mue_link == 0) {
380 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
381 return;
382 }
383
384 if (!(sc->mue_flags & LAN7500)) {
385 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
386 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
387 /* Disable U2 and enable U1. */
388 MUE_CLRBIT(sc, MUE_USB_CFG1,
389 MUE_USB_CFG1_DEV_U2_INIT_EN);
390 MUE_SETBIT(sc, MUE_USB_CFG1,
391 MUE_USB_CFG1_DEV_U1_INIT_EN);
392 } else {
393 /* Enable U1 and U2. */
394 MUE_SETBIT(sc, MUE_USB_CFG1,
395 MUE_USB_CFG1_DEV_U1_INIT_EN |
396 MUE_USB_CFG1_DEV_U2_INIT_EN);
397 }
398 }
399 }
400
401 flow = 0;
402 /* XXX Linux does not check IFM_FDX flag for 7800. */
403 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
404 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
405 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
406 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
407 flow |= MUE_FLOW_RX_FCEN;
408 }
409
410 /* XXX Magic numbers taken from Linux driver. */
411 if (sc->mue_flags & LAN7500)
412 threshold = 0x820;
413 else
414 switch (sc->mue_udev->ud_speed) {
415 case USB_SPEED_SUPER:
416 threshold = 0x817;
417 break;
418 case USB_SPEED_HIGH:
419 threshold = 0x211;
420 break;
421 default:
422 threshold = 0;
423 break;
424 }
425
426 /* Threshold value should be set before enabling flow. */
427 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
428 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
429 mue_csr_write(sc, MUE_FLOW, flow);
430
431 DPRINTF(sc, "done\n");
432 }
433
434 /*
435 * Set media options.
436 */
437 static int
438 mue_ifmedia_upd(struct ifnet *ifp)
439 {
440 struct mue_softc *sc = ifp->if_softc;
441 struct mii_data *mii = GET_MII(sc);
442
443 sc->mue_link = 0; /* XXX */
444
445 if (mii->mii_instance) {
446 struct mii_softc *miisc;
447 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
448 mii_phy_reset(miisc);
449 }
450 return mii_mediachg(mii);
451 }
452
453 /*
454 * Report current media status.
455 */
456 static void
457 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
458 {
459 struct mue_softc *sc = ifp->if_softc;
460 struct mii_data *mii = GET_MII(sc);
461
462 mii_pollstat(mii);
463 ifmr->ifm_active = mii->mii_media_active;
464 ifmr->ifm_status = mii->mii_media_status;
465 }
466
467 static uint8_t
468 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
469 {
470 uint32_t val;
471
472 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
473 MUE_PRINTF(sc, "not ready\n");
474 return ETIMEDOUT;
475 }
476
477 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
478 (off & MUE_E2P_CMD_ADDR_MASK));
479
480 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
481 MUE_E2P_CMD_TIMEOUT)) {
482 MUE_PRINTF(sc, "timed out\n");
483 return ETIMEDOUT;
484 }
485
486 val = mue_csr_read(sc, MUE_E2P_DATA);
487 *dest = val & 0xff;
488
489 return 0;
490 }
491
492 static int
493 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
494 {
495 uint32_t val = 0; /* XXX gcc */
496 uint8_t byte;
497 int i, err;
498
499 /*
500 * EEPROM pins are muxed with the LED function on LAN7800 device.
501 */
502 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
503 val = mue_csr_read(sc, MUE_HW_CFG);
504 mue_csr_write(sc, MUE_HW_CFG,
505 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
506 }
507
508 for (i = 0; i < cnt; i++) {
509 err = mue_eeprom_getbyte(sc, off + i, &byte);
510 if (err)
511 break;
512 *(dest + i) = byte;
513 }
514
515 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
516 mue_csr_write(sc, MUE_HW_CFG, val);
517
518 return err ? 1 : 0;
519 }
520
521 static bool
522 mue_eeprom_present(struct mue_softc *sc)
523 {
524 uint32_t val;
525 uint8_t sig;
526 int ret;
527
528 if (sc->mue_flags & LAN7500) {
529 val = mue_csr_read(sc, MUE_E2P_CMD);
530 return val & MUE_E2P_CMD_LOADED;
531 } else {
532 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
533 return (ret == 0) && (sig == MUE_E2P_IND);
534 }
535 }
536
537 static int
538 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
539 {
540 uint32_t val;
541 int i, err;
542
543 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
544
545 /* Checking if bit is set. */
546 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
547 /* Clear it, then wait for it to be cleared. */
548 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
549 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
550 0);
551 if (err) {
552 MUE_PRINTF(sc, "not ready\n");
553 return 1;
554 }
555 }
556
557 /* Start reading the bytes, one at a time. */
558 for (i = 0; i < cnt; i++) {
559 mue_csr_write(sc, MUE_OTP_ADDR1,
560 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
561 mue_csr_write(sc, MUE_OTP_ADDR2,
562 ((off + i) & MUE_OTP_ADDR2_MASK));
563 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
564 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
565
566 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
567 if (err) {
568 MUE_PRINTF(sc, "timed out\n");
569 return 1;
570 }
571 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
572 *(dest + i) = (uint8_t)(val & 0xff);
573 }
574
575 return 0;
576 }
577
578 static int
579 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
580 {
581 uint8_t sig;
582 int err;
583
584 if (sc->mue_flags & LAN7500)
585 return 1;
586
587 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
588 if (err)
589 return 1;
590 switch (sig) {
591 case MUE_OTP_IND_1:
592 break;
593 case MUE_OTP_IND_2:
594 off += 0x100;
595 break;
596 default:
597 DPRINTF(sc, "OTP not found\n");
598 return 1;
599 }
600 err = mue_read_otp_raw(sc, dest, off, cnt);
601 return err;
602 }
603
604 static void
605 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
606 uint32_t cnt, uint32_t *data)
607 {
608 uint32_t i;
609
610 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
611 MUE_PRINTF(sc, "not ready\n");
612 return;
613 }
614
615 mue_csr_write(sc, MUE_DP_SEL,
616 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
617
618 for (i = 0; i < cnt; i++) {
619 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
620 mue_csr_write(sc, MUE_DP_DATA, data[i]);
621 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
622 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
623 MUE_PRINTF(sc, "timed out\n");
624 return;
625 }
626 }
627 }
628
629 static void
630 mue_init_ltm(struct mue_softc *sc)
631 {
632 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
633 uint8_t temp[2];
634 size_t i;
635
636 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
637 if (mue_eeprom_present(sc) &&
638 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
639 if (temp[0] != sizeof(idx)) {
640 DPRINTF(sc, "EEPROM: unexpected size\n");
641 goto done;
642 }
643 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
644 sizeof(idx))) {
645 DPRINTF(sc, "EEPROM: failed to read\n");
646 goto done;
647 }
648 DPRINTF(sc, "success\n");
649 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
650 if (temp[0] != sizeof(idx)) {
651 DPRINTF(sc, "OTP: unexpected size\n");
652 goto done;
653 }
654 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
655 sizeof(idx))) {
656 DPRINTF(sc, "OTP: failed to read\n");
657 goto done;
658 }
659 DPRINTF(sc, "success\n");
660 } else {
661 DPRINTF(sc, "nothing to do\n");
662 }
663 } else {
664 DPRINTF(sc, "nothing to do\n");
665 }
666 done:
667 for (i = 0; i < __arraycount(idx); i++)
668 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
669 }
670
671 static int
672 mue_chip_init(struct mue_softc *sc)
673 {
674 uint32_t val;
675
676 if ((sc->mue_flags & LAN7500) &&
677 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
678 MUE_PRINTF(sc, "not ready\n");
679 return ETIMEDOUT;
680 }
681
682 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
683 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
684 MUE_PRINTF(sc, "timed out\n");
685 return ETIMEDOUT;
686 }
687
688 /* Respond to the IN token with a NAK. */
689 if (sc->mue_flags & LAN7500)
690 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
691 else
692 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
693
694 if (sc->mue_flags & LAN7500) {
695 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
696 val = MUE_7500_HS_RX_BUFSIZE /
697 MUE_HS_USB_PKT_SIZE;
698 else
699 val = MUE_7500_FS_RX_BUFSIZE /
700 MUE_FS_USB_PKT_SIZE;
701 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
702 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
703 MUE_7500_DEFAULT_BULKIN_DELAY);
704
705 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
706
707 /* Set FIFO sizes. */
708 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
709 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
710 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
711 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
712 } else {
713 /* Init LTM. */
714 mue_init_ltm(sc);
715
716 val = MUE_7800_RX_BUFSIZE;
717 switch (sc->mue_udev->ud_speed) {
718 case USB_SPEED_SUPER:
719 val /= MUE_SS_USB_PKT_SIZE;
720 break;
721 case USB_SPEED_HIGH:
722 val /= MUE_HS_USB_PKT_SIZE;
723 break;
724 default:
725 val /= MUE_FS_USB_PKT_SIZE;
726 break;
727 }
728 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
729 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
730 MUE_7800_DEFAULT_BULKIN_DELAY);
731
732 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
733 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
734
735 /*
736 * Set FCL's RX and TX FIFO sizes: according to data sheet this
737 * is already the default value. But we initialize it to the
738 * same value anyways, as that's what the Linux driver does.
739 */
740 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
741 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
742 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
743 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
744 }
745
746 /* Enabling interrupts. */
747 mue_csr_write(sc, MUE_INT_STATUS, ~0);
748
749 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
750 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
751 mue_csr_write(sc, MUE_FLOW, 0);
752
753 /* Reset PHY. */
754 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
755 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
756 MUE_PRINTF(sc, "PHY not ready\n");
757 return ETIMEDOUT;
758 }
759
760 /* LAN7801 only has RGMII mode. */
761 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
762 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
763
764 if ((sc->mue_flags & LAN7500) ||
765 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
766 !mue_eeprom_present(sc))) {
767 /* Allow MAC to detect speed and duplex from PHY. */
768 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
769 MUE_MAC_CR_AUTO_DUPLEX);
770 }
771
772 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
773 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
774 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
775
776 /* Set the maximum frame size. */
777 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
778 val = mue_csr_read(sc, MUE_MAC_RX);
779 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
780 val |= MUE_MAC_RX_MAX_LEN(ETHER_MAX_LEN);
781 mue_csr_write(sc, MUE_MAC_RX, val);
782 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
783
784 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
785 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
786
787 /* Set default GPIO/LED settings only if no EEPROM is detected. */
788 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
789 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
790 MUE_SETBIT(sc, MUE_LED_CFG,
791 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
792 }
793
794 /* XXX We assume two LEDs at least when EEPROM is missing. */
795 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
796 !mue_eeprom_present(sc))
797 MUE_SETBIT(sc, MUE_HW_CFG,
798 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
799
800 return 0;
801 }
802
803 static void
804 mue_set_macaddr(struct mue_softc *sc)
805 {
806 struct ifnet *ifp = GET_IFP(sc);
807 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
808 uint32_t lo, hi;
809
810 lo = MUE_ENADDR_LO(enaddr);
811 hi = MUE_ENADDR_HI(enaddr);
812
813 mue_csr_write(sc, MUE_RX_ADDRL, lo);
814 mue_csr_write(sc, MUE_RX_ADDRH, hi);
815 }
816
817 static int
818 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
819 {
820 prop_data_t eaprop;
821 uint32_t low, high;
822
823 if (!(sc->mue_flags & LAN7500)) {
824 low = mue_csr_read(sc, MUE_RX_ADDRL);
825 high = mue_csr_read(sc, MUE_RX_ADDRH);
826 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
827 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
828 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
829 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
830 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
831 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
832 if (ETHER_IS_VALID(sc->mue_enaddr))
833 return 0;
834 else {
835 DPRINTF(sc, "registers: %s\n",
836 ether_sprintf(sc->mue_enaddr));
837 }
838 }
839
840 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
841 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
842 if (ETHER_IS_VALID(sc->mue_enaddr))
843 return 0;
844 else {
845 DPRINTF(sc, "EEPROM: %s\n",
846 ether_sprintf(sc->mue_enaddr));
847 }
848 }
849
850 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
851 ETHER_ADDR_LEN) == 0) {
852 if (ETHER_IS_VALID(sc->mue_enaddr))
853 return 0;
854 else {
855 DPRINTF(sc, "OTP: %s\n",
856 ether_sprintf(sc->mue_enaddr));
857 }
858 }
859
860 /*
861 * Other MD methods. This should be tried only if other methods fail.
862 * Otherwise, MAC address for internal device can be assinged to
863 * external devices on Raspberry Pi, for example.
864 */
865 eaprop = prop_dictionary_get(dict, "mac-address");
866 if (eaprop != NULL) {
867 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
868 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
869 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
870 ETHER_ADDR_LEN);
871 if (ETHER_IS_VALID(sc->mue_enaddr))
872 return 0;
873 else {
874 DPRINTF(sc, "prop_dictionary_get: %s\n",
875 ether_sprintf(sc->mue_enaddr));
876 }
877 }
878
879 return 1;
880 }
881
882
883 /*
884 * Probe for a Microchip chip. */
885 static int
886 mue_match(device_t parent, cfdata_t match, void *aux)
887 {
888 struct usb_attach_arg *uaa = aux;
889
890 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
891 }
892
893 static void
894 mue_attach(device_t parent, device_t self, void *aux)
895 {
896 struct mue_softc *sc = device_private(self);
897 prop_dictionary_t dict = device_properties(self);
898 struct usb_attach_arg *uaa = aux;
899 struct usbd_device *dev = uaa->uaa_device;
900 usb_interface_descriptor_t *id;
901 usb_endpoint_descriptor_t *ed;
902 char *devinfop;
903 struct mii_data *mii;
904 struct ifnet *ifp;
905 usbd_status err;
906 uint8_t i;
907 int s;
908
909 aprint_naive("\n");
910 aprint_normal("\n");
911
912 sc->mue_dev = self;
913 sc->mue_udev = dev;
914
915 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
916 aprint_normal_dev(self, "%s\n", devinfop);
917 usbd_devinfo_free(devinfop);
918
919 #define MUE_CONFIG_NO 1
920 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
921 if (err) {
922 aprint_error_dev(self, "failed to set configuration: %s\n",
923 usbd_errstr(err));
924 return;
925 }
926
927 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
928 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
929 usb_init_task(&sc->mue_stop_task, (void (*)(void *))mue_stop, sc, 0);
930
931 #define MUE_IFACE_IDX 0
932 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
933 if (err) {
934 aprint_error_dev(self, "failed to get interface handle: %s\n",
935 usbd_errstr(err));
936 return;
937 }
938
939 sc->mue_product = uaa->uaa_product;
940 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
941
942 /* Decide on what our bufsize will be. */
943 if (sc->mue_flags & LAN7500)
944 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
945 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
946 else
947 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
948 sc->mue_txbufsz = MUE_TX_BUFSIZE;
949
950 /* Find endpoints. */
951 id = usbd_get_interface_descriptor(sc->mue_iface);
952 for (i = 0; i < id->bNumEndpoints; i++) {
953 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
954 if (ed == NULL) {
955 aprint_error_dev(self, "failed to get ep %hhd\n", i);
956 return;
957 }
958 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
959 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
960 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
961 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
962 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
963 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
964 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
965 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
966 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
967 }
968 }
969 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
970 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
971 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
972
973 s = splnet();
974
975 sc->mue_phyno = 1;
976
977 if (mue_chip_init(sc)) {
978 aprint_error_dev(self, "failed to initialize chip\n");
979 splx(s);
980 return;
981 }
982
983 /* A Microchip chip was detected. Inform the world. */
984 if (sc->mue_flags & LAN7500)
985 aprint_normal_dev(self, "LAN7500\n");
986 else
987 aprint_normal_dev(self, "LAN7800\n");
988
989 if (mue_get_macaddr(sc, dict)) {
990 aprint_error_dev(self, "Ethernet address assigned randomly\n");
991 cprng_fast(sc->mue_enaddr, ETHER_ADDR_LEN);
992 sc->mue_enaddr[0] &= ~0x01; /* unicast */
993 sc->mue_enaddr[0] |= 0x02; /* locally administered */
994 }
995
996 aprint_normal_dev(self, "Ethernet address %s\n",
997 ether_sprintf(sc->mue_enaddr));
998
999 /* Initialize interface info.*/
1000 ifp = GET_IFP(sc);
1001 ifp->if_softc = sc;
1002 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
1003 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1004 ifp->if_init = mue_init;
1005 ifp->if_ioctl = mue_ioctl;
1006 ifp->if_start = mue_start;
1007 ifp->if_stop = mue_stop;
1008 ifp->if_watchdog = mue_watchdog;
1009
1010 IFQ_SET_READY(&ifp->if_snd);
1011
1012 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6;
1013
1014 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1015
1016 /* Initialize MII/media info. */
1017 mii = GET_MII(sc);
1018 mii->mii_ifp = ifp;
1019 mii->mii_readreg = mue_miibus_readreg;
1020 mii->mii_writereg = mue_miibus_writereg;
1021 mii->mii_statchg = mue_miibus_statchg;
1022 mii->mii_flags = MIIF_AUTOTSLEEP;
1023
1024 sc->mue_ec.ec_mii = mii;
1025 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1026 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1027
1028 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1029 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1030 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1031 } else
1032 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1033
1034 /* Attach the interface. */
1035 if_attach(ifp);
1036 ether_ifattach(ifp, sc->mue_enaddr);
1037
1038 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1039 RND_TYPE_NET, RND_FLAG_DEFAULT);
1040
1041 callout_init(&sc->mue_stat_ch, 0);
1042
1043 splx(s);
1044
1045 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1046 }
1047
1048 static int
1049 mue_detach(device_t self, int flags)
1050 {
1051 struct mue_softc *sc = device_private(self);
1052 struct ifnet *ifp = GET_IFP(sc);
1053 size_t i;
1054 int s;
1055
1056 sc->mue_dying = true;
1057
1058 callout_halt(&sc->mue_stat_ch, NULL);
1059
1060 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1061 if (sc->mue_ep[i] != NULL)
1062 usbd_abort_pipe(sc->mue_ep[i]);
1063
1064 /*
1065 * Remove any pending tasks. They cannot be executing because they run
1066 * in the same thread as detach.
1067 */
1068 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1069 NULL);
1070 usb_rem_task_wait(sc->mue_udev, &sc->mue_stop_task, USB_TASKQ_DRIVER,
1071 NULL);
1072
1073 s = splusb();
1074
1075 if (ifp->if_flags & IFF_RUNNING)
1076 mue_stop(ifp, 1);
1077
1078 rnd_detach_source(&sc->mue_rnd_source);
1079 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1080 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1081 if (ifp->if_softc != NULL) {
1082 ether_ifdetach(ifp);
1083 if_detach(ifp);
1084 }
1085
1086 if (--sc->mue_refcnt >= 0) {
1087 /* Wait for processes to go away. */
1088 usb_detach_waitold(sc->mue_dev);
1089 }
1090 splx(s);
1091
1092 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1093
1094 mutex_destroy(&sc->mue_mii_lock);
1095
1096 return 0;
1097 }
1098
1099 static int
1100 mue_activate(device_t self, enum devact act)
1101 {
1102 struct mue_softc *sc = device_private(self);
1103 struct ifnet *ifp = GET_IFP(sc);
1104
1105 switch (act) {
1106 case DVACT_DEACTIVATE:
1107 if_deactivate(ifp);
1108 sc->mue_dying = true;
1109 return 0;
1110 default:
1111 return EOPNOTSUPP;
1112 }
1113 return 0;
1114 }
1115
1116 static int
1117 mue_rx_list_init(struct mue_softc *sc)
1118 {
1119 struct mue_cdata *cd;
1120 struct mue_chain *c;
1121 size_t i;
1122 int err;
1123
1124 cd = &sc->mue_cdata;
1125 for (i = 0; i < __arraycount(cd->mue_rx_chain); i++) {
1126 c = &cd->mue_rx_chain[i];
1127 c->mue_sc = sc;
1128 c->mue_idx = i;
1129 if (c->mue_xfer == NULL) {
1130 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1131 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1132 if (err)
1133 return err;
1134 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1135 }
1136 }
1137
1138 return 0;
1139 }
1140
1141 static int
1142 mue_tx_list_init(struct mue_softc *sc)
1143 {
1144 struct mue_cdata *cd;
1145 struct mue_chain *c;
1146 size_t i;
1147 int err;
1148
1149 cd = &sc->mue_cdata;
1150 for (i = 0; i < __arraycount(cd->mue_tx_chain); i++) {
1151 c = &cd->mue_tx_chain[i];
1152 c->mue_sc = sc;
1153 c->mue_idx = i;
1154 if (c->mue_xfer == NULL) {
1155 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1156 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1157 &c->mue_xfer);
1158 if (err)
1159 return err;
1160 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1161 }
1162 }
1163
1164 return 0;
1165 }
1166
1167 static int
1168 mue_open_pipes(struct mue_softc *sc)
1169 {
1170 usbd_status err;
1171
1172 /* Open RX and TX pipes. */
1173 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1174 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1175 if (err) {
1176 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1177 return EIO;
1178 }
1179 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1180 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1181 if (err) {
1182 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1183 return EIO;
1184 }
1185 return 0;
1186 }
1187
1188 static void
1189 mue_start_rx(struct mue_softc *sc)
1190 {
1191 struct mue_chain *c;
1192 size_t i;
1193
1194 /* Start up the receive pipe. */
1195 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++) {
1196 c = &sc->mue_cdata.mue_rx_chain[i];
1197 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1198 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1199 usbd_transfer(c->mue_xfer);
1200 }
1201 }
1202
1203 static int
1204 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1205 {
1206 struct ifnet *ifp = GET_IFP(sc);
1207 struct mue_chain *c;
1208 usbd_status err;
1209 struct mue_txbuf_hdr hdr;
1210 int len;
1211
1212 c = &sc->mue_cdata.mue_tx_chain[idx];
1213
1214 hdr.tx_cmd_a = htole32((m->m_pkthdr.len & MUE_TX_CMD_A_LEN_MASK) |
1215 MUE_TX_CMD_A_FCS);
1216
1217 if (m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) {
1218 hdr.tx_cmd_a |= htole32(MUE_TX_CMD_A_LSO);
1219 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1220 hdr.tx_cmd_b = htole32(m->m_pkthdr.segsz <<
1221 MUE_TX_CMD_B_MSS_SHIFT);
1222 else
1223 hdr.tx_cmd_b = htole32(MUE_TX_MSS_MIN <<
1224 MUE_TX_CMD_B_MSS_SHIFT);
1225 hdr.tx_cmd_b &= htole32(MUE_TX_CMD_B_MSS_MASK);
1226 mue_tx_offload(sc, m);
1227 } else
1228 hdr.tx_cmd_b = 0;
1229
1230 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1231 len = sizeof(hdr);
1232
1233 KASSERTMSG((unsigned)(len + m->m_pkthdr.len) <= sc->mue_txbufsz,
1234 "%d <= %u", len + m->m_pkthdr.len, sc->mue_txbufsz);
1235
1236 m_copydata(m, 0, m->m_pkthdr.len, c->mue_buf + len);
1237 len += m->m_pkthdr.len;
1238
1239 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len,
1240 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1241
1242 /* Transmit */
1243 err = usbd_transfer(c->mue_xfer);
1244 if (__predict_false(err != USBD_IN_PROGRESS)) {
1245 DPRINTF(sc, "%s\n", usbd_errstr(err));
1246 mue_stop(ifp, 0);
1247 return EIO;
1248 }
1249
1250 sc->mue_cdata.mue_tx_cnt++;
1251
1252 return 0;
1253 }
1254
1255 static void
1256 mue_tx_offload(struct mue_softc *sc, struct mbuf *m)
1257 {
1258 struct ether_header *eh;
1259 struct ip *ip;
1260 struct ip6_hdr *ip6;
1261 int offset;
1262 bool v4;
1263
1264 eh = mtod(m, struct ether_header *);
1265 switch (htons(eh->ether_type)) {
1266 case ETHERTYPE_IP:
1267 case ETHERTYPE_IPV6:
1268 offset = ETHER_HDR_LEN;
1269 break;
1270 case ETHERTYPE_VLAN:
1271 /* XXX not yet supported */
1272 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1273 break;
1274 default:
1275 /* XXX */
1276 panic("%s: unsupported ethertype\n", __func__);
1277 /* NOTREACHED */
1278 }
1279
1280 v4 = (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
1281
1282 #ifdef DIAGNOSTIC /* XXX */
1283 int hlen = offset;
1284 if (v4)
1285 hlen += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data);
1286 else
1287 hlen += M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data);
1288 KASSERT(m->m_len >= (int)(hlen + sizeof(struct tcphdr)));
1289 #endif
1290
1291 /* Packet length should be cleared. */
1292 if (v4) {
1293 ip = (void *)(mtod(m, char *) + offset);
1294 ip->ip_len = 0;
1295 } else {
1296 ip6 = (void *)(mtod(m, char *) + offset);
1297 ip6->ip6_plen = 0;
1298 }
1299 }
1300
1301 static void
1302 mue_setmulti(struct mue_softc *sc)
1303 {
1304 struct ifnet *ifp = GET_IFP(sc);
1305 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1306 struct ether_multi *enm;
1307 struct ether_multistep step;
1308 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1309 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1310 uint32_t reg, rxfilt, h, hireg, loreg;
1311 size_t i;
1312
1313 if (sc->mue_dying)
1314 return;
1315
1316 /* Clear perfect filter and hash tables. */
1317 memset(pfiltbl, 0, sizeof(pfiltbl));
1318 memset(hashtbl, 0, sizeof(hashtbl));
1319
1320 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1321 rxfilt = mue_csr_read(sc, reg);
1322 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1323 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1324
1325 /* Always accept broadcast frames. */
1326 rxfilt |= MUE_RFE_CTL_BROADCAST;
1327
1328 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1329 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1330 if (ifp->if_flags & IFF_PROMISC) {
1331 rxfilt |= MUE_RFE_CTL_UNICAST;
1332 DPRINTF(sc, "promisc\n");
1333 } else {
1334 DPRINTF(sc, "allmulti\n");
1335 }
1336 } else {
1337 /* Now program new ones. */
1338 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1339 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1340 i = 1;
1341 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1342 while (enm != NULL) {
1343 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1344 ETHER_ADDR_LEN)) {
1345 memset(pfiltbl, 0, sizeof(pfiltbl));
1346 memset(hashtbl, 0, sizeof(hashtbl));
1347 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1348 goto allmulti;
1349 }
1350 if (i < MUE_NUM_ADDR_FILTX) {
1351 /* Use perfect address table if possible. */
1352 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1353 MUE_ADDR_FILTX_VALID;
1354 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1355 } else {
1356 /* Otherwise, use hash table. */
1357 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1358 h = (ether_crc32_be(enm->enm_addrlo,
1359 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1360 hashtbl[h / 32] |= 1 << (h % 32);
1361 }
1362 i++;
1363 ETHER_NEXT_MULTI(step, enm);
1364 }
1365 rxfilt |= MUE_RFE_CTL_PERFECT;
1366 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH) {
1367 DPRINTF(sc, "perfect filter and hash tables\n");
1368 } else {
1369 DPRINTF(sc, "perfect filter\n");
1370 }
1371 }
1372
1373 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1374 hireg = (sc->mue_flags & LAN7500) ?
1375 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1376 loreg = hireg + 4;
1377 mue_csr_write(sc, hireg, 0);
1378 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1379 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1380 }
1381
1382 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1383 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1384
1385 mue_csr_write(sc, reg, rxfilt);
1386 }
1387
1388 static void
1389 mue_sethwcsum(struct mue_softc *sc)
1390 {
1391 struct ifnet *ifp = GET_IFP(sc);
1392 uint32_t reg, val;
1393
1394 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1395 val = mue_csr_read(sc, reg);
1396
1397 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) {
1398 DPRINTF(sc, "enabled\n");;
1399 val |= MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE;
1400 val |= MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE;
1401 } else {
1402 DPRINTF(sc, "disabled\n");;
1403 val &=
1404 ~(MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE);
1405 val &=
1406 ~(MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE);
1407 }
1408
1409 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1410
1411 mue_csr_write(sc, reg, val);
1412 }
1413
1414
1415 static void
1416 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1417 {
1418 struct mue_chain *c = (struct mue_chain *)priv;
1419 struct mue_softc *sc = c->mue_sc;
1420 struct ifnet *ifp = GET_IFP(sc);
1421 struct mbuf *m;
1422 struct mue_rxbuf_hdr *hdrp;
1423 uint32_t rx_cmd_a, total_len;
1424 uint16_t pktlen;
1425 int s;
1426 char *buf = c->mue_buf;
1427
1428 if (__predict_false(sc->mue_dying)) {
1429 DPRINTF(sc, "dying\n");
1430 return;
1431 }
1432
1433 if (__predict_false(!(ifp->if_flags & IFF_RUNNING))) {
1434 DPRINTF(sc, "not running\n");
1435 return;
1436 }
1437
1438 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1439 DPRINTF(sc, "%s\n", usbd_errstr(status));
1440 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1441 return;
1442 if (usbd_ratecheck(&sc->mue_rx_notice))
1443 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1444 if (status == USBD_STALLED)
1445 usbd_clear_endpoint_stall_async(
1446 sc->mue_ep[MUE_ENDPT_RX]);
1447 goto done;
1448 }
1449
1450 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
1451
1452 KASSERTMSG(total_len <= sc->mue_rxbufsz, "%d <= %u",
1453 total_len, sc->mue_rxbufsz);
1454
1455 do {
1456 if (__predict_false(total_len < sizeof(*hdrp))) {
1457 MUE_PRINTF(sc, "packet length %u too short\n",
1458 total_len);
1459 ifp->if_ierrors++;
1460 goto done;
1461 }
1462
1463 hdrp = (struct mue_rxbuf_hdr *)buf;
1464 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1465
1466 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_RED)) {
1467 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1468 ifp->if_ierrors++;
1469 goto done;
1470 }
1471
1472 /* XXX not yet */
1473 KASSERT((rx_cmd_a & MUE_RX_CMD_A_ICSM) == 0);
1474
1475 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1476 if (sc->mue_flags & LAN7500)
1477 pktlen -= 2;
1478
1479 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1480 pktlen > MCLBYTES - ETHER_ALIGN ||
1481 pktlen + sizeof(*hdrp) > total_len)) {
1482 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1483 ifp->if_ierrors++;
1484 goto done;
1485 }
1486
1487 m = mue_newbuf();
1488 if (__predict_false(m == NULL)) {
1489 MUE_PRINTF(sc, "failed to allocate mbuf\n");
1490 ifp->if_ierrors++;
1491 goto done;
1492 }
1493
1494 m_set_rcvif(m, ifp);
1495 m->m_pkthdr.len = m->m_len = pktlen;
1496 m->m_flags |= M_HASFCS;
1497 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1498
1499 /* Attention: sizeof(hdr) = 10 */
1500 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1501 if (pktlen > total_len)
1502 pktlen = total_len;
1503 total_len -= pktlen;
1504 buf += pktlen;
1505
1506 s = splnet();
1507 if_percpuq_enqueue(ifp->if_percpuq, m);
1508 splx(s);
1509 } while (total_len > 0);
1510
1511 done:
1512 /* Setup new transfer. */
1513 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1514 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1515 usbd_transfer(xfer);
1516 }
1517
1518 static void
1519 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1520 {
1521 struct mue_chain *c = priv;
1522 struct mue_softc *sc = c->mue_sc;
1523 struct ifnet *ifp = GET_IFP(sc);
1524 int s;
1525
1526 if (__predict_false(sc->mue_dying))
1527 return;
1528
1529 s = splnet();
1530
1531 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1532 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1533 splx(s);
1534 return;
1535 }
1536 ifp->if_oerrors++;
1537 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1538 if (status == USBD_STALLED)
1539 usbd_clear_endpoint_stall_async(
1540 sc->mue_ep[MUE_ENDPT_TX]);
1541 splx(s);
1542 return;
1543 }
1544
1545 ifp->if_timer = 0;
1546 ifp->if_flags &= ~IFF_OACTIVE;
1547
1548 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1549 mue_start(ifp);
1550
1551 ifp->if_opackets++;
1552 splx(s);
1553 }
1554
1555 static int
1556 mue_init(struct ifnet *ifp)
1557 {
1558 struct mue_softc *sc = ifp->if_softc;
1559 int s;
1560
1561 if (sc->mue_dying) {
1562 DPRINTF(sc, "dying\n");
1563 return EIO;
1564 }
1565
1566 s = splnet();
1567
1568 /* Cancel pending I/O and free all TX/RX buffers. */
1569 if (ifp->if_flags & IFF_RUNNING)
1570 mue_stop(ifp, 1);
1571
1572 mue_reset(sc);
1573
1574 /* Set MAC address. */
1575 mue_set_macaddr(sc);
1576
1577 /* Load the multicast filter. */
1578 mue_setmulti(sc);
1579
1580 /* TCP/UDP checksum offload engines. */
1581 mue_sethwcsum(sc);
1582
1583 if (mue_open_pipes(sc)) {
1584 splx(s);
1585 return EIO;
1586 }
1587
1588 /* Init RX ring. */
1589 if (mue_rx_list_init(sc)) {
1590 MUE_PRINTF(sc, "failed to init rx list\n");
1591 splx(s);
1592 return ENOBUFS;
1593 }
1594
1595 /* Init TX ring. */
1596 if (mue_tx_list_init(sc)) {
1597 MUE_PRINTF(sc, "failed to init tx list\n");
1598 splx(s);
1599 return ENOBUFS;
1600 }
1601
1602 mue_start_rx(sc);
1603
1604 ifp->if_flags |= IFF_RUNNING;
1605 ifp->if_flags &= ~IFF_OACTIVE;
1606
1607 splx(s);
1608
1609 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1610
1611 return 0;
1612 }
1613
1614 static int
1615 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1616 {
1617 struct mue_softc *sc = ifp->if_softc;
1618 struct ifreq /*const*/ *ifr = data;
1619 int s, error = 0;
1620
1621 s = splnet();
1622
1623 switch(cmd) {
1624 case SIOCSIFFLAGS:
1625 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1626 break;
1627
1628 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1629 case IFF_RUNNING:
1630 mue_stop(ifp, 1);
1631 break;
1632 case IFF_UP:
1633 mue_init(ifp);
1634 break;
1635 case IFF_UP | IFF_RUNNING:
1636 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1637 mue_setmulti(sc);
1638 else
1639 mue_init(ifp);
1640 break;
1641 }
1642 sc->mue_if_flags = ifp->if_flags;
1643 break;
1644 case SIOCGIFMEDIA:
1645 case SIOCSIFMEDIA:
1646 error = ifmedia_ioctl(ifp, ifr, &sc->mue_mii.mii_media, cmd);
1647 break;
1648 default:
1649 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1650 break;
1651 error = 0;
1652 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI)
1653 mue_setmulti(sc);
1654 break;
1655 }
1656 splx(s);
1657
1658 return error;
1659 }
1660
1661 static void
1662 mue_watchdog(struct ifnet *ifp)
1663 {
1664 struct mue_softc *sc = ifp->if_softc;
1665 struct mue_chain *c;
1666 usbd_status stat;
1667 int s;
1668
1669 ifp->if_oerrors++;
1670 MUE_PRINTF(sc, "timed out\n");
1671
1672 s = splusb();
1673 c = &sc->mue_cdata.mue_tx_chain[0];
1674 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1675 mue_txeof(c->mue_xfer, c, stat);
1676
1677 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1678 mue_start(ifp);
1679 splx(s);
1680 }
1681
1682 static void
1683 mue_reset(struct mue_softc *sc)
1684 {
1685 if (sc->mue_dying)
1686 return;
1687
1688 /* Wait a little while for the chip to get its brains in order. */
1689 usbd_delay_ms(sc->mue_udev, 1);
1690
1691 // mue_chip_init(sc); /* XXX */
1692 }
1693
1694 static void
1695 mue_start(struct ifnet *ifp)
1696 {
1697 struct mue_softc *sc = ifp->if_softc;
1698 struct mbuf *m;
1699
1700 if (__predict_false(!sc->mue_link)) {
1701 DPRINTF(sc, "no link\n");
1702 return;
1703 }
1704
1705 if (__predict_false((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING))
1706 != IFF_RUNNING)) {
1707 DPRINTF(sc, "not ready\n");
1708 return;
1709 }
1710
1711 IFQ_POLL(&ifp->if_snd, m);
1712 if (m == NULL)
1713 return;
1714
1715 if (__predict_false(mue_encap(sc, m, 0))) {
1716 DPRINTF(sc, "encap failed\n");
1717 ifp->if_flags |= IFF_OACTIVE;
1718 return;
1719 }
1720 IFQ_DEQUEUE(&ifp->if_snd, m);
1721
1722 bpf_mtap(ifp, m, BPF_D_OUT);
1723 m_freem(m);
1724
1725 ifp->if_flags |= IFF_OACTIVE;
1726
1727 /* Set a timeout in case the chip goes out to lunch. */
1728 ifp->if_timer = 5;
1729 }
1730
1731 static void
1732 mue_stop(struct ifnet *ifp, int disable __unused)
1733 {
1734 struct mue_softc *sc = ifp->if_softc;
1735 usbd_status err;
1736 size_t i;
1737
1738 mue_reset(sc);
1739
1740 ifp->if_timer = 0;
1741 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1742
1743 callout_stop(&sc->mue_stat_ch);
1744
1745 /* Stop transfers. */
1746 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1747 if (sc->mue_ep[i] != NULL) {
1748 err = usbd_abort_pipe(sc->mue_ep[i]);
1749 if (err)
1750 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1751 i, usbd_errstr(err));
1752 }
1753
1754 /* Free RX resources. */
1755 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++)
1756 if (sc->mue_cdata.mue_rx_chain[i].mue_xfer != NULL) {
1757 usbd_destroy_xfer(
1758 sc->mue_cdata.mue_rx_chain[i].mue_xfer);
1759 sc->mue_cdata.mue_rx_chain[i].mue_xfer = NULL;
1760 }
1761
1762 /* Free TX resources. */
1763 for (i = 0; i < __arraycount(sc->mue_cdata.mue_tx_chain); i++)
1764 if (sc->mue_cdata.mue_tx_chain[i].mue_xfer != NULL) {
1765 usbd_destroy_xfer(
1766 sc->mue_cdata.mue_tx_chain[i].mue_xfer);
1767 sc->mue_cdata.mue_tx_chain[i].mue_xfer = NULL;
1768 }
1769
1770 /* Close pipes */
1771 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1772 if (sc->mue_ep[i] != NULL) {
1773 err = usbd_close_pipe(sc->mue_ep[i]);
1774 if (err)
1775 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1776 i, usbd_errstr(err));
1777 sc->mue_ep[i] = NULL;
1778 }
1779
1780 sc->mue_link = 0; /* XXX */
1781
1782 DPRINTF(sc, "done\n");
1783 }
1784
1785 static void
1786 mue_tick(void *xsc)
1787 {
1788 struct mue_softc *sc = xsc;
1789
1790 if (sc == NULL)
1791 return;
1792
1793 if (sc->mue_dying)
1794 return;
1795
1796 /* Perform periodic stuff in process context. */
1797 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1798 }
1799
1800 static void
1801 mue_tick_task(void *xsc)
1802 {
1803 struct mue_softc *sc = xsc;
1804 struct ifnet *ifp = GET_IFP(sc);
1805 struct mii_data *mii = GET_MII(sc);
1806 int s;
1807
1808 if (sc == NULL)
1809 return;
1810
1811 if (sc->mue_dying)
1812 return;
1813
1814 s = splnet();
1815 mii_tick(mii);
1816 if (sc->mue_link == 0)
1817 mue_miibus_statchg(ifp);
1818 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1819 splx(s);
1820 }
1821
1822 static struct mbuf *
1823 mue_newbuf(void)
1824 {
1825 struct mbuf *m;
1826
1827 MGETHDR(m, M_DONTWAIT, MT_DATA);
1828 if (__predict_false(m == NULL))
1829 return NULL;
1830
1831 MCLGET(m, M_DONTWAIT);
1832 if (__predict_false(!(m->m_flags & M_EXT))) {
1833 m_freem(m);
1834 return NULL;
1835 }
1836
1837 m_adj(m, ETHER_ALIGN);
1838
1839 return m;
1840 }
1841