if_mue.c revision 1.22 1 /* $NetBSD: if_mue.c,v 1.22 2018/12/11 13:35:02 rin Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.22 2018/12/11 13:35:02 rin Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/mutex.h>
36 #include <sys/kernel.h>
37 #include <sys/proc.h>
38 #include <sys/socket.h>
39
40 #include <sys/device.h>
41
42 #include <sys/rndsource.h>
43
44 #include <net/if.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_ether.h>
48
49 #include <net/bpf.h>
50
51 #include <netinet/if_inarp.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h> /* XXX for struct ip */
54 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
55
56 #include <dev/mii/mii.h>
57 #include <dev/mii/miivar.h>
58
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
61 #include <dev/usb/usbdi_util.h>
62 #include <dev/usb/usbdivar.h>
63 #include <dev/usb/usbdevs.h>
64
65 #include <dev/usb/if_muereg.h>
66 #include <dev/usb/if_muevar.h>
67
68 #define MUE_PRINTF(sc, fmt, args...) \
69 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
70
71 #ifdef USB_DEBUG
72 int muedebug = 0;
73 #define DPRINTF(sc, fmt, args...) \
74 do { \
75 if (muedebug) \
76 MUE_PRINTF(sc, fmt, ##args); \
77 } while (0 /* CONSTCOND */)
78 #else
79 #define DPRINTF(sc, fmt, args...) /* nothing */
80 #endif
81
82 /*
83 * Various supported device vendors/products.
84 */
85 struct mue_type {
86 struct usb_devno mue_dev;
87 uint16_t mue_flags;
88 #define LAN7500 0x0001 /* LAN7500 */
89 };
90
91 const struct mue_type mue_devs[] = {
92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
97 };
98
99 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
100 uaa->uaa_vendor, uaa->uaa_product))
101
102 #define MUE_ENADDR_LO(enaddr) \
103 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
104 #define MUE_ENADDR_HI(enaddr) \
105 ((enaddr[5] << 8) | enaddr[4])
106
107 static int mue_match(device_t, cfdata_t, void *);
108 static void mue_attach(device_t, device_t, void *);
109 static int mue_detach(device_t, int);
110 static int mue_activate(device_t, enum devact);
111
112 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
113 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
114 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
115 uint32_t, uint32_t);
116
117 static void mue_lock_mii(struct mue_softc *);
118 static void mue_unlock_mii(struct mue_softc *);
119
120 static int mue_miibus_readreg(device_t, int, int);
121 static void mue_miibus_writereg(device_t, int, int, int);
122 static void mue_miibus_statchg(struct ifnet *);
123 static int mue_ifmedia_upd(struct ifnet *);
124 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125
126 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
127 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
128 static bool mue_eeprom_present(struct mue_softc *sc);
129
130 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
131 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
132
133 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
134 uint32_t, uint32_t *);
135
136 static void mue_init_ltm(struct mue_softc *);
137
138 static int mue_chip_init(struct mue_softc *);
139
140 static void mue_set_macaddr(struct mue_softc *);
141 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
142
143 static int mue_rx_list_init(struct mue_softc *);
144 static int mue_tx_list_init(struct mue_softc *);
145 static int mue_open_pipes(struct mue_softc *);
146 static void mue_startup_rx_pipes(struct mue_softc *);
147
148 static int mue_encap(struct mue_softc *, struct mbuf *, int);
149 static void mue_tx_offload(struct mue_softc *, struct mbuf *);
150
151 static void mue_setmulti(struct mue_softc *);
152 static void mue_sethwcsum(struct mue_softc *);
153 static void mue_setmtu(struct mue_softc *);
154
155 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
156 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
157
158 static int mue_init(struct ifnet *);
159 static int mue_ioctl(struct ifnet *, u_long, void *);
160 static void mue_watchdog(struct ifnet *);
161 static void mue_reset(struct mue_softc *);
162 static void mue_start(struct ifnet *);
163 static void mue_stop(struct ifnet *, int);
164 static void mue_tick(void *);
165 static void mue_tick_task(void *);
166
167 static struct mbuf *mue_newbuf(void);
168
169 #define MUE_SETBIT(sc, reg, x) \
170 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
171
172 #define MUE_CLRBIT(sc, reg, x) \
173 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
174
175 #define MUE_WAIT_SET(sc, reg, set, fail) \
176 mue_wait_for_bits(sc, reg, set, ~0, fail)
177
178 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
179 mue_wait_for_bits(sc, reg, 0, clear, fail)
180
181 #define ETHER_IS_VALID(addr) \
182 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
183
184 #define ETHER_IS_ZERO(addr) \
185 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
186
187 #define ETHER_ALIGN 2
188
189 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
190 mue_detach, mue_activate);
191
192 static uint32_t
193 mue_csr_read(struct mue_softc *sc, uint32_t reg)
194 {
195 usb_device_request_t req;
196 usbd_status err;
197 uDWord val;
198
199 if (sc->mue_dying)
200 return 0;
201
202 USETDW(val, 0);
203 req.bmRequestType = UT_READ_VENDOR_DEVICE;
204 req.bRequest = MUE_UR_READREG;
205 USETW(req.wValue, 0);
206 USETW(req.wIndex, reg);
207 USETW(req.wLength, 4);
208
209 err = usbd_do_request(sc->mue_udev, &req, &val);
210 if (err) {
211 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
212 return 0;
213 }
214
215 return UGETDW(val);
216 }
217
218 static int
219 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
220 {
221 usb_device_request_t req;
222 usbd_status err;
223 uDWord val;
224
225 if (sc->mue_dying)
226 return 0;
227
228 USETDW(val, aval);
229 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
230 req.bRequest = MUE_UR_WRITEREG;
231 USETW(req.wValue, 0);
232 USETW(req.wIndex, reg);
233 USETW(req.wLength, 4);
234
235 err = usbd_do_request(sc->mue_udev, &req, &val);
236 if (err) {
237 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
238 return -1;
239 }
240
241 return 0;
242 }
243
244 static int
245 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
246 uint32_t set, uint32_t clear, uint32_t fail)
247 {
248 uint32_t val;
249 int ntries;
250
251 for (ntries = 0; ntries < 1000; ntries++) {
252 val = mue_csr_read(sc, reg);
253 if ((val & set) || !(val & clear))
254 return 0;
255 if (val & fail)
256 return 1;
257 usbd_delay_ms(sc->mue_udev, 1);
258 }
259
260 return 1;
261 }
262
263 /*
264 * Get exclusive access to the MII registers.
265 */
266 static void
267 mue_lock_mii(struct mue_softc *sc)
268 {
269 sc->mue_refcnt++;
270 mutex_enter(&sc->mue_mii_lock);
271 }
272
273 static void
274 mue_unlock_mii(struct mue_softc *sc)
275 {
276 mutex_exit(&sc->mue_mii_lock);
277 if (--sc->mue_refcnt < 0)
278 usb_detach_wakeupold(sc->mue_dev);
279 }
280
281 static int
282 mue_miibus_readreg(device_t dev, int phy, int reg)
283 {
284 struct mue_softc *sc = device_private(dev);
285 uint32_t val;
286
287 if (sc->mue_dying) {
288 DPRINTF(sc, "dying\n");
289 return 0;
290 }
291
292 if (sc->mue_phyno != phy)
293 return 0;
294
295 mue_lock_mii(sc);
296 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
297 mue_unlock_mii(sc);
298 MUE_PRINTF(sc, "not ready\n");
299 return -1;
300 }
301
302 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
303 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
304 MUE_MII_ACCESS_PHYADDR(phy));
305
306 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
307 mue_unlock_mii(sc);
308 MUE_PRINTF(sc, "timed out\n");
309 return -1;
310 }
311
312 val = mue_csr_read(sc, MUE_MII_DATA);
313 mue_unlock_mii(sc);
314 return val & 0xffff;
315 }
316
317 static void
318 mue_miibus_writereg(device_t dev, int phy, int reg, int data)
319 {
320 struct mue_softc *sc = device_private(dev);
321
322 if (sc->mue_dying) {
323 DPRINTF(sc, "dying\n");
324 return;
325 }
326
327 if (sc->mue_phyno != phy) {
328 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
329 sc->mue_phyno, phy);
330 return;
331 }
332
333 mue_lock_mii(sc);
334 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
335 mue_unlock_mii(sc);
336 MUE_PRINTF(sc, "not ready\n");
337 return;
338 }
339
340 mue_csr_write(sc, MUE_MII_DATA, data);
341 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
342 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
343 MUE_MII_ACCESS_PHYADDR(phy));
344
345 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0))
346 MUE_PRINTF(sc, "timed out\n");
347
348 mue_unlock_mii(sc);
349 }
350
351 static void
352 mue_miibus_statchg(struct ifnet *ifp)
353 {
354 struct mue_softc *sc = ifp->if_softc;
355 struct mii_data *mii = GET_MII(sc);
356 uint32_t flow, threshold;
357
358 if (mii == NULL || ifp == NULL || (ifp->if_flags & IFF_RUNNING) == 0) {
359 DPRINTF(sc, "not ready\n");
360 return;
361 }
362
363 sc->mue_link = 0;
364 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
365 (IFM_ACTIVE | IFM_AVALID)) {
366 switch (IFM_SUBTYPE(mii->mii_media_active)) {
367 case IFM_10_T:
368 case IFM_100_TX:
369 case IFM_1000_T:
370 sc->mue_link++;
371 break;
372 default:
373 break;
374 }
375 }
376
377 /* Lost link, do nothing. */
378 if (sc->mue_link == 0) {
379 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
380 return;
381 }
382
383 if (!(sc->mue_flags & LAN7500)) {
384 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
385 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
386 /* Disable U2 and enable U1. */
387 MUE_CLRBIT(sc, MUE_USB_CFG1,
388 MUE_USB_CFG1_DEV_U2_INIT_EN);
389 MUE_SETBIT(sc, MUE_USB_CFG1,
390 MUE_USB_CFG1_DEV_U1_INIT_EN);
391 } else {
392 /* Enable U1 and U2. */
393 MUE_SETBIT(sc, MUE_USB_CFG1,
394 MUE_USB_CFG1_DEV_U1_INIT_EN |
395 MUE_USB_CFG1_DEV_U2_INIT_EN);
396 }
397 }
398 }
399
400 flow = 0;
401 /* XXX Linux does not check IFM_FDX flag for 7800. */
402 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
403 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
404 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
405 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
406 flow |= MUE_FLOW_RX_FCEN;
407 }
408
409 /* XXX Magic numbers taken from Linux driver. */
410 if (sc->mue_flags & LAN7500)
411 threshold = 0x820;
412 else
413 switch (sc->mue_udev->ud_speed) {
414 case USB_SPEED_SUPER:
415 threshold = 0x817;
416 break;
417 case USB_SPEED_HIGH:
418 threshold = 0x211;
419 break;
420 default:
421 threshold = 0;
422 break;
423 }
424
425 /* Threshold value should be set before enabling flow. */
426 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
427 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
428 mue_csr_write(sc, MUE_FLOW, flow);
429
430 DPRINTF(sc, "done\n");
431 }
432
433 /*
434 * Set media options.
435 */
436 static int
437 mue_ifmedia_upd(struct ifnet *ifp)
438 {
439 struct mue_softc *sc = ifp->if_softc;
440 struct mii_data *mii = GET_MII(sc);
441
442 sc->mue_link = 0; /* XXX */
443
444 if (mii->mii_instance) {
445 struct mii_softc *miisc;
446 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
447 mii_phy_reset(miisc);
448 }
449 return mii_mediachg(mii);
450 }
451
452 /*
453 * Report current media status.
454 */
455 static void
456 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
457 {
458 struct mue_softc *sc = ifp->if_softc;
459 struct mii_data *mii = GET_MII(sc);
460
461 mii_pollstat(mii);
462 ifmr->ifm_active = mii->mii_media_active;
463 ifmr->ifm_status = mii->mii_media_status;
464 }
465
466 static uint8_t
467 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
468 {
469 uint32_t val;
470
471 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
472 MUE_PRINTF(sc, "not ready\n");
473 return ETIMEDOUT;
474 }
475
476 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
477 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
478 off);
479
480 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
481 MUE_E2P_CMD_TIMEOUT)) {
482 MUE_PRINTF(sc, "timed out\n");
483 return ETIMEDOUT;
484 }
485
486 val = mue_csr_read(sc, MUE_E2P_DATA);
487 *dest = val & 0xff;
488
489 return 0;
490 }
491
492 static int
493 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
494 {
495 uint32_t val = 0; /* XXX gcc */
496 uint8_t byte;
497 int i, err;
498
499 /*
500 * EEPROM pins are muxed with the LED function on LAN7800 device.
501 */
502 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
503 val = mue_csr_read(sc, MUE_HW_CFG);
504 mue_csr_write(sc, MUE_HW_CFG,
505 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
506 }
507
508 for (i = 0; i < cnt; i++) {
509 err = mue_eeprom_getbyte(sc, off + i, &byte);
510 if (err)
511 break;
512 *(dest + i) = byte;
513 }
514
515 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
516 mue_csr_write(sc, MUE_HW_CFG, val);
517
518 return err ? 1 : 0;
519 }
520
521 static bool
522 mue_eeprom_present(struct mue_softc *sc)
523 {
524 uint32_t val;
525 uint8_t sig;
526 int ret;
527
528 if (sc->mue_flags & LAN7500) {
529 val = mue_csr_read(sc, MUE_E2P_CMD);
530 return val & MUE_E2P_CMD_LOADED;
531 } else {
532 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
533 return (ret == 0) && (sig == MUE_E2P_IND);
534 }
535 }
536
537 static int
538 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
539 {
540 uint32_t val;
541 int i, err;
542
543 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
544
545 /* Checking if bit is set. */
546 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
547 /* Clear it, then wait for it to be cleared. */
548 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
549 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
550 0);
551 if (err) {
552 MUE_PRINTF(sc, "not ready\n");
553 return 1;
554 }
555 }
556
557 /* Start reading the bytes, one at a time. */
558 for (i = 0; i < cnt; i++) {
559 mue_csr_write(sc, MUE_OTP_ADDR1,
560 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
561 mue_csr_write(sc, MUE_OTP_ADDR2,
562 ((off + i) & MUE_OTP_ADDR2_MASK));
563 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
564 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
565
566 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
567 if (err) {
568 MUE_PRINTF(sc, "timed out\n");
569 return 1;
570 }
571 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
572 *(dest + i) = (uint8_t)(val & 0xff);
573 }
574
575 return 0;
576 }
577
578 static int
579 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
580 {
581 uint8_t sig;
582 int err;
583
584 if (sc->mue_flags & LAN7500)
585 return 1;
586
587 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
588 if (err)
589 return 1;
590 switch (sig) {
591 case MUE_OTP_IND_1:
592 break;
593 case MUE_OTP_IND_2:
594 off += 0x100;
595 break;
596 default:
597 DPRINTF(sc, "OTP not found\n");
598 return 1;
599 }
600 err = mue_read_otp_raw(sc, dest, off, cnt);
601 return err;
602 }
603
604 static void
605 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
606 uint32_t cnt, uint32_t *data)
607 {
608 uint32_t i;
609
610 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
611 MUE_PRINTF(sc, "not ready\n");
612 return;
613 }
614
615 mue_csr_write(sc, MUE_DP_SEL,
616 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
617
618 for (i = 0; i < cnt; i++) {
619 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
620 mue_csr_write(sc, MUE_DP_DATA, data[i]);
621 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
622 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
623 MUE_PRINTF(sc, "timed out\n");
624 return;
625 }
626 }
627 }
628
629 static void
630 mue_init_ltm(struct mue_softc *sc)
631 {
632 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
633 uint8_t temp[2];
634 size_t i;
635
636 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
637 if (mue_eeprom_present(sc) &&
638 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
639 if (temp[0] != sizeof(idx)) {
640 DPRINTF(sc, "EEPROM: unexpected size\n");
641 goto done;
642 }
643 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
644 sizeof(idx))) {
645 DPRINTF(sc, "EEPROM: failed to read\n");
646 goto done;
647 }
648 DPRINTF(sc, "success\n");
649 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
650 if (temp[0] != sizeof(idx)) {
651 DPRINTF(sc, "OTP: unexpected size\n");
652 goto done;
653 }
654 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
655 sizeof(idx))) {
656 DPRINTF(sc, "OTP: failed to read\n");
657 goto done;
658 }
659 DPRINTF(sc, "success\n");
660 } else {
661 DPRINTF(sc, "nothing to do\n");
662 }
663 } else {
664 DPRINTF(sc, "nothing to do\n");
665 }
666 done:
667 for (i = 0; i < __arraycount(idx); i++)
668 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
669 }
670
671 static int
672 mue_chip_init(struct mue_softc *sc)
673 {
674 uint32_t val;
675
676 if ((sc->mue_flags & LAN7500) &&
677 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
678 MUE_PRINTF(sc, "not ready\n");
679 return ETIMEDOUT;
680 }
681
682 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
683 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
684 MUE_PRINTF(sc, "timed out\n");
685 return ETIMEDOUT;
686 }
687
688 /* Respond to the IN token with a NAK. */
689 if (sc->mue_flags & LAN7500)
690 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
691 else
692 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
693
694 if (sc->mue_flags & LAN7500) {
695 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
696 val = MUE_7500_HS_RX_BUFSIZE /
697 MUE_HS_USB_PKT_SIZE;
698 else
699 val = MUE_7500_FS_RX_BUFSIZE /
700 MUE_FS_USB_PKT_SIZE;
701 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
702 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
703 MUE_7500_DEFAULT_BULKIN_DELAY);
704
705 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
706
707 /* Set FIFO sizes. */
708 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
709 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
710 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
711 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
712 } else {
713 /* Init LTM. */
714 mue_init_ltm(sc);
715
716 val = MUE_7800_RX_BUFSIZE;
717 switch (sc->mue_udev->ud_speed) {
718 case USB_SPEED_SUPER:
719 val /= MUE_SS_USB_PKT_SIZE;
720 break;
721 case USB_SPEED_HIGH:
722 val /= MUE_HS_USB_PKT_SIZE;
723 break;
724 default:
725 val /= MUE_FS_USB_PKT_SIZE;
726 break;
727 }
728 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
729 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
730 MUE_7800_DEFAULT_BULKIN_DELAY);
731
732 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
733 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
734
735 /*
736 * Set FCL's RX and TX FIFO sizes: according to data sheet this
737 * is already the default value. But we initialize it to the
738 * same value anyways, as that's what the Linux driver does.
739 */
740 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
741 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
742 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
743 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
744 }
745
746 /* Enabling interrupts. */
747 mue_csr_write(sc, MUE_INT_STATUS, ~0);
748
749 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
750 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
751 mue_csr_write(sc, MUE_FLOW, 0);
752
753 /* Reset PHY. */
754 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
755 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
756 MUE_PRINTF(sc, "PHY not ready\n");
757 return ETIMEDOUT;
758 }
759
760 /* LAN7801 only has RGMII mode. */
761 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
762 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
763
764 if ((sc->mue_flags & LAN7500) ||
765 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
766 !mue_eeprom_present(sc))) {
767 /* Allow MAC to detect speed and duplex from PHY. */
768 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
769 MUE_MAC_CR_AUTO_DUPLEX);
770 }
771
772 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
773 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
774 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
775
776 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
777 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
778
779 /* Set default GPIO/LED settings only if no EEPROM is detected. */
780 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
781 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
782 MUE_SETBIT(sc, MUE_LED_CFG,
783 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
784 }
785
786 /* XXX We assume two LEDs at least when EEPROM is missing. */
787 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
788 !mue_eeprom_present(sc))
789 MUE_SETBIT(sc, MUE_HW_CFG,
790 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
791
792 return 0;
793 }
794
795 static void
796 mue_set_macaddr(struct mue_softc *sc)
797 {
798 struct ifnet *ifp = GET_IFP(sc);
799 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
800 uint32_t lo, hi;
801
802 lo = MUE_ENADDR_LO(enaddr);
803 hi = MUE_ENADDR_HI(enaddr);
804
805 mue_csr_write(sc, MUE_RX_ADDRL, lo);
806 mue_csr_write(sc, MUE_RX_ADDRH, hi);
807 }
808
809 static int
810 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
811 {
812 prop_data_t eaprop;
813 uint32_t low, high;
814
815 if (!(sc->mue_flags & LAN7500)) {
816 low = mue_csr_read(sc, MUE_RX_ADDRL);
817 high = mue_csr_read(sc, MUE_RX_ADDRH);
818 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
819 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
820 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
821 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
822 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
823 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
824 if (ETHER_IS_VALID(sc->mue_enaddr))
825 return 0;
826 else {
827 DPRINTF(sc, "registers: %s\n",
828 ether_sprintf(sc->mue_enaddr));
829 }
830 }
831
832 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
833 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
834 if (ETHER_IS_VALID(sc->mue_enaddr))
835 return 0;
836 else {
837 DPRINTF(sc, "EEPROM: %s\n",
838 ether_sprintf(sc->mue_enaddr));
839 }
840 }
841
842 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
843 ETHER_ADDR_LEN) == 0) {
844 if (ETHER_IS_VALID(sc->mue_enaddr))
845 return 0;
846 else {
847 DPRINTF(sc, "OTP: %s\n",
848 ether_sprintf(sc->mue_enaddr));
849 }
850 }
851
852 /*
853 * Other MD methods. This should be tried only if other methods fail.
854 * Otherwise, MAC address for internal device can be assinged to
855 * external devices on Raspberry Pi, for example.
856 */
857 eaprop = prop_dictionary_get(dict, "mac-address");
858 if (eaprop != NULL) {
859 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
860 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
861 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
862 ETHER_ADDR_LEN);
863 if (ETHER_IS_VALID(sc->mue_enaddr))
864 return 0;
865 else {
866 DPRINTF(sc, "prop_dictionary_get: %s\n",
867 ether_sprintf(sc->mue_enaddr));
868 }
869 }
870
871 return 1;
872 }
873
874
875 /*
876 * Probe for a Microchip chip. */
877 static int
878 mue_match(device_t parent, cfdata_t match, void *aux)
879 {
880 struct usb_attach_arg *uaa = aux;
881
882 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
883 }
884
885 static void
886 mue_attach(device_t parent, device_t self, void *aux)
887 {
888 struct mue_softc *sc = device_private(self);
889 prop_dictionary_t dict = device_properties(self);
890 struct usb_attach_arg *uaa = aux;
891 struct usbd_device *dev = uaa->uaa_device;
892 usb_interface_descriptor_t *id;
893 usb_endpoint_descriptor_t *ed;
894 char *devinfop;
895 struct mii_data *mii;
896 struct ifnet *ifp;
897 usbd_status err;
898 uint8_t i;
899 int s;
900
901 aprint_naive("\n");
902 aprint_normal("\n");
903
904 sc->mue_dev = self;
905 sc->mue_udev = dev;
906
907 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
908 aprint_normal_dev(self, "%s\n", devinfop);
909 usbd_devinfo_free(devinfop);
910
911 #define MUE_CONFIG_NO 1
912 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
913 if (err) {
914 aprint_error_dev(self, "failed to set configuration: %s\n",
915 usbd_errstr(err));
916 return;
917 }
918
919 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
920 usb_init_task(&sc->mue_stop_task, (void (*)(void *))mue_stop, sc, 0);
921
922 #define MUE_IFACE_IDX 0
923 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
924 if (err) {
925 aprint_error_dev(self, "failed to get interface handle: %s\n",
926 usbd_errstr(err));
927 return;
928 }
929
930 sc->mue_product = uaa->uaa_product;
931 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
932
933 /* Decide on what our bufsize will be. */
934 if (sc->mue_flags & LAN7500)
935 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
936 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
937 else
938 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
939 sc->mue_txbufsz = MUE_TX_BUFSIZE;
940
941 /* Find endpoints. */
942 id = usbd_get_interface_descriptor(sc->mue_iface);
943 for (i = 0; i < id->bNumEndpoints; i++) {
944 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
945 if (ed == NULL) {
946 aprint_error_dev(self, "failed to get ep %hhd\n", i);
947 return;
948 }
949 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
950 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
951 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
952 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
953 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
954 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
955 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
956 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
957 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
958 }
959 }
960 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
961 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
962 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
963
964 s = splnet();
965
966 sc->mue_phyno = 1;
967
968 if (mue_chip_init(sc)) {
969 aprint_error_dev(self, "failed to initialize chip\n");
970 splx(s);
971 return;
972 }
973
974 /* A Microchip chip was detected. Inform the world. */
975 if (sc->mue_flags & LAN7500)
976 aprint_normal_dev(self, "LAN7500\n");
977 else
978 aprint_normal_dev(self, "LAN7800\n");
979
980 if (mue_get_macaddr(sc, dict)) {
981 aprint_error_dev(self, "failed to read MAC address\n");
982 splx(s);
983 return;
984 }
985
986 aprint_normal_dev(self, "Ethernet address %s\n",
987 ether_sprintf(sc->mue_enaddr));
988
989 /* Initialize interface info.*/
990 ifp = GET_IFP(sc);
991 ifp->if_softc = sc;
992 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
993 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
994 ifp->if_init = mue_init;
995 ifp->if_ioctl = mue_ioctl;
996 ifp->if_start = mue_start;
997 ifp->if_stop = mue_stop;
998 ifp->if_watchdog = mue_watchdog;
999
1000 IFQ_SET_READY(&ifp->if_snd);
1001
1002 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
1003 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1004 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1005 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1006 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
1007 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
1008
1009 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1010 #if 0 /* XXX not yet */
1011 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
1012 #endif
1013
1014 /* Initialize MII/media info. */
1015 mii = GET_MII(sc);
1016 mii->mii_ifp = ifp;
1017 mii->mii_readreg = mue_miibus_readreg;
1018 mii->mii_writereg = mue_miibus_writereg;
1019 mii->mii_statchg = mue_miibus_statchg;
1020 mii->mii_flags = MIIF_AUTOTSLEEP;
1021
1022 sc->mue_ec.ec_mii = mii;
1023 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1024 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1025
1026 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1027 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1028 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1029 } else
1030 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1031
1032 /* Attach the interface. */
1033 if_attach(ifp);
1034 ether_ifattach(ifp, sc->mue_enaddr);
1035
1036 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1037 RND_TYPE_NET, RND_FLAG_DEFAULT);
1038
1039 callout_init(&sc->mue_stat_ch, 0);
1040
1041 splx(s);
1042
1043 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
1044
1045 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1046 }
1047
1048 static int
1049 mue_detach(device_t self, int flags)
1050 {
1051 struct mue_softc *sc = device_private(self);
1052 struct ifnet *ifp = GET_IFP(sc);
1053 size_t i;
1054 int s;
1055
1056 sc->mue_dying = true;
1057
1058 callout_halt(&sc->mue_stat_ch, NULL);
1059
1060 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1061 if (sc->mue_ep[i] != NULL)
1062 usbd_abort_pipe(sc->mue_ep[i]);
1063
1064 /*
1065 * Remove any pending tasks. They cannot be executing because they run
1066 * in the same thread as detach.
1067 */
1068 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1069 NULL);
1070 usb_rem_task_wait(sc->mue_udev, &sc->mue_stop_task, USB_TASKQ_DRIVER,
1071 NULL);
1072
1073 s = splusb();
1074
1075 if (ifp->if_flags & IFF_RUNNING)
1076 mue_stop(ifp, 1);
1077
1078 rnd_detach_source(&sc->mue_rnd_source);
1079 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1080 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1081 if (ifp->if_softc != NULL) {
1082 ether_ifdetach(ifp);
1083 if_detach(ifp);
1084 }
1085
1086 if (--sc->mue_refcnt >= 0) {
1087 /* Wait for processes to go away. */
1088 usb_detach_waitold(sc->mue_dev);
1089 }
1090 splx(s);
1091
1092 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1093
1094 mutex_destroy(&sc->mue_mii_lock);
1095
1096 return 0;
1097 }
1098
1099 static int
1100 mue_activate(device_t self, enum devact act)
1101 {
1102 struct mue_softc *sc = device_private(self);
1103 struct ifnet *ifp = GET_IFP(sc);
1104
1105 switch (act) {
1106 case DVACT_DEACTIVATE:
1107 if_deactivate(ifp);
1108 sc->mue_dying = true;
1109 return 0;
1110 default:
1111 return EOPNOTSUPP;
1112 }
1113 return 0;
1114 }
1115
1116 static int
1117 mue_rx_list_init(struct mue_softc *sc)
1118 {
1119 struct mue_cdata *cd;
1120 struct mue_chain *c;
1121 size_t i;
1122 int err;
1123
1124 cd = &sc->mue_cdata;
1125 for (i = 0; i < __arraycount(cd->mue_rx_chain); i++) {
1126 c = &cd->mue_rx_chain[i];
1127 c->mue_sc = sc;
1128 c->mue_idx = i;
1129 if (c->mue_xfer == NULL) {
1130 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1131 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1132 if (err)
1133 return err;
1134 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1135 }
1136 }
1137
1138 return 0;
1139 }
1140
1141 static int
1142 mue_tx_list_init(struct mue_softc *sc)
1143 {
1144 struct mue_cdata *cd;
1145 struct mue_chain *c;
1146 size_t i;
1147 int err;
1148
1149 cd = &sc->mue_cdata;
1150 for (i = 0; i < __arraycount(cd->mue_tx_chain); i++) {
1151 c = &cd->mue_tx_chain[i];
1152 c->mue_sc = sc;
1153 c->mue_idx = i;
1154 if (c->mue_xfer == NULL) {
1155 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1156 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1157 &c->mue_xfer);
1158 if (err)
1159 return err;
1160 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1161 }
1162 }
1163
1164 return 0;
1165 }
1166
1167 static int
1168 mue_open_pipes(struct mue_softc *sc)
1169 {
1170 usbd_status err;
1171
1172 /* Open RX and TX pipes. */
1173 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1174 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1175 if (err) {
1176 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1177 return EIO;
1178 }
1179 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1180 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1181 if (err) {
1182 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1183 return EIO;
1184 }
1185 return 0;
1186 }
1187
1188 static void
1189 mue_startup_rx_pipes(struct mue_softc *sc)
1190 {
1191 struct mue_chain *c;
1192 size_t i;
1193
1194 /* Start up the receive pipe. */
1195 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++) {
1196 c = &sc->mue_cdata.mue_rx_chain[i];
1197 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1198 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1199 usbd_transfer(c->mue_xfer);
1200 }
1201 }
1202
1203 static int
1204 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1205 {
1206 struct ifnet *ifp = GET_IFP(sc);
1207 struct mue_chain *c;
1208 usbd_status err;
1209 struct mue_txbuf_hdr hdr;
1210 uint32_t tx_cmd_a, tx_cmd_b;
1211 int csum, len;
1212 bool tso, ipe, tpe;
1213
1214 csum = m->m_pkthdr.csum_flags;
1215 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
1216 ipe = csum & M_CSUM_IPv4;
1217 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
1218 M_CSUM_TCPv6 | M_CSUM_UDPv6);
1219
1220 len = m->m_pkthdr.len;
1221 if (__predict_false((!tso && len > MUE_FRAME_LEN(ifp->if_mtu)) ||
1222 ( tso && len > MUE_TSO_FRAME_LEN))) {
1223 MUE_PRINTF(sc, "packet length %d\n too long", len);
1224 return EINVAL;
1225 }
1226
1227 c = &sc->mue_cdata.mue_tx_chain[idx];
1228
1229 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
1230 tx_cmd_a = len | MUE_TX_CMD_A_FCS;
1231
1232 if (tso) {
1233 tx_cmd_a |= MUE_TX_CMD_A_LSO;
1234 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1235 tx_cmd_b = m->m_pkthdr.segsz;
1236 else
1237 tx_cmd_b = MUE_TX_MSS_MIN;
1238 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
1239 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
1240 mue_tx_offload(sc, m);
1241 } else {
1242 if (ipe)
1243 tx_cmd_a |= MUE_TX_CMD_A_IPE;
1244 if (tpe)
1245 tx_cmd_a |= MUE_TX_CMD_A_TPE;
1246 tx_cmd_b = 0;
1247 }
1248
1249 hdr.tx_cmd_a = htole32(tx_cmd_a);
1250 hdr.tx_cmd_b = htole32(tx_cmd_b);
1251
1252 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1253 m_copydata(m, 0, len, c->mue_buf + sizeof(hdr));
1254
1255 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr),
1256 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1257
1258 /* Transmit */
1259 err = usbd_transfer(c->mue_xfer);
1260 if (__predict_false(err != USBD_IN_PROGRESS)) {
1261 MUE_PRINTF(sc, "%s\n", usbd_errstr(err));
1262 mue_stop(ifp, 0);
1263 return EIO;
1264 }
1265
1266 sc->mue_cdata.mue_tx_cnt++;
1267
1268 return 0;
1269 }
1270
1271 static void
1272 mue_tx_offload(struct mue_softc *sc, struct mbuf *m)
1273 {
1274 struct ether_header *eh;
1275 struct ip *ip;
1276 struct ip6_hdr *ip6;
1277 int off;
1278
1279 eh = mtod(m, struct ether_header *);
1280 switch (htons(eh->ether_type)) {
1281 case ETHERTYPE_IP:
1282 case ETHERTYPE_IPV6:
1283 off = ETHER_HDR_LEN;
1284 break;
1285 case ETHERTYPE_VLAN:
1286 /* XXX not yet supported */
1287 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1288 break;
1289 default:
1290 /* XXX */
1291 panic("%s: unsupported ethertype\n", __func__);
1292 /* NOTREACHED */
1293 }
1294
1295 /* Packet length should be cleared. */
1296 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1297 ip = (void *)(mtod(m, char *) + off);
1298 ip->ip_len = 0;
1299 } else {
1300 ip6 = (void *)(mtod(m, char *) + off);
1301 ip6->ip6_plen = 0;
1302 }
1303 }
1304
1305 static void
1306 mue_setmulti(struct mue_softc *sc)
1307 {
1308 struct ifnet *ifp = GET_IFP(sc);
1309 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1310 struct ether_multi *enm;
1311 struct ether_multistep step;
1312 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1313 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1314 uint32_t reg, rxfilt, h, hireg, loreg;
1315 size_t i;
1316
1317 if (sc->mue_dying)
1318 return;
1319
1320 /* Clear perfect filter and hash tables. */
1321 memset(pfiltbl, 0, sizeof(pfiltbl));
1322 memset(hashtbl, 0, sizeof(hashtbl));
1323
1324 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1325 rxfilt = mue_csr_read(sc, reg);
1326 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1327 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1328
1329 /* Always accept broadcast frames. */
1330 rxfilt |= MUE_RFE_CTL_BROADCAST;
1331
1332 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1333 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1334 if (ifp->if_flags & IFF_PROMISC) {
1335 rxfilt |= MUE_RFE_CTL_UNICAST;
1336 DPRINTF(sc, "promisc\n");
1337 } else {
1338 DPRINTF(sc, "allmulti\n");
1339 }
1340 } else {
1341 /* Now program new ones. */
1342 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1343 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1344 i = 1;
1345 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1346 while (enm != NULL) {
1347 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1348 ETHER_ADDR_LEN)) {
1349 memset(pfiltbl, 0, sizeof(pfiltbl));
1350 memset(hashtbl, 0, sizeof(hashtbl));
1351 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1352 goto allmulti;
1353 }
1354 if (i < MUE_NUM_ADDR_FILTX) {
1355 /* Use perfect address table if possible. */
1356 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1357 MUE_ADDR_FILTX_VALID;
1358 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1359 } else {
1360 /* Otherwise, use hash table. */
1361 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1362 h = (ether_crc32_be(enm->enm_addrlo,
1363 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1364 hashtbl[h / 32] |= 1 << (h % 32);
1365 }
1366 i++;
1367 ETHER_NEXT_MULTI(step, enm);
1368 }
1369 rxfilt |= MUE_RFE_CTL_PERFECT;
1370 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH) {
1371 DPRINTF(sc, "perfect filter and hash tables\n");
1372 } else {
1373 DPRINTF(sc, "perfect filter\n");
1374 }
1375 }
1376
1377 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1378 hireg = (sc->mue_flags & LAN7500) ?
1379 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1380 loreg = hireg + 4;
1381 mue_csr_write(sc, hireg, 0);
1382 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1383 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1384 }
1385
1386 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1387 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1388
1389 mue_csr_write(sc, reg, rxfilt);
1390 }
1391
1392 static void
1393 mue_sethwcsum(struct mue_softc *sc)
1394 {
1395 struct ifnet *ifp = GET_IFP(sc);
1396 uint32_t reg, val;
1397
1398 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1399 val = mue_csr_read(sc, reg);
1400
1401 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) {
1402 DPRINTF(sc, "enabled\n");
1403 val |= MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE;
1404 val |= MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE;
1405 } else {
1406 DPRINTF(sc, "disabled\n");
1407 val &=
1408 ~(MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE);
1409 val &=
1410 ~(MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE);
1411 }
1412
1413 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1414
1415 mue_csr_write(sc, reg, val);
1416 }
1417
1418 static void
1419 mue_setmtu(struct mue_softc *sc)
1420 {
1421 struct ifnet *ifp = GET_IFP(sc);
1422 uint32_t val;
1423
1424 /* Set the maximum frame size. */
1425 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1426 val = mue_csr_read(sc, MUE_MAC_RX);
1427 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1428 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1429 mue_csr_write(sc, MUE_MAC_RX, val);
1430 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1431 }
1432
1433 static void
1434 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1435 {
1436 struct mue_chain *c = (struct mue_chain *)priv;
1437 struct mue_softc *sc = c->mue_sc;
1438 struct ifnet *ifp = GET_IFP(sc);
1439 struct mbuf *m;
1440 struct mue_rxbuf_hdr *hdrp;
1441 uint32_t rx_cmd_a, totlen;
1442 uint16_t pktlen;
1443 int s;
1444 int csum;
1445 char *buf = c->mue_buf;
1446 bool v6;
1447
1448 if (__predict_false(sc->mue_dying)) {
1449 DPRINTF(sc, "dying\n");
1450 return;
1451 }
1452
1453 if (__predict_false(!(ifp->if_flags & IFF_RUNNING))) {
1454 DPRINTF(sc, "not running\n");
1455 return;
1456 }
1457
1458 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1459 DPRINTF(sc, "%s\n", usbd_errstr(status));
1460 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1461 return;
1462 if (usbd_ratecheck(&sc->mue_rx_notice))
1463 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1464 if (status == USBD_STALLED)
1465 usbd_clear_endpoint_stall_async(
1466 sc->mue_ep[MUE_ENDPT_RX]);
1467 goto done;
1468 }
1469
1470 usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL);
1471
1472 KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u",
1473 totlen, sc->mue_rxbufsz);
1474
1475 do {
1476 if (__predict_false(totlen < sizeof(*hdrp))) {
1477 MUE_PRINTF(sc, "packet length %u too short\n", totlen);
1478 ifp->if_ierrors++;
1479 goto done;
1480 }
1481
1482 hdrp = (struct mue_rxbuf_hdr *)buf;
1483 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1484
1485 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1486 /*
1487 * We cannot use MUE_RX_CMD_A_RED bit here;
1488 * it is turned on in the cases of L3/L4
1489 * checksum errors which we handle below.
1490 */
1491 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1492 ifp->if_ierrors++;
1493 goto done;
1494 }
1495
1496 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1497 if (sc->mue_flags & LAN7500)
1498 pktlen -= 2;
1499
1500 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1501 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1502 pktlen + sizeof(*hdrp) > totlen)) {
1503 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1504 ifp->if_ierrors++;
1505 goto done;
1506 }
1507
1508 m = mue_newbuf();
1509 if (__predict_false(m == NULL)) {
1510 MUE_PRINTF(sc, "failed to allocate mbuf\n");
1511 ifp->if_ierrors++;
1512 goto done;
1513 }
1514
1515 m_set_rcvif(m, ifp);
1516 m->m_pkthdr.len = m->m_len = pktlen;
1517 m->m_flags |= M_HASFCS;
1518
1519 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1520 csum = 0;
1521 } else {
1522 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1523 switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1524 case MUE_RX_CMD_A_PID_TCP:
1525 csum = v6 ?
1526 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1527 break;
1528 case MUE_RX_CMD_A_PID_UDP:
1529 csum = v6 ?
1530 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1531 break;
1532 case MUE_RX_CMD_A_PID_IP:
1533 csum = v6 ? 0 : M_CSUM_IPv4;
1534 break;
1535 default:
1536 csum = 0;
1537 break;
1538 }
1539 csum &= ifp->if_csum_flags_rx;
1540 if (__predict_false((csum & M_CSUM_IPv4) &&
1541 (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1542 csum |= M_CSUM_IPv4_BAD;
1543 if (__predict_false((csum & ~M_CSUM_IPv4) &&
1544 (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1545 csum |= M_CSUM_TCP_UDP_BAD;
1546 }
1547 m->m_pkthdr.csum_flags = csum;
1548 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1549
1550 /* Attention: sizeof(hdr) = 10 */
1551 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1552 if (pktlen > totlen)
1553 pktlen = totlen;
1554 totlen -= pktlen;
1555 buf += pktlen;
1556
1557 s = splnet();
1558 if_percpuq_enqueue(ifp->if_percpuq, m);
1559 splx(s);
1560 } while (totlen > 0);
1561
1562 done:
1563 /* Setup new transfer. */
1564 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1565 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1566 usbd_transfer(xfer);
1567 }
1568
1569 static void
1570 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1571 {
1572 struct mue_chain *c = priv;
1573 struct mue_softc *sc = c->mue_sc;
1574 struct ifnet *ifp = GET_IFP(sc);
1575 int s;
1576
1577 if (__predict_false(sc->mue_dying))
1578 return;
1579
1580 s = splnet();
1581
1582 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1583 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1584 splx(s);
1585 return;
1586 }
1587 ifp->if_oerrors++;
1588 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1589 if (status == USBD_STALLED)
1590 usbd_clear_endpoint_stall_async(
1591 sc->mue_ep[MUE_ENDPT_TX]);
1592 splx(s);
1593 return;
1594 }
1595
1596 ifp->if_timer = 0;
1597 ifp->if_flags &= ~IFF_OACTIVE;
1598
1599 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1600 mue_start(ifp);
1601
1602 ifp->if_opackets++;
1603 splx(s);
1604 }
1605
1606 static int
1607 mue_init(struct ifnet *ifp)
1608 {
1609 struct mue_softc *sc = ifp->if_softc;
1610 int s;
1611
1612 if (sc->mue_dying) {
1613 DPRINTF(sc, "dying\n");
1614 return EIO;
1615 }
1616
1617 s = splnet();
1618
1619 /* Cancel pending I/O and free all TX/RX buffers. */
1620 if (ifp->if_flags & IFF_RUNNING)
1621 mue_stop(ifp, 1);
1622
1623 mue_reset(sc);
1624
1625 /* Set MAC address. */
1626 mue_set_macaddr(sc);
1627
1628 /* Load the multicast filter. */
1629 mue_setmulti(sc);
1630
1631 /* TCP/UDP checksum offload engines. */
1632 mue_sethwcsum(sc);
1633
1634 /* Set MTU. */
1635 mue_setmtu(sc);
1636
1637 if (mue_open_pipes(sc)) {
1638 splx(s);
1639 return EIO;
1640 }
1641
1642 /* Init RX ring. */
1643 if (mue_rx_list_init(sc)) {
1644 MUE_PRINTF(sc, "failed to init rx list\n");
1645 splx(s);
1646 return ENOBUFS;
1647 }
1648
1649 /* Init TX ring. */
1650 if (mue_tx_list_init(sc)) {
1651 MUE_PRINTF(sc, "failed to init tx list\n");
1652 splx(s);
1653 return ENOBUFS;
1654 }
1655
1656 mue_startup_rx_pipes(sc);
1657
1658 ifp->if_flags |= IFF_RUNNING;
1659 ifp->if_flags &= ~IFF_OACTIVE;
1660
1661 splx(s);
1662
1663 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1664
1665 return 0;
1666 }
1667
1668 static int
1669 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1670 {
1671 struct mue_softc *sc = ifp->if_softc;
1672 struct ifreq /*const*/ *ifr = data;
1673 int s, error = 0;
1674
1675 s = splnet();
1676
1677 switch (cmd) {
1678 case SIOCSIFFLAGS:
1679 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1680 break;
1681
1682 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1683 case IFF_RUNNING:
1684 mue_stop(ifp, 1);
1685 break;
1686 case IFF_UP:
1687 mue_init(ifp);
1688 break;
1689 case IFF_UP | IFF_RUNNING:
1690 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1691 mue_setmulti(sc);
1692 else
1693 mue_init(ifp);
1694 break;
1695 }
1696 sc->mue_if_flags = ifp->if_flags;
1697 break;
1698 case SIOCGIFMEDIA:
1699 case SIOCSIFMEDIA:
1700 error = ifmedia_ioctl(ifp, ifr, &sc->mue_mii.mii_media, cmd);
1701 break;
1702 default:
1703 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1704 break;
1705 error = 0;
1706 switch (cmd) {
1707 case SIOCADDMULTI:
1708 case SIOCDELMULTI:
1709 mue_setmulti(sc);
1710 break;
1711 case SIOCSIFCAP:
1712 mue_sethwcsum(sc);
1713 break;
1714 case SIOCSIFMTU:
1715 mue_setmtu(sc);
1716 break;
1717 default:
1718 break;
1719 }
1720 break;
1721 }
1722 splx(s);
1723
1724 return error;
1725 }
1726
1727 static void
1728 mue_watchdog(struct ifnet *ifp)
1729 {
1730 struct mue_softc *sc = ifp->if_softc;
1731 struct mue_chain *c;
1732 usbd_status stat;
1733 int s;
1734
1735 ifp->if_oerrors++;
1736 MUE_PRINTF(sc, "timed out\n");
1737
1738 s = splusb();
1739 c = &sc->mue_cdata.mue_tx_chain[0];
1740 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1741 mue_txeof(c->mue_xfer, c, stat);
1742
1743 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1744 mue_start(ifp);
1745 splx(s);
1746 }
1747
1748 static void
1749 mue_reset(struct mue_softc *sc)
1750 {
1751 if (sc->mue_dying)
1752 return;
1753
1754 /* Wait a little while for the chip to get its brains in order. */
1755 usbd_delay_ms(sc->mue_udev, 1);
1756
1757 // mue_chip_init(sc); /* XXX */
1758 }
1759
1760 static void
1761 mue_start(struct ifnet *ifp)
1762 {
1763 struct mue_softc *sc = ifp->if_softc;
1764 struct mbuf *m;
1765
1766 if (__predict_false(!sc->mue_link)) {
1767 DPRINTF(sc, "no link\n");
1768 return;
1769 }
1770
1771 if (__predict_false((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING))
1772 != IFF_RUNNING)) {
1773 DPRINTF(sc, "not ready\n");
1774 return;
1775 }
1776
1777 IFQ_POLL(&ifp->if_snd, m);
1778 if (m == NULL)
1779 return;
1780
1781 if (__predict_false(mue_encap(sc, m, 0))) {
1782 ifp->if_oerrors++;
1783 return;
1784 }
1785 IFQ_DEQUEUE(&ifp->if_snd, m);
1786
1787 bpf_mtap(ifp, m, BPF_D_OUT);
1788 m_freem(m);
1789
1790 ifp->if_flags |= IFF_OACTIVE;
1791
1792 /* Set a timeout in case the chip goes out to lunch. */
1793 ifp->if_timer = 5;
1794 }
1795
1796 static void
1797 mue_stop(struct ifnet *ifp, int disable __unused)
1798 {
1799 struct mue_softc *sc = ifp->if_softc;
1800 usbd_status err;
1801 size_t i;
1802
1803 mue_reset(sc);
1804
1805 ifp->if_timer = 0;
1806 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1807
1808 callout_stop(&sc->mue_stat_ch);
1809
1810 /* Stop transfers. */
1811 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1812 if (sc->mue_ep[i] != NULL) {
1813 err = usbd_abort_pipe(sc->mue_ep[i]);
1814 if (err)
1815 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1816 i, usbd_errstr(err));
1817 }
1818
1819 /* Free RX resources. */
1820 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++)
1821 if (sc->mue_cdata.mue_rx_chain[i].mue_xfer != NULL) {
1822 usbd_destroy_xfer(
1823 sc->mue_cdata.mue_rx_chain[i].mue_xfer);
1824 sc->mue_cdata.mue_rx_chain[i].mue_xfer = NULL;
1825 }
1826
1827 /* Free TX resources. */
1828 for (i = 0; i < __arraycount(sc->mue_cdata.mue_tx_chain); i++)
1829 if (sc->mue_cdata.mue_tx_chain[i].mue_xfer != NULL) {
1830 usbd_destroy_xfer(
1831 sc->mue_cdata.mue_tx_chain[i].mue_xfer);
1832 sc->mue_cdata.mue_tx_chain[i].mue_xfer = NULL;
1833 }
1834
1835 /* Close pipes */
1836 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1837 if (sc->mue_ep[i] != NULL) {
1838 err = usbd_close_pipe(sc->mue_ep[i]);
1839 if (err)
1840 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1841 i, usbd_errstr(err));
1842 sc->mue_ep[i] = NULL;
1843 }
1844
1845 sc->mue_link = 0; /* XXX */
1846
1847 DPRINTF(sc, "done\n");
1848 }
1849
1850 static void
1851 mue_tick(void *xsc)
1852 {
1853 struct mue_softc *sc = xsc;
1854
1855 if (sc == NULL)
1856 return;
1857
1858 if (sc->mue_dying)
1859 return;
1860
1861 /* Perform periodic stuff in process context. */
1862 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1863 }
1864
1865 static void
1866 mue_tick_task(void *xsc)
1867 {
1868 struct mue_softc *sc = xsc;
1869 struct ifnet *ifp = GET_IFP(sc);
1870 struct mii_data *mii = GET_MII(sc);
1871 int s;
1872
1873 if (sc == NULL)
1874 return;
1875
1876 if (sc->mue_dying)
1877 return;
1878
1879 s = splnet();
1880 mii_tick(mii);
1881 if (sc->mue_link == 0)
1882 mue_miibus_statchg(ifp);
1883 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1884 splx(s);
1885 }
1886
1887 static struct mbuf *
1888 mue_newbuf(void)
1889 {
1890 struct mbuf *m;
1891
1892 MGETHDR(m, M_DONTWAIT, MT_DATA);
1893 if (__predict_false(m == NULL))
1894 return NULL;
1895
1896 MCLGET(m, M_DONTWAIT);
1897 if (__predict_false(!(m->m_flags & M_EXT))) {
1898 m_freem(m);
1899 return NULL;
1900 }
1901
1902 m_adj(m, ETHER_ALIGN);
1903
1904 return m;
1905 }
1906