if_mue.c revision 1.26 1 /* $NetBSD: if_mue.c,v 1.26 2018/12/28 22:55:20 rin Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.26 2018/12/28 22:55:20 rin Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/mutex.h>
36 #include <sys/kernel.h>
37 #include <sys/proc.h>
38 #include <sys/socket.h>
39
40 #include <sys/device.h>
41
42 #include <sys/rndsource.h>
43
44 #include <net/if.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_ether.h>
48
49 #include <net/bpf.h>
50
51 #include <netinet/if_inarp.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h> /* XXX for struct ip */
54 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
55
56 #include <dev/mii/mii.h>
57 #include <dev/mii/miivar.h>
58
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
61 #include <dev/usb/usbdi_util.h>
62 #include <dev/usb/usbdivar.h>
63 #include <dev/usb/usbdevs.h>
64
65 #include <dev/usb/if_muereg.h>
66 #include <dev/usb/if_muevar.h>
67
68 #define MUE_PRINTF(sc, fmt, args...) \
69 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
70
71 #ifdef USB_DEBUG
72 int muedebug = 0;
73 #define DPRINTF(sc, fmt, args...) \
74 do { \
75 if (muedebug) \
76 MUE_PRINTF(sc, fmt, ##args); \
77 } while (0 /* CONSTCOND */)
78 #else
79 #define DPRINTF(sc, fmt, args...) __nothing
80 #endif
81
82 /*
83 * Various supported device vendors/products.
84 */
85 struct mue_type {
86 struct usb_devno mue_dev;
87 uint16_t mue_flags;
88 #define LAN7500 0x0001 /* LAN7500 */
89 };
90
91 const struct mue_type mue_devs[] = {
92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
97 };
98
99 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
100 uaa->uaa_vendor, uaa->uaa_product))
101
102 #define MUE_ENADDR_LO(enaddr) \
103 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
104 #define MUE_ENADDR_HI(enaddr) \
105 ((enaddr[5] << 8) | enaddr[4])
106
107 static int mue_match(device_t, cfdata_t, void *);
108 static void mue_attach(device_t, device_t, void *);
109 static int mue_detach(device_t, int);
110 static int mue_activate(device_t, enum devact);
111
112 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
113 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
114 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
115 uint32_t, uint32_t);
116
117 static void mue_lock_mii(struct mue_softc *);
118 static void mue_unlock_mii(struct mue_softc *);
119
120 static int mue_miibus_readreg(device_t, int, int);
121 static void mue_miibus_writereg(device_t, int, int, int);
122 static void mue_miibus_statchg(struct ifnet *);
123 static int mue_ifmedia_upd(struct ifnet *);
124 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125
126 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
127 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
128 static bool mue_eeprom_present(struct mue_softc *sc);
129
130 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
131 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
132
133 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
134 uint32_t, uint32_t *);
135
136 static void mue_init_ltm(struct mue_softc *);
137
138 static int mue_chip_init(struct mue_softc *);
139
140 static void mue_set_macaddr(struct mue_softc *);
141 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
142
143 static int mue_rx_list_init(struct mue_softc *);
144 static int mue_tx_list_init(struct mue_softc *);
145 static int mue_open_pipes(struct mue_softc *);
146 static void mue_startup_rx_pipes(struct mue_softc *);
147
148 static int mue_encap(struct mue_softc *, struct mbuf *, int);
149 static void mue_tx_offload(struct mue_softc *, struct mbuf *);
150
151 static void mue_setmulti(struct mue_softc *);
152 static void mue_sethwcsum(struct mue_softc *);
153 static void mue_setmtu(struct mue_softc *);
154
155 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
156 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
157
158 static int mue_init(struct ifnet *);
159 static int mue_ioctl(struct ifnet *, u_long, void *);
160 static void mue_watchdog(struct ifnet *);
161 static void mue_reset(struct mue_softc *);
162 static void mue_start(struct ifnet *);
163 static void mue_stop(struct ifnet *, int);
164 static void mue_tick(void *);
165 static void mue_tick_task(void *);
166
167 static struct mbuf *mue_newbuf(void);
168
169 #define MUE_SETBIT(sc, reg, x) \
170 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
171
172 #define MUE_CLRBIT(sc, reg, x) \
173 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
174
175 #define MUE_WAIT_SET(sc, reg, set, fail) \
176 mue_wait_for_bits(sc, reg, set, ~0, fail)
177
178 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
179 mue_wait_for_bits(sc, reg, 0, clear, fail)
180
181 #define ETHER_IS_VALID(addr) \
182 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
183
184 #define ETHER_IS_ZERO(addr) \
185 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
186
187 #define ETHER_ALIGN 2
188
189 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
190 mue_detach, mue_activate);
191
192 static uint32_t
193 mue_csr_read(struct mue_softc *sc, uint32_t reg)
194 {
195 usb_device_request_t req;
196 usbd_status err;
197 uDWord val;
198
199 if (sc->mue_dying)
200 return 0;
201
202 USETDW(val, 0);
203 req.bmRequestType = UT_READ_VENDOR_DEVICE;
204 req.bRequest = MUE_UR_READREG;
205 USETW(req.wValue, 0);
206 USETW(req.wIndex, reg);
207 USETW(req.wLength, 4);
208
209 err = usbd_do_request(sc->mue_udev, &req, &val);
210 if (err) {
211 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
212 return 0;
213 }
214
215 return UGETDW(val);
216 }
217
218 static int
219 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
220 {
221 usb_device_request_t req;
222 usbd_status err;
223 uDWord val;
224
225 if (sc->mue_dying)
226 return 0;
227
228 USETDW(val, aval);
229 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
230 req.bRequest = MUE_UR_WRITEREG;
231 USETW(req.wValue, 0);
232 USETW(req.wIndex, reg);
233 USETW(req.wLength, 4);
234
235 err = usbd_do_request(sc->mue_udev, &req, &val);
236 if (err) {
237 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
238 return -1;
239 }
240
241 return 0;
242 }
243
244 static int
245 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
246 uint32_t set, uint32_t clear, uint32_t fail)
247 {
248 uint32_t val;
249 int ntries;
250
251 for (ntries = 0; ntries < 1000; ntries++) {
252 val = mue_csr_read(sc, reg);
253 if ((val & set) || !(val & clear))
254 return 0;
255 if (val & fail)
256 return 1;
257 usbd_delay_ms(sc->mue_udev, 1);
258 }
259
260 return 1;
261 }
262
263 /*
264 * Get exclusive access to the MII registers.
265 */
266 static void
267 mue_lock_mii(struct mue_softc *sc)
268 {
269 sc->mue_refcnt++;
270 mutex_enter(&sc->mue_mii_lock);
271 }
272
273 static void
274 mue_unlock_mii(struct mue_softc *sc)
275 {
276 mutex_exit(&sc->mue_mii_lock);
277 if (--sc->mue_refcnt < 0)
278 usb_detach_wakeupold(sc->mue_dev);
279 }
280
281 static int
282 mue_miibus_readreg(device_t dev, int phy, int reg)
283 {
284 struct mue_softc *sc = device_private(dev);
285 uint32_t val;
286
287 if (sc->mue_dying) {
288 DPRINTF(sc, "dying\n");
289 return 0;
290 }
291
292 if (sc->mue_phyno != phy)
293 return 0;
294
295 mue_lock_mii(sc);
296 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
297 mue_unlock_mii(sc);
298 MUE_PRINTF(sc, "not ready\n");
299 return -1;
300 }
301
302 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
303 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
304 MUE_MII_ACCESS_PHYADDR(phy));
305
306 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
307 mue_unlock_mii(sc);
308 MUE_PRINTF(sc, "timed out\n");
309 return -1;
310 }
311
312 val = mue_csr_read(sc, MUE_MII_DATA);
313 mue_unlock_mii(sc);
314 return val & 0xffff;
315 }
316
317 static void
318 mue_miibus_writereg(device_t dev, int phy, int reg, int data)
319 {
320 struct mue_softc *sc = device_private(dev);
321
322 if (sc->mue_dying) {
323 DPRINTF(sc, "dying\n");
324 return;
325 }
326
327 if (sc->mue_phyno != phy) {
328 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
329 sc->mue_phyno, phy);
330 return;
331 }
332
333 mue_lock_mii(sc);
334 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
335 mue_unlock_mii(sc);
336 MUE_PRINTF(sc, "not ready\n");
337 return;
338 }
339
340 mue_csr_write(sc, MUE_MII_DATA, data);
341 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
342 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
343 MUE_MII_ACCESS_PHYADDR(phy));
344
345 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0))
346 MUE_PRINTF(sc, "timed out\n");
347
348 mue_unlock_mii(sc);
349 }
350
351 static void
352 mue_miibus_statchg(struct ifnet *ifp)
353 {
354 struct mue_softc *sc = ifp->if_softc;
355 struct mii_data *mii = GET_MII(sc);
356 uint32_t flow, threshold;
357
358 if (mii == NULL || ifp == NULL || (ifp->if_flags & IFF_RUNNING) == 0) {
359 DPRINTF(sc, "not ready\n");
360 return;
361 }
362
363 sc->mue_link = 0;
364 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
365 (IFM_ACTIVE | IFM_AVALID)) {
366 switch (IFM_SUBTYPE(mii->mii_media_active)) {
367 case IFM_10_T:
368 case IFM_100_TX:
369 case IFM_1000_T:
370 sc->mue_link++;
371 break;
372 default:
373 break;
374 }
375 }
376
377 /* Lost link, do nothing. */
378 if (sc->mue_link == 0) {
379 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
380 return;
381 }
382
383 if (!(sc->mue_flags & LAN7500)) {
384 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
385 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
386 /* Disable U2 and enable U1. */
387 MUE_CLRBIT(sc, MUE_USB_CFG1,
388 MUE_USB_CFG1_DEV_U2_INIT_EN);
389 MUE_SETBIT(sc, MUE_USB_CFG1,
390 MUE_USB_CFG1_DEV_U1_INIT_EN);
391 } else {
392 /* Enable U1 and U2. */
393 MUE_SETBIT(sc, MUE_USB_CFG1,
394 MUE_USB_CFG1_DEV_U1_INIT_EN |
395 MUE_USB_CFG1_DEV_U2_INIT_EN);
396 }
397 }
398 }
399
400 flow = 0;
401 /* XXX Linux does not check IFM_FDX flag for 7800. */
402 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
403 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
404 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
405 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
406 flow |= MUE_FLOW_RX_FCEN;
407 }
408
409 /* XXX Magic numbers taken from Linux driver. */
410 if (sc->mue_flags & LAN7500)
411 threshold = 0x820;
412 else
413 switch (sc->mue_udev->ud_speed) {
414 case USB_SPEED_SUPER:
415 threshold = 0x817;
416 break;
417 case USB_SPEED_HIGH:
418 threshold = 0x211;
419 break;
420 default:
421 threshold = 0;
422 break;
423 }
424
425 /* Threshold value should be set before enabling flow. */
426 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
427 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
428 mue_csr_write(sc, MUE_FLOW, flow);
429
430 DPRINTF(sc, "done\n");
431 }
432
433 /*
434 * Set media options.
435 */
436 static int
437 mue_ifmedia_upd(struct ifnet *ifp)
438 {
439 struct mue_softc *sc = ifp->if_softc;
440 struct mii_data *mii = GET_MII(sc);
441
442 sc->mue_link = 0; /* XXX */
443
444 if (mii->mii_instance) {
445 struct mii_softc *miisc;
446 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
447 mii_phy_reset(miisc);
448 }
449 return mii_mediachg(mii);
450 }
451
452 /*
453 * Report current media status.
454 */
455 static void
456 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
457 {
458 struct mue_softc *sc = ifp->if_softc;
459 struct mii_data *mii = GET_MII(sc);
460
461 mii_pollstat(mii);
462 ifmr->ifm_active = mii->mii_media_active;
463 ifmr->ifm_status = mii->mii_media_status;
464 }
465
466 static uint8_t
467 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
468 {
469 uint32_t val;
470
471 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
472 MUE_PRINTF(sc, "not ready\n");
473 return ETIMEDOUT;
474 }
475
476 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
477 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
478 off);
479
480 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
481 MUE_E2P_CMD_TIMEOUT)) {
482 MUE_PRINTF(sc, "timed out\n");
483 return ETIMEDOUT;
484 }
485
486 val = mue_csr_read(sc, MUE_E2P_DATA);
487 *dest = val & 0xff;
488
489 return 0;
490 }
491
492 static int
493 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
494 {
495 uint32_t val = 0; /* XXX gcc */
496 uint8_t byte;
497 int i, err;
498
499 /*
500 * EEPROM pins are muxed with the LED function on LAN7800 device.
501 */
502 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
503 val = mue_csr_read(sc, MUE_HW_CFG);
504 mue_csr_write(sc, MUE_HW_CFG,
505 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
506 }
507
508 for (i = 0; i < cnt; i++) {
509 err = mue_eeprom_getbyte(sc, off + i, &byte);
510 if (err)
511 break;
512 *(dest + i) = byte;
513 }
514
515 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
516 mue_csr_write(sc, MUE_HW_CFG, val);
517
518 return err ? 1 : 0;
519 }
520
521 static bool
522 mue_eeprom_present(struct mue_softc *sc)
523 {
524 uint32_t val;
525 uint8_t sig;
526 int ret;
527
528 if (sc->mue_flags & LAN7500) {
529 val = mue_csr_read(sc, MUE_E2P_CMD);
530 return val & MUE_E2P_CMD_LOADED;
531 } else {
532 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
533 return (ret == 0) && (sig == MUE_E2P_IND);
534 }
535 }
536
537 static int
538 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
539 {
540 uint32_t val;
541 int i, err;
542
543 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
544
545 /* Checking if bit is set. */
546 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
547 /* Clear it, then wait for it to be cleared. */
548 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
549 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
550 0);
551 if (err) {
552 MUE_PRINTF(sc, "not ready\n");
553 return 1;
554 }
555 }
556
557 /* Start reading the bytes, one at a time. */
558 for (i = 0; i < cnt; i++) {
559 mue_csr_write(sc, MUE_OTP_ADDR1,
560 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
561 mue_csr_write(sc, MUE_OTP_ADDR2,
562 ((off + i) & MUE_OTP_ADDR2_MASK));
563 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
564 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
565
566 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
567 if (err) {
568 MUE_PRINTF(sc, "timed out\n");
569 return 1;
570 }
571 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
572 *(dest + i) = (uint8_t)(val & 0xff);
573 }
574
575 return 0;
576 }
577
578 static int
579 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
580 {
581 uint8_t sig;
582 int err;
583
584 if (sc->mue_flags & LAN7500)
585 return 1;
586
587 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
588 if (err)
589 return 1;
590 switch (sig) {
591 case MUE_OTP_IND_1:
592 break;
593 case MUE_OTP_IND_2:
594 off += 0x100;
595 break;
596 default:
597 DPRINTF(sc, "OTP not found\n");
598 return 1;
599 }
600 err = mue_read_otp_raw(sc, dest, off, cnt);
601 return err;
602 }
603
604 static void
605 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
606 uint32_t cnt, uint32_t *data)
607 {
608 uint32_t i;
609
610 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
611 MUE_PRINTF(sc, "not ready\n");
612 return;
613 }
614
615 mue_csr_write(sc, MUE_DP_SEL,
616 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
617
618 for (i = 0; i < cnt; i++) {
619 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
620 mue_csr_write(sc, MUE_DP_DATA, data[i]);
621 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
622 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
623 MUE_PRINTF(sc, "timed out\n");
624 return;
625 }
626 }
627 }
628
629 static void
630 mue_init_ltm(struct mue_softc *sc)
631 {
632 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
633 uint8_t temp[2];
634 size_t i;
635
636 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
637 if (mue_eeprom_present(sc) &&
638 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
639 if (temp[0] != sizeof(idx)) {
640 DPRINTF(sc, "EEPROM: unexpected size\n");
641 goto done;
642 }
643 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
644 sizeof(idx))) {
645 DPRINTF(sc, "EEPROM: failed to read\n");
646 goto done;
647 }
648 DPRINTF(sc, "success\n");
649 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
650 if (temp[0] != sizeof(idx)) {
651 DPRINTF(sc, "OTP: unexpected size\n");
652 goto done;
653 }
654 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
655 sizeof(idx))) {
656 DPRINTF(sc, "OTP: failed to read\n");
657 goto done;
658 }
659 DPRINTF(sc, "success\n");
660 } else
661 DPRINTF(sc, "nothing to do\n");
662 } else
663 DPRINTF(sc, "nothing to do\n");
664 done:
665 for (i = 0; i < __arraycount(idx); i++)
666 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
667 }
668
669 static int
670 mue_chip_init(struct mue_softc *sc)
671 {
672 uint32_t val;
673
674 if ((sc->mue_flags & LAN7500) &&
675 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
676 MUE_PRINTF(sc, "not ready\n");
677 return ETIMEDOUT;
678 }
679
680 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
681 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
682 MUE_PRINTF(sc, "timed out\n");
683 return ETIMEDOUT;
684 }
685
686 /* Respond to the IN token with a NAK. */
687 if (sc->mue_flags & LAN7500)
688 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
689 else
690 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
691
692 if (sc->mue_flags & LAN7500) {
693 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
694 val = MUE_7500_HS_RX_BUFSIZE /
695 MUE_HS_USB_PKT_SIZE;
696 else
697 val = MUE_7500_FS_RX_BUFSIZE /
698 MUE_FS_USB_PKT_SIZE;
699 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
700 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
701 MUE_7500_DEFAULT_BULKIN_DELAY);
702
703 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
704
705 /* Set FIFO sizes. */
706 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
707 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
708 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
709 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
710 } else {
711 /* Init LTM. */
712 mue_init_ltm(sc);
713
714 val = MUE_7800_RX_BUFSIZE;
715 switch (sc->mue_udev->ud_speed) {
716 case USB_SPEED_SUPER:
717 val /= MUE_SS_USB_PKT_SIZE;
718 break;
719 case USB_SPEED_HIGH:
720 val /= MUE_HS_USB_PKT_SIZE;
721 break;
722 default:
723 val /= MUE_FS_USB_PKT_SIZE;
724 break;
725 }
726 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
727 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
728 MUE_7800_DEFAULT_BULKIN_DELAY);
729
730 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
731 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
732
733 /*
734 * Set FCL's RX and TX FIFO sizes: according to data sheet this
735 * is already the default value. But we initialize it to the
736 * same value anyways, as that's what the Linux driver does.
737 */
738 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
739 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
740 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
741 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
742 }
743
744 /* Enabling interrupts. */
745 mue_csr_write(sc, MUE_INT_STATUS, ~0);
746
747 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
748 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
749 mue_csr_write(sc, MUE_FLOW, 0);
750
751 /* Reset PHY. */
752 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
753 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
754 MUE_PRINTF(sc, "PHY not ready\n");
755 return ETIMEDOUT;
756 }
757
758 /* LAN7801 only has RGMII mode. */
759 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
760 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
761
762 if ((sc->mue_flags & LAN7500) ||
763 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
764 !mue_eeprom_present(sc))) {
765 /* Allow MAC to detect speed and duplex from PHY. */
766 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
767 MUE_MAC_CR_AUTO_DUPLEX);
768 }
769
770 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
771 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
772 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
773
774 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
775 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
776
777 /* Set default GPIO/LED settings only if no EEPROM is detected. */
778 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
779 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
780 MUE_SETBIT(sc, MUE_LED_CFG,
781 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
782 }
783
784 /* XXX We assume two LEDs at least when EEPROM is missing. */
785 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
786 !mue_eeprom_present(sc))
787 MUE_SETBIT(sc, MUE_HW_CFG,
788 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
789
790 return 0;
791 }
792
793 static void
794 mue_set_macaddr(struct mue_softc *sc)
795 {
796 struct ifnet *ifp = GET_IFP(sc);
797 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
798 uint32_t lo, hi;
799
800 lo = MUE_ENADDR_LO(enaddr);
801 hi = MUE_ENADDR_HI(enaddr);
802
803 mue_csr_write(sc, MUE_RX_ADDRL, lo);
804 mue_csr_write(sc, MUE_RX_ADDRH, hi);
805 }
806
807 static int
808 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
809 {
810 prop_data_t eaprop;
811 uint32_t low, high;
812
813 if (!(sc->mue_flags & LAN7500)) {
814 low = mue_csr_read(sc, MUE_RX_ADDRL);
815 high = mue_csr_read(sc, MUE_RX_ADDRH);
816 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
817 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
818 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
819 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
820 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
821 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
822 if (ETHER_IS_VALID(sc->mue_enaddr))
823 return 0;
824 else
825 DPRINTF(sc, "registers: %s\n",
826 ether_sprintf(sc->mue_enaddr));
827 }
828
829 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
830 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
831 if (ETHER_IS_VALID(sc->mue_enaddr))
832 return 0;
833 else
834 DPRINTF(sc, "EEPROM: %s\n",
835 ether_sprintf(sc->mue_enaddr));
836 }
837
838 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
839 ETHER_ADDR_LEN) == 0) {
840 if (ETHER_IS_VALID(sc->mue_enaddr))
841 return 0;
842 else
843 DPRINTF(sc, "OTP: %s\n",
844 ether_sprintf(sc->mue_enaddr));
845 }
846
847 /*
848 * Other MD methods. This should be tried only if other methods fail.
849 * Otherwise, MAC address for internal device can be assinged to
850 * external devices on Raspberry Pi, for example.
851 */
852 eaprop = prop_dictionary_get(dict, "mac-address");
853 if (eaprop != NULL) {
854 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
855 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
856 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
857 ETHER_ADDR_LEN);
858 if (ETHER_IS_VALID(sc->mue_enaddr))
859 return 0;
860 else
861 DPRINTF(sc, "prop_dictionary_get: %s\n",
862 ether_sprintf(sc->mue_enaddr));
863 }
864
865 return 1;
866 }
867
868
869 /*
870 * Probe for a Microchip chip. */
871 static int
872 mue_match(device_t parent, cfdata_t match, void *aux)
873 {
874 struct usb_attach_arg *uaa = aux;
875
876 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
877 }
878
879 static void
880 mue_attach(device_t parent, device_t self, void *aux)
881 {
882 struct mue_softc *sc = device_private(self);
883 prop_dictionary_t dict = device_properties(self);
884 struct usb_attach_arg *uaa = aux;
885 struct usbd_device *dev = uaa->uaa_device;
886 usb_interface_descriptor_t *id;
887 usb_endpoint_descriptor_t *ed;
888 char *devinfop;
889 struct mii_data *mii;
890 struct ifnet *ifp;
891 usbd_status err;
892 uint8_t i;
893 int s;
894
895 aprint_naive("\n");
896 aprint_normal("\n");
897
898 sc->mue_dev = self;
899 sc->mue_udev = dev;
900
901 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
902 aprint_normal_dev(self, "%s\n", devinfop);
903 usbd_devinfo_free(devinfop);
904
905 #define MUE_CONFIG_NO 1
906 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
907 if (err) {
908 aprint_error_dev(self, "failed to set configuration: %s\n",
909 usbd_errstr(err));
910 return;
911 }
912
913 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
914 usb_init_task(&sc->mue_stop_task, (void (*)(void *))mue_stop, sc, 0);
915
916 #define MUE_IFACE_IDX 0
917 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
918 if (err) {
919 aprint_error_dev(self, "failed to get interface handle: %s\n",
920 usbd_errstr(err));
921 return;
922 }
923
924 sc->mue_product = uaa->uaa_product;
925 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
926
927 /* Decide on what our bufsize will be. */
928 if (sc->mue_flags & LAN7500)
929 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
930 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
931 else
932 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
933 sc->mue_txbufsz = MUE_TX_BUFSIZE;
934
935 /* Find endpoints. */
936 id = usbd_get_interface_descriptor(sc->mue_iface);
937 for (i = 0; i < id->bNumEndpoints; i++) {
938 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
939 if (ed == NULL) {
940 aprint_error_dev(self, "failed to get ep %hhd\n", i);
941 return;
942 }
943 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
944 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
945 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
946 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
947 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
948 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
949 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
950 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
951 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
952 }
953 }
954 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
955 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
956 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
957
958 s = splnet();
959
960 sc->mue_phyno = 1;
961
962 if (mue_chip_init(sc)) {
963 aprint_error_dev(self, "failed to initialize chip\n");
964 splx(s);
965 return;
966 }
967
968 /* A Microchip chip was detected. Inform the world. */
969 if (sc->mue_flags & LAN7500)
970 aprint_normal_dev(self, "LAN7500\n");
971 else
972 aprint_normal_dev(self, "LAN7800\n");
973
974 if (mue_get_macaddr(sc, dict)) {
975 aprint_error_dev(self, "failed to read MAC address\n");
976 splx(s);
977 return;
978 }
979
980 aprint_normal_dev(self, "Ethernet address %s\n",
981 ether_sprintf(sc->mue_enaddr));
982
983 /* Initialize interface info.*/
984 ifp = GET_IFP(sc);
985 ifp->if_softc = sc;
986 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
987 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
988 ifp->if_init = mue_init;
989 ifp->if_ioctl = mue_ioctl;
990 ifp->if_start = mue_start;
991 ifp->if_stop = mue_stop;
992 ifp->if_watchdog = mue_watchdog;
993
994 IFQ_SET_READY(&ifp->if_snd);
995
996 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
997 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
998 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
999 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1000 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
1001 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
1002
1003 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1004 #if 0 /* XXX not yet */
1005 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
1006 #endif
1007
1008 /* Initialize MII/media info. */
1009 mii = GET_MII(sc);
1010 mii->mii_ifp = ifp;
1011 mii->mii_readreg = mue_miibus_readreg;
1012 mii->mii_writereg = mue_miibus_writereg;
1013 mii->mii_statchg = mue_miibus_statchg;
1014 mii->mii_flags = MIIF_AUTOTSLEEP;
1015
1016 sc->mue_ec.ec_mii = mii;
1017 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1018 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1019
1020 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1021 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1022 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1023 } else
1024 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1025
1026 /* Attach the interface. */
1027 if_attach(ifp);
1028 ether_ifattach(ifp, sc->mue_enaddr);
1029
1030 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1031 RND_TYPE_NET, RND_FLAG_DEFAULT);
1032
1033 callout_init(&sc->mue_stat_ch, 0);
1034
1035 splx(s);
1036
1037 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
1038
1039 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1040 }
1041
1042 static int
1043 mue_detach(device_t self, int flags)
1044 {
1045 struct mue_softc *sc = device_private(self);
1046 struct ifnet *ifp = GET_IFP(sc);
1047 size_t i;
1048 int s;
1049
1050 sc->mue_dying = true;
1051
1052 callout_halt(&sc->mue_stat_ch, NULL);
1053
1054 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1055 if (sc->mue_ep[i] != NULL)
1056 usbd_abort_pipe(sc->mue_ep[i]);
1057
1058 /*
1059 * Remove any pending tasks. They cannot be executing because they run
1060 * in the same thread as detach.
1061 */
1062 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1063 NULL);
1064 usb_rem_task_wait(sc->mue_udev, &sc->mue_stop_task, USB_TASKQ_DRIVER,
1065 NULL);
1066
1067 s = splusb();
1068
1069 if (ifp->if_flags & IFF_RUNNING)
1070 mue_stop(ifp, 1);
1071
1072 rnd_detach_source(&sc->mue_rnd_source);
1073 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1074 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1075 if (ifp->if_softc != NULL) {
1076 ether_ifdetach(ifp);
1077 if_detach(ifp);
1078 }
1079
1080 if (--sc->mue_refcnt >= 0) {
1081 /* Wait for processes to go away. */
1082 usb_detach_waitold(sc->mue_dev);
1083 }
1084 splx(s);
1085
1086 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1087
1088 mutex_destroy(&sc->mue_mii_lock);
1089
1090 return 0;
1091 }
1092
1093 static int
1094 mue_activate(device_t self, enum devact act)
1095 {
1096 struct mue_softc *sc = device_private(self);
1097 struct ifnet *ifp = GET_IFP(sc);
1098
1099 switch (act) {
1100 case DVACT_DEACTIVATE:
1101 if_deactivate(ifp);
1102 sc->mue_dying = true;
1103 return 0;
1104 default:
1105 return EOPNOTSUPP;
1106 }
1107 return 0;
1108 }
1109
1110 static int
1111 mue_rx_list_init(struct mue_softc *sc)
1112 {
1113 struct mue_cdata *cd;
1114 struct mue_chain *c;
1115 size_t i;
1116 int err;
1117
1118 cd = &sc->mue_cdata;
1119 for (i = 0; i < __arraycount(cd->mue_rx_chain); i++) {
1120 c = &cd->mue_rx_chain[i];
1121 c->mue_sc = sc;
1122 c->mue_idx = i;
1123 if (c->mue_xfer == NULL) {
1124 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1125 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1126 if (err)
1127 return err;
1128 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1129 }
1130 }
1131
1132 return 0;
1133 }
1134
1135 static int
1136 mue_tx_list_init(struct mue_softc *sc)
1137 {
1138 struct mue_cdata *cd;
1139 struct mue_chain *c;
1140 size_t i;
1141 int err;
1142
1143 cd = &sc->mue_cdata;
1144 for (i = 0; i < __arraycount(cd->mue_tx_chain); i++) {
1145 c = &cd->mue_tx_chain[i];
1146 c->mue_sc = sc;
1147 c->mue_idx = i;
1148 if (c->mue_xfer == NULL) {
1149 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1150 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1151 &c->mue_xfer);
1152 if (err)
1153 return err;
1154 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1155 }
1156 }
1157
1158 return 0;
1159 }
1160
1161 static int
1162 mue_open_pipes(struct mue_softc *sc)
1163 {
1164 usbd_status err;
1165
1166 /* Open RX and TX pipes. */
1167 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1168 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1169 if (err) {
1170 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1171 return EIO;
1172 }
1173 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1174 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1175 if (err) {
1176 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1177 return EIO;
1178 }
1179 return 0;
1180 }
1181
1182 static void
1183 mue_startup_rx_pipes(struct mue_softc *sc)
1184 {
1185 struct mue_chain *c;
1186 size_t i;
1187
1188 /* Start up the receive pipe. */
1189 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++) {
1190 c = &sc->mue_cdata.mue_rx_chain[i];
1191 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1192 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1193 usbd_transfer(c->mue_xfer);
1194 }
1195 }
1196
1197 static int
1198 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1199 {
1200 struct ifnet *ifp = GET_IFP(sc);
1201 struct mue_chain *c;
1202 usbd_status err;
1203 struct mue_txbuf_hdr hdr;
1204 uint32_t tx_cmd_a, tx_cmd_b;
1205 int csum, len;
1206 bool tso, ipe, tpe;
1207
1208 csum = m->m_pkthdr.csum_flags;
1209 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
1210 ipe = csum & M_CSUM_IPv4;
1211 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
1212 M_CSUM_TCPv6 | M_CSUM_UDPv6);
1213
1214 len = m->m_pkthdr.len;
1215 if (__predict_false((!tso &&
1216 (unsigned)len > MUE_FRAME_LEN(ifp->if_mtu)) ||
1217 ( tso && len > MUE_TSO_FRAME_LEN))) {
1218 MUE_PRINTF(sc, "packet length %d\n too long", len);
1219 return EINVAL;
1220 }
1221
1222 c = &sc->mue_cdata.mue_tx_chain[idx];
1223
1224 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
1225 tx_cmd_a = len | MUE_TX_CMD_A_FCS;
1226
1227 if (tso) {
1228 tx_cmd_a |= MUE_TX_CMD_A_LSO;
1229 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1230 tx_cmd_b = m->m_pkthdr.segsz;
1231 else
1232 tx_cmd_b = MUE_TX_MSS_MIN;
1233 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
1234 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
1235 mue_tx_offload(sc, m);
1236 } else {
1237 if (ipe)
1238 tx_cmd_a |= MUE_TX_CMD_A_IPE;
1239 if (tpe)
1240 tx_cmd_a |= MUE_TX_CMD_A_TPE;
1241 tx_cmd_b = 0;
1242 }
1243
1244 hdr.tx_cmd_a = htole32(tx_cmd_a);
1245 hdr.tx_cmd_b = htole32(tx_cmd_b);
1246
1247 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1248 m_copydata(m, 0, len, c->mue_buf + sizeof(hdr));
1249
1250 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr),
1251 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1252
1253 /* Transmit */
1254 err = usbd_transfer(c->mue_xfer);
1255 if (__predict_false(err != USBD_IN_PROGRESS)) {
1256 MUE_PRINTF(sc, "%s\n", usbd_errstr(err));
1257 mue_stop(ifp, 0);
1258 return EIO;
1259 }
1260
1261 sc->mue_cdata.mue_tx_cnt++;
1262
1263 return 0;
1264 }
1265
1266 static void
1267 mue_tx_offload(struct mue_softc *sc, struct mbuf *m)
1268 {
1269 struct ether_header *eh;
1270 struct ip *ip;
1271 struct ip6_hdr *ip6;
1272 int off;
1273
1274 eh = mtod(m, struct ether_header *);
1275 switch (htons(eh->ether_type)) {
1276 case ETHERTYPE_IP:
1277 case ETHERTYPE_IPV6:
1278 off = ETHER_HDR_LEN;
1279 break;
1280 case ETHERTYPE_VLAN:
1281 /* XXX not yet supported */
1282 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1283 break;
1284 default:
1285 /* XXX */
1286 panic("%s: unsupported ethertype\n", __func__);
1287 /* NOTREACHED */
1288 }
1289
1290 /* Packet length should be cleared. */
1291 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1292 ip = (void *)(mtod(m, char *) + off);
1293 ip->ip_len = 0;
1294 } else {
1295 ip6 = (void *)(mtod(m, char *) + off);
1296 ip6->ip6_plen = 0;
1297 }
1298 }
1299
1300 static void
1301 mue_setmulti(struct mue_softc *sc)
1302 {
1303 struct ifnet *ifp = GET_IFP(sc);
1304 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1305 struct ether_multi *enm;
1306 struct ether_multistep step;
1307 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1308 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1309 uint32_t reg, rxfilt, h, hireg, loreg;
1310 size_t i;
1311
1312 if (sc->mue_dying)
1313 return;
1314
1315 /* Clear perfect filter and hash tables. */
1316 memset(pfiltbl, 0, sizeof(pfiltbl));
1317 memset(hashtbl, 0, sizeof(hashtbl));
1318
1319 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1320 rxfilt = mue_csr_read(sc, reg);
1321 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1322 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1323
1324 /* Always accept broadcast frames. */
1325 rxfilt |= MUE_RFE_CTL_BROADCAST;
1326
1327 if (ifp->if_flags & IFF_PROMISC) {
1328 rxfilt |= MUE_RFE_CTL_UNICAST;
1329 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1330 ifp->if_flags |= IFF_ALLMULTI;
1331 if (ifp->if_flags & IFF_PROMISC)
1332 DPRINTF(sc, "promisc\n");
1333 else
1334 DPRINTF(sc, "allmulti\n");
1335 } else {
1336 /* Now program new ones. */
1337 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1338 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1339 i = 1;
1340 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1341 while (enm != NULL) {
1342 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1343 ETHER_ADDR_LEN)) {
1344 memset(pfiltbl, 0, sizeof(pfiltbl));
1345 memset(hashtbl, 0, sizeof(hashtbl));
1346 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1347 goto allmulti;
1348 }
1349 if (i < MUE_NUM_ADDR_FILTX) {
1350 /* Use perfect address table if possible. */
1351 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1352 MUE_ADDR_FILTX_VALID;
1353 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1354 } else {
1355 /* Otherwise, use hash table. */
1356 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1357 h = (ether_crc32_be(enm->enm_addrlo,
1358 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1359 hashtbl[h / 32] |= 1 << (h % 32);
1360 }
1361 i++;
1362 ETHER_NEXT_MULTI(step, enm);
1363 }
1364 rxfilt |= MUE_RFE_CTL_PERFECT;
1365 ifp->if_flags &= ~IFF_ALLMULTI;
1366 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH)
1367 DPRINTF(sc, "perfect filter and hash tables\n");
1368 else
1369 DPRINTF(sc, "perfect filter\n");
1370 }
1371
1372 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1373 hireg = (sc->mue_flags & LAN7500) ?
1374 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1375 loreg = hireg + 4;
1376 mue_csr_write(sc, hireg, 0);
1377 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1378 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1379 }
1380
1381 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1382 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1383
1384 mue_csr_write(sc, reg, rxfilt);
1385 }
1386
1387 static void
1388 mue_sethwcsum(struct mue_softc *sc)
1389 {
1390 struct ifnet *ifp = GET_IFP(sc);
1391 uint32_t reg, val;
1392
1393 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1394 val = mue_csr_read(sc, reg);
1395
1396 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) {
1397 DPRINTF(sc, "enabled\n");
1398 val |= MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE;
1399 val |= MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE;
1400 } else {
1401 DPRINTF(sc, "disabled\n");
1402 val &=
1403 ~(MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE);
1404 val &=
1405 ~(MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE);
1406 }
1407
1408 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1409
1410 mue_csr_write(sc, reg, val);
1411 }
1412
1413 static void
1414 mue_setmtu(struct mue_softc *sc)
1415 {
1416 struct ifnet *ifp = GET_IFP(sc);
1417 uint32_t val;
1418
1419 /* Set the maximum frame size. */
1420 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1421 val = mue_csr_read(sc, MUE_MAC_RX);
1422 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1423 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1424 mue_csr_write(sc, MUE_MAC_RX, val);
1425 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1426 }
1427
1428 static void
1429 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1430 {
1431 struct mue_chain *c = (struct mue_chain *)priv;
1432 struct mue_softc *sc = c->mue_sc;
1433 struct ifnet *ifp = GET_IFP(sc);
1434 struct mbuf *m;
1435 struct mue_rxbuf_hdr *hdrp;
1436 uint32_t rx_cmd_a, totlen;
1437 uint16_t pktlen;
1438 int s;
1439 int csum;
1440 char *buf = c->mue_buf;
1441 bool v6;
1442
1443 if (__predict_false(sc->mue_dying)) {
1444 DPRINTF(sc, "dying\n");
1445 return;
1446 }
1447
1448 if (__predict_false(!(ifp->if_flags & IFF_RUNNING))) {
1449 DPRINTF(sc, "not running\n");
1450 return;
1451 }
1452
1453 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1454 DPRINTF(sc, "%s\n", usbd_errstr(status));
1455 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1456 return;
1457 if (usbd_ratecheck(&sc->mue_rx_notice))
1458 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1459 if (status == USBD_STALLED)
1460 usbd_clear_endpoint_stall_async(
1461 sc->mue_ep[MUE_ENDPT_RX]);
1462 goto done;
1463 }
1464
1465 usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL);
1466
1467 KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u",
1468 totlen, sc->mue_rxbufsz);
1469
1470 do {
1471 if (__predict_false(totlen < sizeof(*hdrp))) {
1472 MUE_PRINTF(sc, "packet length %u too short\n", totlen);
1473 ifp->if_ierrors++;
1474 goto done;
1475 }
1476
1477 hdrp = (struct mue_rxbuf_hdr *)buf;
1478 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1479
1480 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1481 /*
1482 * We cannot use MUE_RX_CMD_A_RED bit here;
1483 * it is turned on in the cases of L3/L4
1484 * checksum errors which we handle below.
1485 */
1486 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1487 ifp->if_ierrors++;
1488 goto done;
1489 }
1490
1491 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1492 if (sc->mue_flags & LAN7500)
1493 pktlen -= 2;
1494
1495 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1496 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1497 pktlen + sizeof(*hdrp) > totlen)) {
1498 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1499 ifp->if_ierrors++;
1500 goto done;
1501 }
1502
1503 m = mue_newbuf();
1504 if (__predict_false(m == NULL)) {
1505 MUE_PRINTF(sc, "failed to allocate mbuf\n");
1506 ifp->if_ierrors++;
1507 goto done;
1508 }
1509
1510 m_set_rcvif(m, ifp);
1511 m->m_pkthdr.len = m->m_len = pktlen;
1512 m->m_flags |= M_HASFCS;
1513
1514 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1515 csum = 0;
1516 } else {
1517 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1518 switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1519 case MUE_RX_CMD_A_PID_TCP:
1520 csum = v6 ?
1521 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1522 break;
1523 case MUE_RX_CMD_A_PID_UDP:
1524 csum = v6 ?
1525 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1526 break;
1527 case MUE_RX_CMD_A_PID_IP:
1528 csum = v6 ? 0 : M_CSUM_IPv4;
1529 break;
1530 default:
1531 csum = 0;
1532 break;
1533 }
1534 csum &= ifp->if_csum_flags_rx;
1535 if (__predict_false((csum & M_CSUM_IPv4) &&
1536 (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1537 csum |= M_CSUM_IPv4_BAD;
1538 if (__predict_false((csum & ~M_CSUM_IPv4) &&
1539 (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1540 csum |= M_CSUM_TCP_UDP_BAD;
1541 }
1542 m->m_pkthdr.csum_flags = csum;
1543 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1544
1545 /* Attention: sizeof(hdr) = 10 */
1546 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1547 if (pktlen > totlen)
1548 pktlen = totlen;
1549 totlen -= pktlen;
1550 buf += pktlen;
1551
1552 s = splnet();
1553 if_percpuq_enqueue(ifp->if_percpuq, m);
1554 splx(s);
1555 } while (totlen > 0);
1556
1557 done:
1558 /* Setup new transfer. */
1559 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1560 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1561 usbd_transfer(xfer);
1562 }
1563
1564 static void
1565 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1566 {
1567 struct mue_chain *c = priv;
1568 struct mue_softc *sc = c->mue_sc;
1569 struct ifnet *ifp = GET_IFP(sc);
1570 int s;
1571
1572 if (__predict_false(sc->mue_dying))
1573 return;
1574
1575 s = splnet();
1576
1577 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1578 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1579 splx(s);
1580 return;
1581 }
1582 ifp->if_oerrors++;
1583 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1584 if (status == USBD_STALLED)
1585 usbd_clear_endpoint_stall_async(
1586 sc->mue_ep[MUE_ENDPT_TX]);
1587 splx(s);
1588 return;
1589 }
1590
1591 ifp->if_timer = 0;
1592 ifp->if_flags &= ~IFF_OACTIVE;
1593
1594 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1595 mue_start(ifp);
1596
1597 ifp->if_opackets++;
1598 splx(s);
1599 }
1600
1601 static int
1602 mue_init(struct ifnet *ifp)
1603 {
1604 struct mue_softc *sc = ifp->if_softc;
1605 int s;
1606
1607 if (sc->mue_dying) {
1608 DPRINTF(sc, "dying\n");
1609 return EIO;
1610 }
1611
1612 s = splnet();
1613
1614 /* Cancel pending I/O and free all TX/RX buffers. */
1615 if (ifp->if_flags & IFF_RUNNING)
1616 mue_stop(ifp, 1);
1617
1618 mue_reset(sc);
1619
1620 /* Set MAC address. */
1621 mue_set_macaddr(sc);
1622
1623 /* Load the multicast filter. */
1624 mue_setmulti(sc);
1625
1626 /* TCP/UDP checksum offload engines. */
1627 mue_sethwcsum(sc);
1628
1629 /* Set MTU. */
1630 mue_setmtu(sc);
1631
1632 if (mue_open_pipes(sc)) {
1633 splx(s);
1634 return EIO;
1635 }
1636
1637 /* Init RX ring. */
1638 if (mue_rx_list_init(sc)) {
1639 MUE_PRINTF(sc, "failed to init rx list\n");
1640 splx(s);
1641 return ENOBUFS;
1642 }
1643
1644 /* Init TX ring. */
1645 if (mue_tx_list_init(sc)) {
1646 MUE_PRINTF(sc, "failed to init tx list\n");
1647 splx(s);
1648 return ENOBUFS;
1649 }
1650
1651 mue_startup_rx_pipes(sc);
1652
1653 ifp->if_flags |= IFF_RUNNING;
1654 ifp->if_flags &= ~IFF_OACTIVE;
1655
1656 splx(s);
1657
1658 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1659
1660 return 0;
1661 }
1662
1663 static int
1664 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1665 {
1666 struct mue_softc *sc = ifp->if_softc;
1667 struct ifreq /*const*/ *ifr = data;
1668 int s, error = 0;
1669
1670 s = splnet();
1671
1672 switch (cmd) {
1673 case SIOCSIFFLAGS:
1674 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1675 break;
1676
1677 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1678 case IFF_RUNNING:
1679 mue_stop(ifp, 1);
1680 break;
1681 case IFF_UP:
1682 mue_init(ifp);
1683 break;
1684 case IFF_UP | IFF_RUNNING:
1685 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1686 mue_setmulti(sc);
1687 else
1688 mue_init(ifp);
1689 break;
1690 }
1691 sc->mue_if_flags = ifp->if_flags;
1692 break;
1693 case SIOCGIFMEDIA:
1694 case SIOCSIFMEDIA:
1695 error = ifmedia_ioctl(ifp, ifr, &sc->mue_mii.mii_media, cmd);
1696 break;
1697 default:
1698 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1699 break;
1700 error = 0;
1701 switch (cmd) {
1702 case SIOCADDMULTI:
1703 case SIOCDELMULTI:
1704 mue_setmulti(sc);
1705 break;
1706 case SIOCSIFCAP:
1707 mue_sethwcsum(sc);
1708 break;
1709 case SIOCSIFMTU:
1710 mue_setmtu(sc);
1711 break;
1712 default:
1713 break;
1714 }
1715 break;
1716 }
1717 splx(s);
1718
1719 return error;
1720 }
1721
1722 static void
1723 mue_watchdog(struct ifnet *ifp)
1724 {
1725 struct mue_softc *sc = ifp->if_softc;
1726 struct mue_chain *c;
1727 usbd_status stat;
1728 int s;
1729
1730 ifp->if_oerrors++;
1731 MUE_PRINTF(sc, "timed out\n");
1732
1733 s = splusb();
1734 c = &sc->mue_cdata.mue_tx_chain[0];
1735 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1736 mue_txeof(c->mue_xfer, c, stat);
1737
1738 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1739 mue_start(ifp);
1740 splx(s);
1741 }
1742
1743 static void
1744 mue_reset(struct mue_softc *sc)
1745 {
1746 if (sc->mue_dying)
1747 return;
1748
1749 /* Wait a little while for the chip to get its brains in order. */
1750 usbd_delay_ms(sc->mue_udev, 1);
1751
1752 // mue_chip_init(sc); /* XXX */
1753 }
1754
1755 static void
1756 mue_start(struct ifnet *ifp)
1757 {
1758 struct mue_softc *sc = ifp->if_softc;
1759 struct mbuf *m;
1760
1761 if (__predict_false(!sc->mue_link)) {
1762 DPRINTF(sc, "no link\n");
1763 return;
1764 }
1765
1766 if (__predict_false((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING))
1767 != IFF_RUNNING)) {
1768 DPRINTF(sc, "not ready\n");
1769 return;
1770 }
1771
1772 IFQ_POLL(&ifp->if_snd, m);
1773 if (m == NULL)
1774 return;
1775
1776 if (__predict_false(mue_encap(sc, m, 0))) {
1777 ifp->if_oerrors++;
1778 return;
1779 }
1780 IFQ_DEQUEUE(&ifp->if_snd, m);
1781
1782 bpf_mtap(ifp, m, BPF_D_OUT);
1783 m_freem(m);
1784
1785 ifp->if_flags |= IFF_OACTIVE;
1786
1787 /* Set a timeout in case the chip goes out to lunch. */
1788 ifp->if_timer = 5;
1789 }
1790
1791 static void
1792 mue_stop(struct ifnet *ifp, int disable __unused)
1793 {
1794 struct mue_softc *sc = ifp->if_softc;
1795 usbd_status err;
1796 size_t i;
1797
1798 mue_reset(sc);
1799
1800 ifp->if_timer = 0;
1801 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1802
1803 callout_stop(&sc->mue_stat_ch);
1804
1805 /* Stop transfers. */
1806 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1807 if (sc->mue_ep[i] != NULL) {
1808 err = usbd_abort_pipe(sc->mue_ep[i]);
1809 if (err)
1810 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1811 i, usbd_errstr(err));
1812 }
1813
1814 /* Free RX resources. */
1815 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++)
1816 if (sc->mue_cdata.mue_rx_chain[i].mue_xfer != NULL) {
1817 usbd_destroy_xfer(
1818 sc->mue_cdata.mue_rx_chain[i].mue_xfer);
1819 sc->mue_cdata.mue_rx_chain[i].mue_xfer = NULL;
1820 }
1821
1822 /* Free TX resources. */
1823 for (i = 0; i < __arraycount(sc->mue_cdata.mue_tx_chain); i++)
1824 if (sc->mue_cdata.mue_tx_chain[i].mue_xfer != NULL) {
1825 usbd_destroy_xfer(
1826 sc->mue_cdata.mue_tx_chain[i].mue_xfer);
1827 sc->mue_cdata.mue_tx_chain[i].mue_xfer = NULL;
1828 }
1829
1830 /* Close pipes */
1831 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1832 if (sc->mue_ep[i] != NULL) {
1833 err = usbd_close_pipe(sc->mue_ep[i]);
1834 if (err)
1835 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1836 i, usbd_errstr(err));
1837 sc->mue_ep[i] = NULL;
1838 }
1839
1840 sc->mue_link = 0; /* XXX */
1841
1842 DPRINTF(sc, "done\n");
1843 }
1844
1845 static void
1846 mue_tick(void *xsc)
1847 {
1848 struct mue_softc *sc = xsc;
1849
1850 if (sc == NULL)
1851 return;
1852
1853 if (sc->mue_dying)
1854 return;
1855
1856 /* Perform periodic stuff in process context. */
1857 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1858 }
1859
1860 static void
1861 mue_tick_task(void *xsc)
1862 {
1863 struct mue_softc *sc = xsc;
1864 struct ifnet *ifp = GET_IFP(sc);
1865 struct mii_data *mii = GET_MII(sc);
1866 int s;
1867
1868 if (sc == NULL)
1869 return;
1870
1871 if (sc->mue_dying)
1872 return;
1873
1874 s = splnet();
1875 mii_tick(mii);
1876 if (sc->mue_link == 0)
1877 mue_miibus_statchg(ifp);
1878 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1879 splx(s);
1880 }
1881
1882 static struct mbuf *
1883 mue_newbuf(void)
1884 {
1885 struct mbuf *m;
1886
1887 MGETHDR(m, M_DONTWAIT, MT_DATA);
1888 if (__predict_false(m == NULL))
1889 return NULL;
1890
1891 MCLGET(m, M_DONTWAIT);
1892 if (__predict_false(!(m->m_flags & M_EXT))) {
1893 m_freem(m);
1894 return NULL;
1895 }
1896
1897 m_adj(m, ETHER_ALIGN);
1898
1899 return m;
1900 }
1901