if_mue.c revision 1.31 1 /* $NetBSD: if_mue.c,v 1.31 2019/02/03 13:11:07 mlelstv Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.31 2019/02/03 13:11:07 mlelstv Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/mutex.h>
36 #include <sys/kernel.h>
37 #include <sys/proc.h>
38 #include <sys/socket.h>
39
40 #include <sys/device.h>
41
42 #include <sys/rndsource.h>
43
44 #include <net/if.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_ether.h>
48
49 #include <net/bpf.h>
50
51 #include <netinet/if_inarp.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h> /* XXX for struct ip */
54 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
55
56 #include <dev/mii/mii.h>
57 #include <dev/mii/miivar.h>
58
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
61 #include <dev/usb/usbdi_util.h>
62 #include <dev/usb/usbdivar.h>
63 #include <dev/usb/usbdevs.h>
64
65 #include <dev/usb/if_muereg.h>
66 #include <dev/usb/if_muevar.h>
67
68 #define MUE_PRINTF(sc, fmt, args...) \
69 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
70
71 #ifdef USB_DEBUG
72 int muedebug = 0;
73 #define DPRINTF(sc, fmt, args...) \
74 do { \
75 if (muedebug) \
76 MUE_PRINTF(sc, fmt, ##args); \
77 } while (0 /* CONSTCOND */)
78 #else
79 #define DPRINTF(sc, fmt, args...) __nothing
80 #endif
81
82 /*
83 * Various supported device vendors/products.
84 */
85 struct mue_type {
86 struct usb_devno mue_dev;
87 uint16_t mue_flags;
88 #define LAN7500 0x0001 /* LAN7500 */
89 };
90
91 const struct mue_type mue_devs[] = {
92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
97 };
98
99 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
100 uaa->uaa_vendor, uaa->uaa_product))
101
102 #define MUE_ENADDR_LO(enaddr) \
103 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
104 #define MUE_ENADDR_HI(enaddr) \
105 ((enaddr[5] << 8) | enaddr[4])
106
107 static int mue_match(device_t, cfdata_t, void *);
108 static void mue_attach(device_t, device_t, void *);
109 static int mue_detach(device_t, int);
110 static int mue_activate(device_t, enum devact);
111
112 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
113 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
114 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
115 uint32_t, uint32_t);
116
117 static void mue_lock_mii(struct mue_softc *);
118 static void mue_unlock_mii(struct mue_softc *);
119
120 static int mue_miibus_readreg(device_t, int, int, uint16_t *);
121 static int mue_miibus_writereg(device_t, int, int, uint16_t);
122 static void mue_miibus_statchg(struct ifnet *);
123 static int mue_ifmedia_upd(struct ifnet *);
124 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125
126 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
127 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
128 static bool mue_eeprom_present(struct mue_softc *sc);
129
130 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
131 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
132
133 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
134 uint32_t, uint32_t *);
135
136 static void mue_init_ltm(struct mue_softc *);
137
138 static int mue_chip_init(struct mue_softc *);
139
140 static void mue_set_macaddr(struct mue_softc *);
141 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
142
143 static int mue_rx_list_init(struct mue_softc *);
144 static int mue_tx_list_init(struct mue_softc *);
145 static int mue_open_pipes(struct mue_softc *);
146 static void mue_startup_rx_pipes(struct mue_softc *);
147
148 static int mue_encap(struct mue_softc *, struct mbuf *, int);
149 static void mue_tx_offload(struct mue_softc *, struct mbuf *);
150
151 static void mue_setmulti(struct mue_softc *);
152 static void mue_sethwcsum(struct mue_softc *);
153 static void mue_setmtu(struct mue_softc *);
154
155 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
156 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
157
158 static int mue_init(struct ifnet *);
159 static int mue_ioctl(struct ifnet *, u_long, void *);
160 static void mue_watchdog(struct ifnet *);
161 static void mue_reset(struct mue_softc *);
162 static void mue_start(struct ifnet *);
163 static void mue_stop(struct ifnet *, int);
164 static void mue_tick(void *);
165 static void mue_tick_task(void *);
166
167 static struct mbuf *mue_newbuf(void);
168
169 #define MUE_SETBIT(sc, reg, x) \
170 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
171
172 #define MUE_CLRBIT(sc, reg, x) \
173 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
174
175 #define MUE_WAIT_SET(sc, reg, set, fail) \
176 mue_wait_for_bits(sc, reg, set, ~0, fail)
177
178 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
179 mue_wait_for_bits(sc, reg, 0, clear, fail)
180
181 #define ETHER_IS_VALID(addr) \
182 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
183
184 #define ETHER_IS_ZERO(addr) \
185 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
186
187 #define ETHER_ALIGN 2
188
189 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
190 mue_detach, mue_activate);
191
192 static uint32_t
193 mue_csr_read(struct mue_softc *sc, uint32_t reg)
194 {
195 usb_device_request_t req;
196 usbd_status err;
197 uDWord val;
198
199 if (sc->mue_dying)
200 return 0;
201
202 USETDW(val, 0);
203 req.bmRequestType = UT_READ_VENDOR_DEVICE;
204 req.bRequest = MUE_UR_READREG;
205 USETW(req.wValue, 0);
206 USETW(req.wIndex, reg);
207 USETW(req.wLength, 4);
208
209 err = usbd_do_request(sc->mue_udev, &req, &val);
210 if (err) {
211 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
212 return 0;
213 }
214
215 return UGETDW(val);
216 }
217
218 static int
219 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
220 {
221 usb_device_request_t req;
222 usbd_status err;
223 uDWord val;
224
225 if (sc->mue_dying)
226 return 0;
227
228 USETDW(val, aval);
229 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
230 req.bRequest = MUE_UR_WRITEREG;
231 USETW(req.wValue, 0);
232 USETW(req.wIndex, reg);
233 USETW(req.wLength, 4);
234
235 err = usbd_do_request(sc->mue_udev, &req, &val);
236 if (err) {
237 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
238 return -1;
239 }
240
241 return 0;
242 }
243
244 static int
245 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
246 uint32_t set, uint32_t clear, uint32_t fail)
247 {
248 uint32_t val;
249 int ntries;
250
251 for (ntries = 0; ntries < 1000; ntries++) {
252 val = mue_csr_read(sc, reg);
253 if ((val & set) || !(val & clear))
254 return 0;
255 if (val & fail)
256 return 1;
257 usbd_delay_ms(sc->mue_udev, 1);
258 }
259
260 return 1;
261 }
262
263 /*
264 * Get exclusive access to the MII registers.
265 */
266 static void
267 mue_lock_mii(struct mue_softc *sc)
268 {
269 sc->mue_refcnt++;
270 mutex_enter(&sc->mue_mii_lock);
271 }
272
273 static void
274 mue_unlock_mii(struct mue_softc *sc)
275 {
276 mutex_exit(&sc->mue_mii_lock);
277 if (--sc->mue_refcnt < 0)
278 usb_detach_wakeupold(sc->mue_dev);
279 }
280
281 static int
282 mue_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
283 {
284 struct mue_softc *sc = device_private(dev);
285 uint32_t data;
286 int rv = 0;
287
288 if (sc->mue_dying) {
289 DPRINTF(sc, "dying\n");
290 return -1;
291 }
292
293 if (sc->mue_phyno != phy)
294 return -1;
295
296 mue_lock_mii(sc);
297 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
298 mue_unlock_mii(sc);
299 MUE_PRINTF(sc, "not ready\n");
300 return -1;
301 }
302
303 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
304 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
305 MUE_MII_ACCESS_PHYADDR(phy));
306
307 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
308 MUE_PRINTF(sc, "timed out\n");
309 rv = ETIMEDOUT;
310 goto out;
311 }
312
313 data = mue_csr_read(sc, MUE_MII_DATA);
314 *val = data & 0xffff;
315
316 out:
317 mue_unlock_mii(sc);
318 return rv;
319 }
320
321 static int
322 mue_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
323 {
324 struct mue_softc *sc = device_private(dev);
325 int rv = 0;
326
327 if (sc->mue_dying) {
328 DPRINTF(sc, "dying\n");
329 return -1;
330 }
331
332 if (sc->mue_phyno != phy) {
333 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
334 sc->mue_phyno, phy);
335 return -1;
336 }
337
338 mue_lock_mii(sc);
339 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
340 MUE_PRINTF(sc, "not ready\n");
341 rv = EBUSY;
342 goto out;
343 }
344
345 mue_csr_write(sc, MUE_MII_DATA, val);
346 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
347 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
348 MUE_MII_ACCESS_PHYADDR(phy));
349
350 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
351 MUE_PRINTF(sc, "timed out\n");
352 rv = ETIMEDOUT;
353 }
354 out:
355 mue_unlock_mii(sc);
356 return rv;
357 }
358
359 static void
360 mue_miibus_statchg(struct ifnet *ifp)
361 {
362 struct mue_softc *sc = ifp->if_softc;
363 struct mii_data *mii = GET_MII(sc);
364 uint32_t flow, threshold;
365
366 if (mii == NULL || ifp == NULL || (ifp->if_flags & IFF_RUNNING) == 0) {
367 DPRINTF(sc, "not ready\n");
368 return;
369 }
370
371 sc->mue_link = 0;
372 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
373 (IFM_ACTIVE | IFM_AVALID)) {
374 switch (IFM_SUBTYPE(mii->mii_media_active)) {
375 case IFM_10_T:
376 case IFM_100_TX:
377 case IFM_1000_T:
378 sc->mue_link++;
379 break;
380 default:
381 break;
382 }
383 }
384
385 /* Lost link, do nothing. */
386 if (sc->mue_link == 0) {
387 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
388 return;
389 }
390
391 if (!(sc->mue_flags & LAN7500)) {
392 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
393 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
394 /* Disable U2 and enable U1. */
395 MUE_CLRBIT(sc, MUE_USB_CFG1,
396 MUE_USB_CFG1_DEV_U2_INIT_EN);
397 MUE_SETBIT(sc, MUE_USB_CFG1,
398 MUE_USB_CFG1_DEV_U1_INIT_EN);
399 } else {
400 /* Enable U1 and U2. */
401 MUE_SETBIT(sc, MUE_USB_CFG1,
402 MUE_USB_CFG1_DEV_U1_INIT_EN |
403 MUE_USB_CFG1_DEV_U2_INIT_EN);
404 }
405 }
406 }
407
408 flow = 0;
409 /* XXX Linux does not check IFM_FDX flag for 7800. */
410 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
411 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
412 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
413 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
414 flow |= MUE_FLOW_RX_FCEN;
415 }
416
417 /* XXX Magic numbers taken from Linux driver. */
418 if (sc->mue_flags & LAN7500)
419 threshold = 0x820;
420 else
421 switch (sc->mue_udev->ud_speed) {
422 case USB_SPEED_SUPER:
423 threshold = 0x817;
424 break;
425 case USB_SPEED_HIGH:
426 threshold = 0x211;
427 break;
428 default:
429 threshold = 0;
430 break;
431 }
432
433 /* Threshold value should be set before enabling flow. */
434 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
435 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
436 mue_csr_write(sc, MUE_FLOW, flow);
437
438 DPRINTF(sc, "done\n");
439 }
440
441 /*
442 * Set media options.
443 */
444 static int
445 mue_ifmedia_upd(struct ifnet *ifp)
446 {
447 struct mue_softc *sc = ifp->if_softc;
448 struct mii_data *mii = GET_MII(sc);
449
450 sc->mue_link = 0; /* XXX */
451
452 if (mii->mii_instance) {
453 struct mii_softc *miisc;
454 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
455 mii_phy_reset(miisc);
456 }
457 return mii_mediachg(mii);
458 }
459
460 /*
461 * Report current media status.
462 */
463 static void
464 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
465 {
466 struct mue_softc *sc = ifp->if_softc;
467 struct mii_data *mii = GET_MII(sc);
468
469 mii_pollstat(mii);
470 ifmr->ifm_active = mii->mii_media_active;
471 ifmr->ifm_status = mii->mii_media_status;
472 }
473
474 static uint8_t
475 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
476 {
477 uint32_t val;
478
479 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
480 MUE_PRINTF(sc, "not ready\n");
481 return ETIMEDOUT;
482 }
483
484 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
485 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
486 off);
487
488 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
489 MUE_E2P_CMD_TIMEOUT)) {
490 MUE_PRINTF(sc, "timed out\n");
491 return ETIMEDOUT;
492 }
493
494 val = mue_csr_read(sc, MUE_E2P_DATA);
495 *dest = val & 0xff;
496
497 return 0;
498 }
499
500 static int
501 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
502 {
503 uint32_t val = 0; /* XXX gcc */
504 uint8_t byte;
505 int i, err;
506
507 /*
508 * EEPROM pins are muxed with the LED function on LAN7800 device.
509 */
510 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
511 val = mue_csr_read(sc, MUE_HW_CFG);
512 mue_csr_write(sc, MUE_HW_CFG,
513 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
514 }
515
516 for (i = 0; i < cnt; i++) {
517 err = mue_eeprom_getbyte(sc, off + i, &byte);
518 if (err)
519 break;
520 *(dest + i) = byte;
521 }
522
523 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
524 mue_csr_write(sc, MUE_HW_CFG, val);
525
526 return err ? 1 : 0;
527 }
528
529 static bool
530 mue_eeprom_present(struct mue_softc *sc)
531 {
532 uint32_t val;
533 uint8_t sig;
534 int ret;
535
536 if (sc->mue_flags & LAN7500) {
537 val = mue_csr_read(sc, MUE_E2P_CMD);
538 return val & MUE_E2P_CMD_LOADED;
539 } else {
540 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
541 return (ret == 0) && (sig == MUE_E2P_IND);
542 }
543 }
544
545 static int
546 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
547 {
548 uint32_t val;
549 int i, err;
550
551 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
552
553 /* Checking if bit is set. */
554 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
555 /* Clear it, then wait for it to be cleared. */
556 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
557 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
558 0);
559 if (err) {
560 MUE_PRINTF(sc, "not ready\n");
561 return 1;
562 }
563 }
564
565 /* Start reading the bytes, one at a time. */
566 for (i = 0; i < cnt; i++) {
567 mue_csr_write(sc, MUE_OTP_ADDR1,
568 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
569 mue_csr_write(sc, MUE_OTP_ADDR2,
570 ((off + i) & MUE_OTP_ADDR2_MASK));
571 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
572 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
573
574 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
575 if (err) {
576 MUE_PRINTF(sc, "timed out\n");
577 return 1;
578 }
579 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
580 *(dest + i) = (uint8_t)(val & 0xff);
581 }
582
583 return 0;
584 }
585
586 static int
587 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
588 {
589 uint8_t sig;
590 int err;
591
592 if (sc->mue_flags & LAN7500)
593 return 1;
594
595 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
596 if (err)
597 return 1;
598 switch (sig) {
599 case MUE_OTP_IND_1:
600 break;
601 case MUE_OTP_IND_2:
602 off += 0x100;
603 break;
604 default:
605 DPRINTF(sc, "OTP not found\n");
606 return 1;
607 }
608 err = mue_read_otp_raw(sc, dest, off, cnt);
609 return err;
610 }
611
612 static void
613 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
614 uint32_t cnt, uint32_t *data)
615 {
616 uint32_t i;
617
618 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
619 MUE_PRINTF(sc, "not ready\n");
620 return;
621 }
622
623 mue_csr_write(sc, MUE_DP_SEL,
624 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
625
626 for (i = 0; i < cnt; i++) {
627 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
628 mue_csr_write(sc, MUE_DP_DATA, data[i]);
629 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
630 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
631 MUE_PRINTF(sc, "timed out\n");
632 return;
633 }
634 }
635 }
636
637 static void
638 mue_init_ltm(struct mue_softc *sc)
639 {
640 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
641 uint8_t temp[2];
642 size_t i;
643
644 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
645 if (mue_eeprom_present(sc) &&
646 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
647 if (temp[0] != sizeof(idx)) {
648 DPRINTF(sc, "EEPROM: unexpected size\n");
649 goto done;
650 }
651 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
652 sizeof(idx))) {
653 DPRINTF(sc, "EEPROM: failed to read\n");
654 goto done;
655 }
656 DPRINTF(sc, "success\n");
657 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
658 if (temp[0] != sizeof(idx)) {
659 DPRINTF(sc, "OTP: unexpected size\n");
660 goto done;
661 }
662 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
663 sizeof(idx))) {
664 DPRINTF(sc, "OTP: failed to read\n");
665 goto done;
666 }
667 DPRINTF(sc, "success\n");
668 } else
669 DPRINTF(sc, "nothing to do\n");
670 } else
671 DPRINTF(sc, "nothing to do\n");
672 done:
673 for (i = 0; i < __arraycount(idx); i++)
674 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
675 }
676
677 static int
678 mue_chip_init(struct mue_softc *sc)
679 {
680 uint32_t val;
681
682 if ((sc->mue_flags & LAN7500) &&
683 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
684 MUE_PRINTF(sc, "not ready\n");
685 return ETIMEDOUT;
686 }
687
688 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
689 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
690 MUE_PRINTF(sc, "timed out\n");
691 return ETIMEDOUT;
692 }
693
694 /* Respond to the IN token with a NAK. */
695 if (sc->mue_flags & LAN7500)
696 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
697 else
698 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
699
700 if (sc->mue_flags & LAN7500) {
701 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
702 val = MUE_7500_HS_RX_BUFSIZE /
703 MUE_HS_USB_PKT_SIZE;
704 else
705 val = MUE_7500_FS_RX_BUFSIZE /
706 MUE_FS_USB_PKT_SIZE;
707 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
708 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
709 MUE_7500_DEFAULT_BULKIN_DELAY);
710
711 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
712
713 /* Set FIFO sizes. */
714 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
715 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
716 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
717 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
718 } else {
719 /* Init LTM. */
720 mue_init_ltm(sc);
721
722 val = MUE_7800_RX_BUFSIZE;
723 switch (sc->mue_udev->ud_speed) {
724 case USB_SPEED_SUPER:
725 val /= MUE_SS_USB_PKT_SIZE;
726 break;
727 case USB_SPEED_HIGH:
728 val /= MUE_HS_USB_PKT_SIZE;
729 break;
730 default:
731 val /= MUE_FS_USB_PKT_SIZE;
732 break;
733 }
734 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
735 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
736 MUE_7800_DEFAULT_BULKIN_DELAY);
737
738 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
739 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
740
741 /*
742 * Set FCL's RX and TX FIFO sizes: according to data sheet this
743 * is already the default value. But we initialize it to the
744 * same value anyways, as that's what the Linux driver does.
745 */
746 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
747 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
748 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
749 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
750 }
751
752 /* Enabling interrupts. */
753 mue_csr_write(sc, MUE_INT_STATUS, ~0);
754
755 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
756 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
757 mue_csr_write(sc, MUE_FLOW, 0);
758
759 /* Reset PHY. */
760 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
761 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
762 MUE_PRINTF(sc, "PHY not ready\n");
763 return ETIMEDOUT;
764 }
765
766 /* LAN7801 only has RGMII mode. */
767 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
768 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
769
770 if ((sc->mue_flags & LAN7500) ||
771 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
772 !mue_eeprom_present(sc))) {
773 /* Allow MAC to detect speed and duplex from PHY. */
774 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
775 MUE_MAC_CR_AUTO_DUPLEX);
776 }
777
778 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
779 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
780 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
781
782 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
783 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
784
785 /* Set default GPIO/LED settings only if no EEPROM is detected. */
786 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
787 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
788 MUE_SETBIT(sc, MUE_LED_CFG,
789 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
790 }
791
792 /* XXX We assume two LEDs at least when EEPROM is missing. */
793 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
794 !mue_eeprom_present(sc))
795 MUE_SETBIT(sc, MUE_HW_CFG,
796 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
797
798 return 0;
799 }
800
801 static void
802 mue_set_macaddr(struct mue_softc *sc)
803 {
804 struct ifnet *ifp = GET_IFP(sc);
805 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
806 uint32_t lo, hi;
807
808 lo = MUE_ENADDR_LO(enaddr);
809 hi = MUE_ENADDR_HI(enaddr);
810
811 mue_csr_write(sc, MUE_RX_ADDRL, lo);
812 mue_csr_write(sc, MUE_RX_ADDRH, hi);
813 }
814
815 static int
816 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
817 {
818 prop_data_t eaprop;
819 uint32_t low, high;
820
821 if (!(sc->mue_flags & LAN7500)) {
822 low = mue_csr_read(sc, MUE_RX_ADDRL);
823 high = mue_csr_read(sc, MUE_RX_ADDRH);
824 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
825 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
826 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
827 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
828 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
829 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
830 if (ETHER_IS_VALID(sc->mue_enaddr))
831 return 0;
832 else
833 DPRINTF(sc, "registers: %s\n",
834 ether_sprintf(sc->mue_enaddr));
835 }
836
837 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
838 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
839 if (ETHER_IS_VALID(sc->mue_enaddr))
840 return 0;
841 else
842 DPRINTF(sc, "EEPROM: %s\n",
843 ether_sprintf(sc->mue_enaddr));
844 }
845
846 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
847 ETHER_ADDR_LEN) == 0) {
848 if (ETHER_IS_VALID(sc->mue_enaddr))
849 return 0;
850 else
851 DPRINTF(sc, "OTP: %s\n",
852 ether_sprintf(sc->mue_enaddr));
853 }
854
855 /*
856 * Other MD methods. This should be tried only if other methods fail.
857 * Otherwise, MAC address for internal device can be assinged to
858 * external devices on Raspberry Pi, for example.
859 */
860 eaprop = prop_dictionary_get(dict, "mac-address");
861 if (eaprop != NULL) {
862 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
863 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
864 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
865 ETHER_ADDR_LEN);
866 if (ETHER_IS_VALID(sc->mue_enaddr))
867 return 0;
868 else
869 DPRINTF(sc, "prop_dictionary_get: %s\n",
870 ether_sprintf(sc->mue_enaddr));
871 }
872
873 return 1;
874 }
875
876
877 /*
878 * Probe for a Microchip chip. */
879 static int
880 mue_match(device_t parent, cfdata_t match, void *aux)
881 {
882 struct usb_attach_arg *uaa = aux;
883
884 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
885 }
886
887 static void
888 mue_attach(device_t parent, device_t self, void *aux)
889 {
890 struct mue_softc *sc = device_private(self);
891 prop_dictionary_t dict = device_properties(self);
892 struct usb_attach_arg *uaa = aux;
893 struct usbd_device *dev = uaa->uaa_device;
894 usb_interface_descriptor_t *id;
895 usb_endpoint_descriptor_t *ed;
896 char *devinfop;
897 struct mii_data *mii;
898 struct ifnet *ifp;
899 usbd_status err;
900 const char *descr;
901 uint8_t i;
902 int s;
903
904 aprint_naive("\n");
905 aprint_normal("\n");
906
907 sc->mue_dev = self;
908 sc->mue_udev = dev;
909
910 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
911 aprint_normal_dev(self, "%s\n", devinfop);
912 usbd_devinfo_free(devinfop);
913
914 #define MUE_CONFIG_NO 1
915 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
916 if (err) {
917 aprint_error_dev(self, "failed to set configuration: %s\n",
918 usbd_errstr(err));
919 return;
920 }
921
922 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
923 usb_init_task(&sc->mue_stop_task, (void (*)(void *))mue_stop, sc, 0);
924
925 #define MUE_IFACE_IDX 0
926 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
927 if (err) {
928 aprint_error_dev(self, "failed to get interface handle: %s\n",
929 usbd_errstr(err));
930 return;
931 }
932
933 sc->mue_product = uaa->uaa_product;
934 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
935
936 sc->mue_id_rev = mue_csr_read(sc, MUE_ID_REV);
937
938 /* Decide on what our bufsize will be. */
939 if (sc->mue_flags & LAN7500) {
940 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
941 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
942 sc->mue_rx_list_cnt = 1;
943 sc->mue_tx_list_cnt = 1;
944 } else {
945 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
946 sc->mue_rx_list_cnt = MUE_RX_LIST_CNT;
947 sc->mue_tx_list_cnt = MUE_TX_LIST_CNT;
948 }
949 sc->mue_txbufsz = MUE_TX_BUFSIZE;
950
951 /* Find endpoints. */
952 id = usbd_get_interface_descriptor(sc->mue_iface);
953 for (i = 0; i < id->bNumEndpoints; i++) {
954 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
955 if (ed == NULL) {
956 aprint_error_dev(self, "failed to get ep %hhd\n", i);
957 return;
958 }
959 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
960 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
961 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
962 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
963 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
964 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
965 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
966 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
967 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
968 }
969 }
970 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
971 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
972 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
973
974 s = splnet();
975
976 sc->mue_phyno = 1;
977
978 if (mue_chip_init(sc)) {
979 aprint_error_dev(self, "failed to initialize chip\n");
980 splx(s);
981 return;
982 }
983
984 /* A Microchip chip was detected. Inform the world. */
985 descr = (sc->mue_flags & LAN7500) ? "LAN7500" : "LAN7800";
986 aprint_normal_dev(self, "%s id 0x%x rev 0x%x\n", descr,
987 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_ID),
988 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_REV));
989
990 if (mue_get_macaddr(sc, dict)) {
991 aprint_error_dev(self, "failed to read MAC address\n");
992 splx(s);
993 return;
994 }
995
996 aprint_normal_dev(self, "Ethernet address %s\n",
997 ether_sprintf(sc->mue_enaddr));
998
999 /* Initialize interface info.*/
1000 ifp = GET_IFP(sc);
1001 ifp->if_softc = sc;
1002 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
1003 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1004 ifp->if_init = mue_init;
1005 ifp->if_ioctl = mue_ioctl;
1006 ifp->if_start = mue_start;
1007 ifp->if_stop = mue_stop;
1008 ifp->if_watchdog = mue_watchdog;
1009
1010 IFQ_SET_READY(&ifp->if_snd);
1011
1012 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
1013 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1014 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1015 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1016 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
1017 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
1018
1019 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1020 #if 0 /* XXX not yet */
1021 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
1022 #endif
1023
1024 /* Initialize MII/media info. */
1025 mii = GET_MII(sc);
1026 mii->mii_ifp = ifp;
1027 mii->mii_readreg = mue_miibus_readreg;
1028 mii->mii_writereg = mue_miibus_writereg;
1029 mii->mii_statchg = mue_miibus_statchg;
1030 mii->mii_flags = MIIF_AUTOTSLEEP;
1031
1032 sc->mue_ec.ec_mii = mii;
1033 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1034 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1035
1036 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1037 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1038 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1039 } else
1040 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1041
1042 /* Attach the interface. */
1043 if_attach(ifp);
1044 ether_ifattach(ifp, sc->mue_enaddr);
1045
1046 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1047 RND_TYPE_NET, RND_FLAG_DEFAULT);
1048
1049 callout_init(&sc->mue_stat_ch, 0);
1050
1051 splx(s);
1052
1053 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
1054
1055 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1056 }
1057
1058 static int
1059 mue_detach(device_t self, int flags)
1060 {
1061 struct mue_softc *sc = device_private(self);
1062 struct ifnet *ifp = GET_IFP(sc);
1063 size_t i;
1064 int s;
1065
1066 sc->mue_dying = true;
1067
1068 callout_halt(&sc->mue_stat_ch, NULL);
1069
1070 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1071 if (sc->mue_ep[i] != NULL)
1072 usbd_abort_pipe(sc->mue_ep[i]);
1073
1074 /*
1075 * Remove any pending tasks. They cannot be executing because they run
1076 * in the same thread as detach.
1077 */
1078 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1079 NULL);
1080 usb_rem_task_wait(sc->mue_udev, &sc->mue_stop_task, USB_TASKQ_DRIVER,
1081 NULL);
1082
1083 s = splusb();
1084
1085 if (ifp->if_flags & IFF_RUNNING)
1086 mue_stop(ifp, 1);
1087
1088 callout_destroy(&sc->mue_stat_ch);
1089 rnd_detach_source(&sc->mue_rnd_source);
1090 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1091 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1092 if (ifp->if_softc != NULL) {
1093 ether_ifdetach(ifp);
1094 if_detach(ifp);
1095 }
1096
1097 if (--sc->mue_refcnt >= 0) {
1098 /* Wait for processes to go away. */
1099 usb_detach_waitold(sc->mue_dev);
1100 }
1101 splx(s);
1102
1103 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1104
1105 mutex_destroy(&sc->mue_mii_lock);
1106
1107 return 0;
1108 }
1109
1110 static int
1111 mue_activate(device_t self, enum devact act)
1112 {
1113 struct mue_softc *sc = device_private(self);
1114 struct ifnet *ifp = GET_IFP(sc);
1115
1116 switch (act) {
1117 case DVACT_DEACTIVATE:
1118 if_deactivate(ifp);
1119 sc->mue_dying = true;
1120 return 0;
1121 default:
1122 return EOPNOTSUPP;
1123 }
1124 return 0;
1125 }
1126
1127 static int
1128 mue_rx_list_init(struct mue_softc *sc)
1129 {
1130 struct mue_cdata *cd;
1131 struct mue_chain *c;
1132 size_t i;
1133 int err;
1134
1135 cd = &sc->mue_cdata;
1136 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1137 c = &cd->mue_rx_chain[i];
1138 c->mue_sc = sc;
1139 c->mue_idx = i;
1140 if (c->mue_xfer == NULL) {
1141 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1142 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1143 if (err)
1144 return err;
1145 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1146 }
1147 }
1148
1149 return 0;
1150 }
1151
1152 static int
1153 mue_tx_list_init(struct mue_softc *sc)
1154 {
1155 struct mue_cdata *cd;
1156 struct mue_chain *c;
1157 size_t i;
1158 int err;
1159
1160 cd = &sc->mue_cdata;
1161 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1162 c = &cd->mue_tx_chain[i];
1163 c->mue_sc = sc;
1164 c->mue_idx = i;
1165 if (c->mue_xfer == NULL) {
1166 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1167 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1168 &c->mue_xfer);
1169 if (err)
1170 return err;
1171 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1172 }
1173 }
1174
1175 cd->mue_tx_prod = 0;
1176 cd->mue_tx_cnt = 0;
1177
1178 return 0;
1179 }
1180
1181 static int
1182 mue_open_pipes(struct mue_softc *sc)
1183 {
1184 usbd_status err;
1185
1186 /* Open RX and TX pipes. */
1187 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1188 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1189 if (err) {
1190 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1191 return EIO;
1192 }
1193 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1194 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1195 if (err) {
1196 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1197 return EIO;
1198 }
1199 return 0;
1200 }
1201
1202 static void
1203 mue_startup_rx_pipes(struct mue_softc *sc)
1204 {
1205 struct mue_chain *c;
1206 size_t i;
1207
1208 /* Start up the receive pipe. */
1209 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1210 c = &sc->mue_cdata.mue_rx_chain[i];
1211 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1212 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1213 usbd_transfer(c->mue_xfer);
1214 }
1215 }
1216
1217 static int
1218 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1219 {
1220 struct ifnet *ifp = GET_IFP(sc);
1221 struct mue_chain *c;
1222 usbd_status err;
1223 struct mue_txbuf_hdr hdr;
1224 uint32_t tx_cmd_a, tx_cmd_b;
1225 int csum, len;
1226 bool tso, ipe, tpe;
1227
1228 csum = m->m_pkthdr.csum_flags;
1229 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
1230 ipe = csum & M_CSUM_IPv4;
1231 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
1232 M_CSUM_TCPv6 | M_CSUM_UDPv6);
1233
1234 len = m->m_pkthdr.len;
1235 if (__predict_false((!tso &&
1236 (unsigned)len > MUE_FRAME_LEN(ifp->if_mtu)) ||
1237 ( tso && len > MUE_TSO_FRAME_LEN))) {
1238 MUE_PRINTF(sc, "packet length %d\n too long", len);
1239 return EINVAL;
1240 }
1241
1242 c = &sc->mue_cdata.mue_tx_chain[idx];
1243
1244 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
1245 tx_cmd_a = len | MUE_TX_CMD_A_FCS;
1246
1247 if (tso) {
1248 tx_cmd_a |= MUE_TX_CMD_A_LSO;
1249 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1250 tx_cmd_b = m->m_pkthdr.segsz;
1251 else
1252 tx_cmd_b = MUE_TX_MSS_MIN;
1253 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
1254 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
1255 mue_tx_offload(sc, m);
1256 } else {
1257 if (ipe)
1258 tx_cmd_a |= MUE_TX_CMD_A_IPE;
1259 if (tpe)
1260 tx_cmd_a |= MUE_TX_CMD_A_TPE;
1261 tx_cmd_b = 0;
1262 }
1263
1264 hdr.tx_cmd_a = htole32(tx_cmd_a);
1265 hdr.tx_cmd_b = htole32(tx_cmd_b);
1266
1267 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1268 m_copydata(m, 0, len, c->mue_buf + sizeof(hdr));
1269
1270 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr),
1271 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1272
1273 /* Transmit */
1274 err = usbd_transfer(c->mue_xfer);
1275 if (__predict_false(err != USBD_IN_PROGRESS)) {
1276 MUE_PRINTF(sc, "%s\n", usbd_errstr(err));
1277 mue_stop(ifp, 0);
1278 return EIO;
1279 }
1280
1281 return 0;
1282 }
1283
1284 static void
1285 mue_tx_offload(struct mue_softc *sc, struct mbuf *m)
1286 {
1287 struct ether_header *eh;
1288 struct ip *ip;
1289 struct ip6_hdr *ip6;
1290 int off;
1291
1292 eh = mtod(m, struct ether_header *);
1293 switch (htons(eh->ether_type)) {
1294 case ETHERTYPE_IP:
1295 case ETHERTYPE_IPV6:
1296 off = ETHER_HDR_LEN;
1297 break;
1298 case ETHERTYPE_VLAN:
1299 /* XXX not yet supported */
1300 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1301 break;
1302 default:
1303 /* XXX */
1304 panic("%s: unsupported ethertype\n", __func__);
1305 /* NOTREACHED */
1306 }
1307
1308 /* Packet length should be cleared. */
1309 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1310 ip = (void *)(mtod(m, char *) + off);
1311 ip->ip_len = 0;
1312 } else {
1313 ip6 = (void *)(mtod(m, char *) + off);
1314 ip6->ip6_plen = 0;
1315 }
1316 }
1317
1318 static void
1319 mue_setmulti(struct mue_softc *sc)
1320 {
1321 struct ifnet *ifp = GET_IFP(sc);
1322 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1323 struct ether_multi *enm;
1324 struct ether_multistep step;
1325 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1326 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1327 uint32_t reg, rxfilt, h, hireg, loreg;
1328 size_t i;
1329
1330 if (sc->mue_dying)
1331 return;
1332
1333 /* Clear perfect filter and hash tables. */
1334 memset(pfiltbl, 0, sizeof(pfiltbl));
1335 memset(hashtbl, 0, sizeof(hashtbl));
1336
1337 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1338 rxfilt = mue_csr_read(sc, reg);
1339 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1340 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1341
1342 /* Always accept broadcast frames. */
1343 rxfilt |= MUE_RFE_CTL_BROADCAST;
1344
1345 if (ifp->if_flags & IFF_PROMISC) {
1346 rxfilt |= MUE_RFE_CTL_UNICAST;
1347 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1348 ifp->if_flags |= IFF_ALLMULTI;
1349 if (ifp->if_flags & IFF_PROMISC)
1350 DPRINTF(sc, "promisc\n");
1351 else
1352 DPRINTF(sc, "allmulti\n");
1353 } else {
1354 /* Now program new ones. */
1355 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1356 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1357 i = 1;
1358 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1359 while (enm != NULL) {
1360 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1361 ETHER_ADDR_LEN)) {
1362 memset(pfiltbl, 0, sizeof(pfiltbl));
1363 memset(hashtbl, 0, sizeof(hashtbl));
1364 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1365 goto allmulti;
1366 }
1367 if (i < MUE_NUM_ADDR_FILTX) {
1368 /* Use perfect address table if possible. */
1369 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1370 MUE_ADDR_FILTX_VALID;
1371 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1372 } else {
1373 /* Otherwise, use hash table. */
1374 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1375 h = (ether_crc32_be(enm->enm_addrlo,
1376 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1377 hashtbl[h / 32] |= 1 << (h % 32);
1378 }
1379 i++;
1380 ETHER_NEXT_MULTI(step, enm);
1381 }
1382 rxfilt |= MUE_RFE_CTL_PERFECT;
1383 ifp->if_flags &= ~IFF_ALLMULTI;
1384 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH)
1385 DPRINTF(sc, "perfect filter and hash tables\n");
1386 else
1387 DPRINTF(sc, "perfect filter\n");
1388 }
1389
1390 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1391 hireg = (sc->mue_flags & LAN7500) ?
1392 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1393 loreg = hireg + 4;
1394 mue_csr_write(sc, hireg, 0);
1395 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1396 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1397 }
1398
1399 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1400 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1401
1402 mue_csr_write(sc, reg, rxfilt);
1403 }
1404
1405 static void
1406 mue_sethwcsum(struct mue_softc *sc)
1407 {
1408 struct ifnet *ifp = GET_IFP(sc);
1409 uint32_t reg, val;
1410
1411 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1412 val = mue_csr_read(sc, reg);
1413
1414 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) {
1415 DPRINTF(sc, "RX IPv4 hwcsum enabled\n");
1416 val |= MUE_RFE_CTL_IP_COE;
1417 } else {
1418 DPRINTF(sc, "RX IPv4 hwcsum disabled\n");
1419 val &= ~MUE_RFE_CTL_IP_COE;
1420 }
1421
1422 if (ifp->if_capenable &
1423 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
1424 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) {
1425 DPRINTF(sc, "RX L4 hwcsum enabled\n");
1426 val |= MUE_RFE_CTL_TCPUDP_COE;
1427 } else {
1428 DPRINTF(sc, "RX L4 hwcsum disabled\n");
1429 val &= ~MUE_RFE_CTL_TCPUDP_COE;
1430 }
1431
1432 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1433
1434 mue_csr_write(sc, reg, val);
1435 }
1436
1437 static void
1438 mue_setmtu(struct mue_softc *sc)
1439 {
1440 struct ifnet *ifp = GET_IFP(sc);
1441 uint32_t val;
1442
1443 /* Set the maximum frame size. */
1444 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1445 val = mue_csr_read(sc, MUE_MAC_RX);
1446 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1447 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1448 mue_csr_write(sc, MUE_MAC_RX, val);
1449 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1450 }
1451
1452 static void
1453 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1454 {
1455 struct mue_chain *c = (struct mue_chain *)priv;
1456 struct mue_softc *sc = c->mue_sc;
1457 struct ifnet *ifp = GET_IFP(sc);
1458 struct mbuf *m;
1459 struct mue_rxbuf_hdr *hdrp;
1460 uint32_t rx_cmd_a, totlen;
1461 uint16_t pktlen;
1462 int s;
1463 int csum;
1464 char *buf = c->mue_buf;
1465 bool v6;
1466
1467 if (__predict_false(sc->mue_dying)) {
1468 DPRINTF(sc, "dying\n");
1469 return;
1470 }
1471
1472 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1473 DPRINTF(sc, "%s\n", usbd_errstr(status));
1474 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1475 return;
1476 if (usbd_ratecheck(&sc->mue_rx_notice))
1477 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1478 if (status == USBD_STALLED)
1479 usbd_clear_endpoint_stall_async(
1480 sc->mue_ep[MUE_ENDPT_RX]);
1481 goto done;
1482 }
1483
1484 usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL);
1485
1486 KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u",
1487 totlen, sc->mue_rxbufsz);
1488
1489 do {
1490 if (__predict_false(totlen < sizeof(*hdrp))) {
1491 MUE_PRINTF(sc, "packet length %u too short\n", totlen);
1492 ifp->if_ierrors++;
1493 goto done;
1494 }
1495
1496 hdrp = (struct mue_rxbuf_hdr *)buf;
1497 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1498
1499 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1500 /*
1501 * We cannot use MUE_RX_CMD_A_RED bit here;
1502 * it is turned on in the cases of L3/L4
1503 * checksum errors which we handle below.
1504 */
1505 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1506 ifp->if_ierrors++;
1507 goto done;
1508 }
1509
1510 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1511 if (sc->mue_flags & LAN7500)
1512 pktlen -= 2;
1513
1514 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1515 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1516 pktlen + sizeof(*hdrp) > totlen)) {
1517 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1518 ifp->if_ierrors++;
1519 goto done;
1520 }
1521
1522 m = mue_newbuf();
1523 if (__predict_false(m == NULL)) {
1524 MUE_PRINTF(sc, "failed to allocate mbuf\n");
1525 ifp->if_ierrors++;
1526 goto done;
1527 }
1528
1529 m_set_rcvif(m, ifp);
1530 m->m_pkthdr.len = m->m_len = pktlen;
1531 m->m_flags |= M_HASFCS;
1532
1533 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1534 csum = 0;
1535 } else {
1536 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1537 switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1538 case MUE_RX_CMD_A_PID_TCP:
1539 csum = v6 ?
1540 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1541 break;
1542 case MUE_RX_CMD_A_PID_UDP:
1543 csum = v6 ?
1544 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1545 break;
1546 case MUE_RX_CMD_A_PID_IP:
1547 csum = v6 ? 0 : M_CSUM_IPv4;
1548 break;
1549 default:
1550 csum = 0;
1551 break;
1552 }
1553 csum &= ifp->if_csum_flags_rx;
1554 if (__predict_false((csum & M_CSUM_IPv4) &&
1555 (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1556 csum |= M_CSUM_IPv4_BAD;
1557 if (__predict_false((csum & ~M_CSUM_IPv4) &&
1558 (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1559 csum |= M_CSUM_TCP_UDP_BAD;
1560 }
1561 m->m_pkthdr.csum_flags = csum;
1562 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1563
1564 /* Attention: sizeof(hdr) = 10 */
1565 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1566 if (pktlen > totlen)
1567 pktlen = totlen;
1568 totlen -= pktlen;
1569 buf += pktlen;
1570
1571 s = splnet();
1572 if_percpuq_enqueue(ifp->if_percpuq, m);
1573 splx(s);
1574 } while (totlen > 0);
1575
1576 done:
1577 /* Setup new transfer. */
1578 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1579 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1580 usbd_transfer(xfer);
1581 }
1582
1583 static void
1584 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1585 {
1586 struct mue_chain *c = priv;
1587 struct mue_softc *sc = c->mue_sc;
1588 struct mue_cdata *cd = &sc->mue_cdata;
1589 struct ifnet *ifp = GET_IFP(sc);
1590 int s;
1591
1592 if (__predict_false(sc->mue_dying))
1593 return;
1594
1595 s = splnet();
1596 KASSERT(cd->mue_tx_cnt > 0);
1597 cd->mue_tx_cnt--;
1598 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1599 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1600 splx(s);
1601 return;
1602 }
1603 ifp->if_oerrors++;
1604 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1605 if (status == USBD_STALLED)
1606 usbd_clear_endpoint_stall_async(
1607 sc->mue_ep[MUE_ENDPT_TX]);
1608 splx(s);
1609 return;
1610 }
1611
1612 ifp->if_timer = 0;
1613 ifp->if_flags &= ~IFF_OACTIVE;
1614
1615 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1616 mue_start(ifp);
1617
1618 ifp->if_opackets++;
1619 splx(s);
1620 }
1621
1622 static int
1623 mue_init(struct ifnet *ifp)
1624 {
1625 struct mue_softc *sc = ifp->if_softc;
1626 int s;
1627
1628 if (sc->mue_dying) {
1629 DPRINTF(sc, "dying\n");
1630 return EIO;
1631 }
1632
1633 s = splnet();
1634
1635 /* Cancel pending I/O and free all TX/RX buffers. */
1636 if (ifp->if_flags & IFF_RUNNING)
1637 mue_stop(ifp, 1);
1638
1639 mue_reset(sc);
1640
1641 /* Set MAC address. */
1642 mue_set_macaddr(sc);
1643
1644 /* Load the multicast filter. */
1645 mue_setmulti(sc);
1646
1647 /* TCP/UDP checksum offload engines. */
1648 mue_sethwcsum(sc);
1649
1650 /* Set MTU. */
1651 mue_setmtu(sc);
1652
1653 if (mue_open_pipes(sc)) {
1654 splx(s);
1655 return EIO;
1656 }
1657
1658 /* Init RX ring. */
1659 if (mue_rx_list_init(sc)) {
1660 MUE_PRINTF(sc, "failed to init rx list\n");
1661 splx(s);
1662 return ENOBUFS;
1663 }
1664
1665 /* Init TX ring. */
1666 if (mue_tx_list_init(sc)) {
1667 MUE_PRINTF(sc, "failed to init tx list\n");
1668 splx(s);
1669 return ENOBUFS;
1670 }
1671
1672 mue_startup_rx_pipes(sc);
1673
1674 ifp->if_flags |= IFF_RUNNING;
1675 ifp->if_flags &= ~IFF_OACTIVE;
1676
1677 splx(s);
1678
1679 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1680
1681 return 0;
1682 }
1683
1684 static int
1685 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1686 {
1687 struct mue_softc *sc = ifp->if_softc;
1688 struct ifreq /*const*/ *ifr = data;
1689 int s, error = 0;
1690
1691 s = splnet();
1692
1693 switch (cmd) {
1694 case SIOCSIFFLAGS:
1695 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1696 break;
1697
1698 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1699 case IFF_RUNNING:
1700 mue_stop(ifp, 1);
1701 break;
1702 case IFF_UP:
1703 mue_init(ifp);
1704 break;
1705 case IFF_UP | IFF_RUNNING:
1706 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1707 mue_setmulti(sc);
1708 else
1709 mue_init(ifp);
1710 break;
1711 }
1712 sc->mue_if_flags = ifp->if_flags;
1713 break;
1714 case SIOCGIFMEDIA:
1715 case SIOCSIFMEDIA:
1716 error = ifmedia_ioctl(ifp, ifr, &sc->mue_mii.mii_media, cmd);
1717 break;
1718 default:
1719 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1720 break;
1721 error = 0;
1722 switch (cmd) {
1723 case SIOCADDMULTI:
1724 case SIOCDELMULTI:
1725 mue_setmulti(sc);
1726 break;
1727 case SIOCSIFCAP:
1728 mue_sethwcsum(sc);
1729 break;
1730 case SIOCSIFMTU:
1731 mue_setmtu(sc);
1732 break;
1733 default:
1734 break;
1735 }
1736 break;
1737 }
1738 splx(s);
1739
1740 return error;
1741 }
1742
1743 static void
1744 mue_watchdog(struct ifnet *ifp)
1745 {
1746 struct mue_softc *sc = ifp->if_softc;
1747 struct mue_chain *c;
1748 usbd_status stat;
1749 int s;
1750
1751 ifp->if_oerrors++;
1752 MUE_PRINTF(sc, "timed out\n");
1753
1754 s = splusb();
1755 c = &sc->mue_cdata.mue_tx_chain[0];
1756 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1757 mue_txeof(c->mue_xfer, c, stat);
1758
1759 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1760 mue_start(ifp);
1761 splx(s);
1762 }
1763
1764 static void
1765 mue_reset(struct mue_softc *sc)
1766 {
1767 if (sc->mue_dying)
1768 return;
1769
1770 /* Wait a little while for the chip to get its brains in order. */
1771 usbd_delay_ms(sc->mue_udev, 1);
1772
1773 // mue_chip_init(sc); /* XXX */
1774 }
1775
1776 static void
1777 mue_start(struct ifnet *ifp)
1778 {
1779 struct mue_softc *sc = ifp->if_softc;
1780 struct mbuf *m;
1781 struct mue_cdata *cd = &sc->mue_cdata;
1782 int idx;
1783
1784 if (__predict_false(!sc->mue_link)) {
1785 DPRINTF(sc, "no link\n");
1786 return;
1787 }
1788
1789 if (__predict_false((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING))
1790 != IFF_RUNNING)) {
1791 DPRINTF(sc, "not ready\n");
1792 return;
1793 }
1794
1795 idx = cd->mue_tx_prod;
1796 while ((unsigned)cd->mue_tx_cnt < sc->mue_tx_list_cnt) {
1797 IFQ_POLL(&ifp->if_snd, m);
1798 if (m == NULL)
1799 break;
1800
1801 if (__predict_false(mue_encap(sc, m, idx))) {
1802 ifp->if_oerrors++;
1803 break;
1804 }
1805 IFQ_DEQUEUE(&ifp->if_snd, m);
1806
1807 bpf_mtap(ifp, m, BPF_D_OUT);
1808 m_freem(m);
1809
1810 idx = (idx + 1) % sc->mue_tx_list_cnt;
1811 cd->mue_tx_cnt++;
1812
1813 }
1814 cd->mue_tx_prod = idx;
1815
1816 if ((unsigned)cd->mue_tx_cnt >= sc->mue_tx_list_cnt)
1817 ifp->if_flags |= IFF_OACTIVE;
1818
1819 /* Set a timeout in case the chip goes out to lunch. */
1820 ifp->if_timer = 5;
1821 }
1822
1823 static void
1824 mue_stop(struct ifnet *ifp, int disable __unused)
1825 {
1826 struct mue_softc *sc = ifp->if_softc;
1827 usbd_status err;
1828 size_t i;
1829
1830 mue_reset(sc);
1831
1832 ifp->if_timer = 0;
1833 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1834
1835 callout_stop(&sc->mue_stat_ch);
1836
1837 /* Stop transfers. */
1838 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1839 if (sc->mue_ep[i] != NULL) {
1840 err = usbd_abort_pipe(sc->mue_ep[i]);
1841 if (err)
1842 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1843 i, usbd_errstr(err));
1844 }
1845
1846 /* Free RX resources. */
1847 for (i = 0; i < sc->mue_rx_list_cnt; i++)
1848 if (sc->mue_cdata.mue_rx_chain[i].mue_xfer != NULL) {
1849 usbd_destroy_xfer(
1850 sc->mue_cdata.mue_rx_chain[i].mue_xfer);
1851 sc->mue_cdata.mue_rx_chain[i].mue_xfer = NULL;
1852 }
1853
1854 /* Free TX resources. */
1855 for (i = 0; i < sc->mue_tx_list_cnt; i++)
1856 if (sc->mue_cdata.mue_tx_chain[i].mue_xfer != NULL) {
1857 usbd_destroy_xfer(
1858 sc->mue_cdata.mue_tx_chain[i].mue_xfer);
1859 sc->mue_cdata.mue_tx_chain[i].mue_xfer = NULL;
1860 }
1861
1862 /* Close pipes */
1863 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1864 if (sc->mue_ep[i] != NULL) {
1865 err = usbd_close_pipe(sc->mue_ep[i]);
1866 if (err)
1867 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1868 i, usbd_errstr(err));
1869 sc->mue_ep[i] = NULL;
1870 }
1871
1872 sc->mue_link = 0; /* XXX */
1873
1874 DPRINTF(sc, "done\n");
1875 }
1876
1877 static void
1878 mue_tick(void *xsc)
1879 {
1880 struct mue_softc *sc = xsc;
1881
1882 if (sc == NULL)
1883 return;
1884
1885 if (sc->mue_dying)
1886 return;
1887
1888 /* Perform periodic stuff in process context. */
1889 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1890 }
1891
1892 static void
1893 mue_tick_task(void *xsc)
1894 {
1895 struct mue_softc *sc = xsc;
1896 struct ifnet *ifp = GET_IFP(sc);
1897 struct mii_data *mii = GET_MII(sc);
1898 int s;
1899
1900 if (sc == NULL)
1901 return;
1902
1903 if (sc->mue_dying)
1904 return;
1905
1906 s = splnet();
1907 mii_tick(mii);
1908 if (sc->mue_link == 0)
1909 mue_miibus_statchg(ifp);
1910 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1911 splx(s);
1912 }
1913
1914 static struct mbuf *
1915 mue_newbuf(void)
1916 {
1917 struct mbuf *m;
1918
1919 MGETHDR(m, M_DONTWAIT, MT_DATA);
1920 if (__predict_false(m == NULL))
1921 return NULL;
1922
1923 MCLGET(m, M_DONTWAIT);
1924 if (__predict_false(!(m->m_flags & M_EXT))) {
1925 m_freem(m);
1926 return NULL;
1927 }
1928
1929 m_adj(m, ETHER_ALIGN);
1930
1931 return m;
1932 }
1933