if_mue.c revision 1.34 1 /* $NetBSD: if_mue.c,v 1.34 2019/02/06 08:23:08 rin Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.34 2019/02/06 08:23:08 rin Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/mutex.h>
36 #include <sys/kernel.h>
37 #include <sys/proc.h>
38 #include <sys/socket.h>
39
40 #include <sys/device.h>
41
42 #include <sys/rndsource.h>
43
44 #include <net/if.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_ether.h>
48
49 #include <net/bpf.h>
50
51 #include <netinet/if_inarp.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h> /* XXX for struct ip */
54 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
55
56 #include <dev/mii/mii.h>
57 #include <dev/mii/miivar.h>
58
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
61 #include <dev/usb/usbdi_util.h>
62 #include <dev/usb/usbdivar.h>
63 #include <dev/usb/usbdevs.h>
64
65 #include <dev/usb/if_muereg.h>
66 #include <dev/usb/if_muevar.h>
67
68 #define MUE_PRINTF(sc, fmt, args...) \
69 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
70
71 #ifdef USB_DEBUG
72 int muedebug = 0;
73 #define DPRINTF(sc, fmt, args...) \
74 do { \
75 if (muedebug) \
76 MUE_PRINTF(sc, fmt, ##args); \
77 } while (0 /* CONSTCOND */)
78 #else
79 #define DPRINTF(sc, fmt, args...) __nothing
80 #endif
81
82 /*
83 * Various supported device vendors/products.
84 */
85 struct mue_type {
86 struct usb_devno mue_dev;
87 uint16_t mue_flags;
88 #define LAN7500 0x0001 /* LAN7500 */
89 };
90
91 const struct mue_type mue_devs[] = {
92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
97 };
98
99 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
100 uaa->uaa_vendor, uaa->uaa_product))
101
102 #define MUE_ENADDR_LO(enaddr) \
103 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
104 #define MUE_ENADDR_HI(enaddr) \
105 ((enaddr[5] << 8) | enaddr[4])
106
107 static int mue_match(device_t, cfdata_t, void *);
108 static void mue_attach(device_t, device_t, void *);
109 static int mue_detach(device_t, int);
110 static int mue_activate(device_t, enum devact);
111
112 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
113 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
114 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
115 uint32_t, uint32_t);
116
117 static void mue_lock_mii(struct mue_softc *);
118 static void mue_unlock_mii(struct mue_softc *);
119
120 static int mue_miibus_readreg(device_t, int, int, uint16_t *);
121 static int mue_miibus_writereg(device_t, int, int, uint16_t);
122 static void mue_miibus_statchg(struct ifnet *);
123 static int mue_ifmedia_upd(struct ifnet *);
124 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125
126 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
127 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
128 static bool mue_eeprom_present(struct mue_softc *sc);
129
130 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
131 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
132
133 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
134 uint32_t, uint32_t *);
135
136 static void mue_init_ltm(struct mue_softc *);
137
138 static int mue_chip_init(struct mue_softc *);
139
140 static void mue_set_macaddr(struct mue_softc *);
141 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
142
143 static int mue_rx_list_init(struct mue_softc *);
144 static int mue_tx_list_init(struct mue_softc *);
145 static int mue_open_pipes(struct mue_softc *);
146 static void mue_startup_rx_pipes(struct mue_softc *);
147
148 static int mue_encap(struct mue_softc *, struct mbuf *, int);
149 static void mue_tx_offload(struct mue_softc *, struct mbuf *);
150
151 static void mue_setmulti(struct mue_softc *);
152 static void mue_sethwcsum(struct mue_softc *);
153 static void mue_setmtu(struct mue_softc *);
154
155 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
156 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
157
158 static int mue_init(struct ifnet *);
159 static int mue_ioctl(struct ifnet *, u_long, void *);
160 static void mue_watchdog(struct ifnet *);
161 static void mue_reset(struct mue_softc *);
162 static void mue_start(struct ifnet *);
163 static void mue_stop(struct ifnet *, int);
164 static void mue_tick(void *);
165 static void mue_tick_task(void *);
166
167 static struct mbuf *mue_newbuf(void);
168
169 #define MUE_SETBIT(sc, reg, x) \
170 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
171
172 #define MUE_CLRBIT(sc, reg, x) \
173 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
174
175 #define MUE_WAIT_SET(sc, reg, set, fail) \
176 mue_wait_for_bits(sc, reg, set, ~0, fail)
177
178 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
179 mue_wait_for_bits(sc, reg, 0, clear, fail)
180
181 #define ETHER_IS_VALID(addr) \
182 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
183
184 #define ETHER_IS_ZERO(addr) \
185 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
186
187 #define ETHER_ALIGN 2
188
189 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
190 mue_detach, mue_activate);
191
192 static uint32_t
193 mue_csr_read(struct mue_softc *sc, uint32_t reg)
194 {
195 usb_device_request_t req;
196 usbd_status err;
197 uDWord val;
198
199 if (sc->mue_dying)
200 return 0;
201
202 USETDW(val, 0);
203 req.bmRequestType = UT_READ_VENDOR_DEVICE;
204 req.bRequest = MUE_UR_READREG;
205 USETW(req.wValue, 0);
206 USETW(req.wIndex, reg);
207 USETW(req.wLength, 4);
208
209 err = usbd_do_request(sc->mue_udev, &req, &val);
210 if (err) {
211 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
212 return 0;
213 }
214
215 return UGETDW(val);
216 }
217
218 static int
219 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
220 {
221 usb_device_request_t req;
222 usbd_status err;
223 uDWord val;
224
225 if (sc->mue_dying)
226 return 0;
227
228 USETDW(val, aval);
229 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
230 req.bRequest = MUE_UR_WRITEREG;
231 USETW(req.wValue, 0);
232 USETW(req.wIndex, reg);
233 USETW(req.wLength, 4);
234
235 err = usbd_do_request(sc->mue_udev, &req, &val);
236 if (err) {
237 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
238 return -1;
239 }
240
241 return 0;
242 }
243
244 static int
245 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
246 uint32_t set, uint32_t clear, uint32_t fail)
247 {
248 uint32_t val;
249 int ntries;
250
251 for (ntries = 0; ntries < 1000; ntries++) {
252 val = mue_csr_read(sc, reg);
253 if ((val & set) || !(val & clear))
254 return 0;
255 if (val & fail)
256 return 1;
257 usbd_delay_ms(sc->mue_udev, 1);
258 }
259
260 return 1;
261 }
262
263 /*
264 * Get exclusive access to the MII registers.
265 */
266 static void
267 mue_lock_mii(struct mue_softc *sc)
268 {
269 sc->mue_refcnt++;
270 mutex_enter(&sc->mue_mii_lock);
271 }
272
273 static void
274 mue_unlock_mii(struct mue_softc *sc)
275 {
276 mutex_exit(&sc->mue_mii_lock);
277 if (--sc->mue_refcnt < 0)
278 usb_detach_wakeupold(sc->mue_dev);
279 }
280
281 static int
282 mue_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
283 {
284 struct mue_softc *sc = device_private(dev);
285 uint32_t data;
286 int rv = 0;
287
288 if (sc->mue_dying) {
289 DPRINTF(sc, "dying\n");
290 return -1;
291 }
292
293 if (sc->mue_phyno != phy)
294 return -1;
295
296 mue_lock_mii(sc);
297 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
298 mue_unlock_mii(sc);
299 MUE_PRINTF(sc, "not ready\n");
300 return -1;
301 }
302
303 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
304 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
305 MUE_MII_ACCESS_PHYADDR(phy));
306
307 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
308 MUE_PRINTF(sc, "timed out\n");
309 rv = ETIMEDOUT;
310 goto out;
311 }
312
313 data = mue_csr_read(sc, MUE_MII_DATA);
314 *val = data & 0xffff;
315
316 out:
317 mue_unlock_mii(sc);
318 return rv;
319 }
320
321 static int
322 mue_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
323 {
324 struct mue_softc *sc = device_private(dev);
325 int rv = 0;
326
327 if (sc->mue_dying) {
328 DPRINTF(sc, "dying\n");
329 return -1;
330 }
331
332 if (sc->mue_phyno != phy) {
333 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
334 sc->mue_phyno, phy);
335 return -1;
336 }
337
338 mue_lock_mii(sc);
339 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
340 MUE_PRINTF(sc, "not ready\n");
341 rv = EBUSY;
342 goto out;
343 }
344
345 mue_csr_write(sc, MUE_MII_DATA, val);
346 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
347 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
348 MUE_MII_ACCESS_PHYADDR(phy));
349
350 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
351 MUE_PRINTF(sc, "timed out\n");
352 rv = ETIMEDOUT;
353 }
354 out:
355 mue_unlock_mii(sc);
356 return rv;
357 }
358
359 static void
360 mue_miibus_statchg(struct ifnet *ifp)
361 {
362 struct mue_softc *sc;
363 struct mii_data *mii;
364 uint32_t flow, threshold;
365
366 if (ifp == NULL) {
367 DPRINTF(sc, "ifp not ready\n");
368 return;
369 }
370
371 if ((ifp->if_flags & IFF_RUNNING) == 0) {
372 DPRINTF(sc, "not running\n");
373 return;
374 }
375
376 sc = ifp->if_softc;
377 mii = GET_MII(sc);
378
379 if (mii == NULL) {
380 DPRINTF(sc, "mii not ready\n");
381 return;
382 }
383
384 sc->mue_link = 0;
385 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
386 (IFM_ACTIVE | IFM_AVALID)) {
387 switch (IFM_SUBTYPE(mii->mii_media_active)) {
388 case IFM_10_T:
389 case IFM_100_TX:
390 case IFM_1000_T:
391 sc->mue_link++;
392 break;
393 default:
394 break;
395 }
396 }
397
398 /* Lost link, do nothing. */
399 if (sc->mue_link == 0) {
400 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
401 return;
402 }
403
404 if (!(sc->mue_flags & LAN7500)) {
405 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
406 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
407 /* Disable U2 and enable U1. */
408 MUE_CLRBIT(sc, MUE_USB_CFG1,
409 MUE_USB_CFG1_DEV_U2_INIT_EN);
410 MUE_SETBIT(sc, MUE_USB_CFG1,
411 MUE_USB_CFG1_DEV_U1_INIT_EN);
412 } else {
413 /* Enable U1 and U2. */
414 MUE_SETBIT(sc, MUE_USB_CFG1,
415 MUE_USB_CFG1_DEV_U1_INIT_EN |
416 MUE_USB_CFG1_DEV_U2_INIT_EN);
417 }
418 }
419 }
420
421 flow = 0;
422 /* XXX Linux does not check IFM_FDX flag for 7800. */
423 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
424 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
425 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
426 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
427 flow |= MUE_FLOW_RX_FCEN;
428 }
429
430 /* XXX Magic numbers taken from Linux driver. */
431 if (sc->mue_flags & LAN7500)
432 threshold = 0x820;
433 else
434 switch (sc->mue_udev->ud_speed) {
435 case USB_SPEED_SUPER:
436 threshold = 0x817;
437 break;
438 case USB_SPEED_HIGH:
439 threshold = 0x211;
440 break;
441 default:
442 threshold = 0;
443 break;
444 }
445
446 /* Threshold value should be set before enabling flow. */
447 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
448 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
449 mue_csr_write(sc, MUE_FLOW, flow);
450
451 DPRINTF(sc, "done\n");
452 }
453
454 /*
455 * Set media options.
456 */
457 static int
458 mue_ifmedia_upd(struct ifnet *ifp)
459 {
460 struct mue_softc *sc = ifp->if_softc;
461 struct mii_data *mii = GET_MII(sc);
462
463 sc->mue_link = 0; /* XXX */
464
465 if (mii->mii_instance) {
466 struct mii_softc *miisc;
467 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
468 mii_phy_reset(miisc);
469 }
470 return mii_mediachg(mii);
471 }
472
473 /*
474 * Report current media status.
475 */
476 static void
477 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
478 {
479 struct mue_softc *sc = ifp->if_softc;
480 struct mii_data *mii = GET_MII(sc);
481
482 mii_pollstat(mii);
483 ifmr->ifm_active = mii->mii_media_active;
484 ifmr->ifm_status = mii->mii_media_status;
485 }
486
487 static uint8_t
488 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
489 {
490 uint32_t val;
491
492 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
493 MUE_PRINTF(sc, "not ready\n");
494 return ETIMEDOUT;
495 }
496
497 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
498 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
499 off);
500
501 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
502 MUE_E2P_CMD_TIMEOUT)) {
503 MUE_PRINTF(sc, "timed out\n");
504 return ETIMEDOUT;
505 }
506
507 val = mue_csr_read(sc, MUE_E2P_DATA);
508 *dest = val & 0xff;
509
510 return 0;
511 }
512
513 static int
514 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
515 {
516 uint32_t val = 0; /* XXX gcc */
517 uint8_t byte;
518 int i, err;
519
520 /*
521 * EEPROM pins are muxed with the LED function on LAN7800 device.
522 */
523 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
524 val = mue_csr_read(sc, MUE_HW_CFG);
525 mue_csr_write(sc, MUE_HW_CFG,
526 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
527 }
528
529 for (i = 0; i < cnt; i++) {
530 err = mue_eeprom_getbyte(sc, off + i, &byte);
531 if (err)
532 break;
533 *(dest + i) = byte;
534 }
535
536 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
537 mue_csr_write(sc, MUE_HW_CFG, val);
538
539 return err ? 1 : 0;
540 }
541
542 static bool
543 mue_eeprom_present(struct mue_softc *sc)
544 {
545 uint32_t val;
546 uint8_t sig;
547 int ret;
548
549 if (sc->mue_flags & LAN7500) {
550 val = mue_csr_read(sc, MUE_E2P_CMD);
551 return val & MUE_E2P_CMD_LOADED;
552 } else {
553 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
554 return (ret == 0) && (sig == MUE_E2P_IND);
555 }
556 }
557
558 static int
559 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
560 {
561 uint32_t val;
562 int i, err;
563
564 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
565
566 /* Checking if bit is set. */
567 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
568 /* Clear it, then wait for it to be cleared. */
569 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
570 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
571 0);
572 if (err) {
573 MUE_PRINTF(sc, "not ready\n");
574 return 1;
575 }
576 }
577
578 /* Start reading the bytes, one at a time. */
579 for (i = 0; i < cnt; i++) {
580 mue_csr_write(sc, MUE_OTP_ADDR1,
581 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
582 mue_csr_write(sc, MUE_OTP_ADDR2,
583 ((off + i) & MUE_OTP_ADDR2_MASK));
584 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
585 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
586
587 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
588 if (err) {
589 MUE_PRINTF(sc, "timed out\n");
590 return 1;
591 }
592 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
593 *(dest + i) = (uint8_t)(val & 0xff);
594 }
595
596 return 0;
597 }
598
599 static int
600 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
601 {
602 uint8_t sig;
603 int err;
604
605 if (sc->mue_flags & LAN7500)
606 return 1;
607
608 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
609 if (err)
610 return 1;
611 switch (sig) {
612 case MUE_OTP_IND_1:
613 break;
614 case MUE_OTP_IND_2:
615 off += 0x100;
616 break;
617 default:
618 DPRINTF(sc, "OTP not found\n");
619 return 1;
620 }
621 err = mue_read_otp_raw(sc, dest, off, cnt);
622 return err;
623 }
624
625 static void
626 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
627 uint32_t cnt, uint32_t *data)
628 {
629 uint32_t i;
630
631 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
632 MUE_PRINTF(sc, "not ready\n");
633 return;
634 }
635
636 mue_csr_write(sc, MUE_DP_SEL,
637 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
638
639 for (i = 0; i < cnt; i++) {
640 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
641 mue_csr_write(sc, MUE_DP_DATA, data[i]);
642 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
643 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
644 MUE_PRINTF(sc, "timed out\n");
645 return;
646 }
647 }
648 }
649
650 static void
651 mue_init_ltm(struct mue_softc *sc)
652 {
653 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
654 uint8_t temp[2];
655 size_t i;
656
657 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
658 if (mue_eeprom_present(sc) &&
659 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
660 if (temp[0] != sizeof(idx)) {
661 DPRINTF(sc, "EEPROM: unexpected size\n");
662 goto done;
663 }
664 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
665 sizeof(idx))) {
666 DPRINTF(sc, "EEPROM: failed to read\n");
667 goto done;
668 }
669 DPRINTF(sc, "success\n");
670 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
671 if (temp[0] != sizeof(idx)) {
672 DPRINTF(sc, "OTP: unexpected size\n");
673 goto done;
674 }
675 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
676 sizeof(idx))) {
677 DPRINTF(sc, "OTP: failed to read\n");
678 goto done;
679 }
680 DPRINTF(sc, "success\n");
681 } else
682 DPRINTF(sc, "nothing to do\n");
683 } else
684 DPRINTF(sc, "nothing to do\n");
685 done:
686 for (i = 0; i < __arraycount(idx); i++)
687 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
688 }
689
690 static int
691 mue_chip_init(struct mue_softc *sc)
692 {
693 uint32_t val;
694
695 if ((sc->mue_flags & LAN7500) &&
696 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
697 MUE_PRINTF(sc, "not ready\n");
698 return ETIMEDOUT;
699 }
700
701 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
702 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
703 MUE_PRINTF(sc, "timed out\n");
704 return ETIMEDOUT;
705 }
706
707 /* Respond to the IN token with a NAK. */
708 if (sc->mue_flags & LAN7500)
709 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
710 else
711 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
712
713 if (sc->mue_flags & LAN7500) {
714 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
715 val = MUE_7500_HS_RX_BUFSIZE /
716 MUE_HS_USB_PKT_SIZE;
717 else
718 val = MUE_7500_FS_RX_BUFSIZE /
719 MUE_FS_USB_PKT_SIZE;
720 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
721 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
722 MUE_7500_DEFAULT_BULKIN_DELAY);
723
724 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
725
726 /* Set FIFO sizes. */
727 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
728 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
729 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
730 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
731 } else {
732 /* Init LTM. */
733 mue_init_ltm(sc);
734
735 val = MUE_7800_RX_BUFSIZE;
736 switch (sc->mue_udev->ud_speed) {
737 case USB_SPEED_SUPER:
738 val /= MUE_SS_USB_PKT_SIZE;
739 break;
740 case USB_SPEED_HIGH:
741 val /= MUE_HS_USB_PKT_SIZE;
742 break;
743 default:
744 val /= MUE_FS_USB_PKT_SIZE;
745 break;
746 }
747 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
748 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
749 MUE_7800_DEFAULT_BULKIN_DELAY);
750
751 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
752 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
753
754 /*
755 * Set FCL's RX and TX FIFO sizes: according to data sheet this
756 * is already the default value. But we initialize it to the
757 * same value anyways, as that's what the Linux driver does.
758 */
759 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
760 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
761 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
762 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
763 }
764
765 /* Enabling interrupts. */
766 mue_csr_write(sc, MUE_INT_STATUS, ~0);
767
768 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
769 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
770 mue_csr_write(sc, MUE_FLOW, 0);
771
772 /* Reset PHY. */
773 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
774 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
775 MUE_PRINTF(sc, "PHY not ready\n");
776 return ETIMEDOUT;
777 }
778
779 /* LAN7801 only has RGMII mode. */
780 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
781 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
782
783 if ((sc->mue_flags & LAN7500) ||
784 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
785 !mue_eeprom_present(sc))) {
786 /* Allow MAC to detect speed and duplex from PHY. */
787 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
788 MUE_MAC_CR_AUTO_DUPLEX);
789 }
790
791 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
792 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
793 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
794
795 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
796 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
797
798 /* Set default GPIO/LED settings only if no EEPROM is detected. */
799 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
800 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
801 MUE_SETBIT(sc, MUE_LED_CFG,
802 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
803 }
804
805 /* XXX We assume two LEDs at least when EEPROM is missing. */
806 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
807 !mue_eeprom_present(sc))
808 MUE_SETBIT(sc, MUE_HW_CFG,
809 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
810
811 return 0;
812 }
813
814 static void
815 mue_set_macaddr(struct mue_softc *sc)
816 {
817 struct ifnet *ifp = GET_IFP(sc);
818 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
819 uint32_t lo, hi;
820
821 lo = MUE_ENADDR_LO(enaddr);
822 hi = MUE_ENADDR_HI(enaddr);
823
824 mue_csr_write(sc, MUE_RX_ADDRL, lo);
825 mue_csr_write(sc, MUE_RX_ADDRH, hi);
826 }
827
828 static int
829 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
830 {
831 prop_data_t eaprop;
832 uint32_t low, high;
833
834 if (!(sc->mue_flags & LAN7500)) {
835 low = mue_csr_read(sc, MUE_RX_ADDRL);
836 high = mue_csr_read(sc, MUE_RX_ADDRH);
837 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
838 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
839 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
840 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
841 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
842 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
843 if (ETHER_IS_VALID(sc->mue_enaddr))
844 return 0;
845 else
846 DPRINTF(sc, "registers: %s\n",
847 ether_sprintf(sc->mue_enaddr));
848 }
849
850 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
851 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
852 if (ETHER_IS_VALID(sc->mue_enaddr))
853 return 0;
854 else
855 DPRINTF(sc, "EEPROM: %s\n",
856 ether_sprintf(sc->mue_enaddr));
857 }
858
859 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
860 ETHER_ADDR_LEN) == 0) {
861 if (ETHER_IS_VALID(sc->mue_enaddr))
862 return 0;
863 else
864 DPRINTF(sc, "OTP: %s\n",
865 ether_sprintf(sc->mue_enaddr));
866 }
867
868 /*
869 * Other MD methods. This should be tried only if other methods fail.
870 * Otherwise, MAC address for internal device can be assinged to
871 * external devices on Raspberry Pi, for example.
872 */
873 eaprop = prop_dictionary_get(dict, "mac-address");
874 if (eaprop != NULL) {
875 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
876 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
877 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
878 ETHER_ADDR_LEN);
879 if (ETHER_IS_VALID(sc->mue_enaddr))
880 return 0;
881 else
882 DPRINTF(sc, "prop_dictionary_get: %s\n",
883 ether_sprintf(sc->mue_enaddr));
884 }
885
886 return 1;
887 }
888
889
890 /*
891 * Probe for a Microchip chip. */
892 static int
893 mue_match(device_t parent, cfdata_t match, void *aux)
894 {
895 struct usb_attach_arg *uaa = aux;
896
897 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
898 }
899
900 static void
901 mue_attach(device_t parent, device_t self, void *aux)
902 {
903 struct mue_softc *sc = device_private(self);
904 prop_dictionary_t dict = device_properties(self);
905 struct usb_attach_arg *uaa = aux;
906 struct usbd_device *dev = uaa->uaa_device;
907 usb_interface_descriptor_t *id;
908 usb_endpoint_descriptor_t *ed;
909 char *devinfop;
910 struct mii_data *mii;
911 struct ifnet *ifp;
912 usbd_status err;
913 const char *descr;
914 uint8_t i;
915 int s;
916
917 aprint_naive("\n");
918 aprint_normal("\n");
919
920 sc->mue_dev = self;
921 sc->mue_udev = dev;
922
923 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
924 aprint_normal_dev(self, "%s\n", devinfop);
925 usbd_devinfo_free(devinfop);
926
927 #define MUE_CONFIG_NO 1
928 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
929 if (err) {
930 aprint_error_dev(self, "failed to set configuration: %s\n",
931 usbd_errstr(err));
932 return;
933 }
934
935 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
936 usb_init_task(&sc->mue_stop_task, (void (*)(void *))mue_stop, sc, 0);
937
938 #define MUE_IFACE_IDX 0
939 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
940 if (err) {
941 aprint_error_dev(self, "failed to get interface handle: %s\n",
942 usbd_errstr(err));
943 return;
944 }
945
946 sc->mue_product = uaa->uaa_product;
947 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
948
949 sc->mue_id_rev = mue_csr_read(sc, MUE_ID_REV);
950
951 /* Decide on what our bufsize will be. */
952 if (sc->mue_flags & LAN7500) {
953 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
954 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
955 sc->mue_rx_list_cnt = 1;
956 sc->mue_tx_list_cnt = 1;
957 } else {
958 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
959 sc->mue_rx_list_cnt = MUE_RX_LIST_CNT;
960 sc->mue_tx_list_cnt = MUE_TX_LIST_CNT;
961 }
962 sc->mue_txbufsz = MUE_TX_BUFSIZE;
963
964 /* Find endpoints. */
965 id = usbd_get_interface_descriptor(sc->mue_iface);
966 for (i = 0; i < id->bNumEndpoints; i++) {
967 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
968 if (ed == NULL) {
969 aprint_error_dev(self, "failed to get ep %hhd\n", i);
970 return;
971 }
972 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
973 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
974 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
975 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
976 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
977 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
978 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
979 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
980 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
981 }
982 }
983 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
984 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
985 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
986
987 s = splnet();
988
989 sc->mue_phyno = 1;
990
991 if (mue_chip_init(sc)) {
992 aprint_error_dev(self, "failed to initialize chip\n");
993 splx(s);
994 return;
995 }
996
997 /* A Microchip chip was detected. Inform the world. */
998 descr = (sc->mue_flags & LAN7500) ? "LAN7500" : "LAN7800";
999 aprint_normal_dev(self, "%s id 0x%x rev 0x%x\n", descr,
1000 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_ID),
1001 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_REV));
1002
1003 if (mue_get_macaddr(sc, dict)) {
1004 aprint_error_dev(self, "failed to read MAC address\n");
1005 splx(s);
1006 return;
1007 }
1008
1009 aprint_normal_dev(self, "Ethernet address %s\n",
1010 ether_sprintf(sc->mue_enaddr));
1011
1012 /* Initialize interface info.*/
1013 ifp = GET_IFP(sc);
1014 ifp->if_softc = sc;
1015 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
1016 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1017 ifp->if_init = mue_init;
1018 ifp->if_ioctl = mue_ioctl;
1019 ifp->if_start = mue_start;
1020 ifp->if_stop = mue_stop;
1021 ifp->if_watchdog = mue_watchdog;
1022
1023 IFQ_SET_READY(&ifp->if_snd);
1024
1025 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
1026 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1027 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1028 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1029 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
1030 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
1031
1032 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1033 #if 0 /* XXX not yet */
1034 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
1035 #endif
1036
1037 /* Initialize MII/media info. */
1038 mii = GET_MII(sc);
1039 mii->mii_ifp = ifp;
1040 mii->mii_readreg = mue_miibus_readreg;
1041 mii->mii_writereg = mue_miibus_writereg;
1042 mii->mii_statchg = mue_miibus_statchg;
1043 mii->mii_flags = MIIF_AUTOTSLEEP;
1044
1045 sc->mue_ec.ec_mii = mii;
1046 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1047 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1048
1049 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1050 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1051 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1052 } else
1053 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1054
1055 /* Attach the interface. */
1056 if_attach(ifp);
1057 ether_ifattach(ifp, sc->mue_enaddr);
1058
1059 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1060 RND_TYPE_NET, RND_FLAG_DEFAULT);
1061
1062 callout_init(&sc->mue_stat_ch, 0);
1063
1064 splx(s);
1065
1066 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
1067
1068 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1069 }
1070
1071 static int
1072 mue_detach(device_t self, int flags)
1073 {
1074 struct mue_softc *sc = device_private(self);
1075 struct ifnet *ifp = GET_IFP(sc);
1076 size_t i;
1077 int s;
1078
1079 sc->mue_dying = true;
1080
1081 callout_halt(&sc->mue_stat_ch, NULL);
1082
1083 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1084 if (sc->mue_ep[i] != NULL)
1085 usbd_abort_pipe(sc->mue_ep[i]);
1086
1087 /*
1088 * Remove any pending tasks. They cannot be executing because they run
1089 * in the same thread as detach.
1090 */
1091 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1092 NULL);
1093 usb_rem_task_wait(sc->mue_udev, &sc->mue_stop_task, USB_TASKQ_DRIVER,
1094 NULL);
1095
1096 s = splusb();
1097
1098 if (ifp->if_flags & IFF_RUNNING)
1099 mue_stop(ifp, 1);
1100
1101 callout_destroy(&sc->mue_stat_ch);
1102 rnd_detach_source(&sc->mue_rnd_source);
1103 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1104 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1105 if (ifp->if_softc != NULL) {
1106 ether_ifdetach(ifp);
1107 if_detach(ifp);
1108 }
1109
1110 if (--sc->mue_refcnt >= 0) {
1111 /* Wait for processes to go away. */
1112 usb_detach_waitold(sc->mue_dev);
1113 }
1114 splx(s);
1115
1116 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1117
1118 mutex_destroy(&sc->mue_mii_lock);
1119
1120 return 0;
1121 }
1122
1123 static int
1124 mue_activate(device_t self, enum devact act)
1125 {
1126 struct mue_softc *sc = device_private(self);
1127 struct ifnet *ifp = GET_IFP(sc);
1128
1129 switch (act) {
1130 case DVACT_DEACTIVATE:
1131 if_deactivate(ifp);
1132 sc->mue_dying = true;
1133 return 0;
1134 default:
1135 return EOPNOTSUPP;
1136 }
1137 return 0;
1138 }
1139
1140 static int
1141 mue_rx_list_init(struct mue_softc *sc)
1142 {
1143 struct mue_cdata *cd;
1144 struct mue_chain *c;
1145 size_t i;
1146 int err;
1147
1148 cd = &sc->mue_cdata;
1149 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1150 c = &cd->mue_rx_chain[i];
1151 c->mue_sc = sc;
1152 c->mue_idx = i;
1153 if (c->mue_xfer == NULL) {
1154 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1155 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1156 if (err)
1157 return err;
1158 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1159 }
1160 }
1161
1162 return 0;
1163 }
1164
1165 static int
1166 mue_tx_list_init(struct mue_softc *sc)
1167 {
1168 struct mue_cdata *cd;
1169 struct mue_chain *c;
1170 size_t i;
1171 int err;
1172
1173 cd = &sc->mue_cdata;
1174 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1175 c = &cd->mue_tx_chain[i];
1176 c->mue_sc = sc;
1177 c->mue_idx = i;
1178 if (c->mue_xfer == NULL) {
1179 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1180 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1181 &c->mue_xfer);
1182 if (err)
1183 return err;
1184 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1185 }
1186 }
1187
1188 cd->mue_tx_prod = 0;
1189 cd->mue_tx_cnt = 0;
1190
1191 return 0;
1192 }
1193
1194 static int
1195 mue_open_pipes(struct mue_softc *sc)
1196 {
1197 usbd_status err;
1198
1199 /* Open RX and TX pipes. */
1200 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1201 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1202 if (err) {
1203 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1204 return EIO;
1205 }
1206 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1207 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1208 if (err) {
1209 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1210 return EIO;
1211 }
1212 return 0;
1213 }
1214
1215 static void
1216 mue_startup_rx_pipes(struct mue_softc *sc)
1217 {
1218 struct mue_chain *c;
1219 size_t i;
1220
1221 /* Start up the receive pipe. */
1222 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1223 c = &sc->mue_cdata.mue_rx_chain[i];
1224 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1225 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1226 usbd_transfer(c->mue_xfer);
1227 }
1228 }
1229
1230 static int
1231 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1232 {
1233 struct ifnet *ifp = GET_IFP(sc);
1234 struct mue_chain *c;
1235 usbd_status err;
1236 struct mue_txbuf_hdr hdr;
1237 uint32_t tx_cmd_a, tx_cmd_b;
1238 int csum, len;
1239 bool tso, ipe, tpe;
1240
1241 csum = m->m_pkthdr.csum_flags;
1242 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
1243 ipe = csum & M_CSUM_IPv4;
1244 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
1245 M_CSUM_TCPv6 | M_CSUM_UDPv6);
1246
1247 len = m->m_pkthdr.len;
1248 if (__predict_false((!tso &&
1249 (unsigned)len > MUE_FRAME_LEN(ifp->if_mtu)) ||
1250 ( tso && len > MUE_TSO_FRAME_LEN))) {
1251 MUE_PRINTF(sc, "packet length %d\n too long", len);
1252 return EINVAL;
1253 }
1254
1255 c = &sc->mue_cdata.mue_tx_chain[idx];
1256
1257 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
1258 tx_cmd_a = len | MUE_TX_CMD_A_FCS;
1259
1260 if (tso) {
1261 tx_cmd_a |= MUE_TX_CMD_A_LSO;
1262 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1263 tx_cmd_b = m->m_pkthdr.segsz;
1264 else
1265 tx_cmd_b = MUE_TX_MSS_MIN;
1266 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
1267 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
1268 mue_tx_offload(sc, m);
1269 } else {
1270 if (ipe)
1271 tx_cmd_a |= MUE_TX_CMD_A_IPE;
1272 if (tpe)
1273 tx_cmd_a |= MUE_TX_CMD_A_TPE;
1274 tx_cmd_b = 0;
1275 }
1276
1277 hdr.tx_cmd_a = htole32(tx_cmd_a);
1278 hdr.tx_cmd_b = htole32(tx_cmd_b);
1279
1280 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1281 m_copydata(m, 0, len, c->mue_buf + sizeof(hdr));
1282
1283 if (__predict_false(c->mue_xfer == NULL))
1284 return EIO; /* XXX plugged out or down */
1285
1286 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr),
1287 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1288
1289 /* Transmit */
1290 err = usbd_transfer(c->mue_xfer);
1291 if (__predict_false(err != USBD_IN_PROGRESS)) {
1292 MUE_PRINTF(sc, "%s\n", usbd_errstr(err));
1293 mue_stop(ifp, 0);
1294 return EIO;
1295 }
1296
1297 return 0;
1298 }
1299
1300 static void
1301 mue_tx_offload(struct mue_softc *sc, struct mbuf *m)
1302 {
1303 struct ether_header *eh;
1304 struct ip *ip;
1305 struct ip6_hdr *ip6;
1306 int off;
1307
1308 eh = mtod(m, struct ether_header *);
1309 switch (htons(eh->ether_type)) {
1310 case ETHERTYPE_IP:
1311 case ETHERTYPE_IPV6:
1312 off = ETHER_HDR_LEN;
1313 break;
1314 case ETHERTYPE_VLAN:
1315 /* XXX not yet supported */
1316 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1317 break;
1318 default:
1319 /* XXX */
1320 panic("%s: unsupported ethertype\n", __func__);
1321 /* NOTREACHED */
1322 }
1323
1324 /* Packet length should be cleared. */
1325 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1326 ip = (void *)(mtod(m, char *) + off);
1327 ip->ip_len = 0;
1328 } else {
1329 ip6 = (void *)(mtod(m, char *) + off);
1330 ip6->ip6_plen = 0;
1331 }
1332 }
1333
1334 static void
1335 mue_setmulti(struct mue_softc *sc)
1336 {
1337 struct ifnet *ifp = GET_IFP(sc);
1338 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1339 struct ether_multi *enm;
1340 struct ether_multistep step;
1341 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1342 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1343 uint32_t reg, rxfilt, h, hireg, loreg;
1344 size_t i;
1345
1346 if (sc->mue_dying)
1347 return;
1348
1349 /* Clear perfect filter and hash tables. */
1350 memset(pfiltbl, 0, sizeof(pfiltbl));
1351 memset(hashtbl, 0, sizeof(hashtbl));
1352
1353 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1354 rxfilt = mue_csr_read(sc, reg);
1355 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1356 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1357
1358 /* Always accept broadcast frames. */
1359 rxfilt |= MUE_RFE_CTL_BROADCAST;
1360
1361 if (ifp->if_flags & IFF_PROMISC) {
1362 rxfilt |= MUE_RFE_CTL_UNICAST;
1363 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1364 ifp->if_flags |= IFF_ALLMULTI;
1365 if (ifp->if_flags & IFF_PROMISC)
1366 DPRINTF(sc, "promisc\n");
1367 else
1368 DPRINTF(sc, "allmulti\n");
1369 } else {
1370 /* Now program new ones. */
1371 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1372 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1373 i = 1;
1374 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1375 while (enm != NULL) {
1376 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1377 ETHER_ADDR_LEN)) {
1378 memset(pfiltbl, 0, sizeof(pfiltbl));
1379 memset(hashtbl, 0, sizeof(hashtbl));
1380 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1381 goto allmulti;
1382 }
1383 if (i < MUE_NUM_ADDR_FILTX) {
1384 /* Use perfect address table if possible. */
1385 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1386 MUE_ADDR_FILTX_VALID;
1387 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1388 } else {
1389 /* Otherwise, use hash table. */
1390 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1391 h = (ether_crc32_be(enm->enm_addrlo,
1392 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1393 hashtbl[h / 32] |= 1 << (h % 32);
1394 }
1395 i++;
1396 ETHER_NEXT_MULTI(step, enm);
1397 }
1398 rxfilt |= MUE_RFE_CTL_PERFECT;
1399 ifp->if_flags &= ~IFF_ALLMULTI;
1400 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH)
1401 DPRINTF(sc, "perfect filter and hash tables\n");
1402 else
1403 DPRINTF(sc, "perfect filter\n");
1404 }
1405
1406 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1407 hireg = (sc->mue_flags & LAN7500) ?
1408 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1409 loreg = hireg + 4;
1410 mue_csr_write(sc, hireg, 0);
1411 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1412 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1413 }
1414
1415 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1416 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1417
1418 mue_csr_write(sc, reg, rxfilt);
1419 }
1420
1421 static void
1422 mue_sethwcsum(struct mue_softc *sc)
1423 {
1424 struct ifnet *ifp = GET_IFP(sc);
1425 uint32_t reg, val;
1426
1427 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1428 val = mue_csr_read(sc, reg);
1429
1430 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) {
1431 DPRINTF(sc, "RX IPv4 hwcsum enabled\n");
1432 val |= MUE_RFE_CTL_IP_COE;
1433 } else {
1434 DPRINTF(sc, "RX IPv4 hwcsum disabled\n");
1435 val &= ~MUE_RFE_CTL_IP_COE;
1436 }
1437
1438 if (ifp->if_capenable &
1439 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
1440 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) {
1441 DPRINTF(sc, "RX L4 hwcsum enabled\n");
1442 val |= MUE_RFE_CTL_TCPUDP_COE;
1443 } else {
1444 DPRINTF(sc, "RX L4 hwcsum disabled\n");
1445 val &= ~MUE_RFE_CTL_TCPUDP_COE;
1446 }
1447
1448 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1449
1450 mue_csr_write(sc, reg, val);
1451 }
1452
1453 static void
1454 mue_setmtu(struct mue_softc *sc)
1455 {
1456 struct ifnet *ifp = GET_IFP(sc);
1457 uint32_t val;
1458
1459 /* Set the maximum frame size. */
1460 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1461 val = mue_csr_read(sc, MUE_MAC_RX);
1462 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1463 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1464 mue_csr_write(sc, MUE_MAC_RX, val);
1465 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1466 }
1467
1468 static void
1469 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1470 {
1471 struct mue_chain *c = (struct mue_chain *)priv;
1472 struct mue_softc *sc = c->mue_sc;
1473 struct ifnet *ifp = GET_IFP(sc);
1474 struct mbuf *m;
1475 struct mue_rxbuf_hdr *hdrp;
1476 uint32_t rx_cmd_a, totlen;
1477 uint16_t pktlen;
1478 int s;
1479 int csum;
1480 char *buf = c->mue_buf;
1481 bool v6;
1482
1483 if (__predict_false(sc->mue_dying)) {
1484 DPRINTF(sc, "dying\n");
1485 return;
1486 }
1487
1488 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1489 DPRINTF(sc, "%s\n", usbd_errstr(status));
1490 if (status == USBD_INVAL)
1491 return; /* XXX plugged out or down */
1492 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1493 return;
1494 if (usbd_ratecheck(&sc->mue_rx_notice))
1495 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1496 if (status == USBD_STALLED)
1497 usbd_clear_endpoint_stall_async(
1498 sc->mue_ep[MUE_ENDPT_RX]);
1499 goto done;
1500 }
1501
1502 usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL);
1503
1504 KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u",
1505 totlen, sc->mue_rxbufsz);
1506
1507 do {
1508 if (__predict_false(totlen < sizeof(*hdrp))) {
1509 MUE_PRINTF(sc, "packet length %u too short\n", totlen);
1510 ifp->if_ierrors++;
1511 goto done;
1512 }
1513
1514 hdrp = (struct mue_rxbuf_hdr *)buf;
1515 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1516
1517 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1518 /*
1519 * We cannot use MUE_RX_CMD_A_RED bit here;
1520 * it is turned on in the cases of L3/L4
1521 * checksum errors which we handle below.
1522 */
1523 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1524 ifp->if_ierrors++;
1525 goto done;
1526 }
1527
1528 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1529 if (sc->mue_flags & LAN7500)
1530 pktlen -= 2;
1531
1532 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1533 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1534 pktlen + sizeof(*hdrp) > totlen)) {
1535 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1536 ifp->if_ierrors++;
1537 goto done;
1538 }
1539
1540 m = mue_newbuf();
1541 if (__predict_false(m == NULL)) {
1542 MUE_PRINTF(sc, "failed to allocate mbuf\n");
1543 ifp->if_ierrors++;
1544 goto done;
1545 }
1546
1547 m_set_rcvif(m, ifp);
1548 m->m_pkthdr.len = m->m_len = pktlen;
1549 m->m_flags |= M_HASFCS;
1550
1551 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1552 csum = 0;
1553 } else {
1554 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1555 switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1556 case MUE_RX_CMD_A_PID_TCP:
1557 csum = v6 ?
1558 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1559 break;
1560 case MUE_RX_CMD_A_PID_UDP:
1561 csum = v6 ?
1562 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1563 break;
1564 case MUE_RX_CMD_A_PID_IP:
1565 csum = v6 ? 0 : M_CSUM_IPv4;
1566 break;
1567 default:
1568 csum = 0;
1569 break;
1570 }
1571 csum &= ifp->if_csum_flags_rx;
1572 if (__predict_false((csum & M_CSUM_IPv4) &&
1573 (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1574 csum |= M_CSUM_IPv4_BAD;
1575 if (__predict_false((csum & ~M_CSUM_IPv4) &&
1576 (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1577 csum |= M_CSUM_TCP_UDP_BAD;
1578 }
1579 m->m_pkthdr.csum_flags = csum;
1580 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1581
1582 /* Attention: sizeof(hdr) = 10 */
1583 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1584 if (pktlen > totlen)
1585 pktlen = totlen;
1586 totlen -= pktlen;
1587 buf += pktlen;
1588
1589 s = splnet();
1590 if_percpuq_enqueue(ifp->if_percpuq, m);
1591 splx(s);
1592 } while (totlen > 0);
1593
1594 done:
1595 /* Setup new transfer. */
1596 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1597 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1598 usbd_transfer(xfer);
1599 }
1600
1601 static void
1602 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1603 {
1604 struct mue_chain *c = priv;
1605 struct mue_softc *sc = c->mue_sc;
1606 struct mue_cdata *cd = &sc->mue_cdata;
1607 struct ifnet *ifp = GET_IFP(sc);
1608 int s;
1609
1610 if (__predict_false(sc->mue_dying))
1611 return;
1612
1613 s = splnet();
1614 KASSERT(cd->mue_tx_cnt > 0);
1615 cd->mue_tx_cnt--;
1616 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1617 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1618 splx(s);
1619 return;
1620 }
1621 ifp->if_oerrors++;
1622 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1623 if (status == USBD_STALLED)
1624 usbd_clear_endpoint_stall_async(
1625 sc->mue_ep[MUE_ENDPT_TX]);
1626 splx(s);
1627 return;
1628 }
1629
1630 ifp->if_timer = 0;
1631 ifp->if_flags &= ~IFF_OACTIVE;
1632
1633 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1634 mue_start(ifp);
1635
1636 ifp->if_opackets++;
1637 splx(s);
1638 }
1639
1640 static int
1641 mue_init(struct ifnet *ifp)
1642 {
1643 struct mue_softc *sc = ifp->if_softc;
1644 int s;
1645
1646 if (sc->mue_dying) {
1647 DPRINTF(sc, "dying\n");
1648 return EIO;
1649 }
1650
1651 s = splnet();
1652
1653 /* Cancel pending I/O and free all TX/RX buffers. */
1654 if (ifp->if_flags & IFF_RUNNING)
1655 mue_stop(ifp, 1);
1656
1657 mue_reset(sc);
1658
1659 /* Set MAC address. */
1660 mue_set_macaddr(sc);
1661
1662 /* Load the multicast filter. */
1663 mue_setmulti(sc);
1664
1665 /* TCP/UDP checksum offload engines. */
1666 mue_sethwcsum(sc);
1667
1668 /* Set MTU. */
1669 mue_setmtu(sc);
1670
1671 if (mue_open_pipes(sc)) {
1672 splx(s);
1673 return EIO;
1674 }
1675
1676 /* Init RX ring. */
1677 if (mue_rx_list_init(sc)) {
1678 MUE_PRINTF(sc, "failed to init rx list\n");
1679 splx(s);
1680 return ENOBUFS;
1681 }
1682
1683 /* Init TX ring. */
1684 if (mue_tx_list_init(sc)) {
1685 MUE_PRINTF(sc, "failed to init tx list\n");
1686 splx(s);
1687 return ENOBUFS;
1688 }
1689
1690 mue_startup_rx_pipes(sc);
1691
1692 ifp->if_flags |= IFF_RUNNING;
1693 ifp->if_flags &= ~IFF_OACTIVE;
1694
1695 splx(s);
1696
1697 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1698
1699 return 0;
1700 }
1701
1702 static int
1703 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1704 {
1705 struct mue_softc *sc = ifp->if_softc;
1706 struct ifreq /*const*/ *ifr = data;
1707 int s, error = 0;
1708
1709 s = splnet();
1710
1711 switch (cmd) {
1712 case SIOCSIFFLAGS:
1713 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1714 break;
1715
1716 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1717 case IFF_RUNNING:
1718 mue_stop(ifp, 1);
1719 break;
1720 case IFF_UP:
1721 mue_init(ifp);
1722 break;
1723 case IFF_UP | IFF_RUNNING:
1724 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1725 mue_setmulti(sc);
1726 else
1727 mue_init(ifp);
1728 break;
1729 }
1730 sc->mue_if_flags = ifp->if_flags;
1731 break;
1732 case SIOCGIFMEDIA:
1733 case SIOCSIFMEDIA:
1734 error = ifmedia_ioctl(ifp, ifr, &sc->mue_mii.mii_media, cmd);
1735 break;
1736 default:
1737 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1738 break;
1739 error = 0;
1740 switch (cmd) {
1741 case SIOCADDMULTI:
1742 case SIOCDELMULTI:
1743 mue_setmulti(sc);
1744 break;
1745 case SIOCSIFCAP:
1746 mue_sethwcsum(sc);
1747 break;
1748 case SIOCSIFMTU:
1749 mue_setmtu(sc);
1750 break;
1751 default:
1752 break;
1753 }
1754 break;
1755 }
1756 splx(s);
1757
1758 return error;
1759 }
1760
1761 static void
1762 mue_watchdog(struct ifnet *ifp)
1763 {
1764 struct mue_softc *sc = ifp->if_softc;
1765 struct mue_chain *c;
1766 usbd_status stat;
1767 int s;
1768
1769 ifp->if_oerrors++;
1770 MUE_PRINTF(sc, "timed out\n");
1771
1772 s = splusb();
1773 c = &sc->mue_cdata.mue_tx_chain[0];
1774 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1775 mue_txeof(c->mue_xfer, c, stat);
1776
1777 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1778 mue_start(ifp);
1779 splx(s);
1780 }
1781
1782 static void
1783 mue_reset(struct mue_softc *sc)
1784 {
1785 if (sc->mue_dying)
1786 return;
1787
1788 /* Wait a little while for the chip to get its brains in order. */
1789 usbd_delay_ms(sc->mue_udev, 1);
1790
1791 // mue_chip_init(sc); /* XXX */
1792 }
1793
1794 static void
1795 mue_start(struct ifnet *ifp)
1796 {
1797 struct mue_softc *sc = ifp->if_softc;
1798 struct mbuf *m;
1799 struct mue_cdata *cd = &sc->mue_cdata;
1800 int idx;
1801
1802 if (__predict_false(!sc->mue_link)) {
1803 DPRINTF(sc, "no link\n");
1804 return;
1805 }
1806
1807 if (__predict_false((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING))
1808 != IFF_RUNNING)) {
1809 DPRINTF(sc, "not ready\n");
1810 return;
1811 }
1812
1813 idx = cd->mue_tx_prod;
1814 while ((unsigned)cd->mue_tx_cnt < sc->mue_tx_list_cnt) {
1815 IFQ_POLL(&ifp->if_snd, m);
1816 if (m == NULL)
1817 break;
1818
1819 if (__predict_false(mue_encap(sc, m, idx))) {
1820 ifp->if_oerrors++;
1821 break;
1822 }
1823 IFQ_DEQUEUE(&ifp->if_snd, m);
1824
1825 bpf_mtap(ifp, m, BPF_D_OUT);
1826 m_freem(m);
1827
1828 idx = (idx + 1) % sc->mue_tx_list_cnt;
1829 cd->mue_tx_cnt++;
1830
1831 }
1832 cd->mue_tx_prod = idx;
1833
1834 if ((unsigned)cd->mue_tx_cnt >= sc->mue_tx_list_cnt)
1835 ifp->if_flags |= IFF_OACTIVE;
1836
1837 /* Set a timeout in case the chip goes out to lunch. */
1838 ifp->if_timer = 5;
1839 }
1840
1841 static void
1842 mue_stop(struct ifnet *ifp, int disable __unused)
1843 {
1844 struct mue_softc *sc = ifp->if_softc;
1845 struct mue_chain *c;
1846 usbd_status err;
1847 size_t i;
1848
1849 mue_reset(sc);
1850
1851 ifp->if_timer = 0;
1852 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1853
1854 callout_stop(&sc->mue_stat_ch);
1855 sc->mue_link = 0;
1856
1857 /* Stop transfers. */
1858 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1859 if (sc->mue_ep[i] != NULL) {
1860 err = usbd_abort_pipe(sc->mue_ep[i]);
1861 if (err)
1862 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1863 i, usbd_errstr(err));
1864 }
1865
1866 /* Free RX resources. */
1867 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1868 c = &sc->mue_cdata.mue_rx_chain[i];
1869 if (c->mue_xfer != NULL) {
1870 usbd_destroy_xfer(c->mue_xfer);
1871 c->mue_xfer = NULL;
1872 }
1873 }
1874
1875 /* Free TX resources. */
1876 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1877 c = &sc->mue_cdata.mue_tx_chain[i];
1878 if (c->mue_xfer != NULL) {
1879 usbd_destroy_xfer(c->mue_xfer);
1880 c->mue_xfer = NULL;
1881 }
1882 }
1883
1884 /* Close pipes */
1885 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1886 if (sc->mue_ep[i] != NULL) {
1887 err = usbd_close_pipe(sc->mue_ep[i]);
1888 if (err)
1889 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1890 i, usbd_errstr(err));
1891 sc->mue_ep[i] = NULL;
1892 }
1893
1894 DPRINTF(sc, "done\n");
1895 }
1896
1897 static void
1898 mue_tick(void *xsc)
1899 {
1900 struct mue_softc *sc = xsc;
1901
1902 if (sc == NULL)
1903 return;
1904
1905 if (sc->mue_dying)
1906 return;
1907
1908 /* Perform periodic stuff in process context. */
1909 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1910 }
1911
1912 static void
1913 mue_tick_task(void *xsc)
1914 {
1915 struct mue_softc *sc = xsc;
1916 struct ifnet *ifp;
1917 struct mii_data *mii;
1918 int s;
1919
1920 if (sc == NULL)
1921 return;
1922
1923 if (sc->mue_dying)
1924 return;
1925
1926 ifp = GET_IFP(sc);
1927 mii = GET_MII(sc);
1928
1929 s = splnet();
1930 mii_tick(mii);
1931 if (sc->mue_link == 0)
1932 mue_miibus_statchg(ifp);
1933 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1934 splx(s);
1935 }
1936
1937 static struct mbuf *
1938 mue_newbuf(void)
1939 {
1940 struct mbuf *m;
1941
1942 MGETHDR(m, M_DONTWAIT, MT_DATA);
1943 if (__predict_false(m == NULL))
1944 return NULL;
1945
1946 MCLGET(m, M_DONTWAIT);
1947 if (__predict_false(!(m->m_flags & M_EXT))) {
1948 m_freem(m);
1949 return NULL;
1950 }
1951
1952 m_adj(m, ETHER_ALIGN);
1953
1954 return m;
1955 }
1956