if_mue.c revision 1.44 1 /* $NetBSD: if_mue.c,v 1.44 2019/05/23 10:57:29 msaitoh Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.44 2019/05/23 10:57:29 msaitoh Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/mutex.h>
36 #include <sys/kernel.h>
37 #include <sys/proc.h>
38 #include <sys/socket.h>
39
40 #include <sys/device.h>
41
42 #include <sys/rndsource.h>
43
44 #include <net/if.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_ether.h>
48
49 #include <net/bpf.h>
50
51 #include <netinet/if_inarp.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h> /* XXX for struct ip */
54 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
55
56 #include <dev/mii/mii.h>
57 #include <dev/mii/miivar.h>
58
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
61 #include <dev/usb/usbdi_util.h>
62 #include <dev/usb/usbdivar.h>
63 #include <dev/usb/usbdevs.h>
64
65 #include <dev/usb/if_muereg.h>
66 #include <dev/usb/if_muevar.h>
67
68 #define MUE_PRINTF(sc, fmt, args...) \
69 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
70
71 #ifdef USB_DEBUG
72 int muedebug = 0;
73 #define DPRINTF(sc, fmt, args...) \
74 do { \
75 if (muedebug) \
76 MUE_PRINTF(sc, fmt, ##args); \
77 } while (0 /* CONSTCOND */)
78 #else
79 #define DPRINTF(sc, fmt, args...) __nothing
80 #endif
81
82 /*
83 * Various supported device vendors/products.
84 */
85 struct mue_type {
86 struct usb_devno mue_dev;
87 uint16_t mue_flags;
88 #define LAN7500 0x0001 /* LAN7500 */
89 };
90
91 const struct mue_type mue_devs[] = {
92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
97 };
98
99 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
100 uaa->uaa_vendor, uaa->uaa_product))
101
102 #define MUE_ENADDR_LO(enaddr) \
103 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
104 #define MUE_ENADDR_HI(enaddr) \
105 ((enaddr[5] << 8) | enaddr[4])
106
107 static int mue_match(device_t, cfdata_t, void *);
108 static void mue_attach(device_t, device_t, void *);
109 static int mue_detach(device_t, int);
110 static int mue_activate(device_t, enum devact);
111
112 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
113 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
114 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
115 uint32_t, uint32_t);
116
117 static void mue_lock_mii(struct mue_softc *);
118 static void mue_unlock_mii(struct mue_softc *);
119
120 static int mue_miibus_readreg(device_t, int, int, uint16_t *);
121 static int mue_miibus_writereg(device_t, int, int, uint16_t);
122 static void mue_miibus_statchg(struct ifnet *);
123 static int mue_ifmedia_upd(struct ifnet *);
124 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125
126 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
127 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
128 static bool mue_eeprom_present(struct mue_softc *sc);
129
130 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
131 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
132
133 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
134 uint32_t, uint32_t *);
135
136 static void mue_init_ltm(struct mue_softc *);
137
138 static int mue_chip_init(struct mue_softc *);
139
140 static void mue_set_macaddr(struct mue_softc *);
141 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
142
143 static int mue_rx_list_init(struct mue_softc *);
144 static int mue_tx_list_init(struct mue_softc *);
145 static int mue_open_pipes(struct mue_softc *);
146 static void mue_startup_rx_pipes(struct mue_softc *);
147
148 static int mue_encap(struct mue_softc *, struct mbuf *, int);
149 static int mue_prepare_tso(struct mue_softc *, struct mbuf *);
150
151 static void mue_setmulti(struct mue_softc *);
152 static void mue_sethwcsum(struct mue_softc *);
153 static void mue_setmtu(struct mue_softc *);
154
155 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
156 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
157
158 static int mue_init(struct ifnet *);
159 static int mue_ioctl(struct ifnet *, u_long, void *);
160 static void mue_watchdog(struct ifnet *);
161 static void mue_reset(struct mue_softc *);
162 static void mue_start(struct ifnet *);
163 static void mue_stop(struct ifnet *, int);
164 static void mue_tick(void *);
165 static void mue_tick_task(void *);
166
167 static struct mbuf *mue_newbuf(void);
168
169 #define MUE_SETBIT(sc, reg, x) \
170 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
171
172 #define MUE_CLRBIT(sc, reg, x) \
173 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
174
175 #define MUE_WAIT_SET(sc, reg, set, fail) \
176 mue_wait_for_bits(sc, reg, set, ~0, fail)
177
178 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
179 mue_wait_for_bits(sc, reg, 0, clear, fail)
180
181 #define ETHER_IS_VALID(addr) \
182 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
183
184 #define ETHER_IS_ZERO(addr) \
185 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
186
187 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
188 mue_detach, mue_activate);
189
190 static uint32_t
191 mue_csr_read(struct mue_softc *sc, uint32_t reg)
192 {
193 usb_device_request_t req;
194 usbd_status err;
195 uDWord val;
196
197 if (sc->mue_dying)
198 return 0;
199
200 USETDW(val, 0);
201 req.bmRequestType = UT_READ_VENDOR_DEVICE;
202 req.bRequest = MUE_UR_READREG;
203 USETW(req.wValue, 0);
204 USETW(req.wIndex, reg);
205 USETW(req.wLength, 4);
206
207 err = usbd_do_request(sc->mue_udev, &req, &val);
208 if (err) {
209 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
210 return 0;
211 }
212
213 return UGETDW(val);
214 }
215
216 static int
217 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
218 {
219 usb_device_request_t req;
220 usbd_status err;
221 uDWord val;
222
223 if (sc->mue_dying)
224 return 0;
225
226 USETDW(val, aval);
227 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
228 req.bRequest = MUE_UR_WRITEREG;
229 USETW(req.wValue, 0);
230 USETW(req.wIndex, reg);
231 USETW(req.wLength, 4);
232
233 err = usbd_do_request(sc->mue_udev, &req, &val);
234 if (err) {
235 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
236 return -1;
237 }
238
239 return 0;
240 }
241
242 static int
243 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
244 uint32_t set, uint32_t clear, uint32_t fail)
245 {
246 uint32_t val;
247 int ntries;
248
249 for (ntries = 0; ntries < 1000; ntries++) {
250 val = mue_csr_read(sc, reg);
251 if ((val & set) || !(val & clear))
252 return 0;
253 if (val & fail)
254 return 1;
255 usbd_delay_ms(sc->mue_udev, 1);
256 }
257
258 return 1;
259 }
260
261 /*
262 * Get exclusive access to the MII registers.
263 */
264 static void
265 mue_lock_mii(struct mue_softc *sc)
266 {
267 sc->mue_refcnt++;
268 mutex_enter(&sc->mue_mii_lock);
269 }
270
271 static void
272 mue_unlock_mii(struct mue_softc *sc)
273 {
274 mutex_exit(&sc->mue_mii_lock);
275 if (--sc->mue_refcnt < 0)
276 usb_detach_wakeupold(sc->mue_dev);
277 }
278
279 static int
280 mue_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
281 {
282 struct mue_softc *sc = device_private(dev);
283 uint32_t data;
284 int rv = 0;
285
286 if (sc->mue_dying) {
287 DPRINTF(sc, "dying\n");
288 return -1;
289 }
290
291 if (sc->mue_phyno != phy)
292 return -1;
293
294 mue_lock_mii(sc);
295 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
296 mue_unlock_mii(sc);
297 MUE_PRINTF(sc, "not ready\n");
298 return -1;
299 }
300
301 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
302 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
303 MUE_MII_ACCESS_PHYADDR(phy));
304
305 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
306 MUE_PRINTF(sc, "timed out\n");
307 rv = ETIMEDOUT;
308 goto out;
309 }
310
311 data = mue_csr_read(sc, MUE_MII_DATA);
312 *val = data & 0xffff;
313
314 out:
315 mue_unlock_mii(sc);
316 return rv;
317 }
318
319 static int
320 mue_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
321 {
322 struct mue_softc *sc = device_private(dev);
323 int rv = 0;
324
325 if (sc->mue_dying) {
326 DPRINTF(sc, "dying\n");
327 return -1;
328 }
329
330 if (sc->mue_phyno != phy) {
331 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
332 sc->mue_phyno, phy);
333 return -1;
334 }
335
336 mue_lock_mii(sc);
337 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
338 MUE_PRINTF(sc, "not ready\n");
339 rv = EBUSY;
340 goto out;
341 }
342
343 mue_csr_write(sc, MUE_MII_DATA, val);
344 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
345 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
346 MUE_MII_ACCESS_PHYADDR(phy));
347
348 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
349 MUE_PRINTF(sc, "timed out\n");
350 rv = ETIMEDOUT;
351 }
352 out:
353 mue_unlock_mii(sc);
354 return rv;
355 }
356
357 static void
358 mue_miibus_statchg(struct ifnet *ifp)
359 {
360 struct mue_softc *sc;
361 struct mii_data *mii;
362 uint32_t flow, threshold;
363
364 if (ifp == NULL) {
365 printf("%s: ifp not ready\n", __func__);
366 return;
367 }
368
369 sc = ifp->if_softc;
370 mii = GET_MII(sc);
371
372 if ((ifp->if_flags & IFF_RUNNING) == 0) {
373 DPRINTF(sc, "not running\n");
374 return;
375 }
376
377 if (mii == NULL) {
378 DPRINTF(sc, "mii not ready\n");
379 return;
380 }
381
382 sc->mue_link = 0;
383 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
384 (IFM_ACTIVE | IFM_AVALID)) {
385 switch (IFM_SUBTYPE(mii->mii_media_active)) {
386 case IFM_10_T:
387 case IFM_100_TX:
388 case IFM_1000_T:
389 sc->mue_link++;
390 break;
391 default:
392 break;
393 }
394 }
395
396 /* Lost link, do nothing. */
397 if (sc->mue_link == 0) {
398 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
399 return;
400 }
401
402 if (!(sc->mue_flags & LAN7500)) {
403 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
404 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
405 /* Disable U2 and enable U1. */
406 MUE_CLRBIT(sc, MUE_USB_CFG1,
407 MUE_USB_CFG1_DEV_U2_INIT_EN);
408 MUE_SETBIT(sc, MUE_USB_CFG1,
409 MUE_USB_CFG1_DEV_U1_INIT_EN);
410 } else {
411 /* Enable U1 and U2. */
412 MUE_SETBIT(sc, MUE_USB_CFG1,
413 MUE_USB_CFG1_DEV_U1_INIT_EN |
414 MUE_USB_CFG1_DEV_U2_INIT_EN);
415 }
416 }
417 }
418
419 flow = 0;
420 /* XXX Linux does not check IFM_FDX flag for 7800. */
421 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
422 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
423 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
424 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
425 flow |= MUE_FLOW_RX_FCEN;
426 }
427
428 /* XXX Magic numbers taken from Linux driver. */
429 if (sc->mue_flags & LAN7500)
430 threshold = 0x820;
431 else
432 switch (sc->mue_udev->ud_speed) {
433 case USB_SPEED_SUPER:
434 threshold = 0x817;
435 break;
436 case USB_SPEED_HIGH:
437 threshold = 0x211;
438 break;
439 default:
440 threshold = 0;
441 break;
442 }
443
444 /* Threshold value should be set before enabling flow. */
445 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
446 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
447 mue_csr_write(sc, MUE_FLOW, flow);
448
449 DPRINTF(sc, "done\n");
450 }
451
452 /*
453 * Set media options.
454 */
455 static int
456 mue_ifmedia_upd(struct ifnet *ifp)
457 {
458 struct mue_softc *sc = ifp->if_softc;
459 struct mii_data *mii = GET_MII(sc);
460
461 sc->mue_link = 0; /* XXX */
462
463 if (mii->mii_instance) {
464 struct mii_softc *miisc;
465 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
466 mii_phy_reset(miisc);
467 }
468 return mii_mediachg(mii);
469 }
470
471 /*
472 * Report current media status.
473 */
474 static void
475 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
476 {
477 struct mue_softc *sc = ifp->if_softc;
478 struct mii_data *mii = GET_MII(sc);
479
480 mii_pollstat(mii);
481 ifmr->ifm_active = mii->mii_media_active;
482 ifmr->ifm_status = mii->mii_media_status;
483 }
484
485 static uint8_t
486 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
487 {
488 uint32_t val;
489
490 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
491 MUE_PRINTF(sc, "not ready\n");
492 return ETIMEDOUT;
493 }
494
495 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
496 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
497 off);
498
499 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
500 MUE_E2P_CMD_TIMEOUT)) {
501 MUE_PRINTF(sc, "timed out\n");
502 return ETIMEDOUT;
503 }
504
505 val = mue_csr_read(sc, MUE_E2P_DATA);
506 *dest = val & 0xff;
507
508 return 0;
509 }
510
511 static int
512 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
513 {
514 uint32_t val = 0; /* XXX gcc */
515 uint8_t byte;
516 int i, err = 0;
517
518 /*
519 * EEPROM pins are muxed with the LED function on LAN7800 device.
520 */
521 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
522 val = mue_csr_read(sc, MUE_HW_CFG);
523 mue_csr_write(sc, MUE_HW_CFG,
524 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
525 }
526
527 for (i = 0; i < cnt; i++) {
528 err = mue_eeprom_getbyte(sc, off + i, &byte);
529 if (err)
530 break;
531 *(dest + i) = byte;
532 }
533
534 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
535 mue_csr_write(sc, MUE_HW_CFG, val);
536
537 return err ? 1 : 0;
538 }
539
540 static bool
541 mue_eeprom_present(struct mue_softc *sc)
542 {
543 uint32_t val;
544 uint8_t sig;
545 int ret;
546
547 if (sc->mue_flags & LAN7500) {
548 val = mue_csr_read(sc, MUE_E2P_CMD);
549 return val & MUE_E2P_CMD_LOADED;
550 } else {
551 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
552 return (ret == 0) && (sig == MUE_E2P_IND);
553 }
554 }
555
556 static int
557 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
558 {
559 uint32_t val;
560 int i, err;
561
562 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
563
564 /* Checking if bit is set. */
565 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
566 /* Clear it, then wait for it to be cleared. */
567 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
568 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
569 0);
570 if (err) {
571 MUE_PRINTF(sc, "not ready\n");
572 return 1;
573 }
574 }
575
576 /* Start reading the bytes, one at a time. */
577 for (i = 0; i < cnt; i++) {
578 mue_csr_write(sc, MUE_OTP_ADDR1,
579 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
580 mue_csr_write(sc, MUE_OTP_ADDR2,
581 ((off + i) & MUE_OTP_ADDR2_MASK));
582 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
583 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
584
585 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
586 if (err) {
587 MUE_PRINTF(sc, "timed out\n");
588 return 1;
589 }
590 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
591 *(dest + i) = (uint8_t)(val & 0xff);
592 }
593
594 return 0;
595 }
596
597 static int
598 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
599 {
600 uint8_t sig;
601 int err;
602
603 if (sc->mue_flags & LAN7500)
604 return 1;
605
606 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
607 if (err)
608 return 1;
609 switch (sig) {
610 case MUE_OTP_IND_1:
611 break;
612 case MUE_OTP_IND_2:
613 off += 0x100;
614 break;
615 default:
616 DPRINTF(sc, "OTP not found\n");
617 return 1;
618 }
619 err = mue_read_otp_raw(sc, dest, off, cnt);
620 return err;
621 }
622
623 static void
624 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
625 uint32_t cnt, uint32_t *data)
626 {
627 uint32_t i;
628
629 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
630 MUE_PRINTF(sc, "not ready\n");
631 return;
632 }
633
634 mue_csr_write(sc, MUE_DP_SEL,
635 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
636
637 for (i = 0; i < cnt; i++) {
638 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
639 mue_csr_write(sc, MUE_DP_DATA, data[i]);
640 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
641 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
642 MUE_PRINTF(sc, "timed out\n");
643 return;
644 }
645 }
646 }
647
648 static void
649 mue_init_ltm(struct mue_softc *sc)
650 {
651 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
652 uint8_t temp[2];
653 size_t i;
654
655 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
656 if (mue_eeprom_present(sc) &&
657 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
658 if (temp[0] != sizeof(idx)) {
659 DPRINTF(sc, "EEPROM: unexpected size\n");
660 goto done;
661 }
662 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
663 sizeof(idx))) {
664 DPRINTF(sc, "EEPROM: failed to read\n");
665 goto done;
666 }
667 DPRINTF(sc, "success\n");
668 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
669 if (temp[0] != sizeof(idx)) {
670 DPRINTF(sc, "OTP: unexpected size\n");
671 goto done;
672 }
673 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
674 sizeof(idx))) {
675 DPRINTF(sc, "OTP: failed to read\n");
676 goto done;
677 }
678 DPRINTF(sc, "success\n");
679 } else
680 DPRINTF(sc, "nothing to do\n");
681 } else
682 DPRINTF(sc, "nothing to do\n");
683 done:
684 for (i = 0; i < __arraycount(idx); i++)
685 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
686 }
687
688 static int
689 mue_chip_init(struct mue_softc *sc)
690 {
691 uint32_t val;
692
693 if ((sc->mue_flags & LAN7500) &&
694 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
695 MUE_PRINTF(sc, "not ready\n");
696 return ETIMEDOUT;
697 }
698
699 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
700 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
701 MUE_PRINTF(sc, "timed out\n");
702 return ETIMEDOUT;
703 }
704
705 /* Respond to the IN token with a NAK. */
706 if (sc->mue_flags & LAN7500)
707 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
708 else
709 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
710
711 if (sc->mue_flags & LAN7500) {
712 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
713 val = MUE_7500_HS_RX_BUFSIZE /
714 MUE_HS_USB_PKT_SIZE;
715 else
716 val = MUE_7500_FS_RX_BUFSIZE /
717 MUE_FS_USB_PKT_SIZE;
718 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
719 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
720 MUE_7500_DEFAULT_BULKIN_DELAY);
721
722 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
723
724 /* Set FIFO sizes. */
725 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
726 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
727 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
728 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
729 } else {
730 /* Init LTM. */
731 mue_init_ltm(sc);
732
733 val = MUE_7800_RX_BUFSIZE;
734 switch (sc->mue_udev->ud_speed) {
735 case USB_SPEED_SUPER:
736 val /= MUE_SS_USB_PKT_SIZE;
737 break;
738 case USB_SPEED_HIGH:
739 val /= MUE_HS_USB_PKT_SIZE;
740 break;
741 default:
742 val /= MUE_FS_USB_PKT_SIZE;
743 break;
744 }
745 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
746 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
747 MUE_7800_DEFAULT_BULKIN_DELAY);
748
749 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
750 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
751
752 /*
753 * Set FCL's RX and TX FIFO sizes: according to data sheet this
754 * is already the default value. But we initialize it to the
755 * same value anyways, as that's what the Linux driver does.
756 */
757 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
758 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
759 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
760 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
761 }
762
763 /* Enabling interrupts. */
764 mue_csr_write(sc, MUE_INT_STATUS, ~0);
765
766 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
767 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
768 mue_csr_write(sc, MUE_FLOW, 0);
769
770 /* Reset PHY. */
771 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
772 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
773 MUE_PRINTF(sc, "PHY not ready\n");
774 return ETIMEDOUT;
775 }
776
777 /* LAN7801 only has RGMII mode. */
778 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
779 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
780
781 if ((sc->mue_flags & LAN7500) ||
782 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
783 !mue_eeprom_present(sc))) {
784 /* Allow MAC to detect speed and duplex from PHY. */
785 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
786 MUE_MAC_CR_AUTO_DUPLEX);
787 }
788
789 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
790 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
791 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
792
793 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
794 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
795
796 /* Set default GPIO/LED settings only if no EEPROM is detected. */
797 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
798 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
799 MUE_SETBIT(sc, MUE_LED_CFG,
800 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
801 }
802
803 /* XXX We assume two LEDs at least when EEPROM is missing. */
804 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
805 !mue_eeprom_present(sc))
806 MUE_SETBIT(sc, MUE_HW_CFG,
807 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
808
809 return 0;
810 }
811
812 static void
813 mue_set_macaddr(struct mue_softc *sc)
814 {
815 struct ifnet *ifp = GET_IFP(sc);
816 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
817 uint32_t lo, hi;
818
819 lo = MUE_ENADDR_LO(enaddr);
820 hi = MUE_ENADDR_HI(enaddr);
821
822 mue_csr_write(sc, MUE_RX_ADDRL, lo);
823 mue_csr_write(sc, MUE_RX_ADDRH, hi);
824 }
825
826 static int
827 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
828 {
829 prop_data_t eaprop;
830 uint32_t low, high;
831
832 if (!(sc->mue_flags & LAN7500)) {
833 low = mue_csr_read(sc, MUE_RX_ADDRL);
834 high = mue_csr_read(sc, MUE_RX_ADDRH);
835 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
836 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
837 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
838 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
839 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
840 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
841 if (ETHER_IS_VALID(sc->mue_enaddr))
842 return 0;
843 else
844 DPRINTF(sc, "registers: %s\n",
845 ether_sprintf(sc->mue_enaddr));
846 }
847
848 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
849 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
850 if (ETHER_IS_VALID(sc->mue_enaddr))
851 return 0;
852 else
853 DPRINTF(sc, "EEPROM: %s\n",
854 ether_sprintf(sc->mue_enaddr));
855 }
856
857 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
858 ETHER_ADDR_LEN) == 0) {
859 if (ETHER_IS_VALID(sc->mue_enaddr))
860 return 0;
861 else
862 DPRINTF(sc, "OTP: %s\n",
863 ether_sprintf(sc->mue_enaddr));
864 }
865
866 /*
867 * Other MD methods. This should be tried only if other methods fail.
868 * Otherwise, MAC address for internal device can be assinged to
869 * external devices on Raspberry Pi, for example.
870 */
871 eaprop = prop_dictionary_get(dict, "mac-address");
872 if (eaprop != NULL) {
873 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
874 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
875 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
876 ETHER_ADDR_LEN);
877 if (ETHER_IS_VALID(sc->mue_enaddr))
878 return 0;
879 else
880 DPRINTF(sc, "prop_dictionary_get: %s\n",
881 ether_sprintf(sc->mue_enaddr));
882 }
883
884 return 1;
885 }
886
887
888 /*
889 * Probe for a Microchip chip. */
890 static int
891 mue_match(device_t parent, cfdata_t match, void *aux)
892 {
893 struct usb_attach_arg *uaa = aux;
894
895 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
896 }
897
898 static void
899 mue_attach(device_t parent, device_t self, void *aux)
900 {
901 struct mue_softc *sc = device_private(self);
902 prop_dictionary_t dict = device_properties(self);
903 struct usb_attach_arg *uaa = aux;
904 struct usbd_device *dev = uaa->uaa_device;
905 usb_interface_descriptor_t *id;
906 usb_endpoint_descriptor_t *ed;
907 char *devinfop;
908 struct mii_data *mii;
909 struct ifnet *ifp;
910 usbd_status err;
911 const char *descr;
912 uint8_t i;
913 int s;
914
915 aprint_naive("\n");
916 aprint_normal("\n");
917
918 sc->mue_dev = self;
919 sc->mue_udev = dev;
920
921 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
922 aprint_normal_dev(self, "%s\n", devinfop);
923 usbd_devinfo_free(devinfop);
924
925 #define MUE_CONFIG_NO 1
926 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
927 if (err) {
928 aprint_error_dev(self, "failed to set configuration: %s\n",
929 usbd_errstr(err));
930 return;
931 }
932
933 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
934
935 #define MUE_IFACE_IDX 0
936 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
937 if (err) {
938 aprint_error_dev(self, "failed to get interface handle: %s\n",
939 usbd_errstr(err));
940 return;
941 }
942
943 sc->mue_product = uaa->uaa_product;
944 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
945
946 sc->mue_id_rev = mue_csr_read(sc, MUE_ID_REV);
947
948 /* Decide on what our bufsize will be. */
949 if (sc->mue_flags & LAN7500) {
950 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
951 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
952 sc->mue_rx_list_cnt = 1;
953 sc->mue_tx_list_cnt = 1;
954 } else {
955 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
956 sc->mue_rx_list_cnt = MUE_RX_LIST_CNT;
957 sc->mue_tx_list_cnt = MUE_TX_LIST_CNT;
958 }
959 sc->mue_txbufsz = MUE_TX_BUFSIZE;
960
961 /* Find endpoints. */
962 id = usbd_get_interface_descriptor(sc->mue_iface);
963 for (i = 0; i < id->bNumEndpoints; i++) {
964 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
965 if (ed == NULL) {
966 aprint_error_dev(self, "failed to get ep %hhd\n", i);
967 return;
968 }
969 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
970 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
971 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
972 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
973 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
974 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
975 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
976 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
977 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
978 }
979 }
980 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
981 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
982 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
983
984 s = splnet();
985
986 sc->mue_phyno = 1;
987
988 if (mue_chip_init(sc)) {
989 aprint_error_dev(self, "failed to initialize chip\n");
990 splx(s);
991 return;
992 }
993
994 /* A Microchip chip was detected. Inform the world. */
995 descr = (sc->mue_flags & LAN7500) ? "LAN7500" : "LAN7800";
996 aprint_normal_dev(self, "%s id 0x%x rev 0x%x\n", descr,
997 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_ID),
998 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_REV));
999
1000 if (mue_get_macaddr(sc, dict)) {
1001 aprint_error_dev(self, "failed to read MAC address\n");
1002 splx(s);
1003 return;
1004 }
1005
1006 aprint_normal_dev(self, "Ethernet address %s\n",
1007 ether_sprintf(sc->mue_enaddr));
1008
1009 /* Initialize interface info.*/
1010 ifp = GET_IFP(sc);
1011 ifp->if_softc = sc;
1012 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
1013 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1014 ifp->if_init = mue_init;
1015 ifp->if_ioctl = mue_ioctl;
1016 ifp->if_start = mue_start;
1017 ifp->if_stop = mue_stop;
1018 ifp->if_watchdog = mue_watchdog;
1019
1020 IFQ_SET_READY(&ifp->if_snd);
1021
1022 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
1023 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1024 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1025 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1026 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
1027 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
1028
1029 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1030 #if 0 /* XXX not yet */
1031 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
1032 #endif
1033
1034 /* Initialize MII/media info. */
1035 mii = GET_MII(sc);
1036 mii->mii_ifp = ifp;
1037 mii->mii_readreg = mue_miibus_readreg;
1038 mii->mii_writereg = mue_miibus_writereg;
1039 mii->mii_statchg = mue_miibus_statchg;
1040 mii->mii_flags = MIIF_AUTOTSLEEP;
1041
1042 sc->mue_ec.ec_mii = mii;
1043 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1044 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1045
1046 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1047 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1048 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1049 } else
1050 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1051
1052 /* Attach the interface. */
1053 if_attach(ifp);
1054 ether_ifattach(ifp, sc->mue_enaddr);
1055
1056 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1057 RND_TYPE_NET, RND_FLAG_DEFAULT);
1058
1059 callout_init(&sc->mue_stat_ch, 0);
1060
1061 splx(s);
1062
1063 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
1064
1065 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1066 }
1067
1068 static int
1069 mue_detach(device_t self, int flags)
1070 {
1071 struct mue_softc *sc = device_private(self);
1072 struct ifnet *ifp = GET_IFP(sc);
1073 size_t i;
1074 int s;
1075
1076 sc->mue_dying = true;
1077
1078 callout_halt(&sc->mue_stat_ch, NULL);
1079
1080 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1081 if (sc->mue_ep[i] != NULL)
1082 usbd_abort_pipe(sc->mue_ep[i]);
1083
1084 /*
1085 * Remove any pending tasks. They cannot be executing because they run
1086 * in the same thread as detach.
1087 */
1088 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1089 NULL);
1090
1091 s = splusb();
1092
1093 if (ifp->if_flags & IFF_RUNNING)
1094 mue_stop(ifp, 1);
1095
1096 callout_destroy(&sc->mue_stat_ch);
1097 rnd_detach_source(&sc->mue_rnd_source);
1098 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1099 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1100 if (ifp->if_softc != NULL) {
1101 ether_ifdetach(ifp);
1102 if_detach(ifp);
1103 }
1104
1105 if (--sc->mue_refcnt >= 0) {
1106 /* Wait for processes to go away. */
1107 usb_detach_waitold(sc->mue_dev);
1108 }
1109 splx(s);
1110
1111 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1112
1113 mutex_destroy(&sc->mue_mii_lock);
1114
1115 return 0;
1116 }
1117
1118 static int
1119 mue_activate(device_t self, enum devact act)
1120 {
1121 struct mue_softc *sc = device_private(self);
1122 struct ifnet *ifp = GET_IFP(sc);
1123
1124 switch (act) {
1125 case DVACT_DEACTIVATE:
1126 if_deactivate(ifp);
1127 sc->mue_dying = true;
1128 return 0;
1129 default:
1130 return EOPNOTSUPP;
1131 }
1132 return 0;
1133 }
1134
1135 static int
1136 mue_rx_list_init(struct mue_softc *sc)
1137 {
1138 struct mue_cdata *cd;
1139 struct mue_chain *c;
1140 size_t i;
1141 int err;
1142
1143 cd = &sc->mue_cdata;
1144 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1145 c = &cd->mue_rx_chain[i];
1146 c->mue_sc = sc;
1147 if (c->mue_xfer == NULL) {
1148 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1149 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1150 if (err)
1151 return err;
1152 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1153 }
1154 }
1155
1156 return 0;
1157 }
1158
1159 static int
1160 mue_tx_list_init(struct mue_softc *sc)
1161 {
1162 struct mue_cdata *cd;
1163 struct mue_chain *c;
1164 size_t i;
1165 int err;
1166
1167 cd = &sc->mue_cdata;
1168 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1169 c = &cd->mue_tx_chain[i];
1170 c->mue_sc = sc;
1171 if (c->mue_xfer == NULL) {
1172 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1173 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1174 &c->mue_xfer);
1175 if (err)
1176 return err;
1177 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1178 }
1179 }
1180
1181 cd->mue_tx_prod = 0;
1182 cd->mue_tx_cnt = 0;
1183
1184 return 0;
1185 }
1186
1187 static int
1188 mue_open_pipes(struct mue_softc *sc)
1189 {
1190 usbd_status err;
1191
1192 /* Open RX and TX pipes. */
1193 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1194 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1195 if (err) {
1196 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1197 return EIO;
1198 }
1199 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1200 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1201 if (err) {
1202 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1203 return EIO;
1204 }
1205 return 0;
1206 }
1207
1208 static void
1209 mue_startup_rx_pipes(struct mue_softc *sc)
1210 {
1211 struct mue_chain *c;
1212 size_t i;
1213
1214 /* Start up the receive pipe. */
1215 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1216 c = &sc->mue_cdata.mue_rx_chain[i];
1217 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1218 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1219 usbd_transfer(c->mue_xfer);
1220 }
1221 }
1222
1223 static int
1224 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1225 {
1226 struct ifnet *ifp = GET_IFP(sc);
1227 struct mue_chain *c;
1228 usbd_status err;
1229 struct mue_txbuf_hdr hdr;
1230 uint32_t tx_cmd_a, tx_cmd_b;
1231 int csum, len, rv;
1232 bool tso, ipe, tpe;
1233
1234 csum = m->m_pkthdr.csum_flags;
1235 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
1236 ipe = csum & M_CSUM_IPv4;
1237 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
1238 M_CSUM_TCPv6 | M_CSUM_UDPv6);
1239
1240 len = m->m_pkthdr.len;
1241 if (__predict_false((!tso && len > (int)MUE_FRAME_LEN(ifp->if_mtu)) ||
1242 ( tso && len > MUE_TSO_FRAME_LEN))) {
1243 MUE_PRINTF(sc, "packet length %d\n too long", len);
1244 return EINVAL;
1245 }
1246
1247 c = &sc->mue_cdata.mue_tx_chain[idx];
1248
1249 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
1250 tx_cmd_a = len | MUE_TX_CMD_A_FCS;
1251
1252 if (tso) {
1253 tx_cmd_a |= MUE_TX_CMD_A_LSO;
1254 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1255 tx_cmd_b = m->m_pkthdr.segsz;
1256 else
1257 tx_cmd_b = MUE_TX_MSS_MIN;
1258 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
1259 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
1260 rv = mue_prepare_tso(sc, m);
1261 if (__predict_false(rv))
1262 return rv;
1263 } else {
1264 if (ipe)
1265 tx_cmd_a |= MUE_TX_CMD_A_IPE;
1266 if (tpe)
1267 tx_cmd_a |= MUE_TX_CMD_A_TPE;
1268 tx_cmd_b = 0;
1269 }
1270
1271 hdr.tx_cmd_a = htole32(tx_cmd_a);
1272 hdr.tx_cmd_b = htole32(tx_cmd_b);
1273
1274 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1275 m_copydata(m, 0, len, c->mue_buf + sizeof(hdr));
1276
1277 if (__predict_false(c->mue_xfer == NULL))
1278 return EIO; /* XXX plugged out or down */
1279
1280 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr),
1281 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1282
1283 /* Transmit */
1284 err = usbd_transfer(c->mue_xfer);
1285 if (__predict_false(err != USBD_IN_PROGRESS)) {
1286 MUE_PRINTF(sc, "%s\n", usbd_errstr(err));
1287 mue_stop(ifp, 0);
1288 return EIO;
1289 }
1290
1291 return 0;
1292 }
1293
1294 /*
1295 * L3 length field should be cleared.
1296 */
1297 static int
1298 mue_prepare_tso(struct mue_softc *sc, struct mbuf *m)
1299 {
1300 struct ether_header *eh;
1301 struct ip *ip;
1302 struct ip6_hdr *ip6;
1303 uint16_t type, len = 0;
1304 int off;
1305
1306 if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
1307 eh = mtod(m, struct ether_header *);
1308 type = eh->ether_type;
1309 } else
1310 m_copydata(m, offsetof(struct ether_header, ether_type),
1311 sizeof(type), &type);
1312 switch (type = htons(type)) {
1313 case ETHERTYPE_IP:
1314 case ETHERTYPE_IPV6:
1315 off = ETHER_HDR_LEN;
1316 break;
1317 case ETHERTYPE_VLAN:
1318 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1319 break;
1320 default:
1321 if (usbd_ratecheck(&sc->mue_tx_notice))
1322 MUE_PRINTF(sc, "dropping invalid frame "
1323 "type 0x%04hx csum_flags 0x%08x\n",
1324 type, m->m_pkthdr.csum_flags);
1325 return EINVAL;
1326 }
1327
1328 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1329 if (__predict_true(m->m_len >= off + (int)sizeof(*ip))) {
1330 ip = (void *)(mtod(m, char *) + off);
1331 ip->ip_len = 0;
1332 } else
1333 m_copyback(m, off + offsetof(struct ip, ip_len),
1334 sizeof(len), &len);
1335 } else {
1336 if (__predict_true(m->m_len >= off + (int)sizeof(*ip6))) {
1337 ip6 = (void *)(mtod(m, char *) + off);
1338 ip6->ip6_plen = 0;
1339 } else
1340 m_copyback(m, off + offsetof(struct ip6_hdr, ip6_plen),
1341 sizeof(len), &len);
1342 }
1343 return 0;
1344 }
1345
1346 static void
1347 mue_setmulti(struct mue_softc *sc)
1348 {
1349 struct ifnet *ifp = GET_IFP(sc);
1350 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1351 struct ether_multi *enm;
1352 struct ether_multistep step;
1353 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1354 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1355 uint32_t reg, rxfilt, h, hireg, loreg;
1356 size_t i;
1357
1358 if (sc->mue_dying)
1359 return;
1360
1361 /* Clear perfect filter and hash tables. */
1362 memset(pfiltbl, 0, sizeof(pfiltbl));
1363 memset(hashtbl, 0, sizeof(hashtbl));
1364
1365 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1366 rxfilt = mue_csr_read(sc, reg);
1367 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1368 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1369
1370 /* Always accept broadcast frames. */
1371 rxfilt |= MUE_RFE_CTL_BROADCAST;
1372
1373 if (ifp->if_flags & IFF_PROMISC) {
1374 rxfilt |= MUE_RFE_CTL_UNICAST;
1375 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1376 ifp->if_flags |= IFF_ALLMULTI;
1377 if (ifp->if_flags & IFF_PROMISC)
1378 DPRINTF(sc, "promisc\n");
1379 else
1380 DPRINTF(sc, "allmulti\n");
1381 } else {
1382 /* Now program new ones. */
1383 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1384 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1385 i = 1;
1386 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1387 while (enm != NULL) {
1388 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1389 ETHER_ADDR_LEN)) {
1390 memset(pfiltbl, 0, sizeof(pfiltbl));
1391 memset(hashtbl, 0, sizeof(hashtbl));
1392 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1393 goto allmulti;
1394 }
1395 if (i < MUE_NUM_ADDR_FILTX) {
1396 /* Use perfect address table if possible. */
1397 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1398 MUE_ADDR_FILTX_VALID;
1399 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1400 } else {
1401 /* Otherwise, use hash table. */
1402 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1403 h = (ether_crc32_be(enm->enm_addrlo,
1404 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1405 hashtbl[h / 32] |= 1 << (h % 32);
1406 }
1407 i++;
1408 ETHER_NEXT_MULTI(step, enm);
1409 }
1410 rxfilt |= MUE_RFE_CTL_PERFECT;
1411 ifp->if_flags &= ~IFF_ALLMULTI;
1412 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH)
1413 DPRINTF(sc, "perfect filter and hash tables\n");
1414 else
1415 DPRINTF(sc, "perfect filter\n");
1416 }
1417
1418 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1419 hireg = (sc->mue_flags & LAN7500) ?
1420 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1421 loreg = hireg + 4;
1422 mue_csr_write(sc, hireg, 0);
1423 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1424 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1425 }
1426
1427 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1428 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1429
1430 mue_csr_write(sc, reg, rxfilt);
1431 }
1432
1433 static void
1434 mue_sethwcsum(struct mue_softc *sc)
1435 {
1436 struct ifnet *ifp = GET_IFP(sc);
1437 uint32_t reg, val;
1438
1439 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1440 val = mue_csr_read(sc, reg);
1441
1442 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) {
1443 DPRINTF(sc, "RX IPv4 hwcsum enabled\n");
1444 val |= MUE_RFE_CTL_IP_COE;
1445 } else {
1446 DPRINTF(sc, "RX IPv4 hwcsum disabled\n");
1447 val &= ~MUE_RFE_CTL_IP_COE;
1448 }
1449
1450 if (ifp->if_capenable &
1451 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
1452 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) {
1453 DPRINTF(sc, "RX L4 hwcsum enabled\n");
1454 val |= MUE_RFE_CTL_TCPUDP_COE;
1455 } else {
1456 DPRINTF(sc, "RX L4 hwcsum disabled\n");
1457 val &= ~MUE_RFE_CTL_TCPUDP_COE;
1458 }
1459
1460 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1461
1462 mue_csr_write(sc, reg, val);
1463 }
1464
1465 static void
1466 mue_setmtu(struct mue_softc *sc)
1467 {
1468 struct ifnet *ifp = GET_IFP(sc);
1469 uint32_t val;
1470
1471 /* Set the maximum frame size. */
1472 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1473 val = mue_csr_read(sc, MUE_MAC_RX);
1474 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1475 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1476 mue_csr_write(sc, MUE_MAC_RX, val);
1477 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1478 }
1479
1480 static void
1481 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1482 {
1483 struct mue_chain *c = (struct mue_chain *)priv;
1484 struct mue_softc *sc = c->mue_sc;
1485 struct ifnet *ifp = GET_IFP(sc);
1486 struct mbuf *m;
1487 struct mue_rxbuf_hdr *hdrp;
1488 uint32_t rx_cmd_a, totlen;
1489 uint16_t pktlen;
1490 int s;
1491 int csum;
1492 char *buf = c->mue_buf;
1493 bool v6;
1494
1495 if (__predict_false(sc->mue_dying)) {
1496 DPRINTF(sc, "dying\n");
1497 return;
1498 }
1499
1500 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1501 DPRINTF(sc, "%s\n", usbd_errstr(status));
1502 if (status == USBD_INVAL)
1503 return; /* XXX plugged out or down */
1504 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1505 return;
1506 if (usbd_ratecheck(&sc->mue_rx_notice))
1507 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1508 if (status == USBD_STALLED)
1509 usbd_clear_endpoint_stall_async(
1510 sc->mue_ep[MUE_ENDPT_RX]);
1511 goto done;
1512 }
1513
1514 usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL);
1515
1516 KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u",
1517 totlen, sc->mue_rxbufsz);
1518
1519 do {
1520 if (__predict_false(totlen < sizeof(*hdrp))) {
1521 MUE_PRINTF(sc, "packet length %u too short\n", totlen);
1522 ifp->if_ierrors++;
1523 goto done;
1524 }
1525
1526 hdrp = (struct mue_rxbuf_hdr *)buf;
1527 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1528
1529 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1530 /*
1531 * We cannot use MUE_RX_CMD_A_RED bit here;
1532 * it is turned on in the cases of L3/L4
1533 * checksum errors which we handle below.
1534 */
1535 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1536 ifp->if_ierrors++;
1537 goto done;
1538 }
1539
1540 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1541 if (sc->mue_flags & LAN7500)
1542 pktlen -= 2;
1543
1544 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1545 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1546 pktlen + sizeof(*hdrp) > totlen)) {
1547 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1548 ifp->if_ierrors++;
1549 goto done;
1550 }
1551
1552 m = mue_newbuf();
1553 if (__predict_false(m == NULL)) {
1554 MUE_PRINTF(sc, "failed to allocate mbuf\n");
1555 ifp->if_ierrors++;
1556 goto done;
1557 }
1558
1559 m_set_rcvif(m, ifp);
1560 m->m_pkthdr.len = m->m_len = pktlen;
1561 m->m_flags |= M_HASFCS;
1562
1563 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1564 csum = 0;
1565 } else {
1566 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1567 switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1568 case MUE_RX_CMD_A_PID_TCP:
1569 csum = v6 ?
1570 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1571 break;
1572 case MUE_RX_CMD_A_PID_UDP:
1573 csum = v6 ?
1574 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1575 break;
1576 case MUE_RX_CMD_A_PID_IP:
1577 csum = v6 ? 0 : M_CSUM_IPv4;
1578 break;
1579 default:
1580 csum = 0;
1581 break;
1582 }
1583 csum &= ifp->if_csum_flags_rx;
1584 if (__predict_false((csum & M_CSUM_IPv4) &&
1585 (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1586 csum |= M_CSUM_IPv4_BAD;
1587 if (__predict_false((csum & ~M_CSUM_IPv4) &&
1588 (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1589 csum |= M_CSUM_TCP_UDP_BAD;
1590 }
1591 m->m_pkthdr.csum_flags = csum;
1592 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1593
1594 /* Attention: sizeof(hdr) = 10 */
1595 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1596 if (pktlen > totlen)
1597 pktlen = totlen;
1598 totlen -= pktlen;
1599 buf += pktlen;
1600
1601 s = splnet();
1602 if_percpuq_enqueue(ifp->if_percpuq, m);
1603 splx(s);
1604 } while (totlen > 0);
1605
1606 done:
1607 /* Setup new transfer. */
1608 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1609 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1610 usbd_transfer(xfer);
1611 }
1612
1613 static void
1614 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1615 {
1616 struct mue_chain *c = priv;
1617 struct mue_softc *sc = c->mue_sc;
1618 struct mue_cdata *cd = &sc->mue_cdata;
1619 struct ifnet *ifp = GET_IFP(sc);
1620 int s;
1621
1622 if (__predict_false(sc->mue_dying))
1623 return;
1624
1625 s = splnet();
1626 KASSERT(cd->mue_tx_cnt > 0);
1627 cd->mue_tx_cnt--;
1628 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1629 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1630 splx(s);
1631 return;
1632 }
1633 ifp->if_oerrors++;
1634 if (usbd_ratecheck(&sc->mue_tx_notice))
1635 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1636 if (status == USBD_STALLED)
1637 usbd_clear_endpoint_stall_async(
1638 sc->mue_ep[MUE_ENDPT_TX]);
1639 splx(s);
1640 return;
1641 }
1642
1643 ifp->if_timer = 0;
1644 ifp->if_flags &= ~IFF_OACTIVE;
1645
1646 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1647 mue_start(ifp);
1648
1649 ifp->if_opackets++;
1650 splx(s);
1651 }
1652
1653 static int
1654 mue_init(struct ifnet *ifp)
1655 {
1656 struct mue_softc *sc = ifp->if_softc;
1657 int s;
1658
1659 if (sc->mue_dying) {
1660 DPRINTF(sc, "dying\n");
1661 return EIO;
1662 }
1663
1664 s = splnet();
1665
1666 /* Cancel pending I/O and free all TX/RX buffers. */
1667 if (ifp->if_flags & IFF_RUNNING)
1668 mue_stop(ifp, 1);
1669
1670 mue_reset(sc);
1671
1672 /* Set MAC address. */
1673 mue_set_macaddr(sc);
1674
1675 /* Load the multicast filter. */
1676 mue_setmulti(sc);
1677
1678 /* TCP/UDP checksum offload engines. */
1679 mue_sethwcsum(sc);
1680
1681 /* Set MTU. */
1682 mue_setmtu(sc);
1683
1684 if (mue_open_pipes(sc)) {
1685 splx(s);
1686 return EIO;
1687 }
1688
1689 /* Init RX ring. */
1690 if (mue_rx_list_init(sc)) {
1691 MUE_PRINTF(sc, "failed to init rx list\n");
1692 splx(s);
1693 return ENOBUFS;
1694 }
1695
1696 /* Init TX ring. */
1697 if (mue_tx_list_init(sc)) {
1698 MUE_PRINTF(sc, "failed to init tx list\n");
1699 splx(s);
1700 return ENOBUFS;
1701 }
1702
1703 mue_startup_rx_pipes(sc);
1704
1705 ifp->if_flags |= IFF_RUNNING;
1706 ifp->if_flags &= ~IFF_OACTIVE;
1707
1708 splx(s);
1709
1710 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1711
1712 return 0;
1713 }
1714
1715 static int
1716 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1717 {
1718 struct mue_softc *sc = ifp->if_softc;
1719 int s, error = 0;
1720
1721 s = splnet();
1722
1723 switch (cmd) {
1724 case SIOCSIFFLAGS:
1725 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1726 break;
1727
1728 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1729 case IFF_RUNNING:
1730 mue_stop(ifp, 1);
1731 break;
1732 case IFF_UP:
1733 mue_init(ifp);
1734 break;
1735 case IFF_UP | IFF_RUNNING:
1736 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1737 mue_setmulti(sc);
1738 else
1739 mue_init(ifp);
1740 break;
1741 }
1742 sc->mue_if_flags = ifp->if_flags;
1743 break;
1744 default:
1745 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1746 break;
1747 error = 0;
1748 switch (cmd) {
1749 case SIOCADDMULTI:
1750 case SIOCDELMULTI:
1751 mue_setmulti(sc);
1752 break;
1753 case SIOCSIFCAP:
1754 mue_sethwcsum(sc);
1755 break;
1756 case SIOCSIFMTU:
1757 mue_setmtu(sc);
1758 break;
1759 default:
1760 break;
1761 }
1762 break;
1763 }
1764 splx(s);
1765
1766 return error;
1767 }
1768
1769 static void
1770 mue_watchdog(struct ifnet *ifp)
1771 {
1772 struct mue_softc *sc = ifp->if_softc;
1773 struct mue_chain *c;
1774 usbd_status stat;
1775 int s;
1776
1777 ifp->if_oerrors++;
1778 MUE_PRINTF(sc, "timed out\n");
1779
1780 s = splusb();
1781 c = &sc->mue_cdata.mue_tx_chain[0];
1782 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1783 mue_txeof(c->mue_xfer, c, stat);
1784
1785 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1786 mue_start(ifp);
1787 splx(s);
1788 }
1789
1790 static void
1791 mue_reset(struct mue_softc *sc)
1792 {
1793 if (sc->mue_dying)
1794 return;
1795
1796 /* Wait a little while for the chip to get its brains in order. */
1797 usbd_delay_ms(sc->mue_udev, 1);
1798
1799 // mue_chip_init(sc); /* XXX */
1800 }
1801
1802 static void
1803 mue_start(struct ifnet *ifp)
1804 {
1805 struct mue_softc *sc = ifp->if_softc;
1806 struct mbuf *m;
1807 struct mue_cdata *cd = &sc->mue_cdata;
1808 int idx;
1809
1810 if (__predict_false(!sc->mue_link)) {
1811 DPRINTF(sc, "no link\n");
1812 return;
1813 }
1814
1815 if (__predict_false((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING))
1816 != IFF_RUNNING)) {
1817 DPRINTF(sc, "not ready\n");
1818 return;
1819 }
1820
1821 idx = cd->mue_tx_prod;
1822 while (cd->mue_tx_cnt < (int)sc->mue_tx_list_cnt) {
1823 IFQ_POLL(&ifp->if_snd, m);
1824 if (m == NULL)
1825 break;
1826
1827 if (__predict_false(mue_encap(sc, m, idx))) {
1828 ifp->if_oerrors++;
1829 break;
1830 }
1831 IFQ_DEQUEUE(&ifp->if_snd, m);
1832
1833 bpf_mtap(ifp, m, BPF_D_OUT);
1834 m_freem(m);
1835
1836 idx = (idx + 1) % sc->mue_tx_list_cnt;
1837 cd->mue_tx_cnt++;
1838
1839 }
1840 cd->mue_tx_prod = idx;
1841
1842 if (cd->mue_tx_cnt >= (int)sc->mue_tx_list_cnt)
1843 ifp->if_flags |= IFF_OACTIVE;
1844
1845 /* Set a timeout in case the chip goes out to lunch. */
1846 ifp->if_timer = 5;
1847 }
1848
1849 static void
1850 mue_stop(struct ifnet *ifp, int disable __unused)
1851 {
1852 struct mue_softc *sc = ifp->if_softc;
1853 struct mue_chain *c;
1854 usbd_status err;
1855 size_t i;
1856
1857 mue_reset(sc);
1858
1859 ifp->if_timer = 0;
1860 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1861
1862 callout_stop(&sc->mue_stat_ch);
1863 sc->mue_link = 0;
1864
1865 /* Stop transfers. */
1866 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1867 if (sc->mue_ep[i] != NULL) {
1868 err = usbd_abort_pipe(sc->mue_ep[i]);
1869 if (err)
1870 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1871 i, usbd_errstr(err));
1872 }
1873
1874 /* Free RX resources. */
1875 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1876 c = &sc->mue_cdata.mue_rx_chain[i];
1877 if (c->mue_xfer != NULL) {
1878 usbd_destroy_xfer(c->mue_xfer);
1879 c->mue_xfer = NULL;
1880 }
1881 }
1882
1883 /* Free TX resources. */
1884 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1885 c = &sc->mue_cdata.mue_tx_chain[i];
1886 if (c->mue_xfer != NULL) {
1887 usbd_destroy_xfer(c->mue_xfer);
1888 c->mue_xfer = NULL;
1889 }
1890 }
1891
1892 /* Close pipes */
1893 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1894 if (sc->mue_ep[i] != NULL) {
1895 err = usbd_close_pipe(sc->mue_ep[i]);
1896 if (err)
1897 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1898 i, usbd_errstr(err));
1899 sc->mue_ep[i] = NULL;
1900 }
1901
1902 DPRINTF(sc, "done\n");
1903 }
1904
1905 static void
1906 mue_tick(void *xsc)
1907 {
1908 struct mue_softc *sc = xsc;
1909
1910 if (sc == NULL)
1911 return;
1912
1913 if (sc->mue_dying)
1914 return;
1915
1916 /* Perform periodic stuff in process context. */
1917 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1918 }
1919
1920 static void
1921 mue_tick_task(void *xsc)
1922 {
1923 struct mue_softc *sc = xsc;
1924 struct ifnet *ifp;
1925 struct mii_data *mii;
1926 int s;
1927
1928 if (sc == NULL)
1929 return;
1930
1931 if (sc->mue_dying)
1932 return;
1933
1934 ifp = GET_IFP(sc);
1935 mii = GET_MII(sc);
1936
1937 s = splnet();
1938 mii_tick(mii);
1939 if (sc->mue_link == 0)
1940 mue_miibus_statchg(ifp);
1941 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1942 splx(s);
1943 }
1944
1945 static struct mbuf *
1946 mue_newbuf(void)
1947 {
1948 struct mbuf *m;
1949
1950 MGETHDR(m, M_DONTWAIT, MT_DATA);
1951 if (__predict_false(m == NULL))
1952 return NULL;
1953
1954 MCLGET(m, M_DONTWAIT);
1955 if (__predict_false(!(m->m_flags & M_EXT))) {
1956 m_freem(m);
1957 return NULL;
1958 }
1959
1960 m_adj(m, ETHER_ALIGN);
1961
1962 return m;
1963 }
1964