if_mue.c revision 1.46 1 /* $NetBSD: if_mue.c,v 1.46 2019/05/26 04:52:07 mlelstv Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.46 2019/05/26 04:52:07 mlelstv Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/mutex.h>
36 #include <sys/kernel.h>
37 #include <sys/proc.h>
38 #include <sys/socket.h>
39
40 #include <sys/device.h>
41
42 #include <sys/rndsource.h>
43
44 #include <net/if.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_ether.h>
48
49 #include <net/bpf.h>
50
51 #include <netinet/if_inarp.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h> /* XXX for struct ip */
54 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
55
56 #include <dev/mii/mii.h>
57 #include <dev/mii/miivar.h>
58
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
61 #include <dev/usb/usbdi_util.h>
62 #include <dev/usb/usbdivar.h>
63 #include <dev/usb/usbdevs.h>
64
65 #include <dev/usb/if_muereg.h>
66 #include <dev/usb/if_muevar.h>
67
68 #define MUE_PRINTF(sc, fmt, args...) \
69 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
70
71 #ifdef USB_DEBUG
72 int muedebug = 0;
73 #define DPRINTF(sc, fmt, args...) \
74 do { \
75 if (muedebug) \
76 MUE_PRINTF(sc, fmt, ##args); \
77 } while (0 /* CONSTCOND */)
78 #else
79 #define DPRINTF(sc, fmt, args...) __nothing
80 #endif
81
82 /*
83 * Various supported device vendors/products.
84 */
85 struct mue_type {
86 struct usb_devno mue_dev;
87 uint16_t mue_flags;
88 #define LAN7500 0x0001 /* LAN7500 */
89 };
90
91 const struct mue_type mue_devs[] = {
92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
97 };
98
99 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
100 uaa->uaa_vendor, uaa->uaa_product))
101
102 #define MUE_ENADDR_LO(enaddr) \
103 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
104 #define MUE_ENADDR_HI(enaddr) \
105 ((enaddr[5] << 8) | enaddr[4])
106
107 static int mue_match(device_t, cfdata_t, void *);
108 static void mue_attach(device_t, device_t, void *);
109 static int mue_detach(device_t, int);
110 static int mue_activate(device_t, enum devact);
111
112 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
113 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
114 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
115 uint32_t, uint32_t);
116
117 static void mue_lock_mii(struct mue_softc *);
118 static void mue_unlock_mii(struct mue_softc *);
119
120 static int mue_miibus_readreg(device_t, int, int, uint16_t *);
121 static int mue_miibus_writereg(device_t, int, int, uint16_t);
122 static void mue_miibus_statchg(struct ifnet *);
123 static int mue_ifmedia_upd(struct ifnet *);
124 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
125
126 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
127 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
128 static bool mue_eeprom_present(struct mue_softc *sc);
129
130 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
131 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
132
133 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
134 uint32_t, uint32_t *);
135
136 static void mue_init_ltm(struct mue_softc *);
137
138 static int mue_chip_init(struct mue_softc *);
139
140 static void mue_set_macaddr(struct mue_softc *);
141 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
142
143 static int mue_rx_list_init(struct mue_softc *);
144 static int mue_tx_list_init(struct mue_softc *);
145 static int mue_open_pipes(struct mue_softc *);
146 static void mue_startup_rx_pipes(struct mue_softc *);
147
148 static int mue_encap(struct mue_softc *, struct mbuf *, int);
149 static int mue_prepare_tso(struct mue_softc *, struct mbuf *);
150
151 static void mue_setmulti(struct mue_softc *);
152 static void mue_sethwcsum(struct mue_softc *);
153 static void mue_setmtu(struct mue_softc *);
154
155 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
156 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
157
158 static int mue_init(struct ifnet *);
159 static int mue_ioctl(struct ifnet *, u_long, void *);
160 static void mue_watchdog(struct ifnet *);
161 static void mue_reset(struct mue_softc *);
162 static void mue_start(struct ifnet *);
163 static void mue_stop(struct ifnet *, int);
164 static void mue_tick(void *);
165 static void mue_tick_task(void *);
166
167 static struct mbuf *mue_newbuf(void);
168
169 #define MUE_SETBIT(sc, reg, x) \
170 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
171
172 #define MUE_CLRBIT(sc, reg, x) \
173 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
174
175 #define MUE_WAIT_SET(sc, reg, set, fail) \
176 mue_wait_for_bits(sc, reg, set, ~0, fail)
177
178 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
179 mue_wait_for_bits(sc, reg, 0, clear, fail)
180
181 #define ETHER_IS_VALID(addr) \
182 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
183
184 #define ETHER_IS_ZERO(addr) \
185 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
186
187 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
188 mue_detach, mue_activate);
189
190 static uint32_t
191 mue_csr_read(struct mue_softc *sc, uint32_t reg)
192 {
193 usb_device_request_t req;
194 usbd_status err;
195 uDWord val;
196
197 if (sc->mue_dying)
198 return 0;
199
200 USETDW(val, 0);
201 req.bmRequestType = UT_READ_VENDOR_DEVICE;
202 req.bRequest = MUE_UR_READREG;
203 USETW(req.wValue, 0);
204 USETW(req.wIndex, reg);
205 USETW(req.wLength, 4);
206
207 err = usbd_do_request(sc->mue_udev, &req, &val);
208 if (err) {
209 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
210 return 0;
211 }
212
213 return UGETDW(val);
214 }
215
216 static int
217 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
218 {
219 usb_device_request_t req;
220 usbd_status err;
221 uDWord val;
222
223 if (sc->mue_dying)
224 return 0;
225
226 USETDW(val, aval);
227 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
228 req.bRequest = MUE_UR_WRITEREG;
229 USETW(req.wValue, 0);
230 USETW(req.wIndex, reg);
231 USETW(req.wLength, 4);
232
233 err = usbd_do_request(sc->mue_udev, &req, &val);
234 if (err) {
235 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
236 return -1;
237 }
238
239 return 0;
240 }
241
242 static int
243 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
244 uint32_t set, uint32_t clear, uint32_t fail)
245 {
246 uint32_t val;
247 int ntries;
248
249 for (ntries = 0; ntries < 1000; ntries++) {
250 val = mue_csr_read(sc, reg);
251 if ((val & set) || !(val & clear))
252 return 0;
253 if (val & fail)
254 return 1;
255 usbd_delay_ms(sc->mue_udev, 1);
256 }
257
258 return 1;
259 }
260
261 /*
262 * Get exclusive access to the MII registers.
263 */
264 static void
265 mue_lock_mii(struct mue_softc *sc)
266 {
267 sc->mue_refcnt++;
268 mutex_enter(&sc->mue_mii_lock);
269 }
270
271 static void
272 mue_unlock_mii(struct mue_softc *sc)
273 {
274 mutex_exit(&sc->mue_mii_lock);
275 if (--sc->mue_refcnt < 0)
276 usb_detach_wakeupold(sc->mue_dev);
277 }
278
279 static int
280 mue_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
281 {
282 struct mue_softc *sc = device_private(dev);
283 uint32_t data;
284 int rv = 0;
285
286 if (sc->mue_dying) {
287 DPRINTF(sc, "dying\n");
288 return -1;
289 }
290
291 if (sc->mue_phyno != phy)
292 return -1;
293
294 mue_lock_mii(sc);
295 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
296 mue_unlock_mii(sc);
297 MUE_PRINTF(sc, "not ready\n");
298 return -1;
299 }
300
301 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
302 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
303 MUE_MII_ACCESS_PHYADDR(phy));
304
305 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
306 MUE_PRINTF(sc, "timed out\n");
307 rv = ETIMEDOUT;
308 goto out;
309 }
310
311 data = mue_csr_read(sc, MUE_MII_DATA);
312 *val = data & 0xffff;
313
314 out:
315 mue_unlock_mii(sc);
316 return rv;
317 }
318
319 static int
320 mue_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
321 {
322 struct mue_softc *sc = device_private(dev);
323 int rv = 0;
324
325 if (sc->mue_dying) {
326 DPRINTF(sc, "dying\n");
327 return -1;
328 }
329
330 if (sc->mue_phyno != phy) {
331 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
332 sc->mue_phyno, phy);
333 return -1;
334 }
335
336 mue_lock_mii(sc);
337 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
338 MUE_PRINTF(sc, "not ready\n");
339 rv = EBUSY;
340 goto out;
341 }
342
343 mue_csr_write(sc, MUE_MII_DATA, val);
344 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
345 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
346 MUE_MII_ACCESS_PHYADDR(phy));
347
348 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
349 MUE_PRINTF(sc, "timed out\n");
350 rv = ETIMEDOUT;
351 }
352 out:
353 mue_unlock_mii(sc);
354 return rv;
355 }
356
357 static void
358 mue_miibus_statchg(struct ifnet *ifp)
359 {
360 struct mue_softc *sc;
361 struct mii_data *mii;
362 uint32_t flow, threshold;
363
364 if (ifp == NULL) {
365 printf("%s: ifp not ready\n", __func__);
366 return;
367 }
368
369 sc = ifp->if_softc;
370 mii = GET_MII(sc);
371
372 if ((ifp->if_flags & IFF_RUNNING) == 0) {
373 DPRINTF(sc, "not running\n");
374 return;
375 }
376
377 if (mii == NULL) {
378 DPRINTF(sc, "mii not ready\n");
379 return;
380 }
381
382 sc->mue_link = 0;
383 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
384 (IFM_ACTIVE | IFM_AVALID)) {
385 switch (IFM_SUBTYPE(mii->mii_media_active)) {
386 case IFM_10_T:
387 case IFM_100_TX:
388 case IFM_1000_T:
389 sc->mue_link++;
390 break;
391 default:
392 break;
393 }
394 }
395
396 /* Lost link, do nothing. */
397 if (sc->mue_link == 0) {
398 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
399 return;
400 }
401
402 if (!(sc->mue_flags & LAN7500)) {
403 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
404 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
405 /* Disable U2 and enable U1. */
406 MUE_CLRBIT(sc, MUE_USB_CFG1,
407 MUE_USB_CFG1_DEV_U2_INIT_EN);
408 MUE_SETBIT(sc, MUE_USB_CFG1,
409 MUE_USB_CFG1_DEV_U1_INIT_EN);
410 } else {
411 /* Enable U1 and U2. */
412 MUE_SETBIT(sc, MUE_USB_CFG1,
413 MUE_USB_CFG1_DEV_U1_INIT_EN |
414 MUE_USB_CFG1_DEV_U2_INIT_EN);
415 }
416 }
417 }
418
419 flow = 0;
420 /* XXX Linux does not check IFM_FDX flag for 7800. */
421 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
422 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
423 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
424 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
425 flow |= MUE_FLOW_RX_FCEN;
426 }
427
428 /* XXX Magic numbers taken from Linux driver. */
429 if (sc->mue_flags & LAN7500)
430 threshold = 0x820;
431 else
432 switch (sc->mue_udev->ud_speed) {
433 case USB_SPEED_SUPER:
434 threshold = 0x817;
435 break;
436 case USB_SPEED_HIGH:
437 threshold = 0x211;
438 break;
439 default:
440 threshold = 0;
441 break;
442 }
443
444 /* Threshold value should be set before enabling flow. */
445 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
446 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
447 mue_csr_write(sc, MUE_FLOW, flow);
448
449 DPRINTF(sc, "done\n");
450 }
451
452 /*
453 * Set media options.
454 */
455 static int
456 mue_ifmedia_upd(struct ifnet *ifp)
457 {
458 struct mue_softc *sc = ifp->if_softc;
459 struct mii_data *mii = GET_MII(sc);
460
461 sc->mue_link = 0; /* XXX */
462
463 if (mii->mii_instance) {
464 struct mii_softc *miisc;
465 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
466 mii_phy_reset(miisc);
467 }
468 return mii_mediachg(mii);
469 }
470
471 /*
472 * Report current media status.
473 */
474 static void
475 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
476 {
477 struct mue_softc *sc = ifp->if_softc;
478 struct mii_data *mii = GET_MII(sc);
479
480 mii_pollstat(mii);
481 ifmr->ifm_active = mii->mii_media_active;
482 ifmr->ifm_status = mii->mii_media_status;
483 }
484
485 static uint8_t
486 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
487 {
488 uint32_t val;
489
490 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
491 MUE_PRINTF(sc, "not ready\n");
492 return ETIMEDOUT;
493 }
494
495 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
496 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
497 off);
498
499 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
500 MUE_E2P_CMD_TIMEOUT)) {
501 MUE_PRINTF(sc, "timed out\n");
502 return ETIMEDOUT;
503 }
504
505 val = mue_csr_read(sc, MUE_E2P_DATA);
506 *dest = val & 0xff;
507
508 return 0;
509 }
510
511 static int
512 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
513 {
514 uint32_t val = 0; /* XXX gcc */
515 uint8_t byte;
516 int i, err = 0;
517
518 /*
519 * EEPROM pins are muxed with the LED function on LAN7800 device.
520 */
521 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
522 val = mue_csr_read(sc, MUE_HW_CFG);
523 mue_csr_write(sc, MUE_HW_CFG,
524 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
525 }
526
527 for (i = 0; i < cnt; i++) {
528 err = mue_eeprom_getbyte(sc, off + i, &byte);
529 if (err)
530 break;
531 *(dest + i) = byte;
532 }
533
534 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
535 mue_csr_write(sc, MUE_HW_CFG, val);
536
537 return err ? 1 : 0;
538 }
539
540 static bool
541 mue_eeprom_present(struct mue_softc *sc)
542 {
543 uint32_t val;
544 uint8_t sig;
545 int ret;
546
547 if (sc->mue_flags & LAN7500) {
548 val = mue_csr_read(sc, MUE_E2P_CMD);
549 return val & MUE_E2P_CMD_LOADED;
550 } else {
551 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
552 return (ret == 0) && (sig == MUE_E2P_IND);
553 }
554 }
555
556 static int
557 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
558 {
559 uint32_t val;
560 int i, err;
561
562 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
563
564 /* Checking if bit is set. */
565 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
566 /* Clear it, then wait for it to be cleared. */
567 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
568 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
569 0);
570 if (err) {
571 MUE_PRINTF(sc, "not ready\n");
572 return 1;
573 }
574 }
575
576 /* Start reading the bytes, one at a time. */
577 for (i = 0; i < cnt; i++) {
578 mue_csr_write(sc, MUE_OTP_ADDR1,
579 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
580 mue_csr_write(sc, MUE_OTP_ADDR2,
581 ((off + i) & MUE_OTP_ADDR2_MASK));
582 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
583 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
584
585 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
586 if (err) {
587 MUE_PRINTF(sc, "timed out\n");
588 return 1;
589 }
590 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
591 *(dest + i) = (uint8_t)(val & 0xff);
592 }
593
594 return 0;
595 }
596
597 static int
598 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
599 {
600 uint8_t sig;
601 int err;
602
603 if (sc->mue_flags & LAN7500)
604 return 1;
605
606 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
607 if (err)
608 return 1;
609 switch (sig) {
610 case MUE_OTP_IND_1:
611 break;
612 case MUE_OTP_IND_2:
613 off += 0x100;
614 break;
615 default:
616 DPRINTF(sc, "OTP not found\n");
617 return 1;
618 }
619 err = mue_read_otp_raw(sc, dest, off, cnt);
620 return err;
621 }
622
623 static void
624 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
625 uint32_t cnt, uint32_t *data)
626 {
627 uint32_t i;
628
629 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
630 MUE_PRINTF(sc, "not ready\n");
631 return;
632 }
633
634 mue_csr_write(sc, MUE_DP_SEL,
635 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
636
637 for (i = 0; i < cnt; i++) {
638 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
639 mue_csr_write(sc, MUE_DP_DATA, data[i]);
640 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
641 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
642 MUE_PRINTF(sc, "timed out\n");
643 return;
644 }
645 }
646 }
647
648 static void
649 mue_init_ltm(struct mue_softc *sc)
650 {
651 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
652 uint8_t temp[2];
653 size_t i;
654
655 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
656 if (mue_eeprom_present(sc) &&
657 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
658 if (temp[0] != sizeof(idx)) {
659 DPRINTF(sc, "EEPROM: unexpected size\n");
660 goto done;
661 }
662 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
663 sizeof(idx))) {
664 DPRINTF(sc, "EEPROM: failed to read\n");
665 goto done;
666 }
667 DPRINTF(sc, "success\n");
668 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
669 if (temp[0] != sizeof(idx)) {
670 DPRINTF(sc, "OTP: unexpected size\n");
671 goto done;
672 }
673 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
674 sizeof(idx))) {
675 DPRINTF(sc, "OTP: failed to read\n");
676 goto done;
677 }
678 DPRINTF(sc, "success\n");
679 } else
680 DPRINTF(sc, "nothing to do\n");
681 } else
682 DPRINTF(sc, "nothing to do\n");
683 done:
684 for (i = 0; i < __arraycount(idx); i++)
685 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
686 }
687
688 static int
689 mue_chip_init(struct mue_softc *sc)
690 {
691 uint32_t val;
692
693 if ((sc->mue_flags & LAN7500) &&
694 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
695 MUE_PRINTF(sc, "not ready\n");
696 return ETIMEDOUT;
697 }
698
699 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
700 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
701 MUE_PRINTF(sc, "timed out\n");
702 return ETIMEDOUT;
703 }
704
705 /* Respond to the IN token with a NAK. */
706 if (sc->mue_flags & LAN7500)
707 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
708 else
709 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
710
711 if (sc->mue_flags & LAN7500) {
712 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
713 val = MUE_7500_HS_RX_BUFSIZE /
714 MUE_HS_USB_PKT_SIZE;
715 else
716 val = MUE_7500_FS_RX_BUFSIZE /
717 MUE_FS_USB_PKT_SIZE;
718 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
719 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
720 MUE_7500_DEFAULT_BULKIN_DELAY);
721
722 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
723
724 /* Set FIFO sizes. */
725 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
726 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
727 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
728 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
729 } else {
730 /* Init LTM. */
731 mue_init_ltm(sc);
732
733 val = MUE_7800_RX_BUFSIZE;
734 switch (sc->mue_udev->ud_speed) {
735 case USB_SPEED_SUPER:
736 val /= MUE_SS_USB_PKT_SIZE;
737 break;
738 case USB_SPEED_HIGH:
739 val /= MUE_HS_USB_PKT_SIZE;
740 break;
741 default:
742 val /= MUE_FS_USB_PKT_SIZE;
743 break;
744 }
745 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
746 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
747 MUE_7800_DEFAULT_BULKIN_DELAY);
748
749 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
750 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
751
752 /*
753 * Set FCL's RX and TX FIFO sizes: according to data sheet this
754 * is already the default value. But we initialize it to the
755 * same value anyways, as that's what the Linux driver does.
756 */
757 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
758 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
759 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
760 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
761 }
762
763 /* Enabling interrupts. */
764 mue_csr_write(sc, MUE_INT_STATUS, ~0);
765
766 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
767 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
768 mue_csr_write(sc, MUE_FLOW, 0);
769
770 /* Reset PHY. */
771 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
772 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
773 MUE_PRINTF(sc, "PHY not ready\n");
774 return ETIMEDOUT;
775 }
776
777 /* LAN7801 only has RGMII mode. */
778 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
779 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
780
781 if ((sc->mue_flags & LAN7500) ||
782 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
783 !mue_eeprom_present(sc))) {
784 /* Allow MAC to detect speed and duplex from PHY. */
785 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
786 MUE_MAC_CR_AUTO_DUPLEX);
787 }
788
789 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
790 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
791 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
792
793 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
794 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
795
796 /* Set default GPIO/LED settings only if no EEPROM is detected. */
797 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
798 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
799 MUE_SETBIT(sc, MUE_LED_CFG,
800 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
801 }
802
803 /* XXX We assume two LEDs at least when EEPROM is missing. */
804 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
805 !mue_eeprom_present(sc))
806 MUE_SETBIT(sc, MUE_HW_CFG,
807 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
808
809 return 0;
810 }
811
812 static void
813 mue_set_macaddr(struct mue_softc *sc)
814 {
815 struct ifnet *ifp = GET_IFP(sc);
816 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
817 uint32_t lo, hi;
818
819 lo = MUE_ENADDR_LO(enaddr);
820 hi = MUE_ENADDR_HI(enaddr);
821
822 mue_csr_write(sc, MUE_RX_ADDRL, lo);
823 mue_csr_write(sc, MUE_RX_ADDRH, hi);
824 }
825
826 static int
827 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
828 {
829 prop_data_t eaprop;
830 uint32_t low, high;
831
832 if (!(sc->mue_flags & LAN7500)) {
833 low = mue_csr_read(sc, MUE_RX_ADDRL);
834 high = mue_csr_read(sc, MUE_RX_ADDRH);
835 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
836 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
837 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
838 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
839 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
840 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
841 if (ETHER_IS_VALID(sc->mue_enaddr))
842 return 0;
843 else
844 DPRINTF(sc, "registers: %s\n",
845 ether_sprintf(sc->mue_enaddr));
846 }
847
848 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
849 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
850 if (ETHER_IS_VALID(sc->mue_enaddr))
851 return 0;
852 else
853 DPRINTF(sc, "EEPROM: %s\n",
854 ether_sprintf(sc->mue_enaddr));
855 }
856
857 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
858 ETHER_ADDR_LEN) == 0) {
859 if (ETHER_IS_VALID(sc->mue_enaddr))
860 return 0;
861 else
862 DPRINTF(sc, "OTP: %s\n",
863 ether_sprintf(sc->mue_enaddr));
864 }
865
866 /*
867 * Other MD methods. This should be tried only if other methods fail.
868 * Otherwise, MAC address for internal device can be assinged to
869 * external devices on Raspberry Pi, for example.
870 */
871 eaprop = prop_dictionary_get(dict, "mac-address");
872 if (eaprop != NULL) {
873 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
874 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
875 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
876 ETHER_ADDR_LEN);
877 if (ETHER_IS_VALID(sc->mue_enaddr))
878 return 0;
879 else
880 DPRINTF(sc, "prop_dictionary_get: %s\n",
881 ether_sprintf(sc->mue_enaddr));
882 }
883
884 return 1;
885 }
886
887
888 /*
889 * Probe for a Microchip chip.
890 */
891 static int
892 mue_match(device_t parent, cfdata_t match, void *aux)
893 {
894 struct usb_attach_arg *uaa = aux;
895
896 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
897 }
898
899 static void
900 mue_attach(device_t parent, device_t self, void *aux)
901 {
902 struct mue_softc *sc = device_private(self);
903 prop_dictionary_t dict = device_properties(self);
904 struct usb_attach_arg *uaa = aux;
905 struct usbd_device *dev = uaa->uaa_device;
906 usb_interface_descriptor_t *id;
907 usb_endpoint_descriptor_t *ed;
908 char *devinfop;
909 struct mii_data *mii;
910 struct ifnet *ifp;
911 usbd_status err;
912 const char *descr;
913 uint8_t i;
914 int s;
915
916 aprint_naive("\n");
917 aprint_normal("\n");
918
919 sc->mue_dev = self;
920 sc->mue_udev = dev;
921
922 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
923 aprint_normal_dev(self, "%s\n", devinfop);
924 usbd_devinfo_free(devinfop);
925
926 #define MUE_CONFIG_NO 1
927 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
928 if (err) {
929 aprint_error_dev(self, "failed to set configuration: %s\n",
930 usbd_errstr(err));
931 return;
932 }
933
934 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
935
936 #define MUE_IFACE_IDX 0
937 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
938 if (err) {
939 aprint_error_dev(self, "failed to get interface handle: %s\n",
940 usbd_errstr(err));
941 return;
942 }
943
944 sc->mue_product = uaa->uaa_product;
945 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
946
947 sc->mue_id_rev = mue_csr_read(sc, MUE_ID_REV);
948
949 /* Decide on what our bufsize will be. */
950 if (sc->mue_flags & LAN7500) {
951 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
952 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
953 sc->mue_rx_list_cnt = 1;
954 sc->mue_tx_list_cnt = 1;
955 } else {
956 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
957 sc->mue_rx_list_cnt = MUE_RX_LIST_CNT;
958 sc->mue_tx_list_cnt = MUE_TX_LIST_CNT;
959 }
960 sc->mue_txbufsz = MUE_TX_BUFSIZE;
961 mutex_init(&sc->mue_usb_lock, MUTEX_DEFAULT, IPL_NET);
962
963 /* Find endpoints. */
964 id = usbd_get_interface_descriptor(sc->mue_iface);
965 for (i = 0; i < id->bNumEndpoints; i++) {
966 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
967 if (ed == NULL) {
968 aprint_error_dev(self, "failed to get ep %hhd\n", i);
969 return;
970 }
971 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
972 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
973 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
974 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
975 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
976 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
977 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
978 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
979 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
980 }
981 }
982 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
983 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
984 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
985
986 s = splnet();
987
988 sc->mue_phyno = 1;
989
990 if (mue_chip_init(sc)) {
991 aprint_error_dev(self, "failed to initialize chip\n");
992 splx(s);
993 return;
994 }
995
996 /* A Microchip chip was detected. Inform the world. */
997 descr = (sc->mue_flags & LAN7500) ? "LAN7500" : "LAN7800";
998 aprint_normal_dev(self, "%s id 0x%x rev 0x%x\n", descr,
999 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_ID),
1000 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_REV));
1001
1002 if (mue_get_macaddr(sc, dict)) {
1003 aprint_error_dev(self, "failed to read MAC address\n");
1004 splx(s);
1005 return;
1006 }
1007
1008 aprint_normal_dev(self, "Ethernet address %s\n",
1009 ether_sprintf(sc->mue_enaddr));
1010
1011 /* Initialize interface info.*/
1012 ifp = GET_IFP(sc);
1013 ifp->if_softc = sc;
1014 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
1015 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1016 ifp->if_init = mue_init;
1017 ifp->if_ioctl = mue_ioctl;
1018 ifp->if_start = mue_start;
1019 ifp->if_stop = mue_stop;
1020 ifp->if_watchdog = mue_watchdog;
1021
1022 IFQ_SET_READY(&ifp->if_snd);
1023
1024 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
1025 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1026 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1027 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1028 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
1029 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
1030
1031 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1032 #if 0 /* XXX not yet */
1033 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
1034 #endif
1035
1036 /* Initialize MII/media info. */
1037 mii = GET_MII(sc);
1038 mii->mii_ifp = ifp;
1039 mii->mii_readreg = mue_miibus_readreg;
1040 mii->mii_writereg = mue_miibus_writereg;
1041 mii->mii_statchg = mue_miibus_statchg;
1042 mii->mii_flags = MIIF_AUTOTSLEEP;
1043
1044 sc->mue_ec.ec_mii = mii;
1045 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1046 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1047
1048 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1049 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1050 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1051 } else
1052 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1053
1054 /* Attach the interface. */
1055 if_attach(ifp);
1056 ether_ifattach(ifp, sc->mue_enaddr);
1057
1058 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1059 RND_TYPE_NET, RND_FLAG_DEFAULT);
1060
1061 callout_init(&sc->mue_stat_ch, 0);
1062
1063 splx(s);
1064
1065 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
1066
1067 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1068 }
1069
1070 static int
1071 mue_detach(device_t self, int flags)
1072 {
1073 struct mue_softc *sc = device_private(self);
1074 struct ifnet *ifp = GET_IFP(sc);
1075 size_t i;
1076 int s;
1077
1078 sc->mue_dying = true;
1079
1080 callout_halt(&sc->mue_stat_ch, NULL);
1081
1082 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1083 if (sc->mue_ep[i] != NULL)
1084 usbd_abort_pipe(sc->mue_ep[i]);
1085
1086 /*
1087 * Remove any pending tasks. They cannot be executing because they run
1088 * in the same thread as detach.
1089 */
1090 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1091 NULL);
1092
1093 s = splusb();
1094
1095 if (ifp->if_flags & IFF_RUNNING)
1096 mue_stop(ifp, 1);
1097
1098 callout_destroy(&sc->mue_stat_ch);
1099 rnd_detach_source(&sc->mue_rnd_source);
1100 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1101 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1102 if (ifp->if_softc != NULL) {
1103 ether_ifdetach(ifp);
1104 if_detach(ifp);
1105 }
1106
1107 if (--sc->mue_refcnt >= 0) {
1108 /* Wait for processes to go away. */
1109 usb_detach_waitold(sc->mue_dev);
1110 }
1111 splx(s);
1112
1113 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1114
1115 mutex_destroy(&sc->mue_mii_lock);
1116
1117 return 0;
1118 }
1119
1120 static int
1121 mue_activate(device_t self, enum devact act)
1122 {
1123 struct mue_softc *sc = device_private(self);
1124 struct ifnet *ifp = GET_IFP(sc);
1125
1126 switch (act) {
1127 case DVACT_DEACTIVATE:
1128 if_deactivate(ifp);
1129 sc->mue_dying = true;
1130 return 0;
1131 default:
1132 return EOPNOTSUPP;
1133 }
1134 return 0;
1135 }
1136
1137 static int
1138 mue_rx_list_init(struct mue_softc *sc)
1139 {
1140 struct mue_cdata *cd;
1141 struct mue_chain *c;
1142 size_t i;
1143 int err;
1144
1145 cd = &sc->mue_cdata;
1146 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1147 c = &cd->mue_rx_chain[i];
1148 c->mue_sc = sc;
1149 if (c->mue_xfer == NULL) {
1150 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1151 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1152 if (err)
1153 return err;
1154 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1155 }
1156 }
1157
1158 return 0;
1159 }
1160
1161 static int
1162 mue_tx_list_init(struct mue_softc *sc)
1163 {
1164 struct mue_cdata *cd;
1165 struct mue_chain *c;
1166 size_t i;
1167 int err;
1168
1169 cd = &sc->mue_cdata;
1170 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1171 c = &cd->mue_tx_chain[i];
1172 c->mue_sc = sc;
1173 if (c->mue_xfer == NULL) {
1174 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1175 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1176 &c->mue_xfer);
1177 if (err)
1178 return err;
1179 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1180 }
1181 }
1182
1183 cd->mue_tx_prod = 0;
1184 cd->mue_tx_cnt = 0;
1185
1186 return 0;
1187 }
1188
1189 static int
1190 mue_open_pipes(struct mue_softc *sc)
1191 {
1192 usbd_status err;
1193
1194 /* Open RX and TX pipes. */
1195 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1196 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1197 if (err) {
1198 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1199 return EIO;
1200 }
1201 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1202 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1203 if (err) {
1204 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1205 return EIO;
1206 }
1207 return 0;
1208 }
1209
1210 static void
1211 mue_startup_rx_pipes(struct mue_softc *sc)
1212 {
1213 struct mue_chain *c;
1214 size_t i;
1215
1216 /* Start up the receive pipe. */
1217 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1218 c = &sc->mue_cdata.mue_rx_chain[i];
1219 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1220 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1221 usbd_transfer(c->mue_xfer);
1222 }
1223 }
1224
1225 static int
1226 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1227 {
1228 struct ifnet *ifp = GET_IFP(sc);
1229 struct mue_chain *c;
1230 usbd_status err;
1231 struct mue_txbuf_hdr hdr;
1232 uint32_t tx_cmd_a, tx_cmd_b;
1233 int csum, len, rv;
1234 bool tso, ipe, tpe;
1235
1236 csum = m->m_pkthdr.csum_flags;
1237 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
1238 ipe = csum & M_CSUM_IPv4;
1239 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
1240 M_CSUM_TCPv6 | M_CSUM_UDPv6);
1241
1242 len = m->m_pkthdr.len;
1243 if (__predict_false((!tso && len > (int)MUE_FRAME_LEN(ifp->if_mtu)) ||
1244 ( tso && len > MUE_TSO_FRAME_LEN))) {
1245 MUE_PRINTF(sc, "packet length %d\n too long", len);
1246 return EINVAL;
1247 }
1248
1249 c = &sc->mue_cdata.mue_tx_chain[idx];
1250
1251 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
1252 tx_cmd_a = len | MUE_TX_CMD_A_FCS;
1253
1254 if (tso) {
1255 tx_cmd_a |= MUE_TX_CMD_A_LSO;
1256 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1257 tx_cmd_b = m->m_pkthdr.segsz;
1258 else
1259 tx_cmd_b = MUE_TX_MSS_MIN;
1260 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
1261 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
1262 rv = mue_prepare_tso(sc, m);
1263 if (__predict_false(rv))
1264 return rv;
1265 } else {
1266 if (ipe)
1267 tx_cmd_a |= MUE_TX_CMD_A_IPE;
1268 if (tpe)
1269 tx_cmd_a |= MUE_TX_CMD_A_TPE;
1270 tx_cmd_b = 0;
1271 }
1272
1273 hdr.tx_cmd_a = htole32(tx_cmd_a);
1274 hdr.tx_cmd_b = htole32(tx_cmd_b);
1275
1276 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1277 m_copydata(m, 0, len, c->mue_buf + sizeof(hdr));
1278
1279 if (__predict_false(c->mue_xfer == NULL))
1280 return EIO; /* XXX plugged out or down */
1281
1282 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr),
1283 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1284
1285 /* Transmit */
1286 err = usbd_transfer(c->mue_xfer);
1287 if (__predict_false(err != USBD_IN_PROGRESS)) {
1288 MUE_PRINTF(sc, "%s\n", usbd_errstr(err));
1289 mue_stop(ifp, 0);
1290 return EIO;
1291 }
1292
1293 return 0;
1294 }
1295
1296 /*
1297 * L3 length field should be cleared.
1298 */
1299 static int
1300 mue_prepare_tso(struct mue_softc *sc, struct mbuf *m)
1301 {
1302 struct ether_header *eh;
1303 struct ip *ip;
1304 struct ip6_hdr *ip6;
1305 uint16_t type, len = 0;
1306 int off;
1307
1308 if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
1309 eh = mtod(m, struct ether_header *);
1310 type = eh->ether_type;
1311 } else
1312 m_copydata(m, offsetof(struct ether_header, ether_type),
1313 sizeof(type), &type);
1314 switch (type = htons(type)) {
1315 case ETHERTYPE_IP:
1316 case ETHERTYPE_IPV6:
1317 off = ETHER_HDR_LEN;
1318 break;
1319 case ETHERTYPE_VLAN:
1320 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1321 break;
1322 default:
1323 if (usbd_ratecheck(&sc->mue_tx_notice))
1324 MUE_PRINTF(sc, "dropping invalid frame "
1325 "type 0x%04hx csum_flags 0x%08x\n",
1326 type, m->m_pkthdr.csum_flags);
1327 return EINVAL;
1328 }
1329
1330 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1331 if (__predict_true(m->m_len >= off + (int)sizeof(*ip))) {
1332 ip = (void *)(mtod(m, char *) + off);
1333 ip->ip_len = 0;
1334 } else
1335 m_copyback(m, off + offsetof(struct ip, ip_len),
1336 sizeof(len), &len);
1337 } else {
1338 if (__predict_true(m->m_len >= off + (int)sizeof(*ip6))) {
1339 ip6 = (void *)(mtod(m, char *) + off);
1340 ip6->ip6_plen = 0;
1341 } else
1342 m_copyback(m, off + offsetof(struct ip6_hdr, ip6_plen),
1343 sizeof(len), &len);
1344 }
1345 return 0;
1346 }
1347
1348 static void
1349 mue_setmulti(struct mue_softc *sc)
1350 {
1351 struct ifnet *ifp = GET_IFP(sc);
1352 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1353 struct ether_multi *enm;
1354 struct ether_multistep step;
1355 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1356 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1357 uint32_t reg, rxfilt, h, hireg, loreg;
1358 size_t i;
1359
1360 if (sc->mue_dying)
1361 return;
1362
1363 /* Clear perfect filter and hash tables. */
1364 memset(pfiltbl, 0, sizeof(pfiltbl));
1365 memset(hashtbl, 0, sizeof(hashtbl));
1366
1367 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1368 rxfilt = mue_csr_read(sc, reg);
1369 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1370 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1371
1372 /* Always accept broadcast frames. */
1373 rxfilt |= MUE_RFE_CTL_BROADCAST;
1374
1375 if (ifp->if_flags & IFF_PROMISC) {
1376 rxfilt |= MUE_RFE_CTL_UNICAST;
1377 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1378 ifp->if_flags |= IFF_ALLMULTI;
1379 if (ifp->if_flags & IFF_PROMISC)
1380 DPRINTF(sc, "promisc\n");
1381 else
1382 DPRINTF(sc, "allmulti\n");
1383 } else {
1384 /* Now program new ones. */
1385 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1386 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1387 i = 1;
1388 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1389 while (enm != NULL) {
1390 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1391 ETHER_ADDR_LEN)) {
1392 memset(pfiltbl, 0, sizeof(pfiltbl));
1393 memset(hashtbl, 0, sizeof(hashtbl));
1394 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1395 goto allmulti;
1396 }
1397 if (i < MUE_NUM_ADDR_FILTX) {
1398 /* Use perfect address table if possible. */
1399 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1400 MUE_ADDR_FILTX_VALID;
1401 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1402 } else {
1403 /* Otherwise, use hash table. */
1404 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1405 h = (ether_crc32_be(enm->enm_addrlo,
1406 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1407 hashtbl[h / 32] |= 1 << (h % 32);
1408 }
1409 i++;
1410 ETHER_NEXT_MULTI(step, enm);
1411 }
1412 rxfilt |= MUE_RFE_CTL_PERFECT;
1413 ifp->if_flags &= ~IFF_ALLMULTI;
1414 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH)
1415 DPRINTF(sc, "perfect filter and hash tables\n");
1416 else
1417 DPRINTF(sc, "perfect filter\n");
1418 }
1419
1420 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1421 hireg = (sc->mue_flags & LAN7500) ?
1422 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1423 loreg = hireg + 4;
1424 mue_csr_write(sc, hireg, 0);
1425 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1426 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1427 }
1428
1429 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1430 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1431
1432 mue_csr_write(sc, reg, rxfilt);
1433 }
1434
1435 static void
1436 mue_sethwcsum(struct mue_softc *sc)
1437 {
1438 struct ifnet *ifp = GET_IFP(sc);
1439 uint32_t reg, val;
1440
1441 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1442 val = mue_csr_read(sc, reg);
1443
1444 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) {
1445 DPRINTF(sc, "RX IPv4 hwcsum enabled\n");
1446 val |= MUE_RFE_CTL_IP_COE;
1447 } else {
1448 DPRINTF(sc, "RX IPv4 hwcsum disabled\n");
1449 val &= ~MUE_RFE_CTL_IP_COE;
1450 }
1451
1452 if (ifp->if_capenable &
1453 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
1454 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) {
1455 DPRINTF(sc, "RX L4 hwcsum enabled\n");
1456 val |= MUE_RFE_CTL_TCPUDP_COE;
1457 } else {
1458 DPRINTF(sc, "RX L4 hwcsum disabled\n");
1459 val &= ~MUE_RFE_CTL_TCPUDP_COE;
1460 }
1461
1462 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1463
1464 mue_csr_write(sc, reg, val);
1465 }
1466
1467 static void
1468 mue_setmtu(struct mue_softc *sc)
1469 {
1470 struct ifnet *ifp = GET_IFP(sc);
1471 uint32_t val;
1472
1473 /* Set the maximum frame size. */
1474 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1475 val = mue_csr_read(sc, MUE_MAC_RX);
1476 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1477 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1478 mue_csr_write(sc, MUE_MAC_RX, val);
1479 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1480 }
1481
1482 static void
1483 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1484 {
1485 struct mue_chain *c = (struct mue_chain *)priv;
1486 struct mue_softc *sc = c->mue_sc;
1487 struct ifnet *ifp = GET_IFP(sc);
1488 struct mbuf *m;
1489 struct mue_rxbuf_hdr *hdrp;
1490 uint32_t rx_cmd_a, totlen;
1491 uint16_t pktlen;
1492 int s;
1493 int csum;
1494 char *buf = c->mue_buf;
1495 bool v6;
1496
1497 if (__predict_false(sc->mue_dying)) {
1498 DPRINTF(sc, "dying\n");
1499 return;
1500 }
1501
1502 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1503 DPRINTF(sc, "%s\n", usbd_errstr(status));
1504 if (status == USBD_INVAL)
1505 return; /* XXX plugged out or down */
1506 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1507 return;
1508 if (usbd_ratecheck(&sc->mue_rx_notice))
1509 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1510 if (status == USBD_STALLED)
1511 usbd_clear_endpoint_stall_async(
1512 sc->mue_ep[MUE_ENDPT_RX]);
1513 goto done;
1514 }
1515
1516 usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL);
1517
1518 KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u",
1519 totlen, sc->mue_rxbufsz);
1520
1521 do {
1522 if (__predict_false(totlen < sizeof(*hdrp))) {
1523 MUE_PRINTF(sc, "packet length %u too short\n", totlen);
1524 ifp->if_ierrors++;
1525 goto done;
1526 }
1527
1528 hdrp = (struct mue_rxbuf_hdr *)buf;
1529 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1530
1531 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1532 /*
1533 * We cannot use MUE_RX_CMD_A_RED bit here;
1534 * it is turned on in the cases of L3/L4
1535 * checksum errors which we handle below.
1536 */
1537 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1538 ifp->if_ierrors++;
1539 goto done;
1540 }
1541
1542 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1543 if (sc->mue_flags & LAN7500)
1544 pktlen -= 2;
1545
1546 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1547 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1548 pktlen + sizeof(*hdrp) > totlen)) {
1549 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1550 ifp->if_ierrors++;
1551 goto done;
1552 }
1553
1554 m = mue_newbuf();
1555 if (__predict_false(m == NULL)) {
1556 MUE_PRINTF(sc, "failed to allocate mbuf\n");
1557 ifp->if_ierrors++;
1558 goto done;
1559 }
1560
1561 m_set_rcvif(m, ifp);
1562 m->m_pkthdr.len = m->m_len = pktlen;
1563 m->m_flags |= M_HASFCS;
1564
1565 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1566 csum = 0;
1567 } else {
1568 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1569 switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1570 case MUE_RX_CMD_A_PID_TCP:
1571 csum = v6 ?
1572 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1573 break;
1574 case MUE_RX_CMD_A_PID_UDP:
1575 csum = v6 ?
1576 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1577 break;
1578 case MUE_RX_CMD_A_PID_IP:
1579 csum = v6 ? 0 : M_CSUM_IPv4;
1580 break;
1581 default:
1582 csum = 0;
1583 break;
1584 }
1585 csum &= ifp->if_csum_flags_rx;
1586 if (__predict_false((csum & M_CSUM_IPv4) &&
1587 (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1588 csum |= M_CSUM_IPv4_BAD;
1589 if (__predict_false((csum & ~M_CSUM_IPv4) &&
1590 (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1591 csum |= M_CSUM_TCP_UDP_BAD;
1592 }
1593 m->m_pkthdr.csum_flags = csum;
1594 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1595
1596 /* Attention: sizeof(hdr) = 10 */
1597 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1598 if (pktlen > totlen)
1599 pktlen = totlen;
1600 totlen -= pktlen;
1601 buf += pktlen;
1602
1603 s = splnet();
1604 if_percpuq_enqueue(ifp->if_percpuq, m);
1605 splx(s);
1606 } while (totlen > 0);
1607
1608 done:
1609 /* Setup new transfer. */
1610 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1611 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1612 usbd_transfer(xfer);
1613 }
1614
1615 static void
1616 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1617 {
1618 struct mue_chain *c = priv;
1619 struct mue_softc *sc = c->mue_sc;
1620 struct mue_cdata *cd = &sc->mue_cdata;
1621 struct ifnet *ifp = GET_IFP(sc);
1622 int s;
1623
1624 if (__predict_false(sc->mue_dying))
1625 return;
1626
1627 s = splnet();
1628 KASSERT(cd->mue_tx_cnt > 0);
1629 cd->mue_tx_cnt--;
1630 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1631 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1632 splx(s);
1633 return;
1634 }
1635 ifp->if_oerrors++;
1636 if (usbd_ratecheck(&sc->mue_tx_notice))
1637 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1638 if (status == USBD_STALLED)
1639 usbd_clear_endpoint_stall_async(
1640 sc->mue_ep[MUE_ENDPT_TX]);
1641 splx(s);
1642 return;
1643 }
1644
1645 ifp->if_timer = 0;
1646 ifp->if_flags &= ~IFF_OACTIVE;
1647
1648 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1649 mue_start(ifp);
1650
1651 ifp->if_opackets++;
1652 splx(s);
1653 }
1654
1655 static int
1656 mue_init(struct ifnet *ifp)
1657 {
1658 struct mue_softc *sc = ifp->if_softc;
1659 int s;
1660
1661 if (sc->mue_dying) {
1662 DPRINTF(sc, "dying\n");
1663 return EIO;
1664 }
1665
1666 s = splnet();
1667
1668 /* Cancel pending I/O and free all TX/RX buffers. */
1669 if (ifp->if_flags & IFF_RUNNING)
1670 mue_stop(ifp, 1);
1671
1672 mue_reset(sc);
1673
1674 /* Set MAC address. */
1675 mue_set_macaddr(sc);
1676
1677 /* Load the multicast filter. */
1678 mue_setmulti(sc);
1679
1680 /* TCP/UDP checksum offload engines. */
1681 mue_sethwcsum(sc);
1682
1683 /* Set MTU. */
1684 mue_setmtu(sc);
1685
1686 if (mue_open_pipes(sc)) {
1687 splx(s);
1688 return EIO;
1689 }
1690
1691 /* Init RX ring. */
1692 if (mue_rx_list_init(sc)) {
1693 MUE_PRINTF(sc, "failed to init rx list\n");
1694 splx(s);
1695 return ENOBUFS;
1696 }
1697
1698 /* Init TX ring. */
1699 if (mue_tx_list_init(sc)) {
1700 MUE_PRINTF(sc, "failed to init tx list\n");
1701 splx(s);
1702 return ENOBUFS;
1703 }
1704
1705 mue_startup_rx_pipes(sc);
1706
1707 ifp->if_flags |= IFF_RUNNING;
1708 ifp->if_flags &= ~IFF_OACTIVE;
1709
1710 splx(s);
1711
1712 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1713
1714 return 0;
1715 }
1716
1717 static int
1718 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1719 {
1720 struct mue_softc *sc = ifp->if_softc;
1721 int s, error = 0;
1722
1723 s = splnet();
1724
1725 switch (cmd) {
1726 case SIOCSIFFLAGS:
1727 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1728 break;
1729
1730 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1731 case IFF_RUNNING:
1732 mue_stop(ifp, 1);
1733 break;
1734 case IFF_UP:
1735 mue_init(ifp);
1736 break;
1737 case IFF_UP | IFF_RUNNING:
1738 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1739 mue_setmulti(sc);
1740 else
1741 mue_init(ifp);
1742 break;
1743 }
1744 sc->mue_if_flags = ifp->if_flags;
1745 break;
1746 default:
1747 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1748 break;
1749 error = 0;
1750 switch (cmd) {
1751 case SIOCADDMULTI:
1752 case SIOCDELMULTI:
1753 mue_setmulti(sc);
1754 break;
1755 case SIOCSIFCAP:
1756 mue_sethwcsum(sc);
1757 break;
1758 case SIOCSIFMTU:
1759 mue_setmtu(sc);
1760 break;
1761 default:
1762 break;
1763 }
1764 break;
1765 }
1766 splx(s);
1767
1768 return error;
1769 }
1770
1771 static void
1772 mue_watchdog(struct ifnet *ifp)
1773 {
1774 struct mue_softc *sc = ifp->if_softc;
1775 struct mue_chain *c;
1776 usbd_status stat;
1777 int s;
1778
1779 ifp->if_oerrors++;
1780 MUE_PRINTF(sc, "timed out\n");
1781
1782 s = splusb();
1783 c = &sc->mue_cdata.mue_tx_chain[0];
1784 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1785 mue_txeof(c->mue_xfer, c, stat);
1786
1787 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1788 mue_start(ifp);
1789 splx(s);
1790 }
1791
1792 static void
1793 mue_reset(struct mue_softc *sc)
1794 {
1795 if (sc->mue_dying)
1796 return;
1797
1798 /* Wait a little while for the chip to get its brains in order. */
1799 usbd_delay_ms(sc->mue_udev, 1);
1800
1801 // mue_chip_init(sc); /* XXX */
1802 }
1803
1804 static void
1805 mue_start(struct ifnet *ifp)
1806 {
1807 struct mue_softc *sc = ifp->if_softc;
1808 struct mbuf *m;
1809 struct mue_cdata *cd = &sc->mue_cdata;
1810 int idx;
1811
1812 if (__predict_false(!sc->mue_link)) {
1813 DPRINTF(sc, "no link\n");
1814 return;
1815 }
1816
1817 if (__predict_false((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING))
1818 != IFF_RUNNING)) {
1819 DPRINTF(sc, "not ready\n");
1820 return;
1821 }
1822
1823 mutex_enter(&sc->mue_usb_lock);
1824
1825 idx = cd->mue_tx_prod;
1826 while (cd->mue_tx_cnt < (int)sc->mue_tx_list_cnt) {
1827 IFQ_POLL(&ifp->if_snd, m);
1828 if (m == NULL)
1829 break;
1830
1831 if (__predict_false(mue_encap(sc, m, idx))) {
1832 ifp->if_oerrors++;
1833 break;
1834 }
1835 IFQ_DEQUEUE(&ifp->if_snd, m);
1836
1837 bpf_mtap(ifp, m, BPF_D_OUT);
1838 m_freem(m);
1839
1840 cd->mue_tx_cnt++;
1841 idx = (idx + 1) % sc->mue_tx_list_cnt;
1842 }
1843 cd->mue_tx_prod = idx;
1844
1845 if (cd->mue_tx_cnt >= (int)sc->mue_tx_list_cnt)
1846 ifp->if_flags |= IFF_OACTIVE;
1847
1848 mutex_exit(&sc->mue_usb_lock);
1849
1850 /* Set a timeout in case the chip goes out to lunch. */
1851 ifp->if_timer = 5;
1852 }
1853
1854 static void
1855 mue_stop(struct ifnet *ifp, int disable __unused)
1856 {
1857 struct mue_softc *sc = ifp->if_softc;
1858 struct mue_chain *c;
1859 usbd_status err;
1860 size_t i;
1861
1862 mue_reset(sc);
1863
1864 ifp->if_timer = 0;
1865 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1866
1867 callout_stop(&sc->mue_stat_ch);
1868 sc->mue_link = 0;
1869
1870 /* Stop transfers. */
1871 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1872 if (sc->mue_ep[i] != NULL) {
1873 err = usbd_abort_pipe(sc->mue_ep[i]);
1874 if (err)
1875 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1876 i, usbd_errstr(err));
1877 }
1878
1879 /* Free RX resources. */
1880 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1881 c = &sc->mue_cdata.mue_rx_chain[i];
1882 if (c->mue_xfer != NULL) {
1883 usbd_destroy_xfer(c->mue_xfer);
1884 c->mue_xfer = NULL;
1885 }
1886 }
1887
1888 /* Free TX resources. */
1889 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1890 c = &sc->mue_cdata.mue_tx_chain[i];
1891 if (c->mue_xfer != NULL) {
1892 usbd_destroy_xfer(c->mue_xfer);
1893 c->mue_xfer = NULL;
1894 }
1895 }
1896
1897 /* Close pipes */
1898 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1899 if (sc->mue_ep[i] != NULL) {
1900 err = usbd_close_pipe(sc->mue_ep[i]);
1901 if (err)
1902 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1903 i, usbd_errstr(err));
1904 sc->mue_ep[i] = NULL;
1905 }
1906
1907 DPRINTF(sc, "done\n");
1908 }
1909
1910 static void
1911 mue_tick(void *xsc)
1912 {
1913 struct mue_softc *sc = xsc;
1914
1915 if (sc == NULL)
1916 return;
1917
1918 if (sc->mue_dying)
1919 return;
1920
1921 /* Perform periodic stuff in process context. */
1922 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1923 }
1924
1925 static void
1926 mue_tick_task(void *xsc)
1927 {
1928 struct mue_softc *sc = xsc;
1929 struct ifnet *ifp;
1930 struct mii_data *mii;
1931 int s;
1932
1933 if (sc == NULL)
1934 return;
1935
1936 if (sc->mue_dying)
1937 return;
1938
1939 ifp = GET_IFP(sc);
1940 mii = GET_MII(sc);
1941
1942 s = splnet();
1943 mii_tick(mii);
1944 if (sc->mue_link == 0)
1945 mue_miibus_statchg(ifp);
1946 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1947 splx(s);
1948 }
1949
1950 static struct mbuf *
1951 mue_newbuf(void)
1952 {
1953 struct mbuf *m;
1954
1955 MGETHDR(m, M_DONTWAIT, MT_DATA);
1956 if (__predict_false(m == NULL))
1957 return NULL;
1958
1959 MCLGET(m, M_DONTWAIT);
1960 if (__predict_false(!(m->m_flags & M_EXT))) {
1961 m_freem(m);
1962 return NULL;
1963 }
1964
1965 m_adj(m, ETHER_ALIGN);
1966
1967 return m;
1968 }
1969