if_mue.c revision 1.51 1 /* $NetBSD: if_mue.c,v 1.51 2019/08/01 00:10:22 mrg Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.51 2019/08/01 00:10:22 mrg Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/bus.h>
32 #include <sys/systm.h>
33 #include <sys/sockio.h>
34 #include <sys/mbuf.h>
35 #include <sys/mutex.h>
36 #include <sys/kernel.h>
37 #include <sys/proc.h>
38 #include <sys/socket.h>
39
40 #include <sys/device.h>
41
42 #include <sys/rndsource.h>
43
44 #include <net/if.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_ether.h>
48
49 #include <net/bpf.h>
50
51 #include <netinet/if_inarp.h>
52 #include <netinet/in.h>
53 #include <netinet/ip.h> /* XXX for struct ip */
54 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
55
56 #include <dev/mii/mii.h>
57 #include <dev/mii/miivar.h>
58
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
61 #include <dev/usb/usbdi_util.h>
62 #include <dev/usb/usbdivar.h>
63 #include <dev/usb/usbdevs.h>
64
65 #include <dev/usb/if_muereg.h>
66 #include <dev/usb/if_muevar.h>
67
68 #define MUE_PRINTF(sc, fmt, args...) \
69 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
70
71 #ifdef USB_DEBUG
72 int muedebug = 0;
73 #define DPRINTF(sc, fmt, args...) \
74 do { \
75 if (muedebug) \
76 MUE_PRINTF(sc, fmt, ##args); \
77 } while (0 /* CONSTCOND */)
78 #else
79 #define DPRINTF(sc, fmt, args...) __nothing
80 #endif
81
82 /*
83 * Various supported device vendors/products.
84 */
85 struct mue_type {
86 struct usb_devno mue_dev;
87 uint16_t mue_flags;
88 #define LAN7500 0x0001 /* LAN7500 */
89 };
90
91 const struct mue_type mue_devs[] = {
92 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
93 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
97 };
98
99 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
100 uaa->uaa_vendor, uaa->uaa_product))
101
102 #define MUE_ENADDR_LO(enaddr) \
103 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
104 #define MUE_ENADDR_HI(enaddr) \
105 ((enaddr[5] << 8) | enaddr[4])
106
107 static int mue_match(device_t, cfdata_t, void *);
108 static void mue_attach(device_t, device_t, void *);
109 static int mue_detach(device_t, int);
110 static int mue_activate(device_t, enum devact);
111
112 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
113 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
114 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
115 uint32_t, uint32_t);
116
117 static void mue_lock_mii(struct mue_softc *);
118 static void mue_unlock_mii(struct mue_softc *);
119
120 static int mue_miibus_readreg(device_t, int, int, uint16_t *);
121 static int mue_miibus_writereg(device_t, int, int, uint16_t);
122 static void mue_miibus_statchg(struct ifnet *);
123 static int mue_ifmedia_upd(struct ifnet *);
124
125 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
126 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
127 static bool mue_eeprom_present(struct mue_softc *sc);
128
129 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
130 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
131
132 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
133 uint32_t, uint32_t *);
134
135 static void mue_init_ltm(struct mue_softc *);
136
137 static int mue_chip_init(struct mue_softc *);
138
139 static void mue_set_macaddr(struct mue_softc *);
140 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
141
142 static int mue_rx_list_init(struct mue_softc *);
143 static int mue_tx_list_init(struct mue_softc *);
144 static int mue_open_pipes(struct mue_softc *);
145 static void mue_startup_rx_pipes(struct mue_softc *);
146
147 static int mue_encap(struct mue_softc *, struct mbuf *, int);
148 static int mue_prepare_tso(struct mue_softc *, struct mbuf *);
149
150 static void mue_setmulti(struct mue_softc *);
151 static void mue_sethwcsum(struct mue_softc *);
152 static void mue_setmtu(struct mue_softc *);
153
154 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
155 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
156
157 static int mue_init(struct ifnet *);
158 static int mue_ioctl(struct ifnet *, u_long, void *);
159 static void mue_watchdog(struct ifnet *);
160 static void mue_reset(struct mue_softc *);
161 static void mue_start(struct ifnet *);
162 static void mue_stop(struct ifnet *, int);
163 static void mue_tick(void *);
164 static void mue_tick_task(void *);
165
166 static struct mbuf *mue_newbuf(void);
167
168 #define MUE_SETBIT(sc, reg, x) \
169 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
170
171 #define MUE_CLRBIT(sc, reg, x) \
172 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
173
174 #define MUE_WAIT_SET(sc, reg, set, fail) \
175 mue_wait_for_bits(sc, reg, set, ~0, fail)
176
177 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
178 mue_wait_for_bits(sc, reg, 0, clear, fail)
179
180 #define ETHER_IS_VALID(addr) \
181 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
182
183 #define ETHER_IS_ZERO(addr) \
184 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
185
186 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
187 mue_detach, mue_activate);
188
189 static uint32_t
190 mue_csr_read(struct mue_softc *sc, uint32_t reg)
191 {
192 usb_device_request_t req;
193 usbd_status err;
194 uDWord val;
195
196 if (sc->mue_dying)
197 return 0;
198
199 USETDW(val, 0);
200 req.bmRequestType = UT_READ_VENDOR_DEVICE;
201 req.bRequest = MUE_UR_READREG;
202 USETW(req.wValue, 0);
203 USETW(req.wIndex, reg);
204 USETW(req.wLength, 4);
205
206 err = usbd_do_request(sc->mue_udev, &req, &val);
207 if (err) {
208 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
209 return 0;
210 }
211
212 return UGETDW(val);
213 }
214
215 static int
216 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
217 {
218 usb_device_request_t req;
219 usbd_status err;
220 uDWord val;
221
222 if (sc->mue_dying)
223 return 0;
224
225 USETDW(val, aval);
226 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
227 req.bRequest = MUE_UR_WRITEREG;
228 USETW(req.wValue, 0);
229 USETW(req.wIndex, reg);
230 USETW(req.wLength, 4);
231
232 err = usbd_do_request(sc->mue_udev, &req, &val);
233 if (err) {
234 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
235 return -1;
236 }
237
238 return 0;
239 }
240
241 static int
242 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
243 uint32_t set, uint32_t clear, uint32_t fail)
244 {
245 uint32_t val;
246 int ntries;
247
248 for (ntries = 0; ntries < 1000; ntries++) {
249 val = mue_csr_read(sc, reg);
250 if ((val & set) || !(val & clear))
251 return 0;
252 if (val & fail)
253 return 1;
254 usbd_delay_ms(sc->mue_udev, 1);
255 }
256
257 return 1;
258 }
259
260 /*
261 * Get exclusive access to the MII registers.
262 */
263 static void
264 mue_lock_mii(struct mue_softc *sc)
265 {
266 sc->mue_refcnt++;
267 mutex_enter(&sc->mue_mii_lock);
268 }
269
270 static void
271 mue_unlock_mii(struct mue_softc *sc)
272 {
273 mutex_exit(&sc->mue_mii_lock);
274 if (--sc->mue_refcnt < 0)
275 usb_detach_wakeupold(sc->mue_dev);
276 }
277
278 static int
279 mue_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
280 {
281 struct mue_softc *sc = device_private(dev);
282 uint32_t data;
283 int rv = 0;
284
285 if (sc->mue_dying) {
286 DPRINTF(sc, "dying\n");
287 return -1;
288 }
289
290 if (sc->mue_phyno != phy)
291 return -1;
292
293 mue_lock_mii(sc);
294 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
295 mue_unlock_mii(sc);
296 MUE_PRINTF(sc, "not ready\n");
297 return -1;
298 }
299
300 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
301 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
302 MUE_MII_ACCESS_PHYADDR(phy));
303
304 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
305 MUE_PRINTF(sc, "timed out\n");
306 rv = ETIMEDOUT;
307 goto out;
308 }
309
310 data = mue_csr_read(sc, MUE_MII_DATA);
311 *val = data & 0xffff;
312
313 out:
314 mue_unlock_mii(sc);
315 return rv;
316 }
317
318 static int
319 mue_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
320 {
321 struct mue_softc *sc = device_private(dev);
322 int rv = 0;
323
324 if (sc->mue_dying) {
325 DPRINTF(sc, "dying\n");
326 return -1;
327 }
328
329 if (sc->mue_phyno != phy) {
330 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
331 sc->mue_phyno, phy);
332 return -1;
333 }
334
335 mue_lock_mii(sc);
336 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
337 MUE_PRINTF(sc, "not ready\n");
338 rv = EBUSY;
339 goto out;
340 }
341
342 mue_csr_write(sc, MUE_MII_DATA, val);
343 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
344 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
345 MUE_MII_ACCESS_PHYADDR(phy));
346
347 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
348 MUE_PRINTF(sc, "timed out\n");
349 rv = ETIMEDOUT;
350 }
351 out:
352 mue_unlock_mii(sc);
353 return rv;
354 }
355
356 static void
357 mue_miibus_statchg(struct ifnet *ifp)
358 {
359 struct mue_softc *sc;
360 struct mii_data *mii;
361 uint32_t flow, threshold;
362
363 if (ifp == NULL) {
364 printf("%s: ifp not ready\n", __func__);
365 return;
366 }
367
368 sc = ifp->if_softc;
369 mii = GET_MII(sc);
370
371 if ((ifp->if_flags & IFF_RUNNING) == 0) {
372 DPRINTF(sc, "not running\n");
373 return;
374 }
375
376 if (mii == NULL) {
377 DPRINTF(sc, "mii not ready\n");
378 return;
379 }
380
381 sc->mue_link = 0;
382 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
383 (IFM_ACTIVE | IFM_AVALID)) {
384 switch (IFM_SUBTYPE(mii->mii_media_active)) {
385 case IFM_10_T:
386 case IFM_100_TX:
387 case IFM_1000_T:
388 sc->mue_link++;
389 break;
390 default:
391 break;
392 }
393 }
394
395 /* Lost link, do nothing. */
396 if (sc->mue_link == 0) {
397 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
398 return;
399 }
400
401 if (!(sc->mue_flags & LAN7500)) {
402 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
403 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
404 /* Disable U2 and enable U1. */
405 MUE_CLRBIT(sc, MUE_USB_CFG1,
406 MUE_USB_CFG1_DEV_U2_INIT_EN);
407 MUE_SETBIT(sc, MUE_USB_CFG1,
408 MUE_USB_CFG1_DEV_U1_INIT_EN);
409 } else {
410 /* Enable U1 and U2. */
411 MUE_SETBIT(sc, MUE_USB_CFG1,
412 MUE_USB_CFG1_DEV_U1_INIT_EN |
413 MUE_USB_CFG1_DEV_U2_INIT_EN);
414 }
415 }
416 }
417
418 flow = 0;
419 /* XXX Linux does not check IFM_FDX flag for 7800. */
420 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
421 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
422 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
423 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
424 flow |= MUE_FLOW_RX_FCEN;
425 }
426
427 /* XXX Magic numbers taken from Linux driver. */
428 if (sc->mue_flags & LAN7500)
429 threshold = 0x820;
430 else
431 switch (sc->mue_udev->ud_speed) {
432 case USB_SPEED_SUPER:
433 threshold = 0x817;
434 break;
435 case USB_SPEED_HIGH:
436 threshold = 0x211;
437 break;
438 default:
439 threshold = 0;
440 break;
441 }
442
443 /* Threshold value should be set before enabling flow. */
444 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
445 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
446 mue_csr_write(sc, MUE_FLOW, flow);
447
448 DPRINTF(sc, "done\n");
449 }
450
451 /*
452 * Set media options.
453 */
454 static int
455 mue_ifmedia_upd(struct ifnet *ifp)
456 {
457 struct mue_softc *sc = ifp->if_softc;
458 struct mii_data *mii = GET_MII(sc);
459
460 sc->mue_link = 0;
461
462 if (mii->mii_instance) {
463 struct mii_softc *miisc;
464 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
465 mii_phy_reset(miisc);
466 }
467 return ether_mediachange(ifp);
468 }
469
470 static uint8_t
471 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
472 {
473 uint32_t val;
474
475 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
476 MUE_PRINTF(sc, "not ready\n");
477 return ETIMEDOUT;
478 }
479
480 KASSERT((off & ~MUE_E2P_CMD_ADDR_MASK) == 0);
481 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
482 off);
483
484 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
485 MUE_E2P_CMD_TIMEOUT)) {
486 MUE_PRINTF(sc, "timed out\n");
487 return ETIMEDOUT;
488 }
489
490 val = mue_csr_read(sc, MUE_E2P_DATA);
491 *dest = val & 0xff;
492
493 return 0;
494 }
495
496 static int
497 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
498 {
499 uint32_t val = 0; /* XXX gcc */
500 uint8_t byte;
501 int i, err = 0;
502
503 /*
504 * EEPROM pins are muxed with the LED function on LAN7800 device.
505 */
506 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
507 val = mue_csr_read(sc, MUE_HW_CFG);
508 mue_csr_write(sc, MUE_HW_CFG,
509 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
510 }
511
512 for (i = 0; i < cnt; i++) {
513 err = mue_eeprom_getbyte(sc, off + i, &byte);
514 if (err)
515 break;
516 *(dest + i) = byte;
517 }
518
519 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
520 mue_csr_write(sc, MUE_HW_CFG, val);
521
522 return err ? 1 : 0;
523 }
524
525 static bool
526 mue_eeprom_present(struct mue_softc *sc)
527 {
528 uint32_t val;
529 uint8_t sig;
530 int ret;
531
532 if (sc->mue_flags & LAN7500) {
533 val = mue_csr_read(sc, MUE_E2P_CMD);
534 return val & MUE_E2P_CMD_LOADED;
535 } else {
536 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
537 return (ret == 0) && (sig == MUE_E2P_IND);
538 }
539 }
540
541 static int
542 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
543 {
544 uint32_t val;
545 int i, err;
546
547 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
548
549 /* Checking if bit is set. */
550 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
551 /* Clear it, then wait for it to be cleared. */
552 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
553 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
554 0);
555 if (err) {
556 MUE_PRINTF(sc, "not ready\n");
557 return 1;
558 }
559 }
560
561 /* Start reading the bytes, one at a time. */
562 for (i = 0; i < cnt; i++) {
563 mue_csr_write(sc, MUE_OTP_ADDR1,
564 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
565 mue_csr_write(sc, MUE_OTP_ADDR2,
566 ((off + i) & MUE_OTP_ADDR2_MASK));
567 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
568 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
569
570 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
571 if (err) {
572 MUE_PRINTF(sc, "timed out\n");
573 return 1;
574 }
575 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
576 *(dest + i) = (uint8_t)(val & 0xff);
577 }
578
579 return 0;
580 }
581
582 static int
583 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
584 {
585 uint8_t sig;
586 int err;
587
588 if (sc->mue_flags & LAN7500)
589 return 1;
590
591 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
592 if (err)
593 return 1;
594 switch (sig) {
595 case MUE_OTP_IND_1:
596 break;
597 case MUE_OTP_IND_2:
598 off += 0x100;
599 break;
600 default:
601 DPRINTF(sc, "OTP not found\n");
602 return 1;
603 }
604 err = mue_read_otp_raw(sc, dest, off, cnt);
605 return err;
606 }
607
608 static void
609 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
610 uint32_t cnt, uint32_t *data)
611 {
612 uint32_t i;
613
614 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
615 MUE_PRINTF(sc, "not ready\n");
616 return;
617 }
618
619 mue_csr_write(sc, MUE_DP_SEL,
620 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
621
622 for (i = 0; i < cnt; i++) {
623 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
624 mue_csr_write(sc, MUE_DP_DATA, data[i]);
625 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
626 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
627 MUE_PRINTF(sc, "timed out\n");
628 return;
629 }
630 }
631 }
632
633 static void
634 mue_init_ltm(struct mue_softc *sc)
635 {
636 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
637 uint8_t temp[2];
638 size_t i;
639
640 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
641 if (mue_eeprom_present(sc) &&
642 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
643 if (temp[0] != sizeof(idx)) {
644 DPRINTF(sc, "EEPROM: unexpected size\n");
645 goto done;
646 }
647 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
648 sizeof(idx))) {
649 DPRINTF(sc, "EEPROM: failed to read\n");
650 goto done;
651 }
652 DPRINTF(sc, "success\n");
653 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
654 if (temp[0] != sizeof(idx)) {
655 DPRINTF(sc, "OTP: unexpected size\n");
656 goto done;
657 }
658 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
659 sizeof(idx))) {
660 DPRINTF(sc, "OTP: failed to read\n");
661 goto done;
662 }
663 DPRINTF(sc, "success\n");
664 } else
665 DPRINTF(sc, "nothing to do\n");
666 } else
667 DPRINTF(sc, "nothing to do\n");
668 done:
669 for (i = 0; i < __arraycount(idx); i++)
670 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
671 }
672
673 static int
674 mue_chip_init(struct mue_softc *sc)
675 {
676 uint32_t val;
677
678 if ((sc->mue_flags & LAN7500) &&
679 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
680 MUE_PRINTF(sc, "not ready\n");
681 return ETIMEDOUT;
682 }
683
684 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
685 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
686 MUE_PRINTF(sc, "timed out\n");
687 return ETIMEDOUT;
688 }
689
690 /* Respond to the IN token with a NAK. */
691 if (sc->mue_flags & LAN7500)
692 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
693 else
694 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
695
696 if (sc->mue_flags & LAN7500) {
697 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
698 val = MUE_7500_HS_RX_BUFSIZE /
699 MUE_HS_USB_PKT_SIZE;
700 else
701 val = MUE_7500_FS_RX_BUFSIZE /
702 MUE_FS_USB_PKT_SIZE;
703 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
704 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
705 MUE_7500_DEFAULT_BULKIN_DELAY);
706
707 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
708
709 /* Set FIFO sizes. */
710 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
711 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
712 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
713 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
714 } else {
715 /* Init LTM. */
716 mue_init_ltm(sc);
717
718 val = MUE_7800_RX_BUFSIZE;
719 switch (sc->mue_udev->ud_speed) {
720 case USB_SPEED_SUPER:
721 val /= MUE_SS_USB_PKT_SIZE;
722 break;
723 case USB_SPEED_HIGH:
724 val /= MUE_HS_USB_PKT_SIZE;
725 break;
726 default:
727 val /= MUE_FS_USB_PKT_SIZE;
728 break;
729 }
730 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
731 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
732 MUE_7800_DEFAULT_BULKIN_DELAY);
733
734 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
735 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
736
737 /*
738 * Set FCL's RX and TX FIFO sizes: according to data sheet this
739 * is already the default value. But we initialize it to the
740 * same value anyways, as that's what the Linux driver does.
741 */
742 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
743 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
744 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
745 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
746 }
747
748 /* Enabling interrupts. */
749 mue_csr_write(sc, MUE_INT_STATUS, ~0);
750
751 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
752 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
753 mue_csr_write(sc, MUE_FLOW, 0);
754
755 /* Reset PHY. */
756 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
757 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
758 MUE_PRINTF(sc, "PHY not ready\n");
759 return ETIMEDOUT;
760 }
761
762 /* LAN7801 only has RGMII mode. */
763 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
764 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
765
766 if ((sc->mue_flags & LAN7500) ||
767 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
768 !mue_eeprom_present(sc))) {
769 /* Allow MAC to detect speed and duplex from PHY. */
770 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
771 MUE_MAC_CR_AUTO_DUPLEX);
772 }
773
774 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
775 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
776 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
777
778 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
779 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
780
781 /* Set default GPIO/LED settings only if no EEPROM is detected. */
782 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
783 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
784 MUE_SETBIT(sc, MUE_LED_CFG,
785 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
786 }
787
788 /* XXX We assume two LEDs at least when EEPROM is missing. */
789 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
790 !mue_eeprom_present(sc))
791 MUE_SETBIT(sc, MUE_HW_CFG,
792 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
793
794 return 0;
795 }
796
797 static void
798 mue_set_macaddr(struct mue_softc *sc)
799 {
800 struct ifnet *ifp = GET_IFP(sc);
801 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
802 uint32_t lo, hi;
803
804 lo = MUE_ENADDR_LO(enaddr);
805 hi = MUE_ENADDR_HI(enaddr);
806
807 mue_csr_write(sc, MUE_RX_ADDRL, lo);
808 mue_csr_write(sc, MUE_RX_ADDRH, hi);
809 }
810
811 static int
812 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
813 {
814 prop_data_t eaprop;
815 uint32_t low, high;
816
817 if (!(sc->mue_flags & LAN7500)) {
818 low = mue_csr_read(sc, MUE_RX_ADDRL);
819 high = mue_csr_read(sc, MUE_RX_ADDRH);
820 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
821 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
822 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
823 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
824 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
825 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
826 if (ETHER_IS_VALID(sc->mue_enaddr))
827 return 0;
828 else
829 DPRINTF(sc, "registers: %s\n",
830 ether_sprintf(sc->mue_enaddr));
831 }
832
833 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
834 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
835 if (ETHER_IS_VALID(sc->mue_enaddr))
836 return 0;
837 else
838 DPRINTF(sc, "EEPROM: %s\n",
839 ether_sprintf(sc->mue_enaddr));
840 }
841
842 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
843 ETHER_ADDR_LEN) == 0) {
844 if (ETHER_IS_VALID(sc->mue_enaddr))
845 return 0;
846 else
847 DPRINTF(sc, "OTP: %s\n",
848 ether_sprintf(sc->mue_enaddr));
849 }
850
851 /*
852 * Other MD methods. This should be tried only if other methods fail.
853 * Otherwise, MAC address for internal device can be assinged to
854 * external devices on Raspberry Pi, for example.
855 */
856 eaprop = prop_dictionary_get(dict, "mac-address");
857 if (eaprop != NULL) {
858 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
859 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
860 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
861 ETHER_ADDR_LEN);
862 if (ETHER_IS_VALID(sc->mue_enaddr))
863 return 0;
864 else
865 DPRINTF(sc, "prop_dictionary_get: %s\n",
866 ether_sprintf(sc->mue_enaddr));
867 }
868
869 return 1;
870 }
871
872
873 /*
874 * Probe for a Microchip chip.
875 */
876 static int
877 mue_match(device_t parent, cfdata_t match, void *aux)
878 {
879 struct usb_attach_arg *uaa = aux;
880
881 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
882 }
883
884 static void
885 mue_attach(device_t parent, device_t self, void *aux)
886 {
887 struct mue_softc *sc = device_private(self);
888 prop_dictionary_t dict = device_properties(self);
889 struct usb_attach_arg *uaa = aux;
890 struct usbd_device *dev = uaa->uaa_device;
891 usb_interface_descriptor_t *id;
892 usb_endpoint_descriptor_t *ed;
893 char *devinfop;
894 struct mii_data *mii;
895 struct ifnet *ifp;
896 usbd_status err;
897 const char *descr;
898 uint8_t i;
899 int s;
900
901 aprint_naive("\n");
902 aprint_normal("\n");
903
904 sc->mue_dev = self;
905 sc->mue_udev = dev;
906
907 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
908 aprint_normal_dev(self, "%s\n", devinfop);
909 usbd_devinfo_free(devinfop);
910
911 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
912 mutex_init(&sc->mue_usb_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
913
914 #define MUE_CONFIG_NO 1
915 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
916 if (err) {
917 aprint_error_dev(self, "failed to set configuration: %s\n",
918 usbd_errstr(err));
919 return;
920 }
921
922 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
923
924 #define MUE_IFACE_IDX 0
925 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
926 if (err) {
927 aprint_error_dev(self, "failed to get interface handle: %s\n",
928 usbd_errstr(err));
929 return;
930 }
931
932 sc->mue_product = uaa->uaa_product;
933 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
934
935 sc->mue_id_rev = mue_csr_read(sc, MUE_ID_REV);
936
937 /* Decide on what our bufsize will be. */
938 if (sc->mue_flags & LAN7500) {
939 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
940 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
941 sc->mue_rx_list_cnt = 1;
942 sc->mue_tx_list_cnt = 1;
943 } else {
944 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
945 sc->mue_rx_list_cnt = MUE_RX_LIST_CNT;
946 sc->mue_tx_list_cnt = MUE_TX_LIST_CNT;
947 }
948 sc->mue_txbufsz = MUE_TX_BUFSIZE;
949
950 /* Find endpoints. */
951 id = usbd_get_interface_descriptor(sc->mue_iface);
952 for (i = 0; i < id->bNumEndpoints; i++) {
953 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
954 if (ed == NULL) {
955 aprint_error_dev(self, "failed to get ep %hhd\n", i);
956 return;
957 }
958 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
959 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
960 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
961 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
962 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
963 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
964 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
965 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
966 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
967 }
968 }
969 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
970 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
971 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
972
973 s = splnet();
974
975 sc->mue_phyno = 1;
976
977 if (mue_chip_init(sc)) {
978 aprint_error_dev(self, "failed to initialize chip\n");
979 splx(s);
980 return;
981 }
982
983 /* A Microchip chip was detected. Inform the world. */
984 descr = (sc->mue_flags & LAN7500) ? "LAN7500" : "LAN7800";
985 aprint_normal_dev(self, "%s id 0x%x rev 0x%x\n", descr,
986 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_ID),
987 (unsigned)__SHIFTOUT(sc->mue_id_rev, MUE_ID_REV_REV));
988
989 if (mue_get_macaddr(sc, dict)) {
990 aprint_error_dev(self, "failed to read MAC address\n");
991 splx(s);
992 return;
993 }
994
995 aprint_normal_dev(self, "Ethernet address %s\n",
996 ether_sprintf(sc->mue_enaddr));
997
998 /* Initialize interface info.*/
999 ifp = GET_IFP(sc);
1000 ifp->if_softc = sc;
1001 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
1002 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1003 ifp->if_init = mue_init;
1004 ifp->if_ioctl = mue_ioctl;
1005 ifp->if_start = mue_start;
1006 ifp->if_stop = mue_stop;
1007 ifp->if_watchdog = mue_watchdog;
1008
1009 IFQ_SET_READY(&ifp->if_snd);
1010
1011 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6 |
1012 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1013 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1014 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1015 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_TCPv6_Rx |
1016 IFCAP_CSUM_UDPv6_Tx | IFCAP_CSUM_UDPv6_Rx;
1017
1018 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1019 #if 0 /* XXX not yet */
1020 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU;
1021 #endif
1022
1023 /* Initialize MII/media info. */
1024 mii = GET_MII(sc);
1025 mii->mii_ifp = ifp;
1026 mii->mii_readreg = mue_miibus_readreg;
1027 mii->mii_writereg = mue_miibus_writereg;
1028 mii->mii_statchg = mue_miibus_statchg;
1029 mii->mii_flags = MIIF_AUTOTSLEEP;
1030
1031 sc->mue_ec.ec_mii = mii;
1032 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, ether_mediastatus);
1033 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1034
1035 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1036 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1037 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1038 } else
1039 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1040
1041 /* Attach the interface. */
1042 if_attach(ifp);
1043 ether_ifattach(ifp, sc->mue_enaddr);
1044
1045 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1046 RND_TYPE_NET, RND_FLAG_DEFAULT);
1047
1048 callout_init(&sc->mue_stat_ch, 0);
1049
1050 splx(s);
1051
1052 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1053 }
1054
1055 static int
1056 mue_detach(device_t self, int flags)
1057 {
1058 struct mue_softc *sc = device_private(self);
1059 struct ifnet *ifp = GET_IFP(sc);
1060 size_t i;
1061 int s;
1062
1063 sc->mue_dying = true;
1064
1065 callout_halt(&sc->mue_stat_ch, NULL);
1066
1067 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1068 if (sc->mue_ep[i] != NULL)
1069 usbd_abort_pipe(sc->mue_ep[i]);
1070
1071 /*
1072 * Remove any pending tasks. They cannot be executing because they run
1073 * in the same thread as detach.
1074 */
1075 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1076 NULL);
1077
1078 s = splusb();
1079
1080 if (ifp->if_flags & IFF_RUNNING)
1081 mue_stop(ifp, 1);
1082
1083 callout_destroy(&sc->mue_stat_ch);
1084 rnd_detach_source(&sc->mue_rnd_source);
1085 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1086 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1087 if (ifp->if_softc != NULL) {
1088 ether_ifdetach(ifp);
1089 if_detach(ifp);
1090 }
1091
1092 if (--sc->mue_refcnt >= 0) {
1093 /* Wait for processes to go away. */
1094 usb_detach_waitold(sc->mue_dev);
1095 }
1096 splx(s);
1097
1098 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1099
1100 mutex_destroy(&sc->mue_mii_lock);
1101 mutex_destroy(&sc->mue_usb_lock);
1102
1103 return 0;
1104 }
1105
1106 static int
1107 mue_activate(device_t self, enum devact act)
1108 {
1109 struct mue_softc *sc = device_private(self);
1110 struct ifnet *ifp = GET_IFP(sc);
1111
1112 switch (act) {
1113 case DVACT_DEACTIVATE:
1114 if_deactivate(ifp);
1115 sc->mue_dying = true;
1116 return 0;
1117 default:
1118 return EOPNOTSUPP;
1119 }
1120 return 0;
1121 }
1122
1123 static int
1124 mue_rx_list_init(struct mue_softc *sc)
1125 {
1126 struct mue_cdata *cd;
1127 struct mue_chain *c;
1128 size_t i;
1129 int err;
1130
1131 cd = &sc->mue_cdata;
1132 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1133 c = &cd->mue_rx_chain[i];
1134 c->mue_sc = sc;
1135 if (c->mue_xfer == NULL) {
1136 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1137 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1138 if (err)
1139 return err;
1140 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1141 }
1142 }
1143
1144 return 0;
1145 }
1146
1147 static int
1148 mue_tx_list_init(struct mue_softc *sc)
1149 {
1150 struct mue_cdata *cd;
1151 struct mue_chain *c;
1152 size_t i;
1153 int err;
1154
1155 cd = &sc->mue_cdata;
1156 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1157 c = &cd->mue_tx_chain[i];
1158 c->mue_sc = sc;
1159 if (c->mue_xfer == NULL) {
1160 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1161 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1162 &c->mue_xfer);
1163 if (err)
1164 return err;
1165 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1166 }
1167 }
1168
1169 cd->mue_tx_prod = 0;
1170 cd->mue_tx_cnt = 0;
1171
1172 return 0;
1173 }
1174
1175 static int
1176 mue_open_pipes(struct mue_softc *sc)
1177 {
1178 usbd_status err;
1179
1180 /* Open RX and TX pipes. */
1181 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1182 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1183 if (err) {
1184 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1185 return EIO;
1186 }
1187 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1188 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1189 if (err) {
1190 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1191 return EIO;
1192 }
1193 return 0;
1194 }
1195
1196 static void
1197 mue_startup_rx_pipes(struct mue_softc *sc)
1198 {
1199 struct mue_chain *c;
1200 size_t i;
1201
1202 /* Start up the receive pipe. */
1203 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1204 c = &sc->mue_cdata.mue_rx_chain[i];
1205 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1206 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1207 usbd_transfer(c->mue_xfer);
1208 }
1209 }
1210
1211 static int
1212 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1213 {
1214 struct ifnet *ifp = GET_IFP(sc);
1215 struct mue_chain *c;
1216 usbd_status err;
1217 struct mue_txbuf_hdr hdr;
1218 uint32_t tx_cmd_a, tx_cmd_b;
1219 int csum, len, rv;
1220 bool tso, ipe, tpe;
1221
1222 csum = m->m_pkthdr.csum_flags;
1223 tso = csum & (M_CSUM_TSOv4 | M_CSUM_TSOv6);
1224 ipe = csum & M_CSUM_IPv4;
1225 tpe = csum & (M_CSUM_TCPv4 | M_CSUM_UDPv4 |
1226 M_CSUM_TCPv6 | M_CSUM_UDPv6);
1227
1228 len = m->m_pkthdr.len;
1229 if (__predict_false((!tso && len > (int)MUE_FRAME_LEN(ifp->if_mtu)) ||
1230 ( tso && len > MUE_TSO_FRAME_LEN))) {
1231 MUE_PRINTF(sc, "packet length %d\n too long", len);
1232 return EINVAL;
1233 }
1234
1235 c = &sc->mue_cdata.mue_tx_chain[idx];
1236
1237 KASSERT((len & ~MUE_TX_CMD_A_LEN_MASK) == 0);
1238 tx_cmd_a = len | MUE_TX_CMD_A_FCS;
1239
1240 if (tso) {
1241 tx_cmd_a |= MUE_TX_CMD_A_LSO;
1242 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1243 tx_cmd_b = m->m_pkthdr.segsz;
1244 else
1245 tx_cmd_b = MUE_TX_MSS_MIN;
1246 tx_cmd_b <<= MUE_TX_CMD_B_MSS_SHIFT;
1247 KASSERT((tx_cmd_b & ~MUE_TX_CMD_B_MSS_MASK) == 0);
1248 rv = mue_prepare_tso(sc, m);
1249 if (__predict_false(rv))
1250 return rv;
1251 } else {
1252 if (ipe)
1253 tx_cmd_a |= MUE_TX_CMD_A_IPE;
1254 if (tpe)
1255 tx_cmd_a |= MUE_TX_CMD_A_TPE;
1256 tx_cmd_b = 0;
1257 }
1258
1259 hdr.tx_cmd_a = htole32(tx_cmd_a);
1260 hdr.tx_cmd_b = htole32(tx_cmd_b);
1261
1262 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1263 m_copydata(m, 0, len, c->mue_buf + sizeof(hdr));
1264
1265 if (__predict_false(c->mue_xfer == NULL))
1266 return EIO; /* XXX plugged out or down */
1267
1268 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len + sizeof(hdr),
1269 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1270
1271 /* Transmit */
1272 err = usbd_transfer(c->mue_xfer);
1273 if (__predict_false(err != USBD_IN_PROGRESS)) {
1274 MUE_PRINTF(sc, "%s\n", usbd_errstr(err));
1275 mue_stop(ifp, 0);
1276 return EIO;
1277 }
1278
1279 return 0;
1280 }
1281
1282 /*
1283 * L3 length field should be cleared.
1284 */
1285 static int
1286 mue_prepare_tso(struct mue_softc *sc, struct mbuf *m)
1287 {
1288 struct ether_header *eh;
1289 struct ip *ip;
1290 struct ip6_hdr *ip6;
1291 uint16_t type, len = 0;
1292 int off;
1293
1294 if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
1295 eh = mtod(m, struct ether_header *);
1296 type = eh->ether_type;
1297 } else
1298 m_copydata(m, offsetof(struct ether_header, ether_type),
1299 sizeof(type), &type);
1300 switch (type = htons(type)) {
1301 case ETHERTYPE_IP:
1302 case ETHERTYPE_IPV6:
1303 off = ETHER_HDR_LEN;
1304 break;
1305 case ETHERTYPE_VLAN:
1306 off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1307 break;
1308 default:
1309 if (usbd_ratecheck(&sc->mue_tx_notice))
1310 MUE_PRINTF(sc, "dropping invalid frame "
1311 "type 0x%04hx csum_flags 0x%08x\n",
1312 type, m->m_pkthdr.csum_flags);
1313 return EINVAL;
1314 }
1315
1316 if (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) {
1317 if (__predict_true(m->m_len >= off + (int)sizeof(*ip))) {
1318 ip = (void *)(mtod(m, char *) + off);
1319 ip->ip_len = 0;
1320 } else
1321 m_copyback(m, off + offsetof(struct ip, ip_len),
1322 sizeof(len), &len);
1323 } else {
1324 if (__predict_true(m->m_len >= off + (int)sizeof(*ip6))) {
1325 ip6 = (void *)(mtod(m, char *) + off);
1326 ip6->ip6_plen = 0;
1327 } else
1328 m_copyback(m, off + offsetof(struct ip6_hdr, ip6_plen),
1329 sizeof(len), &len);
1330 }
1331 return 0;
1332 }
1333
1334 static void
1335 mue_setmulti(struct mue_softc *sc)
1336 {
1337 struct ethercom *ec = &sc->mue_ec;
1338 struct ifnet *ifp = GET_IFP(sc);
1339 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1340 struct ether_multi *enm;
1341 struct ether_multistep step;
1342 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1343 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1344 uint32_t reg, rxfilt, h, hireg, loreg;
1345 size_t i;
1346
1347 if (sc->mue_dying)
1348 return;
1349
1350 /* Clear perfect filter and hash tables. */
1351 memset(pfiltbl, 0, sizeof(pfiltbl));
1352 memset(hashtbl, 0, sizeof(hashtbl));
1353
1354 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1355 rxfilt = mue_csr_read(sc, reg);
1356 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1357 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1358
1359 /* Always accept broadcast frames. */
1360 rxfilt |= MUE_RFE_CTL_BROADCAST;
1361
1362 if (ifp->if_flags & IFF_PROMISC) {
1363 rxfilt |= MUE_RFE_CTL_UNICAST;
1364 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1365 ifp->if_flags |= IFF_ALLMULTI;
1366 if (ifp->if_flags & IFF_PROMISC)
1367 DPRINTF(sc, "promisc\n");
1368 else
1369 DPRINTF(sc, "allmulti\n");
1370 } else {
1371 /* Now program new ones. */
1372 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1373 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1374 i = 1;
1375 ETHER_LOCK(ec);
1376 ETHER_FIRST_MULTI(step, ec, enm);
1377 while (enm != NULL) {
1378 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1379 ETHER_ADDR_LEN)) {
1380 memset(pfiltbl, 0, sizeof(pfiltbl));
1381 memset(hashtbl, 0, sizeof(hashtbl));
1382 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1383 ETHER_UNLOCK(ec);
1384 goto allmulti;
1385 }
1386 if (i < MUE_NUM_ADDR_FILTX) {
1387 /* Use perfect address table if possible. */
1388 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1389 MUE_ADDR_FILTX_VALID;
1390 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1391 } else {
1392 /* Otherwise, use hash table. */
1393 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1394 h = (ether_crc32_be(enm->enm_addrlo,
1395 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1396 hashtbl[h / 32] |= 1 << (h % 32);
1397 }
1398 i++;
1399 ETHER_NEXT_MULTI(step, enm);
1400 }
1401 ETHER_UNLOCK(ec);
1402 rxfilt |= MUE_RFE_CTL_PERFECT;
1403 ifp->if_flags &= ~IFF_ALLMULTI;
1404 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH)
1405 DPRINTF(sc, "perfect filter and hash tables\n");
1406 else
1407 DPRINTF(sc, "perfect filter\n");
1408 }
1409
1410 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1411 hireg = (sc->mue_flags & LAN7500) ?
1412 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1413 loreg = hireg + 4;
1414 mue_csr_write(sc, hireg, 0);
1415 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1416 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1417 }
1418
1419 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1420 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1421
1422 mue_csr_write(sc, reg, rxfilt);
1423 }
1424
1425 static void
1426 mue_sethwcsum(struct mue_softc *sc)
1427 {
1428 struct ifnet *ifp = GET_IFP(sc);
1429 uint32_t reg, val;
1430
1431 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1432 val = mue_csr_read(sc, reg);
1433
1434 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) {
1435 DPRINTF(sc, "RX IPv4 hwcsum enabled\n");
1436 val |= MUE_RFE_CTL_IP_COE;
1437 } else {
1438 DPRINTF(sc, "RX IPv4 hwcsum disabled\n");
1439 val &= ~MUE_RFE_CTL_IP_COE;
1440 }
1441
1442 if (ifp->if_capenable &
1443 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx |
1444 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) {
1445 DPRINTF(sc, "RX L4 hwcsum enabled\n");
1446 val |= MUE_RFE_CTL_TCPUDP_COE;
1447 } else {
1448 DPRINTF(sc, "RX L4 hwcsum disabled\n");
1449 val &= ~MUE_RFE_CTL_TCPUDP_COE;
1450 }
1451
1452 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1453
1454 mue_csr_write(sc, reg, val);
1455 }
1456
1457 static void
1458 mue_setmtu(struct mue_softc *sc)
1459 {
1460 struct ifnet *ifp = GET_IFP(sc);
1461 uint32_t val;
1462
1463 /* Set the maximum frame size. */
1464 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1465 val = mue_csr_read(sc, MUE_MAC_RX);
1466 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
1467 val |= MUE_MAC_RX_MAX_LEN(MUE_FRAME_LEN(ifp->if_mtu));
1468 mue_csr_write(sc, MUE_MAC_RX, val);
1469 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
1470 }
1471
1472 static void
1473 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1474 {
1475 struct mue_chain *c = (struct mue_chain *)priv;
1476 struct mue_softc *sc = c->mue_sc;
1477 struct ifnet *ifp = GET_IFP(sc);
1478 struct mbuf *m;
1479 struct mue_rxbuf_hdr *hdrp;
1480 uint32_t rx_cmd_a, totlen;
1481 uint16_t pktlen;
1482 int s;
1483 int csum;
1484 char *buf = c->mue_buf;
1485 bool v6;
1486
1487 if (__predict_false(sc->mue_dying)) {
1488 DPRINTF(sc, "dying\n");
1489 return;
1490 }
1491
1492 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1493 DPRINTF(sc, "%s\n", usbd_errstr(status));
1494 if (status == USBD_INVAL)
1495 return; /* XXX plugged out or down */
1496 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1497 return;
1498 if (usbd_ratecheck(&sc->mue_rx_notice))
1499 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1500 if (status == USBD_STALLED)
1501 usbd_clear_endpoint_stall_async(
1502 sc->mue_ep[MUE_ENDPT_RX]);
1503 goto done;
1504 }
1505
1506 usbd_get_xfer_status(xfer, NULL, NULL, &totlen, NULL);
1507
1508 KASSERTMSG(totlen <= sc->mue_rxbufsz, "%u vs %u",
1509 totlen, sc->mue_rxbufsz);
1510
1511 do {
1512 if (__predict_false(totlen < sizeof(*hdrp))) {
1513 MUE_PRINTF(sc, "packet length %u too short\n", totlen);
1514 ifp->if_ierrors++;
1515 goto done;
1516 }
1517
1518 hdrp = (struct mue_rxbuf_hdr *)buf;
1519 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1520
1521 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ERRORS)) {
1522 /*
1523 * We cannot use MUE_RX_CMD_A_RED bit here;
1524 * it is turned on in the cases of L3/L4
1525 * checksum errors which we handle below.
1526 */
1527 MUE_PRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1528 ifp->if_ierrors++;
1529 goto done;
1530 }
1531
1532 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1533 if (sc->mue_flags & LAN7500)
1534 pktlen -= 2;
1535
1536 if (__predict_false(pktlen < ETHER_HDR_LEN + ETHER_CRC_LEN ||
1537 pktlen > MCLBYTES - ETHER_ALIGN || /* XXX */
1538 pktlen + sizeof(*hdrp) > totlen)) {
1539 MUE_PRINTF(sc, "invalid packet length %d\n", pktlen);
1540 ifp->if_ierrors++;
1541 goto done;
1542 }
1543
1544 m = mue_newbuf();
1545 if (__predict_false(m == NULL)) {
1546 MUE_PRINTF(sc, "failed to allocate mbuf\n");
1547 ifp->if_ierrors++;
1548 goto done;
1549 }
1550
1551 m_set_rcvif(m, ifp);
1552 m->m_pkthdr.len = m->m_len = pktlen;
1553 m->m_flags |= M_HASFCS;
1554
1555 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_ICSM)) {
1556 csum = 0;
1557 } else {
1558 v6 = rx_cmd_a & MUE_RX_CMD_A_IPV;
1559 switch (rx_cmd_a & MUE_RX_CMD_A_PID) {
1560 case MUE_RX_CMD_A_PID_TCP:
1561 csum = v6 ?
1562 M_CSUM_TCPv6 : M_CSUM_IPv4 | M_CSUM_TCPv4;
1563 break;
1564 case MUE_RX_CMD_A_PID_UDP:
1565 csum = v6 ?
1566 M_CSUM_UDPv6 : M_CSUM_IPv4 | M_CSUM_UDPv4;
1567 break;
1568 case MUE_RX_CMD_A_PID_IP:
1569 csum = v6 ? 0 : M_CSUM_IPv4;
1570 break;
1571 default:
1572 csum = 0;
1573 break;
1574 }
1575 csum &= ifp->if_csum_flags_rx;
1576 if (__predict_false((csum & M_CSUM_IPv4) &&
1577 (rx_cmd_a & MUE_RX_CMD_A_ICE)))
1578 csum |= M_CSUM_IPv4_BAD;
1579 if (__predict_false((csum & ~M_CSUM_IPv4) &&
1580 (rx_cmd_a & MUE_RX_CMD_A_TCE)))
1581 csum |= M_CSUM_TCP_UDP_BAD;
1582 }
1583 m->m_pkthdr.csum_flags = csum;
1584 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1585
1586 /* Attention: sizeof(hdr) = 10 */
1587 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1588 if (pktlen > totlen)
1589 pktlen = totlen;
1590 totlen -= pktlen;
1591 buf += pktlen;
1592
1593 s = splnet();
1594 if_percpuq_enqueue(ifp->if_percpuq, m);
1595 splx(s);
1596 } while (totlen > 0);
1597
1598 done:
1599 /* Setup new transfer. */
1600 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1601 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1602 usbd_transfer(xfer);
1603 }
1604
1605 static void
1606 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1607 {
1608 struct mue_chain *c = priv;
1609 struct mue_softc *sc = c->mue_sc;
1610 struct mue_cdata *cd = &sc->mue_cdata;
1611 struct ifnet *ifp = GET_IFP(sc);
1612 int s;
1613
1614 if (__predict_false(sc->mue_dying))
1615 return;
1616
1617 s = splnet();
1618 KASSERT(cd->mue_tx_cnt > 0);
1619 cd->mue_tx_cnt--;
1620 ifp->if_timer = 0;
1621 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1622 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1623 splx(s);
1624 return;
1625 }
1626 ifp->if_oerrors++;
1627 if (usbd_ratecheck(&sc->mue_tx_notice))
1628 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1629 if (status == USBD_STALLED)
1630 usbd_clear_endpoint_stall_async(
1631 sc->mue_ep[MUE_ENDPT_TX]);
1632 splx(s);
1633 ifp->if_flags &= ~IFF_OACTIVE;
1634 return;
1635 }
1636
1637 ifp->if_flags &= ~IFF_OACTIVE;
1638
1639 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1640 mue_start(ifp);
1641
1642 ifp->if_opackets++;
1643 splx(s);
1644 }
1645
1646 static int
1647 mue_init(struct ifnet *ifp)
1648 {
1649 struct mue_softc *sc = ifp->if_softc;
1650 int s;
1651
1652 if (sc->mue_dying) {
1653 DPRINTF(sc, "dying\n");
1654 return EIO;
1655 }
1656
1657 s = splnet();
1658
1659 /* Cancel pending I/O and free all TX/RX buffers. */
1660 if (ifp->if_flags & IFF_RUNNING)
1661 mue_stop(ifp, 1);
1662
1663 mue_reset(sc);
1664
1665 /* Set MAC address. */
1666 mue_set_macaddr(sc);
1667
1668 /* Load the multicast filter. */
1669 mue_setmulti(sc);
1670
1671 /* TCP/UDP checksum offload engines. */
1672 mue_sethwcsum(sc);
1673
1674 /* Set MTU. */
1675 mue_setmtu(sc);
1676
1677 if (mue_open_pipes(sc)) {
1678 splx(s);
1679 return EIO;
1680 }
1681
1682 /* Init RX ring. */
1683 if (mue_rx_list_init(sc)) {
1684 MUE_PRINTF(sc, "failed to init rx list\n");
1685 splx(s);
1686 return ENOBUFS;
1687 }
1688
1689 /* Init TX ring. */
1690 if (mue_tx_list_init(sc)) {
1691 MUE_PRINTF(sc, "failed to init tx list\n");
1692 splx(s);
1693 return ENOBUFS;
1694 }
1695
1696 mue_startup_rx_pipes(sc);
1697
1698 ifp->if_flags |= IFF_RUNNING;
1699 ifp->if_flags &= ~IFF_OACTIVE;
1700
1701 splx(s);
1702
1703 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1704
1705 return 0;
1706 }
1707
1708 static int
1709 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1710 {
1711 struct mue_softc *sc = ifp->if_softc;
1712 int s, error = 0;
1713
1714 s = splnet();
1715
1716 switch (cmd) {
1717 case SIOCSIFFLAGS:
1718 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1719 break;
1720
1721 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1722 case IFF_RUNNING:
1723 mue_stop(ifp, 1);
1724 break;
1725 case IFF_UP:
1726 mue_init(ifp);
1727 break;
1728 case IFF_UP | IFF_RUNNING:
1729 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1730 mue_setmulti(sc);
1731 else
1732 mue_init(ifp);
1733 break;
1734 }
1735 sc->mue_if_flags = ifp->if_flags;
1736 break;
1737 default:
1738 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1739 break;
1740 error = 0;
1741 switch (cmd) {
1742 case SIOCADDMULTI:
1743 case SIOCDELMULTI:
1744 mue_setmulti(sc);
1745 break;
1746 case SIOCSIFCAP:
1747 mue_sethwcsum(sc);
1748 break;
1749 case SIOCSIFMTU:
1750 mue_setmtu(sc);
1751 break;
1752 default:
1753 break;
1754 }
1755 break;
1756 }
1757 splx(s);
1758
1759 return error;
1760 }
1761
1762 static void
1763 mue_watchdog(struct ifnet *ifp)
1764 {
1765 struct mue_softc *sc = ifp->if_softc;
1766 struct mue_chain *c;
1767 usbd_status stat;
1768 int s;
1769
1770 ifp->if_oerrors++;
1771 MUE_PRINTF(sc, "timed out\n");
1772
1773 s = splusb();
1774 c = &sc->mue_cdata.mue_tx_chain[0];
1775 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1776 mue_txeof(c->mue_xfer, c, stat);
1777
1778 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1779 mue_start(ifp);
1780 splx(s);
1781 }
1782
1783 static void
1784 mue_reset(struct mue_softc *sc)
1785 {
1786 if (sc->mue_dying)
1787 return;
1788
1789 /* Wait a little while for the chip to get its brains in order. */
1790 usbd_delay_ms(sc->mue_udev, 1);
1791
1792 // mue_chip_init(sc); /* XXX */
1793 }
1794
1795 static void
1796 mue_start(struct ifnet *ifp)
1797 {
1798 struct mue_softc *sc = ifp->if_softc;
1799 struct mbuf *m;
1800 struct mue_cdata *cd = &sc->mue_cdata;
1801 int idx;
1802
1803 if (__predict_false(!sc->mue_link)) {
1804 DPRINTF(sc, "no link\n");
1805 return;
1806 }
1807
1808 if (__predict_false((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING))
1809 != IFF_RUNNING)) {
1810 DPRINTF(sc, "not ready\n");
1811 return;
1812 }
1813
1814 mutex_enter(&sc->mue_usb_lock);
1815
1816 idx = cd->mue_tx_prod;
1817 while (cd->mue_tx_cnt < (int)sc->mue_tx_list_cnt) {
1818 IFQ_POLL(&ifp->if_snd, m);
1819 if (m == NULL)
1820 break;
1821
1822 if (__predict_false(mue_encap(sc, m, idx))) {
1823 ifp->if_oerrors++;
1824 break;
1825 }
1826 IFQ_DEQUEUE(&ifp->if_snd, m);
1827
1828 bpf_mtap(ifp, m, BPF_D_OUT);
1829 m_freem(m);
1830
1831 cd->mue_tx_cnt++;
1832 idx = (idx + 1) % sc->mue_tx_list_cnt;
1833 }
1834 cd->mue_tx_prod = idx;
1835
1836 if (cd->mue_tx_cnt >= (int)sc->mue_tx_list_cnt)
1837 ifp->if_flags |= IFF_OACTIVE;
1838
1839 mutex_exit(&sc->mue_usb_lock);
1840
1841 /* Set a timeout in case the chip goes out to lunch. */
1842 ifp->if_timer = 5;
1843 }
1844
1845 static void
1846 mue_stop(struct ifnet *ifp, int disable __unused)
1847 {
1848 struct mue_softc *sc = ifp->if_softc;
1849 struct mue_chain *c;
1850 usbd_status err;
1851 size_t i;
1852
1853 mue_reset(sc);
1854
1855 ifp->if_timer = 0;
1856 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1857
1858 callout_stop(&sc->mue_stat_ch);
1859 sc->mue_link = 0;
1860
1861 /* Stop transfers. */
1862 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1863 if (sc->mue_ep[i] != NULL) {
1864 err = usbd_abort_pipe(sc->mue_ep[i]);
1865 if (err)
1866 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1867 i, usbd_errstr(err));
1868 }
1869
1870 /* Free RX resources. */
1871 for (i = 0; i < sc->mue_rx_list_cnt; i++) {
1872 c = &sc->mue_cdata.mue_rx_chain[i];
1873 if (c->mue_xfer != NULL) {
1874 usbd_destroy_xfer(c->mue_xfer);
1875 c->mue_xfer = NULL;
1876 }
1877 }
1878
1879 /* Free TX resources. */
1880 for (i = 0; i < sc->mue_tx_list_cnt; i++) {
1881 c = &sc->mue_cdata.mue_tx_chain[i];
1882 if (c->mue_xfer != NULL) {
1883 usbd_destroy_xfer(c->mue_xfer);
1884 c->mue_xfer = NULL;
1885 }
1886 }
1887
1888 /* Close pipes */
1889 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1890 if (sc->mue_ep[i] != NULL) {
1891 err = usbd_close_pipe(sc->mue_ep[i]);
1892 if (err)
1893 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1894 i, usbd_errstr(err));
1895 sc->mue_ep[i] = NULL;
1896 }
1897
1898 DPRINTF(sc, "done\n");
1899 }
1900
1901 static void
1902 mue_tick(void *xsc)
1903 {
1904 struct mue_softc *sc = xsc;
1905
1906 if (sc == NULL)
1907 return;
1908
1909 if (sc->mue_dying)
1910 return;
1911
1912 /* Perform periodic stuff in process context. */
1913 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1914 }
1915
1916 static void
1917 mue_tick_task(void *xsc)
1918 {
1919 struct mue_softc *sc = xsc;
1920 struct ifnet *ifp;
1921 struct mii_data *mii;
1922 int s;
1923
1924 if (sc == NULL)
1925 return;
1926
1927 if (sc->mue_dying)
1928 return;
1929
1930 ifp = GET_IFP(sc);
1931 mii = GET_MII(sc);
1932
1933 s = splnet();
1934 mii_tick(mii);
1935 if (sc->mue_link == 0)
1936 mue_miibus_statchg(ifp);
1937 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1938 splx(s);
1939 }
1940
1941 static struct mbuf *
1942 mue_newbuf(void)
1943 {
1944 struct mbuf *m;
1945
1946 MGETHDR(m, M_DONTWAIT, MT_DATA);
1947 if (__predict_false(m == NULL))
1948 return NULL;
1949
1950 MCLGET(m, M_DONTWAIT);
1951 if (__predict_false(!(m->m_flags & M_EXT))) {
1952 m_freem(m);
1953 return NULL;
1954 }
1955
1956 m_adj(m, ETHER_ALIGN);
1957
1958 return m;
1959 }
1960