if_mue.c revision 1.6 1 /* $NetBSD: if_mue.c,v 1.6 2018/09/01 09:57:12 mlelstv Exp $ */
2 /* $OpenBSD: if_mue.c,v 1.3 2018/08/04 16:42:46 jsg Exp $ */
3
4 /*
5 * Copyright (c) 2018 Kevin Lo <kevlo (at) openbsd.org>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 /* Driver for Microchip LAN7500/LAN7800 chipsets. */
21
22 #include <sys/cdefs.h>
23 __KERNEL_RCSID(0, "$NetBSD: if_mue.c,v 1.6 2018/09/01 09:57:12 mlelstv Exp $");
24
25 #ifdef _KERNEL_OPT
26 #include "opt_usb.h"
27 #include "opt_inet.h"
28 #endif
29
30 #include <sys/param.h>
31 #include <sys/cprng.h>
32 #include <sys/bus.h>
33 #include <sys/systm.h>
34 #include <sys/sockio.h>
35 #include <sys/mbuf.h>
36 #include <sys/mutex.h>
37 #include <sys/kernel.h>
38 #include <sys/proc.h>
39 #include <sys/socket.h>
40
41 #include <sys/device.h>
42
43 #include <sys/rndsource.h>
44
45 #include <net/if.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
48 #include <net/if_ether.h>
49
50 #include <net/bpf.h>
51
52 #include <netinet/if_inarp.h>
53 #include <netinet/in.h>
54 #include <netinet/ip.h> /* XXX for struct ip */
55 #include <netinet/ip6.h> /* XXX for struct ip6_hdr */
56 #include <netinet/tcp.h> /* XXX for struct tcphdr */
57
58 #include <dev/mii/mii.h>
59 #include <dev/mii/miivar.h>
60
61 #include <dev/usb/usb.h>
62 #include <dev/usb/usbdi.h>
63 #include <dev/usb/usbdi_util.h>
64 #include <dev/usb/usbdivar.h>
65 #include <dev/usb/usbdevs.h>
66
67 #include <dev/usb/if_muereg.h>
68 #include <dev/usb/if_muevar.h>
69
70 #define MUE_PRINTF(sc, fmt, args...) \
71 device_printf((sc)->mue_dev, "%s: " fmt, __func__, ##args);
72
73 #ifdef USB_DEBUG
74 int muedebug = 0;
75 #define DPRINTF(sc, fmt, args...) \
76 do { \
77 if (muedebug) \
78 MUE_PRINTF(sc, fmt, ##args); \
79 } while (0 /* CONSTCOND */)
80 #else
81 #define DPRINTF(sc, fmt, args...) /* nothing */
82 #endif
83
84 /*
85 * Various supported device vendors/products.
86 */
87 struct mue_type {
88 struct usb_devno mue_dev;
89 uint16_t mue_flags;
90 #define LAN7500 0x0001 /* LAN7500 */
91 };
92
93 const struct mue_type mue_devs[] = {
94 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7500 }, LAN7500 },
95 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7505 }, LAN7500 },
96 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7800 }, 0 },
97 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7801 }, 0 },
98 { { USB_VENDOR_SMSC, USB_PRODUCT_SMSC_LAN7850 }, 0 }
99 };
100
101 #define MUE_LOOKUP(uaa) ((const struct mue_type *)usb_lookup(mue_devs, \
102 uaa->uaa_vendor, uaa->uaa_product))
103
104 #define MUE_ENADDR_LO(enaddr) \
105 ((enaddr[3] << 24) | (enaddr[2] << 16) | (enaddr[1] << 8) | enaddr[0])
106 #define MUE_ENADDR_HI(enaddr) \
107 ((enaddr[5] << 8) | enaddr[4])
108
109 static int mue_match(device_t, cfdata_t, void *);
110 static void mue_attach(device_t, device_t, void *);
111 static int mue_detach(device_t, int);
112 static int mue_activate(device_t, enum devact);
113
114 static uint32_t mue_csr_read(struct mue_softc *, uint32_t);
115 static int mue_csr_write(struct mue_softc *, uint32_t, uint32_t);
116 static int mue_wait_for_bits(struct mue_softc *sc, uint32_t, uint32_t,
117 uint32_t, uint32_t);
118
119 static void mue_lock_mii(struct mue_softc *);
120 static void mue_unlock_mii(struct mue_softc *);
121
122 static int mue_miibus_readreg(device_t, int, int);
123 static void mue_miibus_writereg(device_t, int, int, int);
124 static void mue_miibus_statchg(struct ifnet *);
125 static int mue_ifmedia_upd(struct ifnet *);
126 static void mue_ifmedia_sts(struct ifnet *, struct ifmediareq *);
127
128 static uint8_t mue_eeprom_getbyte(struct mue_softc *, int, uint8_t *);
129 static int mue_read_eeprom(struct mue_softc *, uint8_t *, int, int);
130 static bool mue_eeprom_present(struct mue_softc *sc);
131
132 static int mue_read_otp_raw(struct mue_softc *, uint8_t *, int, int);
133 static int mue_read_otp(struct mue_softc *, uint8_t *, int, int);
134
135 static void mue_dataport_write(struct mue_softc *, uint32_t, uint32_t,
136 uint32_t, uint32_t *);
137
138 static void mue_init_ltm(struct mue_softc *);
139
140 static int mue_chip_init(struct mue_softc *);
141
142 static void mue_set_macaddr(struct mue_softc *);
143 static int mue_get_macaddr(struct mue_softc *, prop_dictionary_t);
144
145 static int mue_rx_list_init(struct mue_softc *);
146 static int mue_tx_list_init(struct mue_softc *);
147 static int mue_open_pipes(struct mue_softc *);
148 static void mue_start_rx(struct mue_softc *);
149
150 static int mue_encap(struct mue_softc *, struct mbuf *, int);
151 static void mue_tx_offload(struct mue_softc *, struct mbuf *);
152
153 static void mue_setmulti(struct mue_softc *);
154 static void mue_sethwcsum(struct mue_softc *);
155
156 static void mue_rxeof(struct usbd_xfer *, void *, usbd_status);
157 static void mue_txeof(struct usbd_xfer *, void *, usbd_status);
158
159 static int mue_init(struct ifnet *);
160 static int mue_ioctl(struct ifnet *, u_long, void *);
161 static void mue_watchdog(struct ifnet *);
162 static void mue_reset(struct mue_softc *);
163 static void mue_start(struct ifnet *);
164 static void mue_stop(struct ifnet *, int);
165 static void mue_tick(void *);
166 static void mue_tick_task(void *);
167
168 static struct mbuf *mue_newbuf(void);
169
170 #define MUE_SETBIT(sc, reg, x) \
171 mue_csr_write(sc, reg, mue_csr_read(sc, reg) | (x))
172
173 #define MUE_CLRBIT(sc, reg, x) \
174 mue_csr_write(sc, reg, mue_csr_read(sc, reg) & ~(x))
175
176 #define MUE_WAIT_SET(sc, reg, set, fail) \
177 mue_wait_for_bits(sc, reg, set, ~0, fail)
178
179 #define MUE_WAIT_CLR(sc, reg, clear, fail) \
180 mue_wait_for_bits(sc, reg, 0, clear, fail)
181
182 #define ETHER_IS_VALID(addr) \
183 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr))
184
185 #define ETHER_IS_ZERO(addr) \
186 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))
187
188 #define ETHER_ALIGN 2
189
190 CFATTACH_DECL_NEW(mue, sizeof(struct mue_softc), mue_match, mue_attach,
191 mue_detach, mue_activate);
192
193 static uint32_t
194 mue_csr_read(struct mue_softc *sc, uint32_t reg)
195 {
196 usb_device_request_t req;
197 usbd_status err;
198 uDWord val;
199
200 if (sc->mue_dying)
201 return 0;
202
203 USETDW(val, 0);
204 req.bmRequestType = UT_READ_VENDOR_DEVICE;
205 req.bRequest = MUE_UR_READREG;
206 USETW(req.wValue, 0);
207 USETW(req.wIndex, reg);
208 USETW(req.wLength, 4);
209
210 err = usbd_do_request(sc->mue_udev, &req, &val);
211 if (err) {
212 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
213 return 0;
214 }
215
216 return UGETDW(val);
217 }
218
219 static int
220 mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval)
221 {
222 usb_device_request_t req;
223 usbd_status err;
224 uDWord val;
225
226 if (sc->mue_dying)
227 return 0;
228
229 USETDW(val, aval);
230 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
231 req.bRequest = MUE_UR_WRITEREG;
232 USETW(req.wValue, 0);
233 USETW(req.wIndex, reg);
234 USETW(req.wLength, 4);
235
236 err = usbd_do_request(sc->mue_udev, &req, &val);
237 if (err) {
238 MUE_PRINTF(sc, "reg = 0x%x: %s\n", reg, usbd_errstr(err));
239 return -1;
240 }
241
242 return 0;
243 }
244
245 static int
246 mue_wait_for_bits(struct mue_softc *sc, uint32_t reg,
247 uint32_t set, uint32_t clear, uint32_t fail)
248 {
249 uint32_t val;
250 int ntries;
251
252 for (ntries = 0; ntries < 1000; ntries++) {
253 val = mue_csr_read(sc, reg);
254 if ((val & set) || !(val & clear))
255 return 0;
256 if (val & fail)
257 return 1;
258 usbd_delay_ms(sc->mue_udev, 1);
259 }
260
261 return 1;
262 }
263
264 /*
265 * Get exclusive access to the MII registers.
266 */
267 static void
268 mue_lock_mii(struct mue_softc *sc)
269 {
270 sc->mue_refcnt++;
271 mutex_enter(&sc->mue_mii_lock);
272 }
273
274 static void
275 mue_unlock_mii(struct mue_softc *sc)
276 {
277 mutex_exit(&sc->mue_mii_lock);
278 if (--sc->mue_refcnt < 0)
279 usb_detach_wakeupold(sc->mue_dev);
280 }
281
282 static int
283 mue_miibus_readreg(device_t dev, int phy, int reg)
284 {
285 struct mue_softc *sc = device_private(dev);
286 uint32_t val;
287
288 if (sc->mue_dying) {
289 DPRINTF(sc, "dying\n");
290 return 0;
291 }
292
293 if (sc->mue_phyno != phy)
294 return 0;
295
296 mue_lock_mii(sc);
297 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
298 mue_unlock_mii(sc);
299 MUE_PRINTF(sc, "not ready\n");
300 return -1;
301 }
302
303 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_READ |
304 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
305 MUE_MII_ACCESS_PHYADDR(phy));
306
307 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
308 mue_unlock_mii(sc);
309 MUE_PRINTF(sc, "timed out\n");
310 return -1;
311 }
312
313 val = mue_csr_read(sc, MUE_MII_DATA);
314 mue_unlock_mii(sc);
315 return val & 0xffff;
316 }
317
318 static void
319 mue_miibus_writereg(device_t dev, int phy, int reg, int data)
320 {
321 struct mue_softc *sc = device_private(dev);
322
323 if (sc->mue_dying) {
324 DPRINTF(sc, "dying\n");
325 return;
326 }
327
328 if (sc->mue_phyno != phy) {
329 DPRINTF(sc, "sc->mue_phyno (%d) != phy (%d)\n",
330 sc->mue_phyno, phy);
331 return;
332 }
333
334 mue_lock_mii(sc);
335 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0)) {
336 mue_unlock_mii(sc);
337 MUE_PRINTF(sc, "not ready\n");
338 return;
339 }
340
341 mue_csr_write(sc, MUE_MII_DATA, data);
342 mue_csr_write(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_WRITE |
343 MUE_MII_ACCESS_BUSY | MUE_MII_ACCESS_REGADDR(reg) |
344 MUE_MII_ACCESS_PHYADDR(phy));
345
346 if (MUE_WAIT_CLR(sc, MUE_MII_ACCESS, MUE_MII_ACCESS_BUSY, 0))
347 MUE_PRINTF(sc, "timed out\n");
348
349 mue_unlock_mii(sc);
350 }
351
352 static void
353 mue_miibus_statchg(struct ifnet *ifp)
354 {
355 struct mue_softc *sc = ifp->if_softc;
356 struct mii_data *mii = GET_MII(sc);
357 uint32_t flow, threshold;
358
359 if (mii == NULL || ifp == NULL || (ifp->if_flags & IFF_RUNNING) == 0) {
360 DPRINTF(sc, "not ready\n");
361 return;
362 }
363
364 sc->mue_link = 0;
365 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
366 (IFM_ACTIVE | IFM_AVALID)) {
367 switch (IFM_SUBTYPE(mii->mii_media_active)) {
368 case IFM_10_T:
369 case IFM_100_TX:
370 case IFM_1000_T:
371 sc->mue_link++;
372 break;
373 default:
374 break;
375 }
376 }
377
378 /* Lost link, do nothing. */
379 if (sc->mue_link == 0) {
380 DPRINTF(sc, "mii_media_status = 0x%x\n", mii->mii_media_status);
381 return;
382 }
383
384 if (!(sc->mue_flags & LAN7500)) {
385 if (sc->mue_udev->ud_speed == USB_SPEED_SUPER) {
386 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
387 /* Disable U2 and enable U1. */
388 MUE_CLRBIT(sc, MUE_USB_CFG1,
389 MUE_USB_CFG1_DEV_U2_INIT_EN);
390 MUE_SETBIT(sc, MUE_USB_CFG1,
391 MUE_USB_CFG1_DEV_U1_INIT_EN);
392 } else {
393 /* Enable U1 and U2. */
394 MUE_SETBIT(sc, MUE_USB_CFG1,
395 MUE_USB_CFG1_DEV_U1_INIT_EN |
396 MUE_USB_CFG1_DEV_U2_INIT_EN);
397 }
398 }
399 }
400
401 flow = 0;
402 /* XXX Linux does not check IFM_FDX flag for 7800. */
403 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
404 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
405 flow |= MUE_FLOW_TX_FCEN | MUE_FLOW_PAUSE_TIME;
406 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
407 flow |= MUE_FLOW_RX_FCEN;
408 }
409
410 /* XXX Magic numbers taken from Linux driver. */
411 if (sc->mue_flags & LAN7500)
412 threshold = 0x820;
413 else
414 switch (sc->mue_udev->ud_speed) {
415 case USB_SPEED_SUPER:
416 threshold = 0x817;
417 break;
418 case USB_SPEED_HIGH:
419 threshold = 0x211;
420 break;
421 default:
422 threshold = 0;
423 break;
424 }
425
426 /* Threshold value should be set before enabling flow. */
427 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
428 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, threshold);
429 mue_csr_write(sc, MUE_FLOW, flow);
430
431 DPRINTF(sc, "done\n");
432 }
433
434 /*
435 * Set media options.
436 */
437 static int
438 mue_ifmedia_upd(struct ifnet *ifp)
439 {
440 struct mue_softc *sc = ifp->if_softc;
441 struct mii_data *mii = GET_MII(sc);
442
443 sc->mue_link = 0; /* XXX */
444
445 if (mii->mii_instance) {
446 struct mii_softc *miisc;
447 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
448 mii_phy_reset(miisc);
449 }
450 return mii_mediachg(mii);
451 }
452
453 /*
454 * Report current media status.
455 */
456 static void
457 mue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
458 {
459 struct mue_softc *sc = ifp->if_softc;
460 struct mii_data *mii = GET_MII(sc);
461
462 mii_pollstat(mii);
463 ifmr->ifm_active = mii->mii_media_active;
464 ifmr->ifm_status = mii->mii_media_status;
465 }
466
467 static uint8_t
468 mue_eeprom_getbyte(struct mue_softc *sc, int off, uint8_t *dest)
469 {
470 uint32_t val;
471
472 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY, 0)) {
473 MUE_PRINTF(sc, "not ready\n");
474 return ETIMEDOUT;
475 }
476
477 mue_csr_write(sc, MUE_E2P_CMD, MUE_E2P_CMD_READ | MUE_E2P_CMD_BUSY |
478 (off & MUE_E2P_CMD_ADDR_MASK));
479
480 if (MUE_WAIT_CLR(sc, MUE_E2P_CMD, MUE_E2P_CMD_BUSY,
481 MUE_E2P_CMD_TIMEOUT)) {
482 MUE_PRINTF(sc, "timed out\n");
483 return ETIMEDOUT;
484 }
485
486 val = mue_csr_read(sc, MUE_E2P_DATA);
487 *dest = val & 0xff;
488
489 return 0;
490 }
491
492 static int
493 mue_read_eeprom(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
494 {
495 uint32_t val = 0; /* XXX gcc */
496 uint8_t byte;
497 int i, err;
498
499 /*
500 * EEPROM pins are muxed with the LED function on LAN7800 device.
501 */
502 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800) {
503 val = mue_csr_read(sc, MUE_HW_CFG);
504 mue_csr_write(sc, MUE_HW_CFG,
505 val & ~(MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN));
506 }
507
508 for (i = 0; i < cnt; i++) {
509 err = mue_eeprom_getbyte(sc, off + i, &byte);
510 if (err)
511 break;
512 *(dest + i) = byte;
513 }
514
515 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800)
516 mue_csr_write(sc, MUE_HW_CFG, val);
517
518 return err ? 1 : 0;
519 }
520
521 static bool
522 mue_eeprom_present(struct mue_softc *sc)
523 {
524 uint32_t val;
525 uint8_t sig;
526 int ret;
527
528 if (sc->mue_flags & LAN7500) {
529 val = mue_csr_read(sc, MUE_E2P_CMD);
530 return val & MUE_E2P_CMD_LOADED;
531 } else {
532 ret = mue_read_eeprom(sc, &sig, MUE_E2P_IND_OFFSET, 1);
533 return (ret == 0) && (sig == MUE_E2P_IND);
534 }
535 }
536
537 static int
538 mue_read_otp_raw(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
539 {
540 uint32_t val;
541 int i, err;
542
543 val = mue_csr_read(sc, MUE_OTP_PWR_DN);
544
545 /* Checking if bit is set. */
546 if (val & MUE_OTP_PWR_DN_PWRDN_N) {
547 /* Clear it, then wait for it to be cleared. */
548 mue_csr_write(sc, MUE_OTP_PWR_DN, 0);
549 err = MUE_WAIT_CLR(sc, MUE_OTP_PWR_DN, MUE_OTP_PWR_DN_PWRDN_N,
550 0);
551 if (err) {
552 MUE_PRINTF(sc, "not ready\n");
553 return 1;
554 }
555 }
556
557 /* Start reading the bytes, one at a time. */
558 for (i = 0; i < cnt; i++) {
559 mue_csr_write(sc, MUE_OTP_ADDR1,
560 ((off + i) >> 8) & MUE_OTP_ADDR1_MASK);
561 mue_csr_write(sc, MUE_OTP_ADDR2,
562 ((off + i) & MUE_OTP_ADDR2_MASK));
563 mue_csr_write(sc, MUE_OTP_FUNC_CMD, MUE_OTP_FUNC_CMD_READ);
564 mue_csr_write(sc, MUE_OTP_CMD_GO, MUE_OTP_CMD_GO_GO);
565
566 err = MUE_WAIT_CLR(sc, MUE_OTP_STATUS, MUE_OTP_STATUS_BUSY, 0);
567 if (err) {
568 MUE_PRINTF(sc, "timed out\n");
569 return 1;
570 }
571 val = mue_csr_read(sc, MUE_OTP_RD_DATA);
572 *(dest + i) = (uint8_t)(val & 0xff);
573 }
574
575 return 0;
576 }
577
578 static int
579 mue_read_otp(struct mue_softc *sc, uint8_t *dest, int off, int cnt)
580 {
581 uint8_t sig;
582 int err;
583
584 if (sc->mue_flags & LAN7500)
585 return 1;
586
587 err = mue_read_otp_raw(sc, &sig, MUE_OTP_IND_OFFSET, 1);
588 if (err)
589 return 1;
590 switch (sig) {
591 case MUE_OTP_IND_1:
592 break;
593 case MUE_OTP_IND_2:
594 off += 0x100;
595 break;
596 default:
597 DPRINTF(sc, "OTP not found\n");
598 return 1;
599 }
600 err = mue_read_otp_raw(sc, dest, off, cnt);
601 return err;
602 }
603
604 static void
605 mue_dataport_write(struct mue_softc *sc, uint32_t sel, uint32_t addr,
606 uint32_t cnt, uint32_t *data)
607 {
608 uint32_t i;
609
610 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
611 MUE_PRINTF(sc, "not ready\n");
612 return;
613 }
614
615 mue_csr_write(sc, MUE_DP_SEL,
616 (mue_csr_read(sc, MUE_DP_SEL) & ~MUE_DP_SEL_RSEL_MASK) | sel);
617
618 for (i = 0; i < cnt; i++) {
619 mue_csr_write(sc, MUE_DP_ADDR, addr + i);
620 mue_csr_write(sc, MUE_DP_DATA, data[i]);
621 mue_csr_write(sc, MUE_DP_CMD, MUE_DP_CMD_WRITE);
622 if (MUE_WAIT_SET(sc, MUE_DP_SEL, MUE_DP_SEL_DPRDY, 0)) {
623 MUE_PRINTF(sc, "timed out\n");
624 return;
625 }
626 }
627 }
628
629 static void
630 mue_init_ltm(struct mue_softc *sc)
631 {
632 uint32_t idx[MUE_NUM_LTM_INDEX] = { 0, 0, 0, 0, 0, 0 };
633 uint8_t temp[2];
634 size_t i;
635
636 if (mue_csr_read(sc, MUE_USB_CFG1) & MUE_USB_CFG1_LTM_ENABLE) {
637 if (mue_eeprom_present(sc) &&
638 (mue_read_eeprom(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0)) {
639 if (temp[0] != sizeof(idx)) {
640 DPRINTF(sc, "EEPROM: unexpected size\n");
641 goto done;
642 }
643 if (mue_read_eeprom(sc, (uint8_t *)idx, temp[1] << 1,
644 sizeof(idx))) {
645 DPRINTF(sc, "EEPROM read failed\n");
646 goto done;
647 }
648 DPRINTF(sc, "success\n");
649 } else if (mue_read_otp(sc, temp, MUE_E2P_LTM_OFFSET, 2) == 0) {
650 if (temp[0] != sizeof(idx)) {
651 DPRINTF(sc, "OTP: unexpected size\n");
652 goto done;
653 }
654 if (mue_read_otp(sc, (uint8_t *)idx, temp[1] << 1,
655 sizeof(idx))) {
656 DPRINTF(sc, "OTP read failed\n");
657 goto done;
658 }
659 DPRINTF(sc, "success\n");
660 } else {
661 DPRINTF(sc, "nothing to do\n");
662 }
663 } else {
664 DPRINTF(sc, "nothing to do\n");
665 }
666 done:
667 for (i = 0; i < __arraycount(idx); i++)
668 mue_csr_write(sc, MUE_LTM_INDEX(i), idx[i]);
669 }
670
671 static int
672 mue_chip_init(struct mue_softc *sc)
673 {
674 uint32_t val;
675
676 if ((sc->mue_flags & LAN7500) &&
677 MUE_WAIT_SET(sc, MUE_PMT_CTL, MUE_PMT_CTL_READY, 0)) {
678 MUE_PRINTF(sc, "not ready\n");
679 return ETIMEDOUT;
680 }
681
682 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_LRST);
683 if (MUE_WAIT_CLR(sc, MUE_HW_CFG, MUE_HW_CFG_LRST, 0)) {
684 MUE_PRINTF(sc, "timed out\n");
685 return ETIMEDOUT;
686 }
687
688 /* Respond to the IN token with a NAK. */
689 if (sc->mue_flags & LAN7500)
690 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BIR);
691 else
692 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BIR);
693
694 if (sc->mue_flags & LAN7500) {
695 if (sc->mue_udev->ud_speed == USB_SPEED_HIGH)
696 val = MUE_7500_HS_RX_BUFSIZE /
697 MUE_HS_USB_PKT_SIZE;
698 else
699 val = MUE_7500_FS_RX_BUFSIZE /
700 MUE_FS_USB_PKT_SIZE;
701 mue_csr_write(sc, MUE_7500_BURST_CAP, val);
702 mue_csr_write(sc, MUE_7500_BULKIN_DELAY,
703 MUE_7500_DEFAULT_BULKIN_DELAY);
704
705 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_BCE | MUE_HW_CFG_MEF);
706
707 /* Set FIFO sizes. */
708 val = (MUE_7500_MAX_RX_FIFO_SIZE - 512) / 512;
709 mue_csr_write(sc, MUE_7500_FCT_RX_FIFO_END, val);
710 val = (MUE_7500_MAX_TX_FIFO_SIZE - 512) / 512;
711 mue_csr_write(sc, MUE_7500_FCT_TX_FIFO_END, val);
712 } else {
713 /* Init LTM. */
714 mue_init_ltm(sc);
715
716 val = MUE_7800_RX_BUFSIZE;
717 switch (sc->mue_udev->ud_speed) {
718 case USB_SPEED_SUPER:
719 val /= MUE_SS_USB_PKT_SIZE;
720 break;
721 case USB_SPEED_HIGH:
722 val /= MUE_HS_USB_PKT_SIZE;
723 break;
724 default:
725 val /= MUE_FS_USB_PKT_SIZE;
726 break;
727 }
728 mue_csr_write(sc, MUE_7800_BURST_CAP, val);
729 mue_csr_write(sc, MUE_7800_BULKIN_DELAY,
730 MUE_7800_DEFAULT_BULKIN_DELAY);
731
732 MUE_SETBIT(sc, MUE_HW_CFG, MUE_HW_CFG_MEF);
733 MUE_SETBIT(sc, MUE_USB_CFG0, MUE_USB_CFG0_BCE);
734
735 /*
736 * Set FCL's RX and TX FIFO sizes: according to data sheet this
737 * is already the default value. But we initialize it to the
738 * same value anyways, as that's what the Linux driver does.
739 */
740 val = (MUE_7800_MAX_RX_FIFO_SIZE - 512) / 512;
741 mue_csr_write(sc, MUE_7800_FCT_RX_FIFO_END, val);
742 val = (MUE_7800_MAX_TX_FIFO_SIZE - 512) / 512;
743 mue_csr_write(sc, MUE_7800_FCT_TX_FIFO_END, val);
744 }
745
746 /* Enabling interrupts. */
747 mue_csr_write(sc, MUE_INT_STATUS, ~0);
748
749 mue_csr_write(sc, (sc->mue_flags & LAN7500) ?
750 MUE_7500_FCT_FLOW : MUE_7800_FCT_FLOW, 0);
751 mue_csr_write(sc, MUE_FLOW, 0);
752
753 /* Reset PHY. */
754 MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST);
755 if (MUE_WAIT_CLR(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST, 0)) {
756 MUE_PRINTF(sc, "PHY not ready\n");
757 return ETIMEDOUT;
758 }
759
760 /* LAN7801 only has RGMII mode. */
761 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7801)
762 MUE_CLRBIT(sc, MUE_MAC_CR, MUE_MAC_CR_GMII_EN);
763
764 if ((sc->mue_flags & LAN7500) ||
765 (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
766 !mue_eeprom_present(sc))) {
767 /* Allow MAC to detect speed and duplex from PHY. */
768 MUE_SETBIT(sc, MUE_MAC_CR, MUE_MAC_CR_AUTO_SPEED |
769 MUE_MAC_CR_AUTO_DUPLEX);
770 }
771
772 MUE_SETBIT(sc, MUE_MAC_TX, MUE_MAC_TX_TXEN);
773 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
774 MUE_7500_FCT_TX_CTL : MUE_7800_FCT_TX_CTL, MUE_FCT_TX_CTL_EN);
775
776 /* Set the maximum frame size. */
777 MUE_CLRBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
778 val = mue_csr_read(sc, MUE_MAC_RX);
779 val &= ~MUE_MAC_RX_MAX_SIZE_MASK;
780 val |= MUE_MAC_RX_MAX_LEN(ETHER_MAX_LEN);
781 mue_csr_write(sc, MUE_MAC_RX, val);
782 MUE_SETBIT(sc, MUE_MAC_RX, MUE_MAC_RX_RXEN);
783
784 MUE_SETBIT(sc, (sc->mue_flags & LAN7500) ?
785 MUE_7500_FCT_RX_CTL : MUE_7800_FCT_RX_CTL, MUE_FCT_RX_CTL_EN);
786
787 /* Set default GPIO/LED settings only if no EEPROM is detected. */
788 if ((sc->mue_flags & LAN7500) && !mue_eeprom_present(sc)) {
789 MUE_CLRBIT(sc, MUE_LED_CFG, MUE_LED_CFG_LED10_FUN_SEL);
790 MUE_SETBIT(sc, MUE_LED_CFG,
791 MUE_LED_CFG_LEDGPIO_EN | MUE_LED_CFG_LED2_FUN_SEL);
792 }
793
794 /* XXX We assume two LEDs at least when EEPROM is missing. */
795 if (sc->mue_product == USB_PRODUCT_SMSC_LAN7800 &&
796 !mue_eeprom_present(sc))
797 MUE_SETBIT(sc, MUE_HW_CFG,
798 MUE_HW_CFG_LED0_EN | MUE_HW_CFG_LED1_EN);
799
800 return 0;
801 }
802
803 static void
804 mue_set_macaddr(struct mue_softc *sc)
805 {
806 struct ifnet *ifp = GET_IFP(sc);
807 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
808 uint32_t lo, hi;
809
810 lo = MUE_ENADDR_LO(enaddr);
811 hi = MUE_ENADDR_HI(enaddr);
812
813 mue_csr_write(sc, MUE_RX_ADDRL, lo);
814 mue_csr_write(sc, MUE_RX_ADDRH, hi);
815 }
816
817 static int
818 mue_get_macaddr(struct mue_softc *sc, prop_dictionary_t dict)
819 {
820 prop_data_t eaprop;
821 uint32_t low, high;
822
823 if (!(sc->mue_flags & LAN7500)) {
824 low = mue_csr_read(sc, MUE_RX_ADDRL);
825 high = mue_csr_read(sc, MUE_RX_ADDRH);
826 sc->mue_enaddr[5] = (uint8_t)((high >> 8) & 0xff);
827 sc->mue_enaddr[4] = (uint8_t)((high) & 0xff);
828 sc->mue_enaddr[3] = (uint8_t)((low >> 24) & 0xff);
829 sc->mue_enaddr[2] = (uint8_t)((low >> 16) & 0xff);
830 sc->mue_enaddr[1] = (uint8_t)((low >> 8) & 0xff);
831 sc->mue_enaddr[0] = (uint8_t)((low) & 0xff);
832 if (ETHER_IS_VALID(sc->mue_enaddr))
833 return 0;
834 else {
835 DPRINTF(sc, "registers: %s\n",
836 ether_sprintf(sc->mue_enaddr));
837 }
838 }
839
840 if (mue_eeprom_present(sc) && !mue_read_eeprom(sc, sc->mue_enaddr,
841 MUE_E2P_MAC_OFFSET, ETHER_ADDR_LEN)) {
842 if (ETHER_IS_VALID(sc->mue_enaddr))
843 return 0;
844 else {
845 DPRINTF(sc, "EEPROM: %s\n",
846 ether_sprintf(sc->mue_enaddr));
847 }
848 }
849
850 if (mue_read_otp(sc, sc->mue_enaddr, MUE_OTP_MAC_OFFSET,
851 ETHER_ADDR_LEN) == 0) {
852 if (ETHER_IS_VALID(sc->mue_enaddr))
853 return 0;
854 else {
855 DPRINTF(sc, "OTP: %s\n",
856 ether_sprintf(sc->mue_enaddr));
857 }
858 }
859
860 /*
861 * Other MD methods. This should be tried only if other methods fail.
862 * Otherwise, MAC address for internal device can be assinged to
863 * external devices on Raspberry Pi, for example.
864 */
865 eaprop = prop_dictionary_get(dict, "mac-address");
866 if (eaprop != NULL) {
867 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA);
868 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN);
869 memcpy(sc->mue_enaddr, prop_data_data_nocopy(eaprop),
870 ETHER_ADDR_LEN);
871 if (ETHER_IS_VALID(sc->mue_enaddr))
872 return 0;
873 else {
874 DPRINTF(sc, "prop_dictionary_get: %s\n",
875 ether_sprintf(sc->mue_enaddr));
876 }
877 }
878
879 return 1;
880 }
881
882
883 /*
884 * Probe for a Microchip chip. */
885 static int
886 mue_match(device_t parent, cfdata_t match, void *aux)
887 {
888 struct usb_attach_arg *uaa = aux;
889
890 return (MUE_LOOKUP(uaa) != NULL) ? UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
891 }
892
893 static void
894 mue_attach(device_t parent, device_t self, void *aux)
895 {
896 struct mue_softc *sc = device_private(self);
897 prop_dictionary_t dict = device_properties(self);
898 struct usb_attach_arg *uaa = aux;
899 struct usbd_device *dev = uaa->uaa_device;
900 usb_interface_descriptor_t *id;
901 usb_endpoint_descriptor_t *ed;
902 char *devinfop;
903 struct mii_data *mii;
904 struct ifnet *ifp;
905 usbd_status err;
906 int i, s;
907
908 aprint_naive("\n");
909 aprint_normal("\n");
910
911 sc->mue_dev = self;
912 sc->mue_udev = dev;
913
914 devinfop = usbd_devinfo_alloc(sc->mue_udev, 0);
915 aprint_normal_dev(self, "%s\n", devinfop);
916 usbd_devinfo_free(devinfop);
917
918 #define MUE_CONFIG_NO 1
919 err = usbd_set_config_no(dev, MUE_CONFIG_NO, 1);
920 if (err) {
921 aprint_error_dev(self, "failed to set configuration: %s\n",
922 usbd_errstr(err));
923 return;
924 }
925
926 mutex_init(&sc->mue_mii_lock, MUTEX_DEFAULT, IPL_NONE);
927 usb_init_task(&sc->mue_tick_task, mue_tick_task, sc, 0);
928 usb_init_task(&sc->mue_stop_task, (void (*)(void *))mue_stop, sc, 0);
929
930 #define MUE_IFACE_IDX 0
931 err = usbd_device2interface_handle(dev, MUE_IFACE_IDX, &sc->mue_iface);
932 if (err) {
933 aprint_error_dev(self, "failed to get interface handle: %s\n",
934 usbd_errstr(err));
935 return;
936 }
937
938 sc->mue_product = uaa->uaa_product;
939 sc->mue_flags = MUE_LOOKUP(uaa)->mue_flags;
940
941 /* Decide on what our bufsize will be. */
942 if (sc->mue_flags & LAN7500)
943 sc->mue_rxbufsz = (sc->mue_udev->ud_speed == USB_SPEED_HIGH) ?
944 MUE_7500_HS_RX_BUFSIZE : MUE_7500_FS_RX_BUFSIZE;
945 else
946 sc->mue_rxbufsz = MUE_7800_RX_BUFSIZE;
947 sc->mue_txbufsz = MUE_TX_BUFSIZE;
948
949 /* Find endpoints. */
950 id = usbd_get_interface_descriptor(sc->mue_iface);
951 for (i = 0; i < id->bNumEndpoints; i++) {
952 ed = usbd_interface2endpoint_descriptor(sc->mue_iface, i);
953 if (ed == NULL) {
954 aprint_error_dev(self, "couldn't get ep %d\n", i);
955 return;
956 }
957 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
958 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
959 sc->mue_ed[MUE_ENDPT_RX] = ed->bEndpointAddress;
960 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT &&
961 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) {
962 sc->mue_ed[MUE_ENDPT_TX] = ed->bEndpointAddress;
963 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN &&
964 UE_GET_XFERTYPE(ed->bmAttributes) == UE_INTERRUPT) {
965 sc->mue_ed[MUE_ENDPT_INTR] = ed->bEndpointAddress;
966 }
967 }
968 KASSERT(sc->mue_ed[MUE_ENDPT_RX] != 0);
969 KASSERT(sc->mue_ed[MUE_ENDPT_TX] != 0);
970 KASSERT(sc->mue_ed[MUE_ENDPT_INTR] != 0);
971
972 s = splnet();
973
974 sc->mue_phyno = 1;
975
976 if (mue_chip_init(sc)) {
977 aprint_error_dev(self, "chip initialization failed\n");
978 splx(s);
979 return;
980 }
981
982 /* A Microchip chip was detected. Inform the world. */
983 if (sc->mue_flags & LAN7500)
984 aprint_normal_dev(self, "LAN7500\n");
985 else
986 aprint_normal_dev(self, "LAN7800\n");
987
988 if (mue_get_macaddr(sc, dict)) {
989 aprint_error_dev(self, "Ethernet address assigned randomly\n");
990 cprng_fast(sc->mue_enaddr, ETHER_ADDR_LEN);
991 sc->mue_enaddr[0] &= ~0x01; /* unicast */
992 sc->mue_enaddr[0] |= 0x02; /* locally administered */
993 }
994
995 aprint_normal_dev(self, "Ethernet address %s\n",
996 ether_sprintf(sc->mue_enaddr));
997
998 /* Initialize interface info.*/
999 ifp = GET_IFP(sc);
1000 ifp->if_softc = sc;
1001 strlcpy(ifp->if_xname, device_xname(sc->mue_dev), IFNAMSIZ);
1002 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1003 ifp->if_init = mue_init;
1004 ifp->if_ioctl = mue_ioctl;
1005 ifp->if_start = mue_start;
1006 ifp->if_stop = mue_stop;
1007 ifp->if_watchdog = mue_watchdog;
1008
1009 IFQ_SET_READY(&ifp->if_snd);
1010
1011 ifp->if_capabilities = IFCAP_TSOv4 | IFCAP_TSOv6;
1012
1013 sc->mue_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
1014
1015 /* Initialize MII/media info. */
1016 mii = GET_MII(sc);
1017 mii->mii_ifp = ifp;
1018 mii->mii_readreg = mue_miibus_readreg;
1019 mii->mii_writereg = mue_miibus_writereg;
1020 mii->mii_statchg = mue_miibus_statchg;
1021 mii->mii_flags = MIIF_AUTOTSLEEP;
1022
1023 sc->mue_ec.ec_mii = mii;
1024 ifmedia_init(&mii->mii_media, 0, mue_ifmedia_upd, mue_ifmedia_sts);
1025 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1026
1027 if (LIST_FIRST(&mii->mii_phys) == NULL) {
1028 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1029 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1030 } else
1031 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1032
1033 /* Attach the interface. */
1034 if_attach(ifp);
1035 ether_ifattach(ifp, sc->mue_enaddr);
1036
1037 rnd_attach_source(&sc->mue_rnd_source, device_xname(sc->mue_dev),
1038 RND_TYPE_NET, RND_FLAG_DEFAULT);
1039
1040 callout_init(&sc->mue_stat_ch, 0);
1041
1042 splx(s);
1043
1044 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->mue_udev, sc->mue_dev);
1045 }
1046
1047 static int
1048 mue_detach(device_t self, int flags)
1049 {
1050 struct mue_softc *sc = device_private(self);
1051 struct ifnet *ifp = GET_IFP(sc);
1052 size_t i;
1053 int s;
1054
1055 sc->mue_dying = true;
1056
1057 callout_halt(&sc->mue_stat_ch, NULL);
1058
1059 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1060 if (sc->mue_ep[i] != NULL)
1061 usbd_abort_pipe(sc->mue_ep[i]);
1062
1063 /*
1064 * Remove any pending tasks. They cannot be executing because they run
1065 * in the same thread as detach.
1066 */
1067 usb_rem_task_wait(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER,
1068 NULL);
1069 usb_rem_task_wait(sc->mue_udev, &sc->mue_stop_task, USB_TASKQ_DRIVER,
1070 NULL);
1071
1072 s = splusb();
1073
1074 if (ifp->if_flags & IFF_RUNNING)
1075 mue_stop(ifp, 1);
1076
1077 rnd_detach_source(&sc->mue_rnd_source);
1078 mii_detach(&sc->mue_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1079 ifmedia_delete_instance(&sc->mue_mii.mii_media, IFM_INST_ANY);
1080 if (ifp->if_softc != NULL) {
1081 ether_ifdetach(ifp);
1082 if_detach(ifp);
1083 }
1084
1085 if (--sc->mue_refcnt >= 0) {
1086 /* Wait for processes to go away. */
1087 usb_detach_waitold(sc->mue_dev);
1088 }
1089 splx(s);
1090
1091 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->mue_udev, sc->mue_dev);
1092
1093 mutex_destroy(&sc->mue_mii_lock);
1094
1095 return 0;
1096 }
1097
1098 static int
1099 mue_activate(device_t self, enum devact act)
1100 {
1101 struct mue_softc *sc = device_private(self);
1102 struct ifnet *ifp = GET_IFP(sc);
1103
1104 switch (act) {
1105 case DVACT_DEACTIVATE:
1106 if_deactivate(ifp);
1107 sc->mue_dying = true;
1108 return 0;
1109 default:
1110 return EOPNOTSUPP;
1111 }
1112 return 0;
1113 }
1114
1115 static int
1116 mue_rx_list_init(struct mue_softc *sc)
1117 {
1118 struct mue_cdata *cd;
1119 struct mue_chain *c;
1120 size_t i;
1121 int err;
1122
1123 cd = &sc->mue_cdata;
1124 for (i = 0; i < __arraycount(cd->mue_rx_chain); i++) {
1125 c = &cd->mue_rx_chain[i];
1126 c->mue_sc = sc;
1127 c->mue_idx = i;
1128 if (c->mue_xfer == NULL) {
1129 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_RX],
1130 sc->mue_rxbufsz, 0, 0, &c->mue_xfer);
1131 if (err)
1132 return err;
1133 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1134 }
1135 }
1136
1137 return 0;
1138 }
1139
1140 static int
1141 mue_tx_list_init(struct mue_softc *sc)
1142 {
1143 struct mue_cdata *cd;
1144 struct mue_chain *c;
1145 size_t i;
1146 int err;
1147
1148 cd = &sc->mue_cdata;
1149 for (i = 0; i < __arraycount(cd->mue_tx_chain); i++) {
1150 c = &cd->mue_tx_chain[i];
1151 c->mue_sc = sc;
1152 c->mue_idx = i;
1153 if (c->mue_xfer == NULL) {
1154 err = usbd_create_xfer(sc->mue_ep[MUE_ENDPT_TX],
1155 sc->mue_txbufsz, USBD_FORCE_SHORT_XFER, 0,
1156 &c->mue_xfer);
1157 if (err)
1158 return err;
1159 c->mue_buf = usbd_get_buffer(c->mue_xfer);
1160 }
1161 }
1162
1163 return 0;
1164 }
1165
1166 static int
1167 mue_open_pipes(struct mue_softc *sc)
1168 {
1169 usbd_status err;
1170
1171 /* Open RX and TX pipes. */
1172 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_RX],
1173 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_RX]);
1174 if (err) {
1175 MUE_PRINTF(sc, "rx pipe: %s\n", usbd_errstr(err));
1176 return EIO;
1177 }
1178 err = usbd_open_pipe(sc->mue_iface, sc->mue_ed[MUE_ENDPT_TX],
1179 USBD_EXCLUSIVE_USE, &sc->mue_ep[MUE_ENDPT_TX]);
1180 if (err) {
1181 MUE_PRINTF(sc, "tx pipe: %s\n", usbd_errstr(err));
1182 return EIO;
1183 }
1184 return 0;
1185 }
1186
1187 static void
1188 mue_start_rx(struct mue_softc *sc)
1189 {
1190 struct mue_chain *c;
1191 size_t i;
1192
1193 /* Start up the receive pipe. */
1194 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++) {
1195 c = &sc->mue_cdata.mue_rx_chain[i];
1196 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, sc->mue_rxbufsz,
1197 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1198 usbd_transfer(c->mue_xfer);
1199 }
1200 }
1201
1202 static int
1203 mue_encap(struct mue_softc *sc, struct mbuf *m, int idx)
1204 {
1205 struct ifnet *ifp = GET_IFP(sc);
1206 struct mue_chain *c;
1207 usbd_status err;
1208 struct mue_txbuf_hdr hdr;
1209 int len;
1210
1211 c = &sc->mue_cdata.mue_tx_chain[idx];
1212
1213 hdr.tx_cmd_a = htole32((m->m_pkthdr.len & MUE_TX_CMD_A_LEN_MASK) |
1214 MUE_TX_CMD_A_FCS);
1215
1216 if (m->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) {
1217 hdr.tx_cmd_a |= htole32(MUE_TX_CMD_A_LSO);
1218 if (__predict_true(m->m_pkthdr.segsz > MUE_TX_MSS_MIN))
1219 hdr.tx_cmd_b = htole32(m->m_pkthdr.segsz <<
1220 MUE_TX_CMD_B_MSS_SHIFT);
1221 else
1222 hdr.tx_cmd_b = htole32(MUE_TX_MSS_MIN <<
1223 MUE_TX_CMD_B_MSS_SHIFT);
1224 hdr.tx_cmd_b &= htole32(MUE_TX_CMD_B_MSS_MASK);
1225 mue_tx_offload(sc, m);
1226 } else
1227 hdr.tx_cmd_b = 0;
1228
1229 memcpy(c->mue_buf, &hdr, sizeof(hdr));
1230 len = sizeof(hdr);
1231
1232 KASSERTMSG((unsigned)(len + m->m_pkthdr.len) <= sc->mue_txbufsz,
1233 "%d <= %u", len + m->m_pkthdr.len, sc->mue_txbufsz);
1234
1235 m_copydata(m, 0, m->m_pkthdr.len, c->mue_buf + len);
1236 len += m->m_pkthdr.len;
1237
1238 usbd_setup_xfer(c->mue_xfer, c, c->mue_buf, len,
1239 USBD_FORCE_SHORT_XFER, 10000, mue_txeof);
1240
1241 /* Transmit */
1242 err = usbd_transfer(c->mue_xfer);
1243 if (__predict_false(err != USBD_IN_PROGRESS)) {
1244 DPRINTF(sc, "%s\n", usbd_errstr(err));
1245 mue_stop(ifp, 0);
1246 return EIO;
1247 }
1248
1249 sc->mue_cdata.mue_tx_cnt++;
1250
1251 return 0;
1252 }
1253
1254 static void
1255 mue_tx_offload(struct mue_softc *sc, struct mbuf *m)
1256 {
1257 struct ether_header *eh;
1258 struct ip *ip;
1259 struct ip6_hdr *ip6;
1260 int offset;
1261 bool v4;
1262
1263 eh = mtod(m, struct ether_header *);
1264 switch (htons(eh->ether_type)) {
1265 case ETHERTYPE_IP:
1266 case ETHERTYPE_IPV6:
1267 offset = ETHER_HDR_LEN;
1268 break;
1269 case ETHERTYPE_VLAN:
1270 /* XXX not yet supported */
1271 offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1272 break;
1273 default:
1274 /* XXX */
1275 panic("%s: unsupported ethertype\n", __func__);
1276 /* NOTREACHED */
1277 }
1278
1279 v4 = (m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
1280
1281 #ifdef DIAGNOSTIC /* XXX */
1282 int hlen = offset;
1283 if (v4)
1284 hlen += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data);
1285 else
1286 hlen += M_CSUM_DATA_IPv6_IPHL(m->m_pkthdr.csum_data);
1287 KASSERT(m->m_len >= (int)(hlen + sizeof(struct tcphdr)));
1288 #endif
1289
1290 /* Packet length should be cleared. */
1291 if (v4) {
1292 ip = (void *)(mtod(m, char *) + offset);
1293 ip->ip_len = 0;
1294 } else {
1295 ip6 = (void *)(mtod(m, char *) + offset);
1296 ip6->ip6_plen = 0;
1297 }
1298 }
1299
1300 static void
1301 mue_setmulti(struct mue_softc *sc)
1302 {
1303 struct ifnet *ifp = GET_IFP(sc);
1304 const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
1305 struct ether_multi *enm;
1306 struct ether_multistep step;
1307 uint32_t pfiltbl[MUE_NUM_ADDR_FILTX][2];
1308 uint32_t hashtbl[MUE_DP_SEL_VHF_HASH_LEN];
1309 uint32_t reg, rxfilt, h, hireg, loreg;
1310 int i;
1311
1312 if (sc->mue_dying)
1313 return;
1314
1315 /* Clear perfect filter and hash tables. */
1316 memset(pfiltbl, 0, sizeof(pfiltbl));
1317 memset(hashtbl, 0, sizeof(hashtbl));
1318
1319 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1320 rxfilt = mue_csr_read(sc, reg);
1321 rxfilt &= ~(MUE_RFE_CTL_PERFECT | MUE_RFE_CTL_MULTICAST_HASH |
1322 MUE_RFE_CTL_UNICAST | MUE_RFE_CTL_MULTICAST);
1323
1324 /* Always accept broadcast frames. */
1325 rxfilt |= MUE_RFE_CTL_BROADCAST;
1326
1327 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1328 allmulti: rxfilt |= MUE_RFE_CTL_MULTICAST;
1329 if (ifp->if_flags & IFF_PROMISC) {
1330 rxfilt |= MUE_RFE_CTL_UNICAST;
1331 DPRINTF(sc, "promisc\n");
1332 } else {
1333 DPRINTF(sc, "allmulti\n");
1334 }
1335 } else {
1336 /* Now program new ones. */
1337 pfiltbl[0][0] = MUE_ENADDR_HI(enaddr) | MUE_ADDR_FILTX_VALID;
1338 pfiltbl[0][1] = MUE_ENADDR_LO(enaddr);
1339 i = 1;
1340 ETHER_FIRST_MULTI(step, &sc->mue_ec, enm);
1341 while (enm != NULL) {
1342 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1343 ETHER_ADDR_LEN)) {
1344 memset(pfiltbl, 0, sizeof(pfiltbl));
1345 memset(hashtbl, 0, sizeof(hashtbl));
1346 rxfilt &= ~MUE_RFE_CTL_MULTICAST_HASH;
1347 goto allmulti;
1348 }
1349 if (i < MUE_NUM_ADDR_FILTX) {
1350 /* Use perfect address table if possible. */
1351 pfiltbl[i][0] = MUE_ENADDR_HI(enm->enm_addrlo) |
1352 MUE_ADDR_FILTX_VALID;
1353 pfiltbl[i][1] = MUE_ENADDR_LO(enm->enm_addrlo);
1354 } else {
1355 /* Otherwise, use hash table. */
1356 rxfilt |= MUE_RFE_CTL_MULTICAST_HASH;
1357 h = (ether_crc32_be(enm->enm_addrlo,
1358 ETHER_ADDR_LEN) >> 23) & 0x1ff;
1359 hashtbl[h / 32] |= 1 << (h % 32);
1360 }
1361 i++;
1362 ETHER_NEXT_MULTI(step, enm);
1363 }
1364 rxfilt |= MUE_RFE_CTL_PERFECT;
1365 if (rxfilt & MUE_RFE_CTL_MULTICAST_HASH) {
1366 DPRINTF(sc, "perfect filter and hash tables\n");
1367 } else {
1368 DPRINTF(sc, "perfect filter\n");
1369 }
1370 }
1371
1372 for (i = 0; i < MUE_NUM_ADDR_FILTX; i++) {
1373 hireg = (sc->mue_flags & LAN7500) ?
1374 MUE_7500_ADDR_FILTX(i) : MUE_7800_ADDR_FILTX(i);
1375 loreg = hireg + 4;
1376 mue_csr_write(sc, hireg, 0);
1377 mue_csr_write(sc, loreg, pfiltbl[i][1]);
1378 mue_csr_write(sc, hireg, pfiltbl[i][0]);
1379 }
1380
1381 mue_dataport_write(sc, MUE_DP_SEL_VHF, MUE_DP_SEL_VHF_VLAN_LEN,
1382 MUE_DP_SEL_VHF_HASH_LEN, hashtbl);
1383
1384 mue_csr_write(sc, reg, rxfilt);
1385 }
1386
1387 static void
1388 mue_sethwcsum(struct mue_softc *sc)
1389 {
1390 struct ifnet *ifp = GET_IFP(sc);
1391 uint32_t reg, val;
1392
1393 reg = (sc->mue_flags & LAN7500) ? MUE_7500_RFE_CTL : MUE_7800_RFE_CTL;
1394 val = mue_csr_read(sc, reg);
1395
1396 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) {
1397 DPRINTF(sc, "enabled\n");;
1398 val |= MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE;
1399 val |= MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE;
1400 } else {
1401 DPRINTF(sc, "disabled\n");;
1402 val &=
1403 ~(MUE_RFE_CTL_IGMP_COE | MUE_RFE_CTL_ICMP_COE);
1404 val &=
1405 ~(MUE_RFE_CTL_TCPUDP_COE | MUE_RFE_CTL_IP_COE);
1406 }
1407
1408 val &= ~MUE_RFE_CTL_VLAN_FILTER;
1409
1410 mue_csr_write(sc, reg, val);
1411 }
1412
1413
1414 static void
1415 mue_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1416 {
1417 struct mue_chain *c = (struct mue_chain *)priv;
1418 struct mue_softc *sc = c->mue_sc;
1419 struct ifnet *ifp = GET_IFP(sc);
1420 struct mbuf *m;
1421 struct mue_rxbuf_hdr *hdrp;
1422 uint32_t rx_cmd_a, total_len;
1423 uint16_t pktlen;
1424 int s;
1425 char *buf = c->mue_buf;
1426
1427 if (__predict_false(sc->mue_dying)) {
1428 DPRINTF(sc, "dying\n");
1429 return;
1430 }
1431
1432 if (__predict_false(!(ifp->if_flags & IFF_RUNNING))) {
1433 DPRINTF(sc, "not running\n");
1434 return;
1435 }
1436
1437 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1438 DPRINTF(sc, "%s\n", usbd_errstr(status));
1439 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1440 return;
1441 if (usbd_ratecheck(&sc->mue_rx_notice))
1442 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1443 if (status == USBD_STALLED)
1444 usbd_clear_endpoint_stall_async(
1445 sc->mue_ep[MUE_ENDPT_RX]);
1446 goto done;
1447 }
1448
1449 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
1450
1451 KASSERTMSG(total_len <= sc->mue_rxbufsz, "%d <= %u",
1452 total_len, sc->mue_rxbufsz);
1453
1454 do {
1455 if (__predict_false(total_len < sizeof(*hdrp))) {
1456 DPRINTF(sc, "too short transfer\n");
1457 ifp->if_ierrors++;
1458 goto done;
1459 }
1460
1461 hdrp = (struct mue_rxbuf_hdr *)buf;
1462 rx_cmd_a = le32toh(hdrp->rx_cmd_a);
1463
1464 if (__predict_false(rx_cmd_a & MUE_RX_CMD_A_RED)) {
1465 DPRINTF(sc, "rx_cmd_a: 0x%x\n", rx_cmd_a);
1466 ifp->if_ierrors++;
1467 goto done;
1468 }
1469
1470 /* XXX not yet */
1471 KASSERT((rx_cmd_a & MUE_RX_CMD_A_ICSM) == 0);
1472
1473 pktlen = (uint16_t)(rx_cmd_a & MUE_RX_CMD_A_LEN_MASK);
1474 if (sc->mue_flags & LAN7500)
1475 pktlen -= 2;
1476
1477 if (__predict_false(pktlen < ETHER_HDR_LEN ||
1478 pktlen > MCLBYTES - ETHER_ALIGN ||
1479 pktlen + sizeof(*hdrp) > total_len)) {
1480 DPRINTF(sc, "bad pktlen\n");
1481 ifp->if_ierrors++;
1482 goto done;
1483 }
1484
1485 m = mue_newbuf();
1486 if (__predict_false(m == NULL)) {
1487 DPRINTF(sc, "mbuf allocation failed\n");
1488 ifp->if_ierrors++;
1489 goto done;
1490 }
1491
1492 m_set_rcvif(m, ifp);
1493 m->m_pkthdr.len = m->m_len = pktlen;
1494 m->m_flags |= M_HASFCS;
1495 memcpy(mtod(m, char *), buf + sizeof(*hdrp), pktlen);
1496
1497 /* Attention: sizeof(hdr) = 10 */
1498 pktlen = roundup(pktlen + sizeof(*hdrp), 4);
1499 if (pktlen > total_len)
1500 pktlen = total_len;
1501 total_len -= pktlen;
1502 buf += pktlen;
1503
1504 s = splnet();
1505 if_percpuq_enqueue(ifp->if_percpuq, m);
1506 splx(s);
1507 } while (total_len > 0);
1508
1509 done:
1510 /* Setup new transfer. */
1511 usbd_setup_xfer(xfer, c, c->mue_buf, sc->mue_rxbufsz,
1512 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, mue_rxeof);
1513 usbd_transfer(xfer);
1514 }
1515
1516 static void
1517 mue_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1518 {
1519 struct mue_chain *c = priv;
1520 struct mue_softc *sc = c->mue_sc;
1521 struct ifnet *ifp = GET_IFP(sc);
1522 int s;
1523
1524 if (__predict_false(sc->mue_dying))
1525 return;
1526
1527 s = splnet();
1528
1529
1530 if (__predict_false(status != USBD_NORMAL_COMPLETION)) {
1531 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
1532 splx(s);
1533 return;
1534 }
1535 ifp->if_oerrors++;
1536 MUE_PRINTF(sc, "%s\n", usbd_errstr(status));
1537 if (status == USBD_STALLED)
1538 usbd_clear_endpoint_stall_async(
1539 sc->mue_ep[MUE_ENDPT_TX]);
1540 splx(s);
1541 return;
1542 }
1543
1544 ifp->if_timer = 0;
1545 ifp->if_flags &= ~IFF_OACTIVE;
1546
1547 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1548 mue_start(ifp);
1549
1550 ifp->if_opackets++;
1551 splx(s);
1552 }
1553
1554 static int
1555 mue_init(struct ifnet *ifp)
1556 {
1557 struct mue_softc *sc = ifp->if_softc;
1558 int s;
1559
1560 if (sc->mue_dying) {
1561 DPRINTF(sc, "dying\n");
1562 return EIO;
1563 }
1564
1565 s = splnet();
1566
1567 /* Cancel pending I/O and free all TX/RX buffers. */
1568 if (ifp->if_flags & IFF_RUNNING)
1569 mue_stop(ifp, 1);
1570
1571 mue_reset(sc);
1572
1573 /* Set MAC address. */
1574 mue_set_macaddr(sc);
1575
1576 /* Load the multicast filter. */
1577 mue_setmulti(sc);
1578
1579 /* TCP/UDP checksum offload engines. */
1580 mue_sethwcsum(sc);
1581
1582 if (mue_open_pipes(sc)) {
1583 splx(s);
1584 return EIO;
1585 }
1586
1587 /* Init RX ring. */
1588 if (mue_rx_list_init(sc)) {
1589 MUE_PRINTF(sc, "rx list init failed\n");
1590 splx(s);
1591 return ENOBUFS;
1592 }
1593
1594 /* Init TX ring. */
1595 if (mue_tx_list_init(sc)) {
1596 MUE_PRINTF(sc, "tx list init failed\n");
1597 splx(s);
1598 return ENOBUFS;
1599 }
1600
1601 mue_start_rx(sc);
1602
1603 ifp->if_flags |= IFF_RUNNING;
1604 ifp->if_flags &= ~IFF_OACTIVE;
1605
1606 splx(s);
1607
1608 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1609
1610 return 0;
1611 }
1612
1613 static int
1614 mue_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1615 {
1616 struct mue_softc *sc = ifp->if_softc;
1617 struct ifreq /*const*/ *ifr = data;
1618 int s, error = 0;
1619
1620 s = splnet();
1621
1622 switch(cmd) {
1623 case SIOCSIFFLAGS:
1624 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1625 break;
1626
1627 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1628 case IFF_RUNNING:
1629 mue_stop(ifp, 1);
1630 break;
1631 case IFF_UP:
1632 mue_init(ifp);
1633 break;
1634 case IFF_UP | IFF_RUNNING:
1635 if ((ifp->if_flags ^ sc->mue_if_flags) == IFF_PROMISC)
1636 mue_setmulti(sc);
1637 else
1638 mue_init(ifp);
1639 break;
1640 }
1641 sc->mue_if_flags = ifp->if_flags;
1642 break;
1643 case SIOCGIFMEDIA:
1644 case SIOCSIFMEDIA:
1645 error = ifmedia_ioctl(ifp, ifr, &sc->mue_mii.mii_media, cmd);
1646 break;
1647 default:
1648 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
1649 break;
1650 error = 0;
1651 if (cmd == SIOCADDMULTI || cmd == SIOCDELMULTI)
1652 mue_setmulti(sc);
1653 break;
1654 }
1655 splx(s);
1656
1657 return error;
1658 }
1659
1660 static void
1661 mue_watchdog(struct ifnet *ifp)
1662 {
1663 struct mue_softc *sc = ifp->if_softc;
1664 struct mue_chain *c;
1665 usbd_status stat;
1666 int s;
1667
1668 ifp->if_oerrors++;
1669 MUE_PRINTF(sc, "timed out\n");
1670
1671 s = splusb();
1672 c = &sc->mue_cdata.mue_tx_chain[0];
1673 usbd_get_xfer_status(c->mue_xfer, NULL, NULL, NULL, &stat);
1674 mue_txeof(c->mue_xfer, c, stat);
1675
1676 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1677 mue_start(ifp);
1678 splx(s);
1679 }
1680
1681 static void
1682 mue_reset(struct mue_softc *sc)
1683 {
1684 if (sc->mue_dying)
1685 return;
1686
1687 /* Wait a little while for the chip to get its brains in order. */
1688 usbd_delay_ms(sc->mue_udev, 1);
1689
1690 // mue_chip_init(sc); /* XXX */
1691 }
1692
1693 static void
1694 mue_start(struct ifnet *ifp)
1695 {
1696 struct mue_softc *sc = ifp->if_softc;
1697 struct mbuf *m;
1698
1699 if (__predict_false(!sc->mue_link)) {
1700 DPRINTF(sc, "no link\n");
1701 return;
1702 }
1703
1704 if (__predict_false((ifp->if_flags & (IFF_OACTIVE|IFF_RUNNING))
1705 != IFF_RUNNING)) {
1706 DPRINTF(sc, "not ready\n");
1707 return;
1708 }
1709
1710 IFQ_POLL(&ifp->if_snd, m);
1711 if (m == NULL)
1712 return;
1713
1714 if (__predict_false(mue_encap(sc, m, 0))) {
1715 DPRINTF(sc, "encap failed\n");
1716 ifp->if_flags |= IFF_OACTIVE;
1717 return;
1718 }
1719 IFQ_DEQUEUE(&ifp->if_snd, m);
1720
1721 bpf_mtap(ifp, m, BPF_D_OUT);
1722 m_freem(m);
1723
1724 ifp->if_flags |= IFF_OACTIVE;
1725
1726 /* Set a timeout in case the chip goes out to lunch. */
1727 ifp->if_timer = 5;
1728 }
1729
1730 static void
1731 mue_stop(struct ifnet *ifp, int disable __unused)
1732 {
1733 struct mue_softc *sc = ifp->if_softc;
1734 usbd_status err;
1735 size_t i;
1736
1737 mue_reset(sc);
1738
1739 ifp->if_timer = 0;
1740 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1741
1742 callout_stop(&sc->mue_stat_ch);
1743
1744 /* Stop transfers. */
1745 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1746 if (sc->mue_ep[i] != NULL) {
1747 err = usbd_abort_pipe(sc->mue_ep[i]);
1748 if (err)
1749 MUE_PRINTF(sc, "abort pipe %zu: %s\n",
1750 i, usbd_errstr(err));
1751 }
1752
1753 /* Free RX resources. */
1754 for (i = 0; i < __arraycount(sc->mue_cdata.mue_rx_chain); i++)
1755 if (sc->mue_cdata.mue_rx_chain[i].mue_xfer != NULL) {
1756 usbd_destroy_xfer(
1757 sc->mue_cdata.mue_rx_chain[i].mue_xfer);
1758 sc->mue_cdata.mue_rx_chain[i].mue_xfer = NULL;
1759 }
1760
1761 /* Free TX resources. */
1762 for (i = 0; i < __arraycount(sc->mue_cdata.mue_tx_chain); i++)
1763 if (sc->mue_cdata.mue_tx_chain[i].mue_xfer != NULL) {
1764 usbd_destroy_xfer(
1765 sc->mue_cdata.mue_tx_chain[i].mue_xfer);
1766 sc->mue_cdata.mue_tx_chain[i].mue_xfer = NULL;
1767 }
1768
1769 /* Close pipes */
1770 for (i = 0; i < __arraycount(sc->mue_ep); i++)
1771 if (sc->mue_ep[i] != NULL) {
1772 err = usbd_close_pipe(sc->mue_ep[i]);
1773 if (err)
1774 MUE_PRINTF(sc, "close pipe %zu: %s\n",
1775 i, usbd_errstr(err));
1776 sc->mue_ep[i] = NULL;
1777 }
1778
1779 sc->mue_link = 0; /* XXX */
1780
1781 DPRINTF(sc, "done\n");
1782 }
1783
1784 static void
1785 mue_tick(void *xsc)
1786 {
1787 struct mue_softc *sc = xsc;
1788
1789 if (sc == NULL)
1790 return;
1791
1792 if (sc->mue_dying)
1793 return;
1794
1795 /* Perform periodic stuff in process context. */
1796 usb_add_task(sc->mue_udev, &sc->mue_tick_task, USB_TASKQ_DRIVER);
1797 }
1798
1799 static void
1800 mue_tick_task(void *xsc)
1801 {
1802 struct mue_softc *sc = xsc;
1803 struct ifnet *ifp = GET_IFP(sc);
1804 struct mii_data *mii = GET_MII(sc);
1805 int s;
1806
1807 if (sc == NULL)
1808 return;
1809
1810 if (sc->mue_dying)
1811 return;
1812
1813 s = splnet();
1814 mii_tick(mii);
1815 if (sc->mue_link == 0)
1816 mue_miibus_statchg(ifp);
1817 callout_reset(&sc->mue_stat_ch, hz, mue_tick, sc);
1818 splx(s);
1819 }
1820
1821 static struct mbuf *
1822 mue_newbuf(void)
1823 {
1824 struct mbuf *m;
1825
1826 MGETHDR(m, M_DONTWAIT, MT_DATA);
1827 if (__predict_false(m == NULL))
1828 return NULL;
1829
1830 MCLGET(m, M_DONTWAIT);
1831 if (__predict_false(!(m->m_flags & M_EXT))) {
1832 m_freem(m);
1833 return NULL;
1834 }
1835
1836 m_adj(m, ETHER_ALIGN);
1837
1838 return m;
1839 }
1840