if_otus.c revision 1.1
1 /* $OpenBSD: if_otus.c,v 1.18 2010/08/27 17:08:00 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini (at) free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /*- 20 * Driver for Atheros AR9001U chipset. 21 * http://www.atheros.com/pt/bulletins/AR9001USBBulletin.pdf 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/timeout.h> 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 36 #include <machine/bus.h> 37 #include <machine/endian.h> 38 #include <machine/intr.h> 39 40 #if NBPFILTER > 0 41 #include <net/bpf.h> 42 #endif 43 #include <net/if.h> 44 #include <net/if_arp.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 #include <net/if_types.h> 48 49 #include <netinet/in.h> 50 #include <netinet/in_systm.h> 51 #include <netinet/in_var.h> 52 #include <netinet/if_ether.h> 53 #include <netinet/ip.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_amrr.h> 57 #include <net80211/ieee80211_radiotap.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdi_util.h> 62 #include <dev/usb/usbdevs.h> 63 64 #include <dev/usb/if_otusreg.h> 65 66 #ifdef USB_DEBUG 67 #define OTUS_DEBUG 68 #endif 69 70 #ifdef OTUS_DEBUG 71 #define DPRINTF(x) do { if (otus_debug) printf x; } while (0) 72 #define DPRINTFN(n, x) do { if (otus_debug >= (n)) printf x; } while (0) 73 int otus_debug = 1; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n, x) 77 #endif 78 79 static const struct usb_devno otus_devs[] = { 80 { USB_VENDOR_ACCTON, USB_PRODUCT_ACCTON_WN7512 }, 81 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_3CRUSBN275 }, 82 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_TG121N }, 83 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_AR9170 }, 84 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN612 }, 85 { USB_VENDOR_ATHEROS2, USB_PRODUCT_ATHEROS2_WN821NV2 }, 86 { USB_VENDOR_AVM, USB_PRODUCT_AVM_FRITZWLAN }, 87 { USB_VENDOR_CACE, USB_PRODUCT_CACE_AIRPCAPNX }, 88 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA130D1 }, 89 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A1 }, 90 { USB_VENDOR_DLINK2, USB_PRODUCT_DLINK2_DWA160A2 }, 91 { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNGDNUS2 }, 92 { USB_VENDOR_NEC, USB_PRODUCT_NEC_WL300NUG }, 93 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WN111V2 }, 94 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000 }, 95 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNDA3100 }, 96 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_GW_US300 }, 97 { USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_O8494 }, 98 { USB_VENDOR_WISTRONNEWEB, USB_PRODUCT_WISTRONNEWEB_WNC0600 }, 99 { USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB81 }, 100 { USB_VENDOR_ZCOM, USB_PRODUCT_ZCOM_UB82 }, 101 { USB_VENDOR_ZYDAS, USB_PRODUCT_ZYDAS_ZD1221 }, 102 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_NWD271N } 103 }; 104 105 int otus_match(struct device *, void *, void *); 106 void otus_attach(struct device *, struct device *, void *); 107 int otus_detach(struct device *, int); 108 void otus_attachhook(void *); 109 void otus_get_chanlist(struct otus_softc *); 110 int otus_load_firmware(struct otus_softc *, const char *, 111 uint32_t); 112 int otus_open_pipes(struct otus_softc *); 113 void otus_close_pipes(struct otus_softc *); 114 int otus_alloc_tx_cmd(struct otus_softc *); 115 void otus_free_tx_cmd(struct otus_softc *); 116 int otus_alloc_tx_data_list(struct otus_softc *); 117 void otus_free_tx_data_list(struct otus_softc *); 118 int otus_alloc_rx_data_list(struct otus_softc *); 119 void otus_free_rx_data_list(struct otus_softc *); 120 void otus_next_scan(void *); 121 void otus_task(void *); 122 void otus_do_async(struct otus_softc *, 123 void (*)(struct otus_softc *, void *), void *, int); 124 int otus_newstate(struct ieee80211com *, enum ieee80211_state, 125 int); 126 void otus_newstate_cb(struct otus_softc *, void *); 127 int otus_cmd(struct otus_softc *, uint8_t, const void *, int, 128 void *); 129 void otus_write(struct otus_softc *, uint32_t, uint32_t); 130 int otus_write_barrier(struct otus_softc *); 131 struct ieee80211_node *otus_node_alloc(struct ieee80211com *); 132 int otus_media_change(struct ifnet *); 133 int otus_read_eeprom(struct otus_softc *); 134 void otus_newassoc(struct ieee80211com *, struct ieee80211_node *, 135 int); 136 void otus_intr(usbd_xfer_handle, usbd_private_handle, usbd_status); 137 void otus_cmd_rxeof(struct otus_softc *, uint8_t *, int); 138 void otus_sub_rxeof(struct otus_softc *, uint8_t *, int); 139 void otus_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 140 void otus_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status); 141 int otus_tx(struct otus_softc *, struct mbuf *, 142 struct ieee80211_node *); 143 void otus_start(struct ifnet *); 144 void otus_watchdog(struct ifnet *); 145 int otus_ioctl(struct ifnet *, u_long, caddr_t); 146 int otus_set_multi(struct otus_softc *); 147 void otus_updateedca(struct ieee80211com *); 148 void otus_updateedca_cb(struct otus_softc *, void *); 149 void otus_updateslot(struct ieee80211com *); 150 void otus_updateslot_cb(struct otus_softc *, void *); 151 int otus_init_mac(struct otus_softc *); 152 uint32_t otus_phy_get_def(struct otus_softc *, uint32_t); 153 int otus_set_board_values(struct otus_softc *, 154 struct ieee80211_channel *); 155 int otus_program_phy(struct otus_softc *, 156 struct ieee80211_channel *); 157 int otus_set_rf_bank4(struct otus_softc *, 158 struct ieee80211_channel *); 159 void otus_get_delta_slope(uint32_t, uint32_t *, uint32_t *); 160 int otus_set_chan(struct otus_softc *, struct ieee80211_channel *, 161 int); 162 int otus_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164 void otus_set_key_cb(struct otus_softc *, void *); 165 void otus_delete_key(struct ieee80211com *, struct ieee80211_node *, 166 struct ieee80211_key *); 167 void otus_delete_key_cb(struct otus_softc *, void *); 168 void otus_calibrate_to(void *); 169 int otus_set_bssid(struct otus_softc *, const uint8_t *); 170 int otus_set_macaddr(struct otus_softc *, const uint8_t *); 171 void otus_led_newstate_type1(struct otus_softc *); 172 void otus_led_newstate_type2(struct otus_softc *); 173 void otus_led_newstate_type3(struct otus_softc *); 174 int otus_init(struct ifnet *); 175 void otus_stop(struct ifnet *); 176 177 struct cfdriver otus_cd = { 178 NULL, "otus", DV_IFNET 179 }; 180 181 const struct cfattach otus_ca = { 182 sizeof (struct otus_softc), otus_match, otus_attach, otus_detach 183 }; 184 185 int 186 otus_match(struct device *parent, void *match, void *aux) 187 { 188 struct usb_attach_arg *uaa = aux; 189 190 if (uaa->iface != NULL) 191 return UMATCH_NONE; 192 193 return (usb_lookup(otus_devs, uaa->vendor, uaa->product) != NULL) ? 194 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 195 } 196 197 void 198 otus_attach(struct device *parent, struct device *self, void *aux) 199 { 200 struct otus_softc *sc = (struct otus_softc *)self; 201 struct usb_attach_arg *uaa = aux; 202 int error; 203 204 sc->sc_udev = uaa->device; 205 206 usb_init_task(&sc->sc_task, otus_task, sc); 207 timeout_set(&sc->scan_to, otus_next_scan, sc); 208 timeout_set(&sc->calib_to, otus_calibrate_to, sc); 209 210 sc->amrr.amrr_min_success_threshold = 1; 211 sc->amrr.amrr_max_success_threshold = 10; 212 213 if (usbd_set_config_no(sc->sc_udev, 1, 0) != 0) { 214 printf("%s: could not set configuration no\n", 215 sc->sc_dev.dv_xname); 216 return; 217 } 218 219 /* Get the first interface handle. */ 220 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 221 if (error != 0) { 222 printf("%s: could not get interface handle\n", 223 sc->sc_dev.dv_xname); 224 return; 225 } 226 227 if ((error = otus_open_pipes(sc)) != 0) { 228 printf("%s: could not open pipes\n", sc->sc_dev.dv_xname); 229 return; 230 } 231 232 if (rootvp == NULL) 233 mountroothook_establish(otus_attachhook, sc); 234 else 235 otus_attachhook(sc); 236 237 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, &sc->sc_dev); 238 } 239 240 int 241 otus_detach(struct device *self, int flags) 242 { 243 struct otus_softc *sc = (struct otus_softc *)self; 244 struct ifnet *ifp = &sc->sc_ic.ic_if; 245 int s; 246 247 s = splnet(); 248 249 /* Wait for all queued asynchronous commands to complete. */ 250 while (sc->cmdq.queued > 0) 251 tsleep(&sc->cmdq, 0, "cmdq", 0); 252 253 timeout_del(&sc->scan_to); 254 timeout_del(&sc->calib_to); 255 256 if (ifp->if_flags != 0) { /* if_attach() has been called. */ 257 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 258 ieee80211_ifdetach(ifp); 259 if_detach(ifp); 260 } 261 262 otus_close_pipes(sc); 263 264 splx(s); 265 266 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, &sc->sc_dev); 267 268 return 0; 269 } 270 271 void 272 otus_attachhook(void *xsc) 273 { 274 struct otus_softc *sc = xsc; 275 struct ieee80211com *ic = &sc->sc_ic; 276 struct ifnet *ifp = &ic->ic_if; 277 usb_device_request_t req; 278 uint32_t in, out; 279 int error; 280 281 error = otus_load_firmware(sc, "otus-init", AR_FW_INIT_ADDR); 282 if (error != 0) { 283 printf("%s: could not load %s firmware\n", 284 sc->sc_dev.dv_xname, "init"); 285 return; 286 } 287 288 usbd_delay_ms(sc->sc_udev, 1000); 289 290 error = otus_load_firmware(sc, "otus-main", AR_FW_MAIN_ADDR); 291 if (error != 0) { 292 printf("%s: could not load %s firmware\n", 293 sc->sc_dev.dv_xname, "main"); 294 return; 295 } 296 297 /* Tell device that firmware transfer is complete. */ 298 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 299 req.bRequest = AR_FW_DOWNLOAD_COMPLETE; 300 USETW(req.wValue, 0); 301 USETW(req.wIndex, 0); 302 USETW(req.wLength, 0); 303 if (usbd_do_request(sc->sc_udev, &req, NULL) != 0) { 304 printf("%s: firmware initialization failed\n", 305 sc->sc_dev.dv_xname); 306 return; 307 } 308 309 /* Send an ECHO command to check that everything is settled. */ 310 in = 0xbadc0ffe; 311 if (otus_cmd(sc, AR_CMD_ECHO, &in, sizeof in, &out) != 0) { 312 printf("%s: echo command failed\n", sc->sc_dev.dv_xname); 313 return; 314 } 315 if (in != out) { 316 printf("%s: echo reply mismatch: 0x%08x!=0x%08x\n", 317 sc->sc_dev.dv_xname, in, out); 318 return; 319 } 320 321 /* Read entire EEPROM. */ 322 if (otus_read_eeprom(sc) != 0) { 323 printf("%s: could not read EEPROM\n", sc->sc_dev.dv_xname); 324 return; 325 } 326 327 sc->txmask = sc->eeprom.baseEepHeader.txMask; 328 sc->rxmask = sc->eeprom.baseEepHeader.rxMask; 329 sc->capflags = sc->eeprom.baseEepHeader.opCapFlags; 330 IEEE80211_ADDR_COPY(ic->ic_myaddr, sc->eeprom.baseEepHeader.macAddr); 331 sc->sc_led_newstate = otus_led_newstate_type3; /* XXX */ 332 333 printf("%s: MAC/BBP AR9170, RF AR%X, MIMO %dT%dR, address %s\n", 334 sc->sc_dev.dv_xname, (sc->capflags & AR5416_OPFLAGS_11A) ? 335 0x9104 : ((sc->txmask == 0x5) ? 0x9102 : 0x9101), 336 (sc->txmask == 0x5) ? 2 : 1, (sc->rxmask == 0x5) ? 2 : 1, 337 ether_sprintf(ic->ic_myaddr)); 338 339 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 340 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 341 ic->ic_state = IEEE80211_S_INIT; 342 343 /* Set device capabilities. */ 344 ic->ic_caps = 345 IEEE80211_C_MONITOR | /* monitor mode supported */ 346 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 347 IEEE80211_C_SHSLOT | /* short slot time supported */ 348 IEEE80211_C_WEP | /* WEP */ 349 IEEE80211_C_RSN; /* WPA/RSN */ 350 351 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 352 /* Set supported .11b and .11g rates. */ 353 ic->ic_sup_rates[IEEE80211_MODE_11B] = 354 ieee80211_std_rateset_11b; 355 ic->ic_sup_rates[IEEE80211_MODE_11G] = 356 ieee80211_std_rateset_11g; 357 } 358 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 359 /* Set supported .11a rates. */ 360 ic->ic_sup_rates[IEEE80211_MODE_11A] = 361 ieee80211_std_rateset_11a; 362 } 363 364 /* Build the list of supported channels. */ 365 otus_get_chanlist(sc); 366 367 ifp->if_softc = sc; 368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 369 ifp->if_ioctl = otus_ioctl; 370 ifp->if_start = otus_start; 371 ifp->if_watchdog = otus_watchdog; 372 IFQ_SET_READY(&ifp->if_snd); 373 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 374 375 if_attach(ifp); 376 ieee80211_ifattach(ifp); 377 ic->ic_node_alloc = otus_node_alloc; 378 ic->ic_newassoc = otus_newassoc; 379 ic->ic_updateslot = otus_updateslot; 380 ic->ic_updateedca = otus_updateedca; 381 #ifdef notyet 382 ic->ic_set_key = otus_set_key; 383 ic->ic_delete_key = otus_delete_key; 384 #endif 385 /* Override state transition machine. */ 386 sc->sc_newstate = ic->ic_newstate; 387 ic->ic_newstate = otus_newstate; 388 ieee80211_media_init(ifp, otus_media_change, ieee80211_media_status); 389 390 #if NBPFILTER > 0 391 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 392 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 393 394 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 395 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 396 sc->sc_rxtap.wr_ihdr.it_present = htole32(OTUS_RX_RADIOTAP_PRESENT); 397 398 sc->sc_txtap_len = sizeof sc->sc_txtapu; 399 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 400 sc->sc_txtap.wt_ihdr.it_present = htole32(OTUS_TX_RADIOTAP_PRESENT); 401 #endif 402 } 403 404 void 405 otus_get_chanlist(struct otus_softc *sc) 406 { 407 struct ieee80211com *ic = &sc->sc_ic; 408 uint16_t domain; 409 uint8_t chan; 410 int i; 411 412 /* XXX regulatory domain. */ 413 domain = letoh16(sc->eeprom.baseEepHeader.regDmn[0]); 414 DPRINTF(("regdomain=0x%04x\n", domain)); 415 416 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11G) { 417 for (i = 0; i < 14; i++) { 418 chan = ar_chans[i]; 419 ic->ic_channels[chan].ic_freq = 420 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 421 ic->ic_channels[chan].ic_flags = 422 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 423 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 424 } 425 } 426 if (sc->eeprom.baseEepHeader.opCapFlags & AR5416_OPFLAGS_11A) { 427 for (i = 14; i < nitems(ar_chans); i++) { 428 chan = ar_chans[i]; 429 ic->ic_channels[chan].ic_freq = 430 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 431 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 432 } 433 } 434 } 435 436 int 437 otus_load_firmware(struct otus_softc *sc, const char *name, uint32_t addr) 438 { 439 usb_device_request_t req; 440 size_t size; 441 u_char *fw, *ptr; 442 int mlen, error; 443 444 /* Read firmware image from the filesystem. */ 445 if ((error = loadfirmware(name, &fw, &size)) != 0) { 446 printf("%s: failed loadfirmware of file %s (error %d)\n", 447 sc->sc_dev.dv_xname, name, error); 448 return error; 449 } 450 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 451 req.bRequest = AR_FW_DOWNLOAD; 452 USETW(req.wIndex, 0); 453 454 ptr = fw; 455 addr >>= 8; 456 while (size > 0) { 457 mlen = MIN(size, 4096); 458 459 USETW(req.wValue, addr); 460 USETW(req.wLength, mlen); 461 if (usbd_do_request(sc->sc_udev, &req, ptr) != 0) { 462 error = EIO; 463 break; 464 } 465 addr += mlen >> 8; 466 ptr += mlen; 467 size -= mlen; 468 } 469 free(fw, M_DEVBUF); 470 return error; 471 } 472 473 int 474 otus_open_pipes(struct otus_softc *sc) 475 { 476 usb_endpoint_descriptor_t *ed; 477 int i, isize, error; 478 479 error = usbd_open_pipe(sc->sc_iface, AR_EPT_BULK_RX_NO, 0, 480 &sc->data_rx_pipe); 481 if (error != 0) { 482 printf("%s: could not open Rx bulk pipe\n", 483 sc->sc_dev.dv_xname); 484 goto fail; 485 } 486 487 ed = usbd_get_endpoint_descriptor(sc->sc_iface, AR_EPT_INTR_RX_NO); 488 if (ed == NULL) { 489 printf("%s: could not retrieve Rx intr pipe descriptor\n", 490 sc->sc_dev.dv_xname); 491 goto fail; 492 } 493 isize = UGETW(ed->wMaxPacketSize); 494 if (isize == 0) { 495 printf("%s: invalid Rx intr pipe descriptor\n", 496 sc->sc_dev.dv_xname); 497 goto fail; 498 } 499 sc->ibuf = malloc(isize, M_USBDEV, M_NOWAIT); 500 if (sc->ibuf == NULL) { 501 printf("%s: could not allocate Rx intr buffer\n", 502 sc->sc_dev.dv_xname); 503 goto fail; 504 } 505 error = usbd_open_pipe_intr(sc->sc_iface, AR_EPT_INTR_RX_NO, 506 USBD_SHORT_XFER_OK, &sc->cmd_rx_pipe, sc, sc->ibuf, isize, 507 otus_intr, USBD_DEFAULT_INTERVAL); 508 if (error != 0) { 509 printf("%s: could not open Rx intr pipe\n", 510 sc->sc_dev.dv_xname); 511 goto fail; 512 } 513 514 error = usbd_open_pipe(sc->sc_iface, AR_EPT_BULK_TX_NO, 0, 515 &sc->data_tx_pipe); 516 if (error != 0) { 517 printf("%s: could not open Tx bulk pipe\n", 518 sc->sc_dev.dv_xname); 519 goto fail; 520 } 521 522 error = usbd_open_pipe(sc->sc_iface, AR_EPT_INTR_TX_NO, 0, 523 &sc->cmd_tx_pipe); 524 if (error != 0) { 525 printf("%s: could not open Tx intr pipe\n", 526 sc->sc_dev.dv_xname); 527 goto fail; 528 } 529 530 if (otus_alloc_tx_cmd(sc) != 0) { 531 printf("%s: could not allocate command xfer\n", 532 sc->sc_dev.dv_xname); 533 goto fail; 534 } 535 536 if (otus_alloc_tx_data_list(sc) != 0) { 537 printf("%s: could not allocate Tx xfers\n", 538 sc->sc_dev.dv_xname); 539 goto fail; 540 } 541 542 if (otus_alloc_rx_data_list(sc) != 0) { 543 printf("%s: could not allocate Rx xfers\n", 544 sc->sc_dev.dv_xname); 545 goto fail; 546 } 547 548 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) { 549 struct otus_rx_data *data = &sc->rx_data[i]; 550 551 usbd_setup_xfer(data->xfer, sc->data_rx_pipe, data, data->buf, 552 OTUS_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 553 USBD_NO_TIMEOUT, otus_rxeof); 554 error = usbd_transfer(data->xfer); 555 if (error != USBD_IN_PROGRESS && error != 0) { 556 printf("%s: could not queue Rx xfer\n", 557 sc->sc_dev.dv_xname); 558 goto fail; 559 } 560 } 561 return 0; 562 563 fail: otus_close_pipes(sc); 564 return error; 565 } 566 567 void 568 otus_close_pipes(struct otus_softc *sc) 569 { 570 otus_free_tx_cmd(sc); 571 otus_free_tx_data_list(sc); 572 otus_free_rx_data_list(sc); 573 574 if (sc->data_rx_pipe != NULL) 575 usbd_close_pipe(sc->data_rx_pipe); 576 if (sc->cmd_rx_pipe != NULL) { 577 usbd_abort_pipe(sc->cmd_rx_pipe); 578 usbd_close_pipe(sc->cmd_rx_pipe); 579 } 580 if (sc->ibuf != NULL) 581 free(sc->ibuf, M_USBDEV); 582 if (sc->data_tx_pipe != NULL) 583 usbd_close_pipe(sc->data_tx_pipe); 584 if (sc->cmd_tx_pipe != NULL) 585 usbd_close_pipe(sc->cmd_tx_pipe); 586 } 587 588 int 589 otus_alloc_tx_cmd(struct otus_softc *sc) 590 { 591 struct otus_tx_cmd *cmd = &sc->tx_cmd; 592 593 cmd->xfer = usbd_alloc_xfer(sc->sc_udev); 594 if (cmd->xfer == NULL) { 595 printf("%s: could not allocate xfer\n", 596 sc->sc_dev.dv_xname); 597 return ENOMEM; 598 } 599 cmd->buf = usbd_alloc_buffer(cmd->xfer, OTUS_MAX_TXCMDSZ); 600 if (cmd->buf == NULL) { 601 printf("%s: could not allocate xfer buffer\n", 602 sc->sc_dev.dv_xname); 603 usbd_free_xfer(cmd->xfer); 604 return ENOMEM; 605 } 606 return 0; 607 } 608 609 void 610 otus_free_tx_cmd(struct otus_softc *sc) 611 { 612 /* Make sure no transfers are pending. */ 613 usbd_abort_pipe(sc->cmd_tx_pipe); 614 615 if (sc->tx_cmd.xfer != NULL) 616 usbd_free_xfer(sc->tx_cmd.xfer); 617 } 618 619 int 620 otus_alloc_tx_data_list(struct otus_softc *sc) 621 { 622 struct otus_tx_data *data; 623 int i, error; 624 625 for (i = 0; i < OTUS_TX_DATA_LIST_COUNT; i++) { 626 data = &sc->tx_data[i]; 627 628 data->sc = sc; /* Backpointer for callbacks. */ 629 630 data->xfer = usbd_alloc_xfer(sc->sc_udev); 631 if (data->xfer == NULL) { 632 printf("%s: could not allocate xfer\n", 633 sc->sc_dev.dv_xname); 634 error = ENOMEM; 635 goto fail; 636 } 637 data->buf = usbd_alloc_buffer(data->xfer, OTUS_TXBUFSZ); 638 if (data->buf == NULL) { 639 printf("%s: could not allocate xfer buffer\n", 640 sc->sc_dev.dv_xname); 641 error = ENOMEM; 642 goto fail; 643 } 644 } 645 return 0; 646 647 fail: otus_free_tx_data_list(sc); 648 return error; 649 } 650 651 void 652 otus_free_tx_data_list(struct otus_softc *sc) 653 { 654 int i; 655 656 /* Make sure no transfers are pending. */ 657 usbd_abort_pipe(sc->data_tx_pipe); 658 659 for (i = 0; i < OTUS_TX_DATA_LIST_COUNT; i++) 660 if (sc->tx_data[i].xfer != NULL) 661 usbd_free_xfer(sc->tx_data[i].xfer); 662 } 663 664 int 665 otus_alloc_rx_data_list(struct otus_softc *sc) 666 { 667 struct otus_rx_data *data; 668 int i, error; 669 670 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) { 671 data = &sc->rx_data[i]; 672 673 data->sc = sc; /* Backpointer for callbacks. */ 674 675 data->xfer = usbd_alloc_xfer(sc->sc_udev); 676 if (data->xfer == NULL) { 677 printf("%s: could not allocate xfer\n", 678 sc->sc_dev.dv_xname); 679 error = ENOMEM; 680 goto fail; 681 } 682 data->buf = usbd_alloc_buffer(data->xfer, OTUS_RXBUFSZ); 683 if (data->buf == NULL) { 684 printf("%s: could not allocate xfer buffer\n", 685 sc->sc_dev.dv_xname); 686 error = ENOMEM; 687 goto fail; 688 } 689 } 690 return 0; 691 692 fail: otus_free_rx_data_list(sc); 693 return error; 694 } 695 696 void 697 otus_free_rx_data_list(struct otus_softc *sc) 698 { 699 int i; 700 701 /* Make sure no transfers are pending. */ 702 usbd_abort_pipe(sc->data_rx_pipe); 703 704 for (i = 0; i < OTUS_RX_DATA_LIST_COUNT; i++) 705 if (sc->rx_data[i].xfer != NULL) 706 usbd_free_xfer(sc->rx_data[i].xfer); 707 } 708 709 void 710 otus_next_scan(void *arg) 711 { 712 struct otus_softc *sc = arg; 713 714 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 715 ieee80211_next_scan(&sc->sc_ic.ic_if); 716 } 717 718 void 719 otus_task(void *arg) 720 { 721 struct otus_softc *sc = arg; 722 struct otus_host_cmd_ring *ring = &sc->cmdq; 723 struct otus_host_cmd *cmd; 724 int s; 725 726 /* Process host commands. */ 727 s = splusb(); 728 while (ring->next != ring->cur) { 729 cmd = &ring->cmd[ring->next]; 730 splx(s); 731 /* Callback. */ 732 cmd->cb(sc, cmd->data); 733 s = splusb(); 734 ring->queued--; 735 ring->next = (ring->next + 1) % OTUS_HOST_CMD_RING_COUNT; 736 } 737 wakeup(ring); 738 splx(s); 739 } 740 741 void 742 otus_do_async(struct otus_softc *sc, void (*cb)(struct otus_softc *, void *), 743 void *arg, int len) 744 { 745 struct otus_host_cmd_ring *ring = &sc->cmdq; 746 struct otus_host_cmd *cmd; 747 int s; 748 749 s = splusb(); 750 cmd = &ring->cmd[ring->cur]; 751 cmd->cb = cb; 752 KASSERT(len <= sizeof (cmd->data)); 753 memcpy(cmd->data, arg, len); 754 ring->cur = (ring->cur + 1) % OTUS_HOST_CMD_RING_COUNT; 755 756 /* If there is no pending command already, schedule a task. */ 757 if (++ring->queued == 1) 758 usb_add_task(sc->sc_udev, &sc->sc_task); 759 splx(s); 760 } 761 762 int 763 otus_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 764 { 765 struct otus_softc *sc = ic->ic_softc; 766 struct otus_cmd_newstate cmd; 767 768 /* Do it in a process context. */ 769 cmd.state = nstate; 770 cmd.arg = arg; 771 otus_do_async(sc, otus_newstate_cb, &cmd, sizeof cmd); 772 return 0; 773 } 774 775 void 776 otus_newstate_cb(struct otus_softc *sc, void *arg) 777 { 778 struct otus_cmd_newstate *cmd = arg; 779 struct ieee80211com *ic = &sc->sc_ic; 780 struct ieee80211_node *ni; 781 int s; 782 783 s = splnet(); 784 785 switch (cmd->state) { 786 case IEEE80211_S_INIT: 787 break; 788 789 case IEEE80211_S_SCAN: 790 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 0); 791 timeout_add_msec(&sc->scan_to, 200); 792 break; 793 794 case IEEE80211_S_AUTH: 795 case IEEE80211_S_ASSOC: 796 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 0); 797 break; 798 799 case IEEE80211_S_RUN: 800 (void)otus_set_chan(sc, ic->ic_bss->ni_chan, 1); 801 802 ni = ic->ic_bss; 803 804 if (ic->ic_opmode == IEEE80211_M_STA) { 805 otus_updateslot(ic); 806 otus_set_bssid(sc, ni->ni_bssid); 807 808 /* Fake a join to init the Tx rate. */ 809 otus_newassoc(ic, ni, 1); 810 811 /* Start calibration timer. */ 812 timeout_add_sec(&sc->calib_to, 1); 813 } 814 break; 815 } 816 817 sc->sc_led_newstate(sc); 818 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 819 820 splx(s); 821 } 822 823 int 824 otus_cmd(struct otus_softc *sc, uint8_t code, const void *idata, int ilen, 825 void *odata) 826 { 827 struct otus_tx_cmd *cmd = &sc->tx_cmd; 828 struct ar_cmd_hdr *hdr; 829 int s, xferlen, error; 830 831 /* Always bulk-out a multiple of 4 bytes. */ 832 xferlen = (sizeof (*hdr) + ilen + 3) & ~3; 833 834 hdr = (struct ar_cmd_hdr *)cmd->buf; 835 hdr->code = code; 836 hdr->len = ilen; 837 hdr->token = ++cmd->token; /* Don't care about endianness. */ 838 memcpy((uint8_t *)&hdr[1], idata, ilen); 839 840 DPRINTFN(2, ("sending command code=0x%02x len=%d token=%d\n", 841 code, ilen, hdr->token)); 842 843 s = splusb(); 844 cmd->odata = odata; 845 cmd->done = 0; 846 847 usbd_setup_xfer(cmd->xfer, sc->cmd_tx_pipe, cmd, cmd->buf, xferlen, 848 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, OTUS_CMD_TIMEOUT, NULL); 849 error = usbd_sync_transfer(cmd->xfer); 850 if (error != 0) { 851 splx(s); 852 printf("%s: could not send command 0x%x (error=%s)\n", 853 sc->sc_dev.dv_xname, code, usbd_errstr(error)); 854 return EIO; 855 } 856 if (!cmd->done) 857 error = tsleep(cmd, PCATCH, "otuscmd", hz); 858 cmd->odata = NULL; /* In case answer is received too late. */ 859 splx(s); 860 if (error != 0) { 861 printf("%s: timeout waiting for command 0x%02x reply\n", 862 sc->sc_dev.dv_xname, code); 863 } 864 return error; 865 } 866 867 void 868 otus_write(struct otus_softc *sc, uint32_t reg, uint32_t val) 869 { 870 sc->write_buf[sc->write_idx].reg = htole32(reg); 871 sc->write_buf[sc->write_idx].val = htole32(val); 872 873 if (++sc->write_idx > AR_MAX_WRITE_IDX) 874 (void)otus_write_barrier(sc); 875 } 876 877 int 878 otus_write_barrier(struct otus_softc *sc) 879 { 880 int error; 881 882 if (sc->write_idx == 0) 883 return 0; /* Nothing to flush. */ 884 885 error = otus_cmd(sc, AR_CMD_WREG, sc->write_buf, 886 sizeof (sc->write_buf[0]) * sc->write_idx, NULL); 887 sc->write_idx = 0; 888 return error; 889 } 890 891 struct ieee80211_node * 892 otus_node_alloc(struct ieee80211com *ic) 893 { 894 return malloc(sizeof (struct otus_node), M_DEVBUF, M_NOWAIT | M_ZERO); 895 } 896 897 int 898 otus_media_change(struct ifnet *ifp) 899 { 900 struct otus_softc *sc = ifp->if_softc; 901 struct ieee80211com *ic = &sc->sc_ic; 902 uint8_t rate, ridx; 903 int error; 904 905 error = ieee80211_media_change(ifp); 906 if (error != ENETRESET) 907 return error; 908 909 if (ic->ic_fixed_rate != -1) { 910 rate = ic->ic_sup_rates[ic->ic_curmode]. 911 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 912 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 913 if (otus_rates[ridx].rate == rate) 914 break; 915 sc->fixed_ridx = ridx; 916 } 917 918 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 919 error = otus_init(ifp); 920 921 return error; 922 } 923 924 int 925 otus_read_eeprom(struct otus_softc *sc) 926 { 927 uint32_t regs[8], reg; 928 uint8_t *eep; 929 int i, j, error; 930 931 /* Read EEPROM by blocks of 32 bytes. */ 932 eep = (uint8_t *)&sc->eeprom; 933 reg = AR_EEPROM_OFFSET; 934 for (i = 0; i < sizeof (sc->eeprom) / 32; i++) { 935 for (j = 0; j < 8; j++, reg += 4) 936 regs[j] = htole32(reg); 937 error = otus_cmd(sc, AR_CMD_RREG, regs, sizeof regs, eep); 938 if (error != 0) 939 break; 940 eep += 32; 941 } 942 return error; 943 } 944 945 void 946 otus_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 947 { 948 struct otus_softc *sc = ic->ic_softc; 949 struct otus_node *on = (void *)ni; 950 struct ieee80211_rateset *rs = &ni->ni_rates; 951 uint8_t rate; 952 int ridx, i; 953 954 DPRINTF(("new assoc isnew=%d addr=%s\n", 955 isnew, ether_sprintf(ni->ni_macaddr))); 956 957 ieee80211_amrr_node_init(&sc->amrr, &on->amn); 958 /* Start at lowest available bit-rate, AMRR will raise. */ 959 ni->ni_txrate = 0; 960 961 for (i = 0; i < rs->rs_nrates; i++) { 962 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 963 /* Convert 802.11 rate to hardware rate index. */ 964 for (ridx = 0; ridx <= OTUS_RIDX_MAX; ridx++) 965 if (otus_rates[ridx].rate == rate) 966 break; 967 on->ridx[i] = ridx; 968 DPRINTF(("rate=0x%02x ridx=%d\n", 969 rs->rs_rates[i], on->ridx[i])); 970 } 971 } 972 973 /* ARGSUSED */ 974 void 975 otus_intr(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 976 { 977 #if 0 978 struct otus_softc *sc = priv; 979 int len; 980 981 /* 982 * The Rx intr pipe is unused with current firmware. Notifications 983 * and replies to commands are sent through the Rx bulk pipe instead 984 * (with a magic PLCP header.) 985 */ 986 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 987 DPRINTF(("intr status=%d\n", status)); 988 if (status == USBD_STALLED) 989 usbd_clear_endpoint_stall_async(sc->cmd_rx_pipe); 990 return; 991 } 992 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 993 994 otus_cmd_rxeof(sc, sc->ibuf, len); 995 #endif 996 } 997 998 void 999 otus_cmd_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 1000 { 1001 struct ieee80211com *ic = &sc->sc_ic; 1002 struct otus_tx_cmd *cmd; 1003 struct ar_cmd_hdr *hdr; 1004 int s; 1005 1006 if (__predict_false(len < sizeof (*hdr))) { 1007 DPRINTF(("cmd too small %d\n", len)); 1008 return; 1009 } 1010 hdr = (struct ar_cmd_hdr *)buf; 1011 if (__predict_false(sizeof (*hdr) + hdr->len > len || 1012 sizeof (*hdr) + hdr->len > 64)) { 1013 DPRINTF(("cmd too large %d\n", hdr->len)); 1014 return; 1015 } 1016 1017 if ((hdr->code & 0xc0) != 0xc0) { 1018 DPRINTFN(2, ("received reply code=0x%02x len=%d token=%d\n", 1019 hdr->code, hdr->len, hdr->token)); 1020 cmd = &sc->tx_cmd; 1021 if (__predict_false(hdr->token != cmd->token)) 1022 return; 1023 /* Copy answer into caller's supplied buffer. */ 1024 if (cmd->odata != NULL) 1025 memcpy(cmd->odata, &hdr[1], hdr->len); 1026 cmd->done = 1; 1027 wakeup(cmd); 1028 return; 1029 } 1030 1031 /* Received unsolicited notification. */ 1032 DPRINTF(("received notification code=0x%02x len=%d\n", 1033 hdr->code, hdr->len)); 1034 switch (hdr->code & 0x3f) { 1035 case AR_EVT_BEACON: 1036 break; 1037 case AR_EVT_TX_COMP: 1038 { 1039 struct ar_evt_tx_comp *tx = (struct ar_evt_tx_comp *)&hdr[1]; 1040 struct ieee80211_node *ni; 1041 struct otus_node *on; 1042 1043 DPRINTF(("tx completed %s status=%d phy=0x%x\n", 1044 ether_sprintf(tx->macaddr), letoh16(tx->status), 1045 letoh32(tx->phy))); 1046 s = splnet(); 1047 #ifdef notyet 1048 #ifndef IEEE80211_STA_ONLY 1049 if (ic->ic_opmode != IEEE80211_M_STA) { 1050 ni = ieee80211_find_node(ic, tx->macaddr); 1051 if (__predict_false(ni == NULL)) { 1052 splx(s); 1053 break; 1054 } 1055 } else 1056 #endif 1057 #endif 1058 ni = ic->ic_bss; 1059 /* Update rate control statistics. */ 1060 on = (void *)ni; 1061 /* NB: we do not set the TX_MAC_RATE_PROBING flag. */ 1062 if (__predict_true(tx->status != 0)) 1063 on->amn.amn_retrycnt++; 1064 splx(s); 1065 break; 1066 } 1067 case AR_EVT_TBTT: 1068 break; 1069 } 1070 } 1071 1072 void 1073 otus_sub_rxeof(struct otus_softc *sc, uint8_t *buf, int len) 1074 { 1075 struct ieee80211com *ic = &sc->sc_ic; 1076 struct ifnet *ifp = &ic->ic_if; 1077 struct ieee80211_rxinfo rxi; 1078 struct ieee80211_node *ni; 1079 struct ar_rx_tail *tail; 1080 struct ieee80211_frame *wh; 1081 struct mbuf *m; 1082 uint8_t *plcp; 1083 int s, mlen, align; 1084 1085 if (__predict_false(len < AR_PLCP_HDR_LEN)) { 1086 DPRINTF(("sub-xfer too short %d\n", len)); 1087 return; 1088 } 1089 plcp = buf; 1090 1091 /* All bits in the PLCP header are set to 1 for non-MPDU. */ 1092 if (memcmp(plcp, AR_PLCP_HDR_INTR, AR_PLCP_HDR_LEN) == 0) { 1093 otus_cmd_rxeof(sc, plcp + AR_PLCP_HDR_LEN, 1094 len - AR_PLCP_HDR_LEN); 1095 return; 1096 } 1097 1098 /* Received MPDU. */ 1099 if (__predict_false(len < AR_PLCP_HDR_LEN + sizeof (*tail))) { 1100 DPRINTF(("MPDU too short %d\n", len)); 1101 ifp->if_ierrors++; 1102 return; 1103 } 1104 tail = (struct ar_rx_tail *)(plcp + len - sizeof (*tail)); 1105 1106 /* Discard error frames. */ 1107 if (__predict_false(tail->error != 0)) { 1108 DPRINTF(("error frame 0x%02x\n", tail->error)); 1109 if (tail->error & AR_RX_ERROR_FCS) { 1110 DPRINTFN(3, ("bad FCS\n")); 1111 } else if (tail->error & AR_RX_ERROR_MMIC) { 1112 /* Report Michael MIC failures to net80211. */ 1113 ic->ic_stats.is_rx_locmicfail++; 1114 ieee80211_michael_mic_failure(ic, 0); 1115 } 1116 ifp->if_ierrors++; 1117 return; 1118 } 1119 /* Compute MPDU's length. */ 1120 mlen = len - AR_PLCP_HDR_LEN - sizeof (*tail); 1121 /* Make sure there's room for an 802.11 header + FCS. */ 1122 if (__predict_false(mlen < IEEE80211_MIN_LEN)) { 1123 ifp->if_ierrors++; 1124 return; 1125 } 1126 mlen -= IEEE80211_CRC_LEN; /* strip 802.11 FCS */ 1127 1128 wh = (struct ieee80211_frame *)(plcp + AR_PLCP_HDR_LEN); 1129 /* Provide a 32-bit aligned protocol header to the stack. */ 1130 align = (ieee80211_has_qos(wh) ^ ieee80211_has_addr4(wh)) ? 2 : 0; 1131 1132 MGETHDR(m, M_DONTWAIT, MT_DATA); 1133 if (__predict_false(m == NULL)) { 1134 ifp->if_ierrors++; 1135 return; 1136 } 1137 if (align + mlen > MHLEN) { 1138 MCLGET(m, M_DONTWAIT); 1139 if (__predict_false(!(m->m_flags & M_EXT))) { 1140 ifp->if_ierrors++; 1141 m_freem(m); 1142 return; 1143 } 1144 } 1145 /* Finalize mbuf. */ 1146 m->m_pkthdr.rcvif = ifp; 1147 m->m_data += align; 1148 memcpy(mtod(m, caddr_t), wh, mlen); 1149 m->m_pkthdr.len = m->m_len = mlen; 1150 1151 #if NBPFILTER > 0 1152 if (__predict_false(sc->sc_drvbpf != NULL)) { 1153 struct otus_rx_radiotap_header *tap = &sc->sc_rxtap; 1154 struct mbuf mb; 1155 1156 tap->wr_flags = 0; 1157 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1158 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1159 tap->wr_antsignal = tail->rssi; 1160 tap->wr_rate = 2; /* In case it can't be found below. */ 1161 switch (tail->status & AR_RX_STATUS_MT_MASK) { 1162 case AR_RX_STATUS_MT_CCK: 1163 switch (plcp[0]) { 1164 case 10: tap->wr_rate = 2; break; 1165 case 20: tap->wr_rate = 4; break; 1166 case 55: tap->wr_rate = 11; break; 1167 case 110: tap->wr_rate = 22; break; 1168 } 1169 if (tail->status & AR_RX_STATUS_SHPREAMBLE) 1170 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1171 break; 1172 case AR_RX_STATUS_MT_OFDM: 1173 switch (plcp[0] & 0xf) { 1174 case 0xb: tap->wr_rate = 12; break; 1175 case 0xf: tap->wr_rate = 18; break; 1176 case 0xa: tap->wr_rate = 24; break; 1177 case 0xe: tap->wr_rate = 36; break; 1178 case 0x9: tap->wr_rate = 48; break; 1179 case 0xd: tap->wr_rate = 72; break; 1180 case 0x8: tap->wr_rate = 96; break; 1181 case 0xc: tap->wr_rate = 108; break; 1182 } 1183 break; 1184 } 1185 mb.m_data = (caddr_t)tap; 1186 mb.m_len = sc->sc_rxtap_len; 1187 mb.m_next = m; 1188 mb.m_nextpkt = NULL; 1189 mb.m_type = 0; 1190 mb.m_flags = 0; 1191 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1192 } 1193 #endif 1194 1195 s = splnet(); 1196 ni = ieee80211_find_rxnode(ic, wh); 1197 rxi.rxi_flags = 0; 1198 rxi.rxi_rssi = tail->rssi; 1199 rxi.rxi_tstamp = 0; /* unused */ 1200 ieee80211_input(ifp, m, ni, &rxi); 1201 1202 /* Node is no longer needed. */ 1203 ieee80211_release_node(ic, ni); 1204 splx(s); 1205 } 1206 1207 void 1208 otus_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 1209 { 1210 struct otus_rx_data *data = priv; 1211 struct otus_softc *sc = data->sc; 1212 caddr_t buf = data->buf; 1213 struct ar_rx_head *head; 1214 uint16_t hlen; 1215 int len; 1216 1217 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1218 DPRINTF(("RX status=%d\n", status)); 1219 if (status == USBD_STALLED) 1220 usbd_clear_endpoint_stall_async(sc->data_rx_pipe); 1221 if (status != USBD_CANCELLED) 1222 goto resubmit; 1223 return; 1224 } 1225 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1226 1227 while (len >= sizeof (*head)) { 1228 head = (struct ar_rx_head *)buf; 1229 if (__predict_false(head->tag != htole16(AR_RX_HEAD_TAG))) { 1230 DPRINTF(("tag not valid 0x%x\n", letoh16(head->tag))); 1231 break; 1232 } 1233 hlen = letoh16(head->len); 1234 if (__predict_false(sizeof (*head) + hlen > len)) { 1235 DPRINTF(("xfer too short %d/%d\n", len, hlen)); 1236 break; 1237 } 1238 /* Process sub-xfer. */ 1239 otus_sub_rxeof(sc, (uint8_t *)&head[1], hlen); 1240 1241 /* Next sub-xfer is aligned on a 32-bit boundary. */ 1242 hlen = (sizeof (*head) + hlen + 3) & ~3; 1243 buf += hlen; 1244 len -= hlen; 1245 } 1246 1247 resubmit: 1248 usbd_setup_xfer(xfer, sc->data_rx_pipe, data, data->buf, OTUS_RXBUFSZ, 1249 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, otus_rxeof); 1250 (void)usbd_transfer(data->xfer); 1251 } 1252 1253 void 1254 otus_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) 1255 { 1256 struct otus_tx_data *data = priv; 1257 struct otus_softc *sc = data->sc; 1258 struct ieee80211com *ic = &sc->sc_ic; 1259 struct ifnet *ifp = &ic->ic_if; 1260 int s; 1261 1262 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1263 DPRINTF(("TX status=%d\n", status)); 1264 if (status == USBD_STALLED) 1265 usbd_clear_endpoint_stall_async(sc->data_tx_pipe); 1266 ifp->if_oerrors++; 1267 return; 1268 } 1269 s = splnet(); 1270 sc->tx_queued--; 1271 sc->sc_tx_timer = 0; 1272 ifp->if_flags &= ~IFF_OACTIVE; 1273 otus_start(ifp); 1274 splx(s); 1275 } 1276 1277 int 1278 otus_tx(struct otus_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1279 { 1280 struct ieee80211com *ic = &sc->sc_ic; 1281 struct otus_node *on = (void *)ni; 1282 struct otus_tx_data *data; 1283 struct ieee80211_frame *wh; 1284 struct ieee80211_key *k; 1285 struct ar_tx_head *head; 1286 uint32_t phyctl; 1287 uint16_t macctl, qos; 1288 uint8_t tid, qid; 1289 int error, ridx, hasqos, xferlen; 1290 1291 wh = mtod(m, struct ieee80211_frame *); 1292 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1293 k = ieee80211_get_txkey(ic, wh, ni); 1294 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1295 return ENOBUFS; 1296 wh = mtod(m, struct ieee80211_frame *); 1297 } 1298 1299 if ((hasqos = ieee80211_has_qos(wh))) { 1300 qos = ieee80211_get_qos(wh); 1301 tid = qos & IEEE80211_QOS_TID; 1302 qid = ieee80211_up_to_ac(ic, tid); 1303 } else 1304 qid = EDCA_AC_BE; 1305 1306 /* Pickup a rate index. */ 1307 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1308 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA) 1309 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 1310 OTUS_RIDX_OFDM6 : OTUS_RIDX_CCK1; 1311 else if (ic->ic_fixed_rate != -1) 1312 ridx = sc->fixed_ridx; 1313 else 1314 ridx = on->ridx[ni->ni_txrate]; 1315 1316 phyctl = 0; 1317 macctl = AR_TX_MAC_BACKOFF | AR_TX_MAC_HW_DUR | AR_TX_MAC_QID(qid); 1318 1319 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 1320 (hasqos && ((qos & IEEE80211_QOS_ACK_POLICY_MASK) == 1321 IEEE80211_QOS_ACK_POLICY_NOACK))) 1322 macctl |= AR_TX_MAC_NOACK; 1323 1324 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1325 if (m->m_pkthdr.len + IEEE80211_CRC_LEN >= ic->ic_rtsthreshold) 1326 macctl |= AR_TX_MAC_RTS; 1327 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1328 ridx >= OTUS_RIDX_OFDM6) { 1329 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 1330 macctl |= AR_TX_MAC_CTS; 1331 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 1332 macctl |= AR_TX_MAC_RTS; 1333 } 1334 } 1335 1336 phyctl |= AR_TX_PHY_MCS(otus_rates[ridx].mcs); 1337 if (ridx >= OTUS_RIDX_OFDM6) { 1338 phyctl |= AR_TX_PHY_MT_OFDM; 1339 if (ridx <= OTUS_RIDX_OFDM24) 1340 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 1341 else 1342 phyctl |= AR_TX_PHY_ANTMSK(1); 1343 } else { /* CCK */ 1344 phyctl |= AR_TX_PHY_MT_CCK; 1345 phyctl |= AR_TX_PHY_ANTMSK(sc->txmask); 1346 } 1347 1348 /* Update rate control stats for frames that are ACK'ed. */ 1349 if (!(macctl & AR_TX_MAC_NOACK)) 1350 ((struct otus_node *)ni)->amn.amn_txcnt++; 1351 1352 data = &sc->tx_data[sc->tx_cur]; 1353 /* Fill Tx descriptor. */ 1354 head = (struct ar_tx_head *)data->buf; 1355 head->len = htole16(m->m_pkthdr.len + IEEE80211_CRC_LEN); 1356 head->macctl = htole16(macctl); 1357 head->phyctl = htole32(phyctl); 1358 1359 #if NBPFILTER > 0 1360 if (__predict_false(sc->sc_drvbpf != NULL)) { 1361 struct otus_tx_radiotap_header *tap = &sc->sc_txtap; 1362 struct mbuf mb; 1363 1364 tap->wt_flags = 0; 1365 tap->wt_rate = otus_rates[ridx].rate; 1366 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1367 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1368 1369 mb.m_data = (caddr_t)tap; 1370 mb.m_len = sc->sc_txtap_len; 1371 mb.m_next = m; 1372 mb.m_nextpkt = NULL; 1373 mb.m_type = 0; 1374 mb.m_flags = 0; 1375 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1376 } 1377 #endif 1378 1379 xferlen = sizeof (*head) + m->m_pkthdr.len; 1380 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&head[1]); 1381 m_freem(m); 1382 ieee80211_release_node(ic, ni); 1383 1384 DPRINTFN(5, ("tx queued=%d len=%d mac=0x%04x phy=0x%08x rate=%d\n", 1385 sc->tx_queued, head->len, head->macctl, head->phyctl, 1386 otus_rates[ridx].rate)); 1387 usbd_setup_xfer(data->xfer, sc->data_tx_pipe, data, data->buf, xferlen, 1388 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, OTUS_TX_TIMEOUT, otus_txeof); 1389 error = usbd_transfer(data->xfer); 1390 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 1391 return error; 1392 1393 sc->tx_queued++; 1394 sc->tx_cur = (sc->tx_cur + 1) % OTUS_TX_DATA_LIST_COUNT; 1395 1396 return 0; 1397 } 1398 1399 void 1400 otus_start(struct ifnet *ifp) 1401 { 1402 struct otus_softc *sc = ifp->if_softc; 1403 struct ieee80211com *ic = &sc->sc_ic; 1404 struct ieee80211_node *ni; 1405 struct mbuf *m; 1406 1407 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1408 return; 1409 1410 for (;;) { 1411 if (sc->tx_queued >= OTUS_TX_DATA_LIST_COUNT) { 1412 ifp->if_flags |= IFF_OACTIVE; 1413 break; 1414 } 1415 /* Send pending management frames first. */ 1416 IF_DEQUEUE(&ic->ic_mgtq, m); 1417 if (m != NULL) { 1418 ni = (void *)m->m_pkthdr.rcvif; 1419 goto sendit; 1420 } 1421 if (ic->ic_state != IEEE80211_S_RUN) 1422 break; 1423 1424 /* Encapsulate and send data frames. */ 1425 IFQ_DEQUEUE(&ifp->if_snd, m); 1426 if (m == NULL) 1427 break; 1428 #if NBPFILTER > 0 1429 if (ifp->if_bpf != NULL) 1430 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1431 #endif 1432 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1433 continue; 1434 sendit: 1435 #if NBPFILTER > 0 1436 if (ic->ic_rawbpf != NULL) 1437 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1438 #endif 1439 if (otus_tx(sc, m, ni) != 0) { 1440 ieee80211_release_node(ic, ni); 1441 ifp->if_oerrors++; 1442 continue; 1443 } 1444 1445 sc->sc_tx_timer = 5; 1446 ifp->if_timer = 1; 1447 } 1448 } 1449 1450 void 1451 otus_watchdog(struct ifnet *ifp) 1452 { 1453 struct otus_softc *sc = ifp->if_softc; 1454 1455 ifp->if_timer = 0; 1456 1457 if (sc->sc_tx_timer > 0) { 1458 if (--sc->sc_tx_timer == 0) { 1459 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1460 /* otus_init(ifp); XXX needs a process context! */ 1461 ifp->if_oerrors++; 1462 return; 1463 } 1464 ifp->if_timer = 1; 1465 } 1466 ieee80211_watchdog(ifp); 1467 } 1468 1469 int 1470 otus_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1471 { 1472 struct otus_softc *sc = ifp->if_softc; 1473 struct ieee80211com *ic = &sc->sc_ic; 1474 struct ifaddr *ifa; 1475 struct ifreq *ifr; 1476 int s, error = 0; 1477 1478 s = splnet(); 1479 1480 switch (cmd) { 1481 case SIOCSIFADDR: 1482 ifa = (struct ifaddr *)data; 1483 ifp->if_flags |= IFF_UP; 1484 #ifdef INET 1485 if (ifa->ifa_addr->sa_family == AF_INET) 1486 arp_ifinit(&ic->ic_ac, ifa); 1487 #endif 1488 /* FALLTHROUGH */ 1489 case SIOCSIFFLAGS: 1490 if (ifp->if_flags & IFF_UP) { 1491 if ((ifp->if_flags & IFF_RUNNING) && 1492 ((ifp->if_flags ^ sc->sc_if_flags) & 1493 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1494 otus_set_multi(sc); 1495 } else if (!(ifp->if_flags & IFF_RUNNING)) 1496 otus_init(ifp); 1497 1498 } else if (ifp->if_flags & IFF_RUNNING) 1499 otus_stop(ifp); 1500 1501 sc->sc_if_flags = ifp->if_flags; 1502 break; 1503 case SIOCADDMULTI: 1504 case SIOCDELMULTI: 1505 ifr = (struct ifreq *)data; 1506 error = (cmd == SIOCADDMULTI) ? 1507 ether_addmulti(ifr, &ic->ic_ac) : 1508 ether_delmulti(ifr, &ic->ic_ac); 1509 if (error == ENETRESET) 1510 error = 0; 1511 break; 1512 case SIOCS80211CHANNEL: 1513 error = ieee80211_ioctl(ifp, cmd, data); 1514 if (error == ENETRESET && 1515 ic->ic_opmode == IEEE80211_M_MONITOR) { 1516 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1517 (IFF_UP | IFF_RUNNING)) 1518 otus_set_chan(sc, ic->ic_ibss_chan, 0); 1519 error = 0; 1520 } 1521 break; 1522 default: 1523 error = ieee80211_ioctl(ifp, cmd, data); 1524 } 1525 1526 if (error == ENETRESET) { 1527 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1528 (IFF_UP | IFF_RUNNING)) 1529 otus_init(ifp); 1530 error = 0; 1531 } 1532 1533 splx(s); 1534 return error; 1535 } 1536 1537 int 1538 otus_set_multi(struct otus_softc *sc) 1539 { 1540 struct arpcom *ac = &sc->sc_ic.ic_ac; 1541 struct ifnet *ifp = &ac->ac_if; 1542 struct ether_multi *enm; 1543 struct ether_multistep step; 1544 uint32_t lo, hi; 1545 uint8_t bit; 1546 1547 if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 1548 lo = hi = 0xffffffff; 1549 goto done; 1550 } 1551 lo = hi = 0; 1552 ETHER_FIRST_MULTI(step, ac, enm); 1553 while (enm != NULL) { 1554 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1555 ifp->if_flags |= IFF_ALLMULTI; 1556 lo = hi = 0xffffffff; 1557 goto done; 1558 } 1559 bit = enm->enm_addrlo[5] >> 2; 1560 if (bit < 32) 1561 lo |= 1 << bit; 1562 else 1563 hi |= 1 << (bit - 32); 1564 ETHER_NEXT_MULTI(step, enm); 1565 } 1566 done: 1567 hi |= 1 << 31; /* Make sure the broadcast bit is set. */ 1568 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, lo); 1569 otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hi); 1570 return otus_write_barrier(sc); 1571 } 1572 1573 void 1574 otus_updateedca(struct ieee80211com *ic) 1575 { 1576 /* Do it in a process context. */ 1577 otus_do_async(ic->ic_softc, otus_updateedca_cb, NULL, 0); 1578 } 1579 1580 /* ARGSUSED */ 1581 void 1582 otus_updateedca_cb(struct otus_softc *sc, void *arg) 1583 { 1584 #define EXP2(val) ((1 << (val)) - 1) 1585 #define AIFS(val) ((val) * 9 + 10) 1586 struct ieee80211com *ic = &sc->sc_ic; 1587 const struct ieee80211_edca_ac_params *edca; 1588 int s; 1589 1590 s = splnet(); 1591 1592 edca = (ic->ic_flags & IEEE80211_F_QOS) ? 1593 ic->ic_edca_ac : otus_edca_def; 1594 1595 /* Set CWmin/CWmax values. */ 1596 otus_write(sc, AR_MAC_REG_AC0_CW, 1597 EXP2(edca[EDCA_AC_BE].ac_ecwmax) << 16 | 1598 EXP2(edca[EDCA_AC_BE].ac_ecwmin)); 1599 otus_write(sc, AR_MAC_REG_AC1_CW, 1600 EXP2(edca[EDCA_AC_BK].ac_ecwmax) << 16 | 1601 EXP2(edca[EDCA_AC_BK].ac_ecwmin)); 1602 otus_write(sc, AR_MAC_REG_AC2_CW, 1603 EXP2(edca[EDCA_AC_VI].ac_ecwmax) << 16 | 1604 EXP2(edca[EDCA_AC_VI].ac_ecwmin)); 1605 otus_write(sc, AR_MAC_REG_AC3_CW, 1606 EXP2(edca[EDCA_AC_VO].ac_ecwmax) << 16 | 1607 EXP2(edca[EDCA_AC_VO].ac_ecwmin)); 1608 otus_write(sc, AR_MAC_REG_AC4_CW, /* Special TXQ. */ 1609 EXP2(edca[EDCA_AC_VO].ac_ecwmax) << 16 | 1610 EXP2(edca[EDCA_AC_VO].ac_ecwmin)); 1611 1612 /* Set AIFSN values. */ 1613 otus_write(sc, AR_MAC_REG_AC1_AC0_AIFS, 1614 AIFS(edca[EDCA_AC_VI].ac_aifsn) << 24 | 1615 AIFS(edca[EDCA_AC_BK].ac_aifsn) << 12 | 1616 AIFS(edca[EDCA_AC_BE].ac_aifsn)); 1617 otus_write(sc, AR_MAC_REG_AC3_AC2_AIFS, 1618 AIFS(edca[EDCA_AC_VO].ac_aifsn) << 16 | /* Special TXQ. */ 1619 AIFS(edca[EDCA_AC_VO].ac_aifsn) << 4 | 1620 AIFS(edca[EDCA_AC_VI].ac_aifsn) >> 8); 1621 1622 /* Set TXOP limit. */ 1623 otus_write(sc, AR_MAC_REG_AC1_AC0_TXOP, 1624 edca[EDCA_AC_BK].ac_txoplimit << 16 | 1625 edca[EDCA_AC_BE].ac_txoplimit); 1626 otus_write(sc, AR_MAC_REG_AC3_AC2_TXOP, 1627 edca[EDCA_AC_VO].ac_txoplimit << 16 | 1628 edca[EDCA_AC_VI].ac_txoplimit); 1629 1630 splx(s); 1631 1632 (void)otus_write_barrier(sc); 1633 #undef AIFS 1634 #undef EXP2 1635 } 1636 1637 void 1638 otus_updateslot(struct ieee80211com *ic) 1639 { 1640 /* Do it in a process context. */ 1641 otus_do_async(ic->ic_softc, otus_updateslot_cb, NULL, 0); 1642 } 1643 1644 /* ARGSUSED */ 1645 void 1646 otus_updateslot_cb(struct otus_softc *sc, void *arg) 1647 { 1648 uint32_t slottime; 1649 1650 slottime = (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1651 otus_write(sc, AR_MAC_REG_SLOT_TIME, slottime << 10); 1652 (void)otus_write_barrier(sc); 1653 } 1654 1655 int 1656 otus_init_mac(struct otus_softc *sc) 1657 { 1658 int error; 1659 1660 otus_write(sc, AR_MAC_REG_ACK_EXTENSION, 0x40); 1661 otus_write(sc, AR_MAC_REG_RETRY_MAX, 0); 1662 otus_write(sc, AR_MAC_REG_SNIFFER, 0x2000000); 1663 otus_write(sc, AR_MAC_REG_RX_THRESHOLD, 0xc1f80); 1664 otus_write(sc, AR_MAC_REG_RX_PE_DELAY, 0x70); 1665 otus_write(sc, AR_MAC_REG_EIFS_AND_SIFS, 0xa144000); 1666 otus_write(sc, AR_MAC_REG_SLOT_TIME, 9 << 10); 1667 otus_write(sc, 0x1c3b2c, 0x19000000); 1668 /* NAV protects ACK only (in TXOP). */ 1669 otus_write(sc, 0x1c3b38, 0x201); 1670 /* Set beacon Tx power to 0x7. */ 1671 otus_write(sc, AR_MAC_REG_BCN_HT1, 0x8000170); 1672 otus_write(sc, AR_MAC_REG_BACKOFF_PROTECT, 0x105); 1673 otus_write(sc, 0x1c3b9c, 0x10000a); 1674 /* Filter any control frames, BAR is bit 24. */ 1675 otus_write(sc, 0x1c368c, 0x0500ffff); 1676 otus_write(sc, 0x1c3c40, 0x1); 1677 otus_write(sc, AR_MAC_REG_BASIC_RATE, 0x150f); 1678 otus_write(sc, AR_MAC_REG_MANDATORY_RATE, 0x150f); 1679 otus_write(sc, AR_MAC_REG_RTS_CTS_RATE, 0x10b01bb); 1680 otus_write(sc, 0x1c3694, 0x4003c1e); 1681 /* Enable LED0 and LED1. */ 1682 otus_write(sc, 0x1d0100, 0x3); 1683 otus_write(sc, 0x1d0104, 0x3); 1684 /* Switch MAC to OTUS interface. */ 1685 otus_write(sc, 0x1c3600, 0x3); 1686 otus_write(sc, 0x1c3c50, 0xffff); 1687 otus_write(sc, 0x1c3680, 0xf00008); 1688 /* Disable Rx timeout (workaround). */ 1689 otus_write(sc, 0x1c362c, 0); 1690 1691 /* Set USB Rx stream mode maximum frame number to 2. */ 1692 otus_write(sc, 0x1e1110, 0x4); 1693 /* Set USB Rx stream mode timeout to 10us. */ 1694 otus_write(sc, 0x1e1114, 0x80); 1695 1696 /* Set clock frequency to 88/80MHz. */ 1697 otus_write(sc, 0x1d4008, 0x73); 1698 /* Set WLAN DMA interrupt mode: generate intr per packet. */ 1699 otus_write(sc, 0x1c3d7c, 0x110011); 1700 otus_write(sc, 0x1c3bb0, 0x4); 1701 otus_write(sc, AR_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141e0f48); 1702 1703 /* Disable HW decryption for now. */ 1704 otus_write(sc, 0x1c3678, 0x78); 1705 1706 if ((error = otus_write_barrier(sc)) != 0) 1707 return error; 1708 1709 /* Set default EDCA parameters. */ 1710 otus_updateedca_cb(sc, NULL); 1711 1712 return 0; 1713 } 1714 1715 /* 1716 * Return default value for PHY register based on current operating mode. 1717 */ 1718 uint32_t 1719 otus_phy_get_def(struct otus_softc *sc, uint32_t reg) 1720 { 1721 int i; 1722 1723 for (i = 0; i < nitems(ar5416_phy_regs); i++) 1724 if (AR_PHY(ar5416_phy_regs[i]) == reg) 1725 return sc->phy_vals[i]; 1726 return 0; /* Register not found. */ 1727 } 1728 1729 /* 1730 * Update PHY's programming based on vendor-specific data stored in EEPROM. 1731 * This is for FEM-type devices only. 1732 */ 1733 int 1734 otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c) 1735 { 1736 const struct ModalEepHeader *eep; 1737 uint32_t tmp, offset; 1738 1739 if (IEEE80211_IS_CHAN_5GHZ(c)) 1740 eep = &sc->eeprom.modalHeader[0]; 1741 else 1742 eep = &sc->eeprom.modalHeader[1]; 1743 1744 /* Offset of chain 2. */ 1745 offset = 2 * 0x1000; 1746 1747 tmp = letoh32(eep->antCtrlCommon); 1748 otus_write(sc, AR_PHY_SWITCH_COM, tmp); 1749 1750 tmp = letoh32(eep->antCtrlChain[0]); 1751 otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp); 1752 1753 tmp = letoh32(eep->antCtrlChain[1]); 1754 otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp); 1755 1756 if (1 /* sc->sc_sco == AR_SCO_SCN */) { 1757 tmp = otus_phy_get_def(sc, AR_PHY_SETTLING); 1758 tmp &= ~(0x7f << 7); 1759 tmp |= (eep->switchSettling & 0x7f) << 7; 1760 otus_write(sc, AR_PHY_SETTLING, tmp); 1761 } 1762 1763 tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ); 1764 tmp &= ~0xffff; 1765 tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize; 1766 otus_write(sc, AR_PHY_DESIRED_SZ, tmp); 1767 1768 tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 | 1769 eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn; 1770 otus_write(sc, AR_PHY_RF_CTL4, tmp); 1771 1772 tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3); 1773 tmp &= ~(0xff << 16); 1774 tmp |= eep->txEndToRxOn << 16; 1775 otus_write(sc, AR_PHY_RF_CTL3, tmp); 1776 1777 tmp = otus_phy_get_def(sc, AR_PHY_CCA); 1778 tmp &= ~(0x7f << 12); 1779 tmp |= (eep->thresh62 & 0x7f) << 12; 1780 otus_write(sc, AR_PHY_CCA, tmp); 1781 1782 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN); 1783 tmp &= ~(0x3f << 12); 1784 tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12; 1785 otus_write(sc, AR_PHY_RXGAIN, tmp); 1786 1787 tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset); 1788 tmp &= ~(0x3f << 12); 1789 tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12; 1790 otus_write(sc, AR_PHY_RXGAIN + offset, tmp); 1791 1792 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ); 1793 tmp &= ~(0x3f << 18); 1794 tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18; 1795 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1796 tmp &= ~(0xf << 10); 1797 tmp |= (eep->bswMargin[0] & 0xf) << 10; 1798 } 1799 otus_write(sc, AR_PHY_GAIN_2GHZ, tmp); 1800 1801 tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset); 1802 tmp &= ~(0x3f << 18); 1803 tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18; 1804 otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp); 1805 1806 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); 1807 tmp &= ~(0x3f << 5 | 0x1f); 1808 tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f); 1809 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); 1810 1811 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); 1812 tmp &= ~(0x3f << 5 | 0x1f); 1813 tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f); 1814 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); 1815 1816 tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1); 1817 tmp &= ~(0xf << 16); 1818 tmp |= (eep->xpd & 0xf) << 16; 1819 otus_write(sc, AR_PHY_TPCRG1, tmp); 1820 1821 return otus_write_barrier(sc); 1822 } 1823 1824 int 1825 otus_program_phy(struct otus_softc *sc, struct ieee80211_channel *c) 1826 { 1827 const uint32_t *vals; 1828 int error, i; 1829 1830 /* Select PHY programming based on band and bandwidth. */ 1831 if (IEEE80211_IS_CHAN_2GHZ(c)) 1832 vals = ar5416_phy_vals_2ghz_20mhz; 1833 else 1834 vals = ar5416_phy_vals_5ghz_20mhz; 1835 for (i = 0; i < nitems(ar5416_phy_regs); i++) 1836 otus_write(sc, AR_PHY(ar5416_phy_regs[i]), vals[i]); 1837 sc->phy_vals = vals; 1838 1839 if (sc->eeprom.baseEepHeader.deviceType == 0x80) /* FEM */ 1840 if ((error = otus_set_board_values(sc, c)) != 0) 1841 return error; 1842 1843 /* Initial Tx power settings. */ 1844 otus_write(sc, AR_PHY_POWER_TX_RATE_MAX, 0x7f); 1845 otus_write(sc, AR_PHY_POWER_TX_RATE1, 0x3f3f3f3f); 1846 otus_write(sc, AR_PHY_POWER_TX_RATE2, 0x3f3f3f3f); 1847 otus_write(sc, AR_PHY_POWER_TX_RATE3, 0x3f3f3f3f); 1848 otus_write(sc, AR_PHY_POWER_TX_RATE4, 0x3f3f3f3f); 1849 otus_write(sc, AR_PHY_POWER_TX_RATE5, 0x3f3f3f3f); 1850 otus_write(sc, AR_PHY_POWER_TX_RATE6, 0x3f3f3f3f); 1851 otus_write(sc, AR_PHY_POWER_TX_RATE7, 0x3f3f3f3f); 1852 otus_write(sc, AR_PHY_POWER_TX_RATE8, 0x3f3f3f3f); 1853 otus_write(sc, AR_PHY_POWER_TX_RATE9, 0x3f3f3f3f); 1854 1855 if (IEEE80211_IS_CHAN_2GHZ(c)) 1856 otus_write(sc, 0x1d4014, 0x5163); 1857 else 1858 otus_write(sc, 0x1d4014, 0x5143); 1859 1860 return otus_write_barrier(sc); 1861 } 1862 1863 static __inline uint8_t 1864 otus_reverse_bits(uint8_t v) 1865 { 1866 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1); 1867 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2); 1868 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4); 1869 return v; 1870 } 1871 1872 int 1873 otus_set_rf_bank4(struct otus_softc *sc, struct ieee80211_channel *c) 1874 { 1875 uint8_t chansel, d0, d1; 1876 uint16_t data; 1877 int error; 1878 1879 d0 = 0; 1880 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1881 chansel = (c->ic_freq - 4800) / 5; 1882 if (chansel & 1) 1883 d0 |= AR_BANK4_AMODE_REFSEL(2); 1884 else 1885 d0 |= AR_BANK4_AMODE_REFSEL(1); 1886 } else { 1887 d0 |= AR_BANK4_AMODE_REFSEL(2); 1888 if (c->ic_freq == 2484) { /* CH 14 */ 1889 d0 |= AR_BANK4_BMODE_LF_SYNTH_FREQ; 1890 chansel = 10 + (c->ic_freq - 2274) / 5; 1891 } else 1892 chansel = 16 + (c->ic_freq - 2272) / 5; 1893 chansel <<= 2; 1894 } 1895 d0 |= AR_BANK4_ADDR(1) | AR_BANK4_CHUP; 1896 d1 = otus_reverse_bits(chansel); 1897 1898 /* Write bits 0-4 of d0 and d1. */ 1899 data = (d1 & 0x1f) << 5 | (d0 & 0x1f); 1900 otus_write(sc, AR_PHY(44), data); 1901 /* Write bits 5-7 of d0 and d1. */ 1902 data = (d1 >> 5) << 5 | (d0 >> 5); 1903 otus_write(sc, AR_PHY(58), data); 1904 1905 if ((error = otus_write_barrier(sc)) == 0) 1906 usbd_delay_ms(sc->sc_udev, 10); 1907 return error; 1908 } 1909 1910 void 1911 otus_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa) 1912 { 1913 #define COEFF_SCALE_SHIFT 24 1914 uint32_t exp, man; 1915 1916 /* exponent = 14 - floor(log2(coeff)) */ 1917 for (exp = 31; exp > 0; exp--) 1918 if (coeff & (1 << exp)) 1919 break; 1920 KASSERT(exp != 0); 1921 exp = 14 - (exp - COEFF_SCALE_SHIFT); 1922 1923 /* mantissa = floor(coeff * 2^exponent + 0.5) */ 1924 man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1)); 1925 1926 *mantissa = man >> (COEFF_SCALE_SHIFT - exp); 1927 *exponent = exp - 16; 1928 #undef COEFF_SCALE_SHIFT 1929 } 1930 1931 int 1932 otus_set_chan(struct otus_softc *sc, struct ieee80211_channel *c, int assoc) 1933 { 1934 struct ieee80211com *ic = &sc->sc_ic; 1935 struct ar_cmd_frequency cmd; 1936 struct ar_rsp_frequency rsp; 1937 const uint32_t *vals; 1938 uint32_t coeff, exp, man, tmp; 1939 uint8_t code; 1940 int error, chan, i; 1941 1942 chan = ieee80211_chan2ieee(ic, c); 1943 DPRINTF(("setting channel %d (%dMHz)\n", chan, c->ic_freq)); 1944 1945 tmp = IEEE80211_IS_CHAN_2GHZ(c) ? 0x105 : 0x104; 1946 otus_write(sc, AR_MAC_REG_DYNAMIC_SIFS_ACK, tmp); 1947 if ((error = otus_write_barrier(sc)) != 0) 1948 return error; 1949 1950 /* Disable BB Heavy Clip. */ 1951 otus_write(sc, AR_PHY_HEAVY_CLIP_ENABLE, 0x200); 1952 if ((error = otus_write_barrier(sc)) != 0) 1953 return error; 1954 1955 /* XXX Is that FREQ_START ? */ 1956 error = otus_cmd(sc, AR_CMD_FREQ_STRAT, NULL, 0, NULL); 1957 if (error != 0) 1958 return error; 1959 1960 /* Reprogram PHY and RF on channel band or bandwidth changes. */ 1961 if (sc->bb_reset || c->ic_flags != sc->sc_curchan->ic_flags) { 1962 DPRINTF(("band switch\n")); 1963 1964 /* Cold/Warm reset BB/ADDA. */ 1965 otus_write(sc, 0x1d4004, sc->bb_reset ? 0x800 : 0x400); 1966 if ((error = otus_write_barrier(sc)) != 0) 1967 return error; 1968 otus_write(sc, 0x1d4004, 0); 1969 if ((error = otus_write_barrier(sc)) != 0) 1970 return error; 1971 sc->bb_reset = 0; 1972 1973 if ((error = otus_program_phy(sc, c)) != 0) { 1974 printf("%s: could not program PHY\n", 1975 sc->sc_dev.dv_xname); 1976 return error; 1977 } 1978 1979 /* Select RF programming based on band. */ 1980 if (IEEE80211_IS_CHAN_5GHZ(c)) 1981 vals = ar5416_banks_vals_5ghz; 1982 else 1983 vals = ar5416_banks_vals_2ghz; 1984 for (i = 0; i < nitems(ar5416_banks_regs); i++) 1985 otus_write(sc, AR_PHY(ar5416_banks_regs[i]), vals[i]); 1986 if ((error = otus_write_barrier(sc)) != 0) { 1987 printf("%s: could not program RF\n", 1988 sc->sc_dev.dv_xname); 1989 return error; 1990 } 1991 code = AR_CMD_RF_INIT; 1992 } else { 1993 code = AR_CMD_FREQUENCY; 1994 } 1995 1996 if ((error = otus_set_rf_bank4(sc, c)) != 0) 1997 return error; 1998 1999 tmp = (sc->txmask == 0x5) ? 0x340 : 0x240; 2000 otus_write(sc, AR_PHY_TURBO, tmp); 2001 if ((error = otus_write_barrier(sc)) != 0) 2002 return error; 2003 2004 /* Send firmware command to set channel. */ 2005 cmd.freq = htole32((uint32_t)c->ic_freq * 1000); 2006 cmd.dynht2040 = htole32(0); 2007 cmd.htena = htole32(1); 2008 /* Set Delta Slope (exponent and mantissa). */ 2009 coeff = (100 << 24) / c->ic_freq; 2010 otus_get_delta_slope(coeff, &exp, &man); 2011 cmd.dsc_exp = htole32(exp); 2012 cmd.dsc_man = htole32(man); 2013 DPRINTF(("ds coeff=%u exp=%u man=%u\n", coeff, exp, man)); 2014 /* For Short GI, coeff is 9/10 that of normal coeff. */ 2015 coeff = (9 * coeff) / 10; 2016 otus_get_delta_slope(coeff, &exp, &man); 2017 cmd.dsc_shgi_exp = htole32(exp); 2018 cmd.dsc_shgi_man = htole32(man); 2019 DPRINTF(("ds shgi coeff=%u exp=%u man=%u\n", coeff, exp, man)); 2020 /* Set wait time for AGC and noise calibration (100 or 200ms). */ 2021 cmd.check_loop_count = assoc ? htole32(2000) : htole32(1000); 2022 DPRINTF(("%s\n", (code == AR_CMD_RF_INIT) ? "RF_INIT" : "FREQUENCY")); 2023 error = otus_cmd(sc, code, &cmd, sizeof cmd, &rsp); 2024 if (error != 0) 2025 return error; 2026 if ((rsp.status & htole32(AR_CAL_ERR_AGC | AR_CAL_ERR_NF_VAL)) != 0) { 2027 DPRINTF(("status=0x%x\n", letoh32(rsp.status))); 2028 /* Force cold reset on next channel. */ 2029 sc->bb_reset = 1; 2030 } 2031 #ifdef OTUS_DEBUG 2032 if (otus_debug) { 2033 printf("calibration status=0x%x\n", letoh32(rsp.status)); 2034 for (i = 0; i < 2; i++) { /* 2 Rx chains */ 2035 /* Sign-extend 9-bit NF values. */ 2036 printf("noisefloor chain %d=%d\n", i, 2037 (((int32_t)letoh32(rsp.nf[i])) << 4) >> 23); 2038 printf("noisefloor ext chain %d=%d\n", i, 2039 ((int32_t)letoh32(rsp.nf_ext[i])) >> 23); 2040 } 2041 } 2042 #endif 2043 sc->sc_curchan = c; 2044 return 0; 2045 } 2046 2047 #ifdef notyet 2048 int 2049 otus_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2050 struct ieee80211_key *k) 2051 { 2052 struct otus_softc *sc = ic->ic_softc; 2053 struct otus_cmd_key cmd; 2054 2055 /* Defer setting of WEP keys until interface is brought up. */ 2056 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 2057 (IFF_UP | IFF_RUNNING)) 2058 return 0; 2059 2060 /* Do it in a process context. */ 2061 cmd.key = *k; 2062 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2063 otus_do_async(sc, otus_set_key_cb, &cmd, sizeof cmd); 2064 return 0; 2065 } 2066 2067 void 2068 otus_set_key_cb(struct otus_softc *sc, void *arg) 2069 { 2070 struct otus_cmd_key *cmd = arg; 2071 struct ieee80211_key *k = &cmd->key; 2072 struct ar_cmd_ekey key; 2073 uint16_t cipher; 2074 int error; 2075 2076 memset(&key, 0, sizeof key); 2077 if (k->k_flags & IEEE80211_KEY_GROUP) { 2078 key.uid = htole16(k->k_id); 2079 IEEE80211_ADDR_COPY(key.macaddr, sc->sc_ic.ic_myaddr); 2080 key.macaddr[0] |= 0x80; 2081 } else { 2082 key.uid = htole16(OTUS_UID(cmd->associd)); 2083 IEEE80211_ADDR_COPY(key.macaddr, ni->ni_macaddr); 2084 } 2085 key.kix = htole16(0); 2086 /* Map net80211 cipher to hardware. */ 2087 switch (k->k_cipher) { 2088 case IEEE80211_CIPHER_WEP40: 2089 cipher = AR_CIPHER_WEP64; 2090 break; 2091 case IEEE80211_CIPHER_WEP104: 2092 cipher = AR_CIPHER_WEP128; 2093 break; 2094 case IEEE80211_CIPHER_TKIP: 2095 cipher = AR_CIPHER_TKIP; 2096 break; 2097 case IEEE80211_CIPHER_CCMP: 2098 cipher = AR_CIPHER_AES; 2099 break; 2100 default: 2101 return; 2102 } 2103 key.cipher = htole16(cipher); 2104 memcpy(key.key, k->k_key, MIN(k->k_len, 16)); 2105 error = otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL); 2106 if (error != 0 || k->k_cipher != IEEE80211_CIPHER_TKIP) 2107 return; 2108 2109 /* TKIP: set Tx/Rx MIC Key. */ 2110 key.kix = htole16(1); 2111 memcpy(key.key, k->k_key + 16, 16); 2112 (void)otus_cmd(sc, AR_CMD_EKEY, &key, sizeof key, NULL); 2113 } 2114 2115 void 2116 otus_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2117 struct ieee80211_key *k) 2118 { 2119 struct otus_softc *sc = ic->ic_softc; 2120 struct otus_cmd_key cmd; 2121 2122 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2123 ic->ic_state != IEEE80211_S_RUN) 2124 return; /* Nothing to do. */ 2125 2126 /* Do it in a process context. */ 2127 cmd.key = *k; 2128 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2129 otus_do_async(sc, otus_delete_key_cb, &cmd, sizeof cmd); 2130 } 2131 2132 void 2133 otus_delete_key_cb(struct otus_softc *sc, void *arg) 2134 { 2135 struct otus_cmd_key *cmd = arg; 2136 struct ieee80211_key *k = &cmd->key; 2137 uint32_t uid; 2138 2139 if (k->k_flags & IEEE80211_KEY_GROUP) 2140 uid = htole32(k->k_id); 2141 else 2142 uid = htole32(OTUS_UID(cmd->associd)); 2143 (void)otus_cmd(sc, AR_CMD_DKEY, &uid, sizeof uid, NULL); 2144 } 2145 #endif 2146 2147 void 2148 otus_calibrate_to(void *arg) 2149 { 2150 struct otus_softc *sc = arg; 2151 struct ieee80211com *ic = &sc->sc_ic; 2152 struct ieee80211_node *ni; 2153 int s; 2154 2155 s = splnet(); 2156 ni = ic->ic_bss; 2157 ieee80211_amrr_choose(&sc->amrr, ni, &((struct otus_node *)ni)->amn); 2158 splx(s); 2159 2160 timeout_add_sec(&sc->calib_to, 1); 2161 } 2162 2163 int 2164 otus_set_bssid(struct otus_softc *sc, const uint8_t *bssid) 2165 { 2166 otus_write(sc, AR_MAC_REG_BSSID_L, 2167 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 2168 otus_write(sc, AR_MAC_REG_BSSID_H, 2169 bssid[4] | bssid[5] << 8); 2170 return otus_write_barrier(sc); 2171 } 2172 2173 int 2174 otus_set_macaddr(struct otus_softc *sc, const uint8_t *addr) 2175 { 2176 otus_write(sc, AR_MAC_REG_MAC_ADDR_L, 2177 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2178 otus_write(sc, AR_MAC_REG_MAC_ADDR_H, 2179 addr[4] | addr[5] << 8); 2180 return otus_write_barrier(sc); 2181 } 2182 2183 /* Default single-LED. */ 2184 void 2185 otus_led_newstate_type1(struct otus_softc *sc) 2186 { 2187 /* TBD */ 2188 } 2189 2190 /* NETGEAR, dual-LED. */ 2191 void 2192 otus_led_newstate_type2(struct otus_softc *sc) 2193 { 2194 /* TBD */ 2195 } 2196 2197 /* NETGEAR, single-LED/3 colors (blue, red, purple.) */ 2198 void 2199 otus_led_newstate_type3(struct otus_softc *sc) 2200 { 2201 struct ieee80211com *ic = &sc->sc_ic; 2202 uint32_t state = sc->led_state; 2203 2204 if (ic->ic_state == IEEE80211_S_INIT) { 2205 state = 0; /* LED off. */ 2206 } else if (ic->ic_state == IEEE80211_S_RUN) { 2207 /* Associated, LED always on. */ 2208 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 2209 state = AR_LED0_ON; /* 2GHz=>Red. */ 2210 else 2211 state = AR_LED1_ON; /* 5GHz=>Blue. */ 2212 } else { 2213 /* Scanning, blink LED. */ 2214 state ^= AR_LED0_ON | AR_LED1_ON; 2215 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) 2216 state &= ~AR_LED1_ON; 2217 else 2218 state &= ~AR_LED0_ON; 2219 } 2220 if (state != sc->led_state) { 2221 otus_write(sc, 0x1d0104, state); 2222 if (otus_write_barrier(sc) == 0) 2223 sc->led_state = state; 2224 } 2225 } 2226 2227 int 2228 otus_init(struct ifnet *ifp) 2229 { 2230 struct otus_softc *sc = ifp->if_softc; 2231 struct ieee80211com *ic = &sc->sc_ic; 2232 int error; 2233 2234 /* Init host command ring. */ 2235 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2236 2237 if ((error = otus_init_mac(sc)) != 0) { 2238 printf("%s: could not initialize MAC\n", sc->sc_dev.dv_xname); 2239 return error; 2240 } 2241 2242 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2243 (void)otus_set_macaddr(sc, ic->ic_myaddr); 2244 2245 switch (ic->ic_opmode) { 2246 #ifdef notyet 2247 #ifndef IEEE80211_STA_ONLY 2248 case IEEE80211_M_HOSTAP: 2249 otus_write(sc, 0x1c3700, 0x0f0000a1); 2250 otus_write(sc, 0x1c3c40, 0x1); 2251 break; 2252 case IEEE80211_M_IBSS: 2253 otus_write(sc, 0x1c3700, 0x0f000000); 2254 otus_write(sc, 0x1c3c40, 0x1); 2255 break; 2256 #endif 2257 #endif 2258 case IEEE80211_M_STA: 2259 otus_write(sc, 0x1c3700, 0x0f000002); 2260 otus_write(sc, 0x1c3c40, 0x1); 2261 break; 2262 default: 2263 break; 2264 } 2265 otus_write(sc, AR_MAC_REG_SNIFFER, 2266 (ic->ic_opmode == IEEE80211_M_MONITOR) ? 0x2000001 : 0x2000000); 2267 (void)otus_write_barrier(sc); 2268 2269 sc->bb_reset = 1; /* Force cold reset. */ 2270 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 2271 if ((error = otus_set_chan(sc, ic->ic_ibss_chan, 0)) != 0) { 2272 printf("%s: could not set channel\n", sc->sc_dev.dv_xname); 2273 return error; 2274 } 2275 2276 /* Start Rx. */ 2277 otus_write(sc, 0x1c3d30, 0x100); 2278 (void)otus_write_barrier(sc); 2279 2280 ifp->if_flags &= ~IFF_OACTIVE; 2281 ifp->if_flags |= IFF_RUNNING; 2282 2283 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2284 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2285 else 2286 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2287 2288 return 0; 2289 } 2290 2291 void 2292 otus_stop(struct ifnet *ifp) 2293 { 2294 struct otus_softc *sc = ifp->if_softc; 2295 struct ieee80211com *ic = &sc->sc_ic; 2296 int s; 2297 2298 sc->sc_tx_timer = 0; 2299 ifp->if_timer = 0; 2300 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2301 2302 timeout_del(&sc->scan_to); 2303 timeout_del(&sc->calib_to); 2304 2305 s = splusb(); 2306 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2307 /* Wait for all queued asynchronous commands to complete. */ 2308 while (sc->cmdq.queued > 0) 2309 tsleep(&sc->cmdq, 0, "cmdq", 0); 2310 splx(s); 2311 2312 /* Stop Rx. */ 2313 otus_write(sc, 0x1c3d30, 0); 2314 (void)otus_write_barrier(sc); 2315 2316 sc->tx_queued = 0; 2317 } 2318
Indexes created Mon Sep 29 03:10:08 GMT 2025