if_rsureg.h revision 1.1
1 /* $NetBSD: if_rsureg.h,v 1.1 2026/10/18 20:17:42 nia Exp $ */ 2 /* $OpenBSD: if_rsureg.h,v 1.4 2020/11/30 16:09:33 krw Exp $ */ 3 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* Maximum number of pipes is 11. */ 21 #define R92S_MAX_EP 11 22 23 /* USB Requests. */ 24 #define R92S_REQ_REGS 0x05 25 26 /* 27 * MAC registers. 28 */ 29 #define R92S_SYSCFG 0x0000 30 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 31 #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 32 #define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 33 #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 34 #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 35 #define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 36 #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 37 #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 38 #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 39 #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 40 #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 41 #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 42 #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 43 #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 44 #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 45 #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 46 47 #define R92S_CMDCTRL 0x0040 48 #define R92S_CR (R92S_CMDCTRL + 0x000) 49 #define R92S_TCR (R92S_CMDCTRL + 0x004) 50 #define R92S_RCR (R92S_CMDCTRL + 0x008) 51 52 #define R92S_MACIDSETTING 0x0050 53 #define R92S_MACID (R92S_MACIDSETTING + 0x000) 54 55 #define R92S_GP 0x01e0 56 #define R92S_GPIO_CTRL (R92S_GP + 0x00c) 57 #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 58 #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 59 60 #define R92S_IOCMD_CTRL 0x0370 61 #define R92S_IOCMD_DATA 0x0374 62 63 #define R92S_USB_HRPWM 0xfe58 64 65 /* Bits for R92S_SYS_FUNC_EN. */ 66 #define R92S_FEN_CPUEN 0x0400 67 68 /* Bits for R92S_PMC_FSM. */ 69 #define R92S_PMC_FSM_CUT_M 0x000f8000 70 #define R92S_PMC_FSM_CUT_S 15 71 72 /* Bits for R92S_SYS_CLKR. */ 73 #define R92S_SYS_CLKSEL 0x0001 74 #define R92S_SYS_PS_CLKSEL 0x0002 75 #define R92S_SYS_CPU_CLKSEL 0x0004 76 #define R92S_MAC_CLK_EN 0x0800 77 #define R92S_SYS_CLK_EN 0x1000 78 #define R92S_SWHW_SEL 0x4000 79 #define R92S_FWHW_SEL 0x8000 80 81 /* Bits for R92S_EE_9346CR. */ 82 #define R92S_9356SEL 0x10 83 #define R92S_EEPROM_EN 0x20 84 85 /* Bits for R92S_AFE_MISC. */ 86 #define R92S_AFE_MISC_BGEN 0x01 87 #define R92S_AFE_MISC_MBEN 0x02 88 #define R92S_AFE_MISC_I32_EN 0x08 89 90 /* Bits for R92S_SPS1_CTRL. */ 91 #define R92S_SPS1_LDEN 0x01 92 #define R92S_SPS1_SWEN 0x02 93 94 /* Bits for R92S_LDOA15_CTRL. */ 95 #define R92S_LDA15_EN 0x01 96 97 /* Bits for R92S_LDOV12D_CTRL. */ 98 #define R92S_LDV12_EN 0x01 99 100 /* Bits for R92C_EFUSE_CTRL. */ 101 #define R92S_EFUSE_CTRL_DATA_M 0x000000ff 102 #define R92S_EFUSE_CTRL_DATA_S 0 103 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 104 #define R92S_EFUSE_CTRL_ADDR_S 8 105 #define R92S_EFUSE_CTRL_VALID 0x80000000 106 107 /* Bits for R92S_CR. */ 108 #define R92S_CR_TXDMA_EN 0x10 109 110 /* Bits for R92S_TCR. */ 111 #define R92S_TCR_IMEM_CODE_DONE 0x01 112 #define R92S_TCR_IMEM_CHK_RPT 0x02 113 #define R92S_TCR_EMEM_CODE_DONE 0x04 114 #define R92S_TCR_EMEM_CHK_RPT 0x08 115 #define R92S_TCR_DMEM_CODE_DONE 0x10 116 #define R92S_TCR_IMEM_RDY 0x20 117 #define R92S_TCR_FWRDY 0x80 118 119 /* Bits for R92S_GPIO_IO_SEL. */ 120 #define R92S_GPIO_WPS 0x10 121 122 /* Bits for R92S_MAC_PINMUX_CTRL. */ 123 #define R92S_GPIOSEL_GPIO_M 0x03 124 #define R92S_GPIOSEL_GPIO_S 0 125 #define R92S_GPIOSEL_GPIO_JTAG 0 126 #define R92S_GPIOSEL_GPIO_PHYDBG 1 127 #define R92S_GPIOSEL_GPIO_BT 2 128 #define R92S_GPIOSEL_GPIO_WLANDBG 3 129 #define R92S_GPIOMUX_EN 0x08 130 131 /* Bits for R92S_IOCMD_CTRL. */ 132 #define R92S_IOCMD_CLASS_M 0xff000000 133 #define R92S_IOCMD_CLASS_S 24 134 #define R92S_IOCMD_CLASS_BB_RF 0xf0 135 #define R92S_IOCMD_VALUE_M 0x00ffff00 136 #define R92S_IOCMD_VALUE_S 8 137 #define R92S_IOCMD_INDEX_M 0x000000ff 138 #define R92S_IOCMD_INDEX_S 0 139 #define R92S_IOCMD_INDEX_BB_READ 0 140 #define R92S_IOCMD_INDEX_BB_WRITE 1 141 #define R92S_IOCMD_INDEX_RF_READ 2 142 #define R92S_IOCMD_INDEX_RF_WRITE 3 143 144 /* Bits for R92S_USB_HRPWM. */ 145 #define R92S_USB_HRPWM_PS_ALL_ON 0x04 146 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 147 148 /* 149 * Macros to access subfields in registers. 150 */ 151 /* Mask and Shift (getter). */ 152 #define MS(val, field) \ 153 (((val) & field##_M) >> field##_S) 154 155 /* Shift and Mask (setter). */ 156 #define SM(field, val) \ 157 (((val) << field##_S) & field##_M) 158 159 /* Rewrite. */ 160 #define RW(var, field, val) \ 161 (((var) & ~field##_M) | SM(field, val)) 162 163 /* 164 * Firmware image header. 165 */ 166 struct r92s_fw_priv { 167 /* QWORD0 */ 168 uint16_t signature; 169 uint8_t hci_sel; 170 #define R92S_HCI_SEL_PCIE 0x01 171 #define R92S_HCI_SEL_USB 0x02 172 #define R92S_HCI_SEL_SDIO 0x04 173 #define R92S_HCI_SEL_8172 0x10 174 #define R92S_HCI_SEL_AP 0x80 175 176 uint8_t chip_version; 177 uint16_t custid; 178 uint8_t rf_config; 179 uint8_t nendpoints; 180 /* QWORD1 */ 181 uint32_t regulatory; 182 uint8_t rfintfs; 183 uint8_t def_nettype; 184 uint8_t turbo_mode; 185 uint8_t lowpower_mode; 186 /* QWORD2 */ 187 uint8_t lbk_mode; 188 uint8_t mp_mode; 189 uint8_t vcs_type; 190 #define R92S_VCS_TYPE_DISABLE 0 191 #define R92S_VCS_TYPE_ENABLE 1 192 #define R92S_VCS_TYPE_AUTO 2 193 194 uint8_t vcs_mode; 195 #define R92S_VCS_MODE_NONE 0 196 #define R92S_VCS_MODE_RTS_CTS 1 197 #define R92S_VCS_MODE_CTS2SELF 2 198 199 uint32_t reserved1; 200 /* QWORD3 */ 201 uint8_t qos_en; 202 uint8_t bw40_en; 203 uint8_t amsdu2ampdu_en; 204 uint8_t ampdu_en; 205 uint8_t rc_offload; 206 uint8_t agg_offload; 207 uint16_t reserved2; 208 /* QWORD4 */ 209 uint8_t beacon_offload; 210 uint8_t mlme_offload; 211 uint8_t hwpc_offload; 212 uint8_t tcpcsum_offload; 213 uint8_t tcp_offload; 214 uint8_t ps_offload; 215 uint8_t wwlan_offload; 216 uint8_t reserved3; 217 /* QWORD5 */ 218 uint16_t tcp_tx_len; 219 uint16_t tcp_rx_len; 220 uint32_t reserved4; 221 } __packed; 222 223 struct r92s_fw_hdr { 224 uint16_t signature; 225 uint16_t version; 226 uint32_t dmemsz; 227 uint32_t imemsz; 228 uint32_t sramsz; 229 uint32_t privsz; 230 uint16_t efuse_addr; 231 uint16_t h2c_resp_addr; 232 uint32_t svnrev; 233 uint8_t month; 234 uint8_t day; 235 uint8_t hour; 236 uint8_t minute; 237 struct r92s_fw_priv priv; 238 } __packed; 239 240 /* Structure for FW commands and FW events notifications. */ 241 struct r92s_fw_cmd_hdr { 242 uint16_t len; 243 uint8_t code; 244 uint8_t seq; 245 #define R92S_FW_CMD_MORE 0x80 246 247 uint32_t reserved; 248 } __packed; 249 250 /* FW commands codes. */ 251 #define R92S_CMD_READ_MACREG 0 252 #define R92S_CMD_WRITE_MACREG 1 253 #define R92S_CMD_READ_BBREG 2 254 #define R92S_CMD_WRITE_BBREG 3 255 #define R92S_CMD_READ_RFREG 4 256 #define R92S_CMD_WRITE_RFREG 5 257 #define R92S_CMD_READ_EEPROM 6 258 #define R92S_CMD_WRITE_EEPROM 7 259 #define R92S_CMD_READ_EFUSE 8 260 #define R92S_CMD_WRITE_EFUSE 9 261 #define R92S_CMD_READ_CAM 10 262 #define R92S_CMD_WRITE_CAM 11 263 #define R92S_CMD_SET_BCNITV 12 264 #define R92S_CMD_SET_MBIDCFG 13 265 #define R92S_CMD_JOIN_BSS 14 266 #define R92S_CMD_DISCONNECT 15 267 #define R92S_CMD_CREATE_BSS 16 268 #define R92S_CMD_SET_OPMODE 17 269 #define R92S_CMD_SITE_SURVEY 18 270 #define R92S_CMD_SET_AUTH 19 271 #define R92S_CMD_SET_KEY 20 272 #define R92S_CMD_SET_STA_KEY 21 273 #define R92S_CMD_SET_ASSOC_STA 22 274 #define R92S_CMD_DEL_ASSOC_STA 23 275 #define R92S_CMD_SET_STAPWRSTATE 24 276 #define R92S_CMD_SET_BASIC_RATE 25 277 #define R92S_CMD_GET_BASIC_RATE 26 278 #define R92S_CMD_SET_DATA_RATE 27 279 #define R92S_CMD_GET_DATA_RATE 28 280 #define R92S_CMD_SET_PHY_INFO 29 281 #define R92S_CMD_GET_PHY_INFO 30 282 #define R92S_CMD_SET_PHY 31 283 #define R92S_CMD_GET_PHY 32 284 #define R92S_CMD_READ_RSSI 33 285 #define R92S_CMD_READ_GAIN 34 286 #define R92S_CMD_SET_ATIM 35 287 #define R92S_CMD_SET_PWR_MODE 36 288 #define R92S_CMD_JOIN_BSS_RPT 37 289 #define R92S_CMD_SET_RA_TABLE 38 290 #define R92S_CMD_GET_RA_TABLE 39 291 #define R92S_CMD_GET_CCX_REPORT 40 292 #define R92S_CMD_GET_DTM_REPORT 41 293 #define R92S_CMD_GET_TXRATE_STATS 42 294 #define R92S_CMD_SET_USB_SUSPEND 43 295 #define R92S_CMD_SET_H2C_LBK 44 296 #define R92S_CMD_ADDBA_REQ 45 297 #define R92S_CMD_SET_CHANNEL 46 298 #define R92S_CMD_SET_TXPOWER 47 299 #define R92S_CMD_SWITCH_ANTENNA 48 300 #define R92S_CMD_SET_CRYSTAL_CAL 49 301 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50 302 #define R92S_CMD_SET_SINGLE_TONE_TX 51 303 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52 304 #define R92S_CMD_SET_CONTINUOUS_TX 53 305 #define R92S_CMD_SWITCH_BANDWIDTH 54 306 #define R92S_CMD_TX_BEACON 55 307 #define R92S_CMD_SET_POWER_TRACKING 56 308 #define R92S_CMD_AMSDU_TO_AMPDU 57 309 #define R92S_CMD_SET_MAC_ADDRESS 58 310 #define R92S_CMD_GET_H2C_LBK 59 311 #define R92S_CMD_SET_PBREQ_IE 60 312 #define R92S_CMD_SET_ASSOCREQ_IE 61 313 #define R92S_CMD_SET_PBRESP_IE 62 314 #define R92S_CMD_SET_ASSOCRESP_IE 63 315 #define R92S_CMD_GET_CURDATARATE 64 316 #define R92S_CMD_GET_TXRETRY_CNT 65 317 #define R92S_CMD_GET_RXRETRY_CNT 66 318 #define R92S_CMD_GET_BCNOK_CNT 67 319 #define R92S_CMD_GET_BCNERR_CNT 68 320 #define R92S_CMD_GET_CURTXPWR_LEVEL 69 321 #define R92S_CMD_SET_DIG 70 322 #define R92S_CMD_SET_RA 71 323 #define R92S_CMD_SET_PT 72 324 #define R92S_CMD_READ_TSSI 73 325 326 /* FW events notifications codes. */ 327 #define R92S_EVT_READ_MACREG 0 328 #define R92S_EVT_READ_BBREG 1 329 #define R92S_EVT_READ_RFREG 2 330 #define R92S_EVT_READ_EEPROM 3 331 #define R92S_EVT_READ_EFUSE 4 332 #define R92S_EVT_READ_CAM 5 333 #define R92S_EVT_GET_BASICRATE 6 334 #define R92S_EVT_GET_DATARATE 7 335 #define R92S_EVT_SURVEY 8 336 #define R92S_EVT_SURVEY_DONE 9 337 #define R92S_EVT_JOIN_BSS 10 338 #define R92S_EVT_ADD_STA 11 339 #define R92S_EVT_DEL_STA 12 340 #define R92S_EVT_ATIM_DONE 13 341 #define R92S_EVT_TX_REPORT 14 342 #define R92S_EVT_CCX_REPORT 15 343 #define R92S_EVT_DTM_REPORT 16 344 #define R92S_EVT_TXRATE_STATS 17 345 #define R92S_EVT_C2H_LBK 18 346 #define R92S_EVT_FWDBG 19 347 #define R92S_EVT_C2H_FEEDBACK 20 348 #define R92S_EVT_ADDBA 21 349 #define R92S_EVT_C2H_BCN 22 350 #define R92S_EVT_PWR_STATE 23 351 #define R92S_EVT_WPS_PBC 24 352 #define R92S_EVT_ADDBA_REQ_REPORT 25 353 354 /* Structure for R92S_CMD_SITE_SURVEY. */ 355 struct r92s_fw_cmd_sitesurvey { 356 uint32_t active; 357 uint32_t limit; 358 uint32_t ssidlen; 359 uint8_t ssid[32 + 1]; 360 } __packed; 361 362 /* Structure for R92S_CMD_SET_AUTH. */ 363 struct r92s_fw_cmd_auth { 364 uint8_t mode; 365 #define R92S_AUTHMODE_OPEN 0 366 #define R92S_AUTHMODE_SHARED 1 367 #define R92S_AUTHMODE_WPA 2 368 369 uint8_t dot1x; 370 } __packed; 371 372 /* Structure for R92S_CMD_SET_KEY. */ 373 struct r92s_fw_cmd_set_key { 374 uint8_t algo; 375 #define R92S_KEY_ALGO_NONE 0 376 #define R92S_KEY_ALGO_WEP40 1 377 #define R92S_KEY_ALGO_TKIP 2 378 #define R92S_KEY_ALGO_TKIP_MMIC 3 379 #define R92S_KEY_ALGO_AES 4 380 #define R92S_KEY_ALGO_WEP104 5 381 382 uint8_t id; 383 uint8_t grpkey; 384 uint8_t key[16]; 385 } __packed; 386 387 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 388 /* NDIS_802_11_SSID. */ 389 struct ndis_802_11_ssid { 390 uint32_t ssidlen; 391 uint8_t ssid[32]; 392 } __packed; 393 394 /* NDIS_802_11_CONFIGURATION_FH. */ 395 struct ndis_802_11_configuration_fh { 396 uint32_t len; 397 uint32_t hoppattern; 398 uint32_t hopset; 399 uint32_t dwelltime; 400 } __packed; 401 402 /* NDIS_802_11_CONFIGURATION. */ 403 struct ndis_802_11_configuration { 404 uint32_t len; 405 uint32_t bintval; 406 uint32_t atim; 407 uint32_t dsconfig; 408 struct ndis_802_11_configuration_fh fhconfig; 409 } __packed; 410 411 /* NDIS_WLAN_BSSID_EX. */ 412 struct ndis_wlan_bssid_ex { 413 uint32_t len; 414 uint8_t macaddr[IEEE80211_ADDR_LEN]; 415 uint8_t reserved[2]; 416 struct ndis_802_11_ssid ssid; 417 uint32_t privacy; 418 int32_t rssi; 419 uint32_t networktype; 420 #define NDIS802_11FH 0 421 #define NDIS802_11DS 1 422 #define NDIS802_11OFDM5 2 423 #define NDIS802_11OFDM24 3 424 #define NDIS802_11AUTOMODE 4 425 426 struct ndis_802_11_configuration config; 427 uint32_t inframode; 428 #define NDIS802_11IBSS 0 429 #define NDIS802_11INFRASTRUCTURE 1 430 #define NDIS802_11AUTOUNKNOWN 2 431 #define NDIS802_11MONITOR 3 432 #define NDIS802_11APMODE 4 433 434 uint8_t supprates[16]; 435 uint32_t ieslen; 436 /* Followed by ``ieslen'' bytes. */ 437 } __packed; 438 439 /* NDIS_802_11_FIXED_IEs. */ 440 struct ndis_802_11_fixed_ies { 441 uint8_t tstamp[8]; 442 uint16_t bintval; 443 uint16_t capabilities; 444 } __packed; 445 446 /* Structure for R92S_CMD_SET_PWR_MODE. */ 447 struct r92s_set_pwr_mode { 448 uint8_t mode; 449 #define R92S_PS_MODE_ACTIVE 0 450 #define R92S_PS_MODE_MIN 1 451 #define R92S_PS_MODE_MAX 2 452 #define R92S_PS_MODE_DTIM 3 453 #define R92S_PS_MODE_VOIP 4 454 #define R92S_PS_MODE_UAPSD_WMM 5 455 #define R92S_PS_MODE_UAPSD 6 456 #define R92S_PS_MODE_IBSS 7 457 #define R92S_PS_MODE_WWLAN 8 458 #define R92S_PS_MODE_RADIOOFF 9 459 #define R92S_PS_MODE_DISABLE 10 460 461 uint8_t low_traffic_en; 462 uint8_t lpnav_en; 463 uint8_t rf_low_snr_en; 464 uint8_t dps_en; 465 uint8_t bcn_rx_en; 466 uint8_t bcn_pass_cnt; 467 uint8_t bcn_to; 468 uint16_t bcn_itv; 469 uint8_t app_itv; 470 uint8_t awake_bcn_itv; 471 uint8_t smart_ps; 472 uint8_t bcn_pass_time; 473 } __packed; 474 475 /* Structure for event R92S_EVENT_JOIN_BSS. */ 476 struct r92s_event_join_bss { 477 uint32_t next; 478 uint32_t prev; 479 uint32_t networktype; 480 uint32_t fixed; 481 uint32_t lastscanned; 482 uint32_t associd; 483 uint32_t join_res; 484 struct ndis_wlan_bssid_ex bss; 485 } __packed; 486 487 #define R92S_MACID_BSS 5 488 489 /* Rx MAC descriptor. */ 490 struct r92s_rx_stat { 491 uint32_t rxdw0; 492 #define R92S_RXDW0_PKTLEN_M 0x00003fff 493 #define R92S_RXDW0_PKTLEN_S 0 494 #define R92S_RXDW0_CRCERR 0x00004000 495 #define R92S_RXDW0_INFOSZ_M 0x000f0000 496 #define R92S_RXDW0_INFOSZ_S 16 497 #define R92S_RXDW0_QOS 0x00800000 498 #define R92S_RXDW0_SHIFT_M 0x03000000 499 #define R92S_RXDW0_SHIFT_S 24 500 #define R92S_RXDW0_DECRYPTED 0x08000000 501 502 uint32_t rxdw1; 503 #define R92S_RXDW1_MOREFRAG 0x08000000 504 505 uint32_t rxdw2; 506 #define R92S_RXDW2_FRAG_M 0x0000f000 507 #define R92S_RXDW2_FRAG_S 12 508 #define R92S_RXDW2_PKTCNT_M 0x00ff0000 509 #define R92S_RXDW2_PKTCNT_S 16 510 511 uint32_t rxdw3; 512 #define R92S_RXDW3_RATE_M 0x0000003f 513 #define R92S_RXDW3_RATE_S 0 514 #define R92S_RXDW3_TCPCHKRPT 0x00000800 515 #define R92S_RXDW3_IPCHKRPT 0x00001000 516 #define R92S_RXDW3_TCPCHKVALID 0x00002000 517 #define R92S_RXDW3_HTC 0x00004000 518 519 uint32_t rxdw4; 520 uint32_t rxdw5; 521 } __packed __attribute__((aligned(4))); 522 523 /* Rx PHY descriptor. */ 524 struct r92s_rx_phystat { 525 uint32_t phydw0; 526 uint32_t phydw1; 527 uint32_t phydw2; 528 uint32_t phydw3; 529 uint32_t phydw4; 530 uint32_t phydw5; 531 uint32_t phydw6; 532 uint32_t phydw7; 533 } __packed __attribute__((aligned(4))); 534 535 /* Rx PHY CCK descriptor. */ 536 struct r92s_rx_cck { 537 uint8_t adc_pwdb[4]; 538 uint8_t sq_rpt; 539 uint8_t agc_rpt; 540 } __packed; 541 542 /* Tx MAC descriptor. */ 543 struct r92s_tx_desc { 544 uint32_t txdw0; 545 #define R92S_TXDW0_PKTLEN_M 0x0000ffff 546 #define R92S_TXDW0_PKTLEN_S 0 547 #define R92S_TXDW0_OFFSET_M 0x00ff0000 548 #define R92S_TXDW0_OFFSET_S 16 549 #define R92S_TXDW0_TYPE_M 0x03000000 550 #define R92S_TXDW0_TYPE_S 24 551 #define R92S_TXDW0_LSG 0x04000000 552 #define R92S_TXDW0_FSG 0x08000000 553 #define R92S_TXDW0_LINIP 0x10000000 554 #define R92S_TXDW0_OWN 0x80000000 555 556 uint32_t txdw1; 557 #define R92S_TXDW1_MACID_M 0x0000001f 558 #define R92S_TXDW1_MACID_S 0 559 #define R92S_TXDW1_MOREDATA 0x00000020 560 #define R92S_TXDW1_MOREFRAG 0x00000040 561 #define R92S_TXDW1_QSEL_M 0x00001f00 562 #define R92S_TXDW1_QSEL_S 8 563 #define R92S_TXDW1_QSEL_BE 0x03 564 #define R92S_TXDW1_QSEL_H2C 0x1f 565 #define R92S_TXDW1_NONQOS 0x00010000 566 #define R92S_TXDW1_KEYIDX_M 0x00060000 567 #define R92S_TXDW1_KEYIDX_S 17 568 #define R92S_TXDW1_CIPHER_M 0x00c00000 569 #define R92S_TXDW1_CIPHER_S 22 570 #define R92S_TXDW1_CIPHER_WEP 1 571 #define R92S_TXDW1_CIPHER_TKIP 2 572 #define R92S_TXDW1_CIPHER_AES 3 573 #define R92S_TXDW1_HWPC 0x80000000 574 575 uint32_t txdw2; 576 #define R92S_TXDW2_BMCAST 0x00000080 577 #define R92S_TXDW2_AGGEN 0x20000000 578 #define R92S_TXDW2_BK 0x40000000 579 580 uint32_t txdw3; 581 #define R92S_TXDW3_SEQ_M 0x0fff0000 582 #define R92S_TXDW3_SEQ_S 16 583 #define R92S_TXDW3_FRAG_M 0xf0000000 584 #define R92S_TXDW3_FRAG_S 28 585 586 uint32_t txdw4; 587 #define R92S_TXDW4_TXBW 0x00040000 588 589 uint32_t txdw5; 590 #define R92S_TXDW5_DISFB 0x00008000 591 592 uint16_t ipchksum; 593 uint16_t tcpchksum; 594 595 uint16_t txbufsize; 596 uint16_t reserved1; 597 } __packed __attribute__((aligned(4))); 598 599 600 /* 601 * Driver definitions. 602 */ 603 #define RSU_RX_LIST_COUNT 1 604 #define RSU_TX_LIST_COUNT (8 + 1) /* NB: +1 for FW commands. */ 605 606 #define RSU_HOST_CMD_RING_COUNT 32 607 608 #define RSU_RXBUFSZ (8 * 1024) 609 #define RSU_TXBUFSZ \ 610 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 611 612 #define RSU_TX_TIMEOUT 5000 /* ms */ 613 #define RSU_CMD_TIMEOUT 2000 /* ms */ 614 615 /* Queue ids (used by soft only). */ 616 #define RSU_QID_BCN 0 617 #define RSU_QID_MGT 1 618 #define RSU_QID_BMC 2 619 #define RSU_QID_VO 3 620 #define RSU_QID_VI 4 621 #define RSU_QID_BE 5 622 #define RSU_QID_BK 6 623 #define RSU_QID_RXOFF 7 624 #define RSU_QID_H2C 8 625 #define RSU_QID_C2H 9 626 627 /* Map AC to queue id. */ 628 static const uint8_t rsu_ac2qid[WME_NUM_AC] = { 629 RSU_QID_BE, 630 RSU_QID_BK, 631 RSU_QID_VI, 632 RSU_QID_VO 633 }; 634 635 /* Pipe index to endpoint address mapping. */ 636 static const uint8_t r92s_epaddr[] = 637 { 0x83, 0x04, 0x06, 0x0d, 638 0x05, 0x07, 639 0x89, 0x0a, 0x0b, 0x0c }; 640 641 /* Queue id to pipe index mapping for 4 endpoints configurations. */ 642 static const uint8_t rsu_qid2idx_4ep[] = 643 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 644 645 /* Queue id to pipe index mapping for 6 endpoints configurations. */ 646 static const uint8_t rsu_qid2idx_6ep[] = 647 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 648 649 /* Queue id to pipe index mapping for 11 endpoints configurations. */ 650 static const uint8_t rsu_qid2idx_11ep[] = 651 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 652 653 struct rsu_rx_radiotap_header { 654 struct ieee80211_radiotap_header wr_ihdr; 655 uint8_t wr_flags; 656 uint8_t wr_rate; 657 uint16_t wr_chan_freq; 658 uint16_t wr_chan_flags; 659 uint8_t wr_dbm_antsignal; 660 }; 661 662 #define RSU_RX_RADIOTAP_PRESENT \ 663 (1 << IEEE80211_RADIOTAP_FLAGS | \ 664 1 << IEEE80211_RADIOTAP_RATE | \ 665 1 << IEEE80211_RADIOTAP_CHANNEL | \ 666 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 667 668 struct rsu_tx_radiotap_header { 669 struct ieee80211_radiotap_header wt_ihdr; 670 uint8_t wt_flags; 671 uint16_t wt_chan_freq; 672 uint16_t wt_chan_flags; 673 }; 674 675 #define RSU_TX_RADIOTAP_PRESENT \ 676 (1 << IEEE80211_RADIOTAP_FLAGS | \ 677 1 << IEEE80211_RADIOTAP_CHANNEL) 678 679 struct rsu_softc; 680 681 struct rsu_rx_data { 682 struct rsu_softc *sc; 683 struct usbd_pipe *pipe; 684 struct usbd_xfer *xfer; 685 uint8_t *buf; 686 }; 687 688 struct rsu_tx_data { 689 struct rsu_softc *sc; 690 struct usbd_pipe *pipe; 691 struct usbd_xfer *xfer; 692 uint8_t *buf; 693 TAILQ_ENTRY(rsu_tx_data) next; 694 }; 695 696 struct rsu_host_cmd { 697 void (*cb)(struct rsu_softc *, void *); 698 uint8_t data[256]; 699 }; 700 701 struct rsu_cmd_newstate { 702 enum ieee80211_state state; 703 int arg; 704 }; 705 706 struct rsu_cmd_key { 707 struct ieee80211_key key; 708 struct ieee80211_node *ni; 709 }; 710 711 struct rsu_host_cmd_ring { 712 struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT]; 713 int cur; 714 int next; 715 int queued; 716 }; 717 718 struct rsu_softc { 719 device_t sc_dev; 720 struct ieee80211com sc_ic; 721 struct ethercom sc_ec; 722 int (*sc_newstate)(struct ieee80211com *, 723 enum ieee80211_state, int); 724 struct usbd_device *sc_udev; 725 struct usbd_interface *sc_iface; 726 struct usb_task sc_task; 727 callout_t calib_to; 728 kcondvar_t sc_task_cv; 729 kmutex_t sc_task_mtx; 730 kmutex_t sc_media_mtx; 731 kmutex_t sc_tx_mtx; 732 struct usbd_pipe *pipe[R92S_MAX_EP]; 733 int npipes; 734 const uint8_t *qid2idx; 735 736 u_int cut; 737 int scan_pass; 738 int sc_tx_timer; 739 struct rsu_host_cmd_ring cmdq; 740 struct rsu_rx_data rx_data[RSU_RX_LIST_COUNT]; 741 struct rsu_tx_data tx_data[RSU_TX_LIST_COUNT]; 742 struct rsu_tx_data *fwcmd_data; 743 uint8_t cmd_seq; 744 TAILQ_HEAD(, rsu_tx_data) tx_free_list; 745 uint8_t rom[128]; 746 747 int sc_key_tasks; 748 }; 749
Indexes created Mon Oct 26 00:26:21 UTC 2026