if_run.c revision 1.10.6.14
1 /* $NetBSD: if_run.c,v 1.10.6.14 2017/08/28 17:52:27 skrll Exp $ */ 2 /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.10.6.14 2017/08/28 17:52:27 skrll Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_usb.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <machine/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_amrr.h> 59 #include <net80211/ieee80211_radiotap.h> 60 61 #include <dev/firmload.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usbdivar.h> 66 #include <dev/usb/usbdi_util.h> 67 #include <dev/usb/usbdevs.h> 68 69 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 70 #include <dev/usb/if_runvar.h> 71 72 #ifdef RUN_DEBUG 73 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 74 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 75 int run_debug = 0; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n, x) 79 #endif 80 81 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 82 83 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 84 static const struct usb_devno run_devs[] = { 85 USB_ID(ABOCOM, RT2770), 86 USB_ID(ABOCOM, RT2870), 87 USB_ID(ABOCOM, RT3070), 88 USB_ID(ABOCOM, RT3071), 89 USB_ID(ABOCOM, RT3072), 90 USB_ID(ABOCOM2, RT2870_1), 91 USB_ID(ACCTON, RT2770), 92 USB_ID(ACCTON, RT2870_1), 93 USB_ID(ACCTON, RT2870_2), 94 USB_ID(ACCTON, RT2870_3), 95 USB_ID(ACCTON, RT2870_4), 96 USB_ID(ACCTON, RT2870_5), 97 USB_ID(ACCTON, RT3070), 98 USB_ID(ACCTON, RT3070_1), 99 USB_ID(ACCTON, RT3070_2), 100 USB_ID(ACCTON, RT3070_3), 101 USB_ID(ACCTON, RT3070_4), 102 USB_ID(ACCTON, RT3070_5), 103 USB_ID(ACCTON, RT3070_6), 104 USB_ID(AIRTIES, RT3070), 105 USB_ID(AIRTIES, RT3070_2), 106 USB_ID(ALLWIN, RT2070), 107 USB_ID(ALLWIN, RT2770), 108 USB_ID(ALLWIN, RT2870), 109 USB_ID(ALLWIN, RT3070), 110 USB_ID(ALLWIN, RT3071), 111 USB_ID(ALLWIN, RT3072), 112 USB_ID(ALLWIN, RT3572), 113 USB_ID(AMIGO, RT2870_1), 114 USB_ID(AMIGO, RT2870_2), 115 USB_ID(AMIT, CGWLUSB2GNR), 116 USB_ID(AMIT, RT2870_1), 117 USB_ID(AMIT2, RT2870), 118 USB_ID(ASUSTEK, RT2870_1), 119 USB_ID(ASUSTEK, RT2870_2), 120 USB_ID(ASUSTEK, RT2870_3), 121 USB_ID(ASUSTEK, RT2870_4), 122 USB_ID(ASUSTEK, RT2870_5), 123 USB_ID(ASUSTEK, RT3070), 124 USB_ID(ASUSTEK, RT3070_1), 125 USB_ID(ASUSTEK2, USBN11), 126 USB_ID(AZUREWAVE, RT2870_1), 127 USB_ID(AZUREWAVE, RT2870_2), 128 USB_ID(AZUREWAVE, RT3070), 129 USB_ID(AZUREWAVE, RT3070_2), 130 USB_ID(AZUREWAVE, RT3070_3), 131 USB_ID(AZUREWAVE, RT3070_4), 132 USB_ID(AZUREWAVE, RT3070_5), 133 USB_ID(BELKIN, F5D8053V3), 134 USB_ID(BELKIN, F5D8055), 135 USB_ID(BELKIN, F5D8055V2), 136 USB_ID(BELKIN, F6D4050V1), 137 USB_ID(BELKIN, F6D4050V2), 138 USB_ID(BELKIN, F7D1101V2), 139 USB_ID(BELKIN, RT2870_1), 140 USB_ID(BELKIN, RT2870_2), 141 USB_ID(BEWAN, RT3070), 142 USB_ID(CISCOLINKSYS, AE1000), 143 USB_ID(CISCOLINKSYS, AM10), 144 USB_ID(CISCOLINKSYS2, RT3070), 145 USB_ID(CISCOLINKSYS3, RT3070), 146 USB_ID(CONCEPTRONIC, RT2870_1), 147 USB_ID(CONCEPTRONIC, RT2870_2), 148 USB_ID(CONCEPTRONIC, RT2870_3), 149 USB_ID(CONCEPTRONIC, RT2870_4), 150 USB_ID(CONCEPTRONIC, RT2870_5), 151 USB_ID(CONCEPTRONIC, RT2870_6), 152 USB_ID(CONCEPTRONIC, RT2870_7), 153 USB_ID(CONCEPTRONIC, RT2870_8), 154 USB_ID(CONCEPTRONIC, RT3070_1), 155 USB_ID(CONCEPTRONIC, RT3070_2), 156 USB_ID(CONCEPTRONIC, RT3070_3), 157 USB_ID(COREGA, CGWLUSB300GNM), 158 USB_ID(COREGA, RT2870_1), 159 USB_ID(COREGA, RT2870_2), 160 USB_ID(COREGA, RT2870_3), 161 USB_ID(COREGA, RT3070), 162 USB_ID(CYBERTAN, RT2870), 163 USB_ID(DLINK, RT2870), 164 USB_ID(DLINK, RT3072), 165 USB_ID(DLINK2, DWA130), 166 USB_ID(DLINK2, RT2870_1), 167 USB_ID(DLINK2, RT2870_2), 168 USB_ID(DLINK2, RT3070_1), 169 USB_ID(DLINK2, RT3070_2), 170 USB_ID(DLINK2, RT3070_3), 171 USB_ID(DLINK2, RT3070_4), 172 USB_ID(DLINK2, RT3070_5), 173 USB_ID(DLINK2, RT3072), 174 USB_ID(DLINK2, RT3072_1), 175 USB_ID(DVICO, RT3070), 176 USB_ID(EDIMAX, EW7717), 177 USB_ID(EDIMAX, EW7718), 178 USB_ID(EDIMAX, EW7722UTN), 179 USB_ID(EDIMAX, RT2870_1), 180 USB_ID(ENCORE, RT3070), 181 USB_ID(ENCORE, RT3070_2), 182 USB_ID(ENCORE, RT3070_3), 183 USB_ID(GIGABYTE, GNWB31N), 184 USB_ID(GIGABYTE, GNWB32L), 185 USB_ID(GIGABYTE, RT2870_1), 186 USB_ID(GIGASET, RT3070_1), 187 USB_ID(GIGASET, RT3070_2), 188 USB_ID(GUILLEMOT, HWNU300), 189 USB_ID(HAWKING, HWUN2), 190 USB_ID(HAWKING, RT2870_1), 191 USB_ID(HAWKING, RT2870_2), 192 USB_ID(HAWKING, RT2870_3), 193 USB_ID(HAWKING, RT2870_4), 194 USB_ID(HAWKING, RT2870_5), 195 USB_ID(HAWKING, RT3070), 196 USB_ID(IODATA, RT3072_1), 197 USB_ID(IODATA, RT3072_2), 198 USB_ID(IODATA, RT3072_3), 199 USB_ID(IODATA, RT3072_4), 200 USB_ID(LINKSYS4, RT3070), 201 USB_ID(LINKSYS4, WUSB100), 202 USB_ID(LINKSYS4, WUSB54GC_3), 203 USB_ID(LINKSYS4, WUSB600N), 204 USB_ID(LINKSYS4, WUSB600NV2), 205 USB_ID(LOGITEC, LANW300NU2), 206 USB_ID(LOGITEC, RT2870_1), 207 USB_ID(LOGITEC, RT2870_2), 208 USB_ID(LOGITEC, RT2870_3), 209 USB_ID(LOGITEC, RT3020), 210 USB_ID(MELCO, RT2870_1), 211 USB_ID(MELCO, RT2870_2), 212 USB_ID(MELCO, WLIUCAG300N), 213 USB_ID(MELCO, WLIUCG300N), 214 USB_ID(MELCO, WLIUCG301N), 215 USB_ID(MELCO, WLIUCGN), 216 USB_ID(MELCO, WLIUCGNHP), 217 USB_ID(MELCO, WLIUCGNM), 218 USB_ID(MELCO, WLIUCGNM2T), 219 USB_ID(MOTOROLA4, RT2770), 220 USB_ID(MOTOROLA4, RT3070), 221 USB_ID(MSI, RT3070), 222 USB_ID(MSI, RT3070_2), 223 USB_ID(MSI, RT3070_3), 224 USB_ID(MSI, RT3070_4), 225 USB_ID(MSI, RT3070_5), 226 USB_ID(MSI, RT3070_6), 227 USB_ID(MSI, RT3070_7), 228 USB_ID(MSI, RT3070_8), 229 USB_ID(MSI, RT3070_9), 230 USB_ID(MSI, RT3070_10), 231 USB_ID(MSI, RT3070_11), 232 USB_ID(MSI, RT3070_12), 233 USB_ID(MSI, RT3070_13), 234 USB_ID(MSI, RT3070_14), 235 USB_ID(MSI, RT3070_15), 236 USB_ID(OVISLINK, RT3071), 237 USB_ID(OVISLINK, RT3072), 238 USB_ID(PARA, RT3070), 239 USB_ID(PEGATRON, RT2870), 240 USB_ID(PEGATRON, RT3070), 241 USB_ID(PEGATRON, RT3070_2), 242 USB_ID(PEGATRON, RT3070_3), 243 USB_ID(PEGATRON, RT3072), 244 USB_ID(PHILIPS, RT2870), 245 USB_ID(PLANEX2, GWUS300MINIS), 246 USB_ID(PLANEX2, GWUSMICRO300), 247 USB_ID(PLANEX2, GWUSMICRON), 248 USB_ID(PLANEX2, GWUS300MINIX), 249 USB_ID(PLANEX2, RT3070), 250 USB_ID(QCOM, RT2870), 251 USB_ID(QUANTA, RT3070), 252 USB_ID(RALINK, RT2070), 253 USB_ID(RALINK, RT2770), 254 USB_ID(RALINK, RT2870), 255 USB_ID(RALINK, RT3070), 256 USB_ID(RALINK, RT3071), 257 USB_ID(RALINK, RT3072), 258 USB_ID(RALINK, RT3370), 259 USB_ID(RALINK, RT3572), 260 USB_ID(RALINK, RT5370), 261 USB_ID(RALINK, RT5572), 262 USB_ID(RALINK, RT8070), 263 USB_ID(SAMSUNG, RT2870_1), 264 USB_ID(SENAO, RT2870_1), 265 USB_ID(SENAO, RT2870_2), 266 USB_ID(SENAO, RT2870_3), 267 USB_ID(SENAO, RT2870_4), 268 USB_ID(SENAO, RT3070), 269 USB_ID(SENAO, RT3071), 270 USB_ID(SENAO, RT3072), 271 USB_ID(SENAO, RT3072_2), 272 USB_ID(SENAO, RT3072_3), 273 USB_ID(SENAO, RT3072_4), 274 USB_ID(SENAO, RT3072_5), 275 USB_ID(SITECOMEU, RT2870_1), 276 USB_ID(SITECOMEU, RT2870_2), 277 USB_ID(SITECOMEU, RT2870_3), 278 USB_ID(SITECOMEU, RT3070_1), 279 USB_ID(SITECOMEU, RT3072_3), 280 USB_ID(SITECOMEU, RT3072_4), 281 USB_ID(SITECOMEU, RT3072_5), 282 USB_ID(SITECOMEU, WL302), 283 USB_ID(SITECOMEU, WL315), 284 USB_ID(SITECOMEU, WL321), 285 USB_ID(SITECOMEU, WL324), 286 USB_ID(SITECOMEU, WL329), 287 USB_ID(SITECOMEU, WL343), 288 USB_ID(SITECOMEU, WL344), 289 USB_ID(SITECOMEU, WL345), 290 USB_ID(SITECOMEU, WL349V4), 291 USB_ID(SITECOMEU, WL608), 292 USB_ID(SITECOMEU, WLA4000), 293 USB_ID(SITECOMEU, WLA5000), 294 USB_ID(SPARKLAN, RT2870_1), 295 USB_ID(SPARKLAN, RT2870_2), 296 USB_ID(SPARKLAN, RT3070), 297 USB_ID(SWEEX2, LW153), 298 USB_ID(SWEEX2, LW303), 299 USB_ID(SWEEX2, LW313), 300 USB_ID(TOSHIBA, RT3070), 301 USB_ID(UMEDIA, RT2870_1), 302 USB_ID(UMEDIA, TEW645UB), 303 USB_ID(ZCOM, RT2870_1), 304 USB_ID(ZCOM, RT2870_2), 305 USB_ID(ZINWELL, RT2870_1), 306 USB_ID(ZINWELL, RT2870_2), 307 USB_ID(ZINWELL, RT3070), 308 USB_ID(ZINWELL, RT3072), 309 USB_ID(ZINWELL, RT3072_2), 310 USB_ID(ZYXEL, NWD2105), 311 USB_ID(ZYXEL, NWD211AN), 312 USB_ID(ZYXEL, RT2870_1), 313 USB_ID(ZYXEL, RT2870_2), 314 USB_ID(ZYXEL, RT3070), 315 }; 316 317 static int run_match(device_t, cfdata_t, void *); 318 static void run_attach(device_t, device_t, void *); 319 static int run_detach(device_t, int); 320 static int run_activate(device_t, enum devact); 321 322 CFATTACH_DECL_NEW(run, sizeof(struct run_softc), 323 run_match, run_attach, run_detach, run_activate); 324 325 static int run_alloc_rx_ring(struct run_softc *); 326 static void run_free_rx_ring(struct run_softc *); 327 static int run_alloc_tx_ring(struct run_softc *, int); 328 static void run_free_tx_ring(struct run_softc *, int); 329 static int run_load_microcode(struct run_softc *); 330 static int run_reset(struct run_softc *); 331 static int run_read(struct run_softc *, uint16_t, uint32_t *); 332 static int run_read_region_1(struct run_softc *, uint16_t, 333 uint8_t *, int); 334 static int run_write_2(struct run_softc *, uint16_t, uint16_t); 335 static int run_write(struct run_softc *, uint16_t, uint32_t); 336 static int run_write_region_1(struct run_softc *, uint16_t, 337 const uint8_t *, int); 338 static int run_set_region_4(struct run_softc *, uint16_t, 339 uint32_t, int); 340 static int run_efuse_read(struct run_softc *, uint16_t, 341 uint16_t *, int); 342 static int run_efuse_read_2(struct run_softc *, uint16_t, 343 uint16_t *); 344 static int run_eeprom_read_2(struct run_softc *, uint16_t, 345 uint16_t *); 346 static int run_rt2870_rf_write(struct run_softc *, uint8_t, 347 uint32_t); 348 static int run_rt3070_rf_read(struct run_softc *, uint8_t, 349 uint8_t *); 350 static int run_rt3070_rf_write(struct run_softc *, uint8_t, 351 uint8_t); 352 static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 353 static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 354 static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 355 static const char * run_get_rf(int); 356 static void run_rt3593_get_txpower(struct run_softc *); 357 static void run_get_txpower(struct run_softc *); 358 static int run_read_eeprom(struct run_softc *); 359 static struct ieee80211_node * 360 run_node_alloc(struct ieee80211_node_table *); 361 static int run_media_change(struct ifnet *); 362 static void run_next_scan(void *); 363 static void run_task(void *); 364 static void run_do_async(struct run_softc *, 365 void (*)(struct run_softc *, void *), void *, int); 366 static int run_newstate(struct ieee80211com *, 367 enum ieee80211_state, int); 368 static void run_newstate_cb(struct run_softc *, void *); 369 static int run_updateedca(struct ieee80211com *); 370 static void run_updateedca_cb(struct run_softc *, void *); 371 #ifdef RUN_HWCRYPTO 372 static int run_set_key(struct ieee80211com *, 373 const struct ieee80211_key *, const uint8_t *); 374 static void run_set_key_cb(struct run_softc *, void *); 375 static int run_delete_key(struct ieee80211com *, 376 const struct ieee80211_key *); 377 static void run_delete_key_cb(struct run_softc *, void *); 378 #endif 379 static void run_calibrate_to(void *); 380 static void run_calibrate_cb(struct run_softc *, void *); 381 static void run_newassoc(struct ieee80211_node *, int); 382 static void run_rx_frame(struct run_softc *, uint8_t *, int); 383 static void run_rxeof(struct usbd_xfer *, void *, 384 usbd_status); 385 static void run_txeof(struct usbd_xfer *, void *, 386 usbd_status); 387 static int run_tx(struct run_softc *, struct mbuf *, 388 struct ieee80211_node *); 389 static void run_start(struct ifnet *); 390 static void run_watchdog(struct ifnet *); 391 static int run_ioctl(struct ifnet *, u_long, void *); 392 static void run_select_chan_group(struct run_softc *, int); 393 static void run_iq_calib(struct run_softc *, u_int); 394 static void run_set_agc(struct run_softc *, uint8_t); 395 static void run_set_rx_antenna(struct run_softc *, int); 396 static void run_rt2870_set_chan(struct run_softc *, u_int); 397 static void run_rt3070_set_chan(struct run_softc *, u_int); 398 static void run_rt3572_set_chan(struct run_softc *, u_int); 399 static void run_rt3593_set_chan(struct run_softc *, u_int); 400 static void run_rt5390_set_chan(struct run_softc *, u_int); 401 static void run_rt5592_set_chan(struct run_softc *, u_int); 402 static int run_set_chan(struct run_softc *, 403 struct ieee80211_channel *); 404 static void run_updateprot(struct run_softc *); 405 static void run_enable_tsf_sync(struct run_softc *); 406 static void run_enable_mrr(struct run_softc *); 407 static void run_set_txpreamble(struct run_softc *); 408 static void run_set_basicrates(struct run_softc *); 409 static void run_set_leds(struct run_softc *, uint16_t); 410 static void run_set_bssid(struct run_softc *, const uint8_t *); 411 static void run_set_macaddr(struct run_softc *, const uint8_t *); 412 static void run_updateslot(struct ifnet *); 413 static void run_updateslot_cb(struct run_softc *, void *); 414 static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 415 static void run_rt5390_bbp_init(struct run_softc *); 416 static int run_bbp_init(struct run_softc *); 417 static int run_rt3070_rf_init(struct run_softc *); 418 static int run_rt3593_rf_init(struct run_softc *); 419 static int run_rt5390_rf_init(struct run_softc *); 420 static int run_rt3070_filter_calib(struct run_softc *, uint8_t, 421 uint8_t, uint8_t *); 422 static void run_rt3070_rf_setup(struct run_softc *); 423 static void run_rt3593_rf_setup(struct run_softc *); 424 static void run_rt5390_rf_setup(struct run_softc *); 425 static int run_txrx_enable(struct run_softc *); 426 static int run_adjust_freq_offset(struct run_softc *); 427 static int run_init(struct ifnet *); 428 static void run_stop(struct ifnet *, int); 429 #ifndef IEEE80211_STA_ONLY 430 static int run_setup_beacon(struct run_softc *); 431 #endif 432 433 static const struct { 434 uint32_t reg; 435 uint32_t val; 436 } rt2870_def_mac[] = { 437 RT2870_DEF_MAC 438 }; 439 440 static const struct { 441 uint8_t reg; 442 uint8_t val; 443 } rt2860_def_bbp[] = { 444 RT2860_DEF_BBP 445 }, rt5390_def_bbp[] = { 446 RT5390_DEF_BBP 447 }, rt5592_def_bbp[] = { 448 RT5592_DEF_BBP 449 }; 450 451 /* 452 * Default values for BBP register R196 for RT5592. 453 */ 454 static const uint8_t rt5592_bbp_r196[] = { 455 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 456 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 457 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 458 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 459 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 460 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 462 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 463 0x2e, 0x36, 0x30, 0x6e 464 }; 465 466 static const struct rfprog { 467 uint8_t chan; 468 uint32_t r1, r2, r3, r4; 469 } rt2860_rf2850[] = { 470 RT2860_RF2850 471 }; 472 473 static const struct { 474 uint8_t n, r, k; 475 } rt3070_freqs[] = { 476 RT3070_RF3052 477 }; 478 479 static const struct rt5592_freqs { 480 uint16_t n; 481 uint8_t k, m, r; 482 } rt5592_freqs_20mhz[] = { 483 RT5592_RF5592_20MHZ 484 },rt5592_freqs_40mhz[] = { 485 RT5592_RF5592_40MHZ 486 }; 487 488 static const struct { 489 uint8_t reg; 490 uint8_t val; 491 } rt3070_def_rf[] = { 492 RT3070_DEF_RF 493 }, rt3572_def_rf[] = { 494 RT3572_DEF_RF 495 },rt3593_def_rf[] = { 496 RT3593_DEF_RF 497 },rt5390_def_rf[] = { 498 RT5390_DEF_RF 499 },rt5392_def_rf[] = { 500 RT5392_DEF_RF 501 },rt5592_def_rf[] = { 502 RT5592_DEF_RF 503 },rt5592_2ghz_def_rf[] = { 504 RT5592_2GHZ_DEF_RF 505 },rt5592_5ghz_def_rf[] = { 506 RT5592_5GHZ_DEF_RF 507 }; 508 509 static const struct { 510 u_int firstchan; 511 u_int lastchan; 512 uint8_t reg; 513 uint8_t val; 514 } rt5592_chan_5ghz[] = { 515 RT5592_CHAN_5GHZ 516 }; 517 518 static int 519 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 520 size_t *sizep) 521 { 522 firmware_handle_t fh; 523 int error; 524 525 if ((error = firmware_open(dname, iname, &fh)) != 0) 526 return error; 527 *sizep = firmware_get_size(fh); 528 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 529 firmware_close(fh); 530 return ENOMEM; 531 } 532 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 533 firmware_free(*ucodep, *sizep); 534 firmware_close(fh); 535 536 return error; 537 } 538 539 static int 540 run_match(device_t parent, cfdata_t match, void *aux) 541 { 542 struct usb_attach_arg *uaa = aux; 543 544 return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? 545 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 546 } 547 548 static void 549 run_attach(device_t parent, device_t self, void *aux) 550 { 551 struct run_softc *sc = device_private(self); 552 struct usb_attach_arg *uaa = aux; 553 struct ieee80211com *ic = &sc->sc_ic; 554 struct ifnet *ifp = &sc->sc_if; 555 usb_interface_descriptor_t *id; 556 usb_endpoint_descriptor_t *ed; 557 char *devinfop; 558 int i, nrx, ntx, ntries, error; 559 uint32_t ver; 560 561 aprint_naive("\n"); 562 aprint_normal("\n"); 563 564 sc->sc_dev = self; 565 sc->sc_udev = uaa->uaa_device; 566 567 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 568 aprint_normal_dev(sc->sc_dev, "%s\n", devinfop); 569 usbd_devinfo_free(devinfop); 570 571 error = usbd_set_config_no(sc->sc_udev, 1, 0); 572 if (error != 0) { 573 aprint_error_dev(sc->sc_dev, "failed to set configuration" 574 ", err=%s\n", usbd_errstr(error)); 575 return; 576 } 577 578 /* get the first interface handle */ 579 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 580 if (error != 0) { 581 aprint_error_dev(sc->sc_dev, 582 "could not get interface handle\n"); 583 return; 584 } 585 586 /* 587 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 588 * and 6 for TX (4 EDCAs + HCCA + Prio). 589 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 590 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 591 */ 592 nrx = ntx = 0; 593 id = usbd_get_interface_descriptor(sc->sc_iface); 594 for (i = 0; i < id->bNumEndpoints; i++) { 595 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 596 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 597 continue; 598 599 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 600 sc->rxq.pipe_no = ed->bEndpointAddress; 601 nrx++; 602 } else if (ntx < 4) { 603 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 604 ntx++; 605 } 606 } 607 /* make sure we've got them all */ 608 if (nrx < 1 || ntx < 4) { 609 aprint_error_dev(sc->sc_dev, "missing endpoint\n"); 610 return; 611 } 612 613 usb_init_task(&sc->sc_task, run_task, sc, 0); 614 callout_init(&sc->scan_to, 0); 615 callout_setfunc(&sc->scan_to, run_next_scan, sc); 616 callout_init(&sc->calib_to, 0); 617 callout_setfunc(&sc->calib_to, run_calibrate_to, sc); 618 619 sc->amrr.amrr_min_success_threshold = 1; 620 sc->amrr.amrr_max_success_threshold = 10; 621 622 /* wait for the chip to settle */ 623 for (ntries = 0; ntries < 100; ntries++) { 624 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 625 return; 626 if (ver != 0 && ver != 0xffffffff) 627 break; 628 DELAY(10); 629 } 630 if (ntries == 100) { 631 aprint_error_dev(sc->sc_dev, 632 "timeout waiting for NIC to initialize\n"); 633 return; 634 } 635 sc->mac_ver = ver >> 16; 636 sc->mac_rev = ver & 0xffff; 637 638 /* retrieve RF rev. no and various other things from EEPROM */ 639 run_read_eeprom(sc); 640 641 aprint_error_dev(sc->sc_dev, 642 "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n", 643 sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 644 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 645 646 ic->ic_ifp = ifp; 647 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 648 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 649 ic->ic_state = IEEE80211_S_INIT; 650 651 /* set device capabilities */ 652 ic->ic_caps = 653 IEEE80211_C_MONITOR | /* monitor mode supported */ 654 #ifndef IEEE80211_STA_ONLY 655 IEEE80211_C_IBSS | /* IBSS mode supported */ 656 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 657 #endif 658 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 659 IEEE80211_C_SHSLOT | /* short slot time supported */ 660 #ifdef RUN_HWCRYPTO 661 IEEE80211_C_WEP | /* WEP */ 662 IEEE80211_C_TKIP | /* TKIP */ 663 IEEE80211_C_AES_CCM | /* AES CCMP */ 664 IEEE80211_C_TKIPMIC | /* TKIPMIC */ 665 #endif 666 IEEE80211_C_WME | /* WME */ 667 IEEE80211_C_WPA; /* WPA/RSN */ 668 669 if (sc->rf_rev == RT2860_RF_2750 || 670 sc->rf_rev == RT2860_RF_2850 || 671 sc->rf_rev == RT3070_RF_3052 || 672 sc->rf_rev == RT3070_RF_3053 || 673 sc->rf_rev == RT5592_RF_5592) { 674 /* set supported .11a rates */ 675 ic->ic_sup_rates[IEEE80211_MODE_11A] = 676 ieee80211_std_rateset_11a; 677 678 /* set supported .11a channels */ 679 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 680 uint8_t chan = rt2860_rf2850[i].chan; 681 ic->ic_channels[chan].ic_freq = 682 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 683 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 684 } 685 } 686 687 /* set supported .11b and .11g rates */ 688 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 689 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 690 691 /* set supported .11b and .11g channels (1 through 14) */ 692 for (i = 1; i <= 14; i++) { 693 ic->ic_channels[i].ic_freq = 694 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 695 ic->ic_channels[i].ic_flags = 696 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 697 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 698 } 699 700 ifp->if_softc = sc; 701 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 702 ifp->if_init = run_init; 703 ifp->if_ioctl = run_ioctl; 704 ifp->if_start = run_start; 705 ifp->if_watchdog = run_watchdog; 706 IFQ_SET_READY(&ifp->if_snd); 707 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 708 709 if_attach(ifp); 710 ieee80211_ifattach(ic); 711 ic->ic_node_alloc = run_node_alloc; 712 ic->ic_newassoc = run_newassoc; 713 ic->ic_updateslot = run_updateslot; 714 ic->ic_wme.wme_update = run_updateedca; 715 #ifdef RUN_HWCRYPTO 716 ic->ic_crypto.cs_key_set = run_set_key; 717 ic->ic_crypto.cs_key_delete = run_delete_key; 718 #endif 719 /* override state transition machine */ 720 sc->sc_newstate = ic->ic_newstate; 721 ic->ic_newstate = run_newstate; 722 ieee80211_media_init(ic, run_media_change, ieee80211_media_status); 723 724 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 725 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 726 &sc->sc_drvbpf); 727 728 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 729 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 730 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 731 732 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 733 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 734 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 735 736 ieee80211_announce(ic); 737 738 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 739 740 if (!pmf_device_register(self, NULL, NULL)) 741 aprint_error_dev(self, "couldn't establish power handler\n"); 742 } 743 744 static int 745 run_detach(device_t self, int flags) 746 { 747 struct run_softc *sc = device_private(self); 748 struct ifnet *ifp = &sc->sc_if; 749 struct ieee80211com *ic = &sc->sc_ic; 750 int s; 751 752 if (ifp->if_softc == NULL) 753 return 0; 754 755 pmf_device_deregister(self); 756 757 s = splusb(); 758 759 sc->sc_flags |= RUN_DETACHING; 760 761 if (ifp->if_flags & IFF_RUNNING) { 762 usb_rem_task(sc->sc_udev, &sc->sc_task); 763 run_stop(ifp, 0); 764 } 765 766 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 767 bpf_detach(ifp); 768 ieee80211_ifdetach(ic); 769 if_detach(ifp); 770 771 splx(s); 772 773 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 774 775 callout_stop(&sc->scan_to); 776 callout_stop(&sc->calib_to); 777 778 callout_destroy(&sc->scan_to); 779 callout_destroy(&sc->calib_to); 780 781 return 0; 782 } 783 784 static int 785 run_activate(device_t self, enum devact act) 786 { 787 struct run_softc *sc = device_private(self); 788 789 switch (act) { 790 case DVACT_DEACTIVATE: 791 if_deactivate(sc->sc_ic.ic_ifp); 792 return 0; 793 default: 794 return EOPNOTSUPP; 795 } 796 } 797 798 static int 799 run_alloc_rx_ring(struct run_softc *sc) 800 { 801 struct run_rx_ring *rxq = &sc->rxq; 802 int i, error; 803 804 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 805 if (error != 0) 806 goto fail; 807 808 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 809 struct run_rx_data *data = &rxq->data[i]; 810 811 data->sc = sc; /* backpointer for callbacks */ 812 813 error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, 814 USBD_SHORT_XFER_OK, 0, &data->xfer); 815 if (error) 816 goto fail; 817 818 data->buf = usbd_get_buffer(data->xfer); 819 } 820 if (error != 0) 821 fail: run_free_rx_ring(sc); 822 return error; 823 } 824 825 static void 826 run_free_rx_ring(struct run_softc *sc) 827 { 828 struct run_rx_ring *rxq = &sc->rxq; 829 int i; 830 831 if (rxq->pipeh != NULL) { 832 usbd_abort_pipe(rxq->pipeh); 833 } 834 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 835 if (rxq->data[i].xfer != NULL) 836 usbd_destroy_xfer(rxq->data[i].xfer); 837 rxq->data[i].xfer = NULL; 838 } 839 if (rxq->pipeh != NULL) { 840 usbd_close_pipe(rxq->pipeh); 841 rxq->pipeh = NULL; 842 } 843 } 844 845 static int 846 run_alloc_tx_ring(struct run_softc *sc, int qid) 847 { 848 struct run_tx_ring *txq = &sc->txq[qid]; 849 int i, error; 850 851 txq->cur = txq->queued = 0; 852 853 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 854 if (error != 0) 855 goto fail; 856 857 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 858 struct run_tx_data *data = &txq->data[i]; 859 860 data->sc = sc; /* backpointer for callbacks */ 861 data->qid = qid; 862 863 error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, 864 USBD_FORCE_SHORT_XFER, 0, &data->xfer); 865 if (error) 866 goto fail; 867 868 data->buf = usbd_get_buffer(data->xfer); 869 /* zeroize the TXD + TXWI part */ 870 memset(data->buf, 0, sizeof(struct rt2870_txd) + 871 sizeof(struct rt2860_txwi)); 872 } 873 if (error != 0) 874 fail: run_free_tx_ring(sc, qid); 875 return error; 876 } 877 878 static void 879 run_free_tx_ring(struct run_softc *sc, int qid) 880 { 881 struct run_tx_ring *txq = &sc->txq[qid]; 882 int i; 883 884 if (txq->pipeh != NULL) { 885 usbd_abort_pipe(txq->pipeh); 886 usbd_close_pipe(txq->pipeh); 887 txq->pipeh = NULL; 888 } 889 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 890 if (txq->data[i].xfer != NULL) 891 usbd_destroy_xfer(txq->data[i].xfer); 892 txq->data[i].xfer = NULL; 893 } 894 } 895 896 static int 897 run_load_microcode(struct run_softc *sc) 898 { 899 usb_device_request_t req; 900 const char *fwname; 901 u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ 902 size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ 903 uint32_t tmp; 904 int ntries, error; 905 906 /* RT3071/RT3072 use a different firmware */ 907 if (sc->mac_ver != 0x2860 && 908 sc->mac_ver != 0x2872 && 909 sc->mac_ver != 0x3070) 910 fwname = "run-rt3071"; 911 else 912 fwname = "run-rt2870"; 913 914 if ((error = firmware_load("run", fwname, &ucode, &size)) != 0) { 915 aprint_error_dev(sc->sc_dev, 916 "error %d, could not read firmware %s\n", error, fwname); 917 return error; 918 } 919 if (size != 4096) { 920 aprint_error_dev(sc->sc_dev, 921 "invalid firmware size (should be 4KB)\n"); 922 firmware_free(ucode, size); 923 return EINVAL; 924 } 925 926 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 927 /* write microcode image */ 928 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 929 firmware_free(ucode, size); 930 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 931 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 932 933 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 934 req.bRequest = RT2870_RESET; 935 USETW(req.wValue, 8); 936 USETW(req.wIndex, 0); 937 USETW(req.wLength, 0); 938 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 939 return error; 940 941 usbd_delay_ms(sc->sc_udev, 10); 942 run_write(sc, RT2860_H2M_MAILBOX, 0); 943 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 944 return error; 945 946 /* wait until microcontroller is ready */ 947 for (ntries = 0; ntries < 1000; ntries++) { 948 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 949 return error; 950 if (tmp & RT2860_MCU_READY) 951 break; 952 usbd_delay_ms(sc->sc_udev, 10); 953 } 954 if (ntries == 1000) { 955 aprint_error_dev(sc->sc_dev, 956 "timeout waiting for MCU to initialize\n"); 957 return ETIMEDOUT; 958 } 959 960 sc->sc_flags |= RUN_FWLOADED; 961 962 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 963 return 0; 964 } 965 966 static int 967 run_reset(struct run_softc *sc) 968 { 969 usb_device_request_t req; 970 971 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 972 req.bRequest = RT2870_RESET; 973 USETW(req.wValue, 1); 974 USETW(req.wIndex, 0); 975 USETW(req.wLength, 0); 976 return usbd_do_request(sc->sc_udev, &req, NULL); 977 } 978 979 static int 980 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 981 { 982 uint32_t tmp; 983 int error; 984 985 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 986 if (error == 0) 987 *val = le32toh(tmp); 988 else 989 *val = 0xffffffff; 990 return error; 991 } 992 993 static int 994 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 995 { 996 usb_device_request_t req; 997 998 req.bmRequestType = UT_READ_VENDOR_DEVICE; 999 req.bRequest = RT2870_READ_REGION_1; 1000 USETW(req.wValue, 0); 1001 USETW(req.wIndex, reg); 1002 USETW(req.wLength, len); 1003 return usbd_do_request(sc->sc_udev, &req, buf); 1004 } 1005 1006 static int 1007 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 1008 { 1009 usb_device_request_t req; 1010 1011 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1012 req.bRequest = RT2870_WRITE_2; 1013 USETW(req.wValue, val); 1014 USETW(req.wIndex, reg); 1015 USETW(req.wLength, 0); 1016 return usbd_do_request(sc->sc_udev, &req, NULL); 1017 } 1018 1019 static int 1020 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 1021 { 1022 int error; 1023 1024 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 1025 error = run_write_2(sc, reg + 2, val >> 16); 1026 return error; 1027 } 1028 1029 static int 1030 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 1031 int len) 1032 { 1033 #if 1 1034 int i, error = 0; 1035 /* 1036 * NB: the WRITE_REGION_1 command is not stable on RT2860. 1037 * We thus issue multiple WRITE_2 commands instead. 1038 */ 1039 KASSERT((len & 1) == 0); 1040 for (i = 0; i < len && error == 0; i += 2) 1041 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 1042 return error; 1043 #else 1044 usb_device_request_t req; 1045 1046 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1047 req.bRequest = RT2870_WRITE_REGION_1; 1048 USETW(req.wValue, 0); 1049 USETW(req.wIndex, reg); 1050 USETW(req.wLength, len); 1051 return usbd_do_request(sc->sc_udev, &req, buf); 1052 #endif 1053 } 1054 1055 static int 1056 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 1057 { 1058 int error = 0; 1059 1060 for (; count > 0 && error == 0; count--, reg += 4) 1061 error = run_write(sc, reg, val); 1062 return error; 1063 } 1064 1065 static int 1066 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) 1067 { 1068 uint32_t tmp; 1069 uint16_t reg; 1070 int error, ntries; 1071 1072 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1073 return error; 1074 1075 if (count == 2) 1076 addr *= 2; 1077 /*- 1078 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1079 * DATA0: F E D C 1080 * DATA1: B A 9 8 1081 * DATA2: 7 6 5 4 1082 * DATA3: 3 2 1 0 1083 */ 1084 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1085 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1086 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1087 for (ntries = 0; ntries < 100; ntries++) { 1088 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1089 return error; 1090 if (!(tmp & RT3070_EFSROM_KICK)) 1091 break; 1092 usbd_delay_ms(sc->sc_udev, 2); 1093 } 1094 if (ntries == 100) 1095 return ETIMEDOUT; 1096 1097 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1098 *val = 0xffff; /* address not found */ 1099 return 0; 1100 } 1101 /* determine to which 32-bit register our 16-bit word belongs */ 1102 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1103 if ((error = run_read(sc, reg, &tmp)) != 0) 1104 return error; 1105 1106 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1107 return 0; 1108 } 1109 1110 /* Read 16-bit from eFUSE ROM for RT3xxxx. */ 1111 static int 1112 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1113 { 1114 return run_efuse_read(sc, addr, val, 2); 1115 } 1116 1117 static int 1118 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1119 { 1120 usb_device_request_t req; 1121 uint16_t tmp; 1122 int error; 1123 1124 addr *= 2; 1125 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1126 req.bRequest = RT2870_EEPROM_READ; 1127 USETW(req.wValue, 0); 1128 USETW(req.wIndex, addr); 1129 USETW(req.wLength, sizeof(tmp)); 1130 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1131 if (error == 0) 1132 *val = le16toh(tmp); 1133 else 1134 *val = 0xffff; 1135 return error; 1136 } 1137 1138 static __inline int 1139 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1140 { 1141 1142 /* either eFUSE ROM or EEPROM */ 1143 return sc->sc_srom_read(sc, addr, val); 1144 } 1145 1146 static int 1147 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1148 { 1149 uint32_t tmp; 1150 int error, ntries; 1151 1152 for (ntries = 0; ntries < 10; ntries++) { 1153 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1154 return error; 1155 if (!(tmp & RT2860_RF_REG_CTRL)) 1156 break; 1157 } 1158 if (ntries == 10) 1159 return ETIMEDOUT; 1160 1161 /* RF registers are 24-bit on the RT2860 */ 1162 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1163 (val & 0x3fffff) << 2 | (reg & 3); 1164 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1165 } 1166 1167 static int 1168 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1169 { 1170 uint32_t tmp; 1171 int error, ntries; 1172 1173 for (ntries = 0; ntries < 100; ntries++) { 1174 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1175 return error; 1176 if (!(tmp & RT3070_RF_KICK)) 1177 break; 1178 } 1179 if (ntries == 100) 1180 return ETIMEDOUT; 1181 1182 tmp = RT3070_RF_KICK | reg << 8; 1183 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1184 return error; 1185 1186 for (ntries = 0; ntries < 100; ntries++) { 1187 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1188 return error; 1189 if (!(tmp & RT3070_RF_KICK)) 1190 break; 1191 } 1192 if (ntries == 100) 1193 return ETIMEDOUT; 1194 1195 *val = tmp & 0xff; 1196 return 0; 1197 } 1198 1199 static int 1200 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1201 { 1202 uint32_t tmp; 1203 int error, ntries; 1204 1205 for (ntries = 0; ntries < 10; ntries++) { 1206 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1207 return error; 1208 if (!(tmp & RT3070_RF_KICK)) 1209 break; 1210 } 1211 if (ntries == 10) 1212 return ETIMEDOUT; 1213 1214 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1215 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1216 } 1217 1218 static int 1219 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1220 { 1221 uint32_t tmp; 1222 int ntries, error; 1223 1224 for (ntries = 0; ntries < 10; ntries++) { 1225 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1226 return error; 1227 if (!(tmp & RT2860_BBP_CSR_KICK)) 1228 break; 1229 } 1230 if (ntries == 10) 1231 return ETIMEDOUT; 1232 1233 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1234 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1235 return error; 1236 1237 for (ntries = 0; ntries < 10; ntries++) { 1238 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1239 return error; 1240 if (!(tmp & RT2860_BBP_CSR_KICK)) 1241 break; 1242 } 1243 if (ntries == 10) 1244 return ETIMEDOUT; 1245 1246 *val = tmp & 0xff; 1247 return 0; 1248 } 1249 1250 static int 1251 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1252 { 1253 uint32_t tmp; 1254 int ntries, error; 1255 1256 for (ntries = 0; ntries < 10; ntries++) { 1257 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1258 return error; 1259 if (!(tmp & RT2860_BBP_CSR_KICK)) 1260 break; 1261 } 1262 if (ntries == 10) 1263 return ETIMEDOUT; 1264 1265 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1266 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1267 } 1268 1269 /* 1270 * Send a command to the 8051 microcontroller unit. 1271 */ 1272 static int 1273 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1274 { 1275 uint32_t tmp; 1276 int error, ntries; 1277 1278 for (ntries = 0; ntries < 100; ntries++) { 1279 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1280 return error; 1281 if (!(tmp & RT2860_H2M_BUSY)) 1282 break; 1283 } 1284 if (ntries == 100) 1285 return ETIMEDOUT; 1286 1287 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1288 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1289 error = run_write(sc, RT2860_HOST_CMD, cmd); 1290 return error; 1291 } 1292 1293 /* 1294 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1295 * Used to adjust per-rate Tx power registers. 1296 */ 1297 static __inline uint32_t 1298 b4inc(uint32_t b32, int8_t delta) 1299 { 1300 int8_t i, b4; 1301 1302 for (i = 0; i < 8; i++) { 1303 b4 = b32 & 0xf; 1304 b4 += delta; 1305 if (b4 < 0) 1306 b4 = 0; 1307 else if (b4 > 0xf) 1308 b4 = 0xf; 1309 b32 = b32 >> 4 | b4 << 28; 1310 } 1311 return b32; 1312 } 1313 1314 static const char * 1315 run_get_rf(int rev) 1316 { 1317 switch (rev) { 1318 case RT2860_RF_2820: return "RT2820"; 1319 case RT2860_RF_2850: return "RT2850"; 1320 case RT2860_RF_2720: return "RT2720"; 1321 case RT2860_RF_2750: return "RT2750"; 1322 case RT3070_RF_3020: return "RT3020"; 1323 case RT3070_RF_2020: return "RT2020"; 1324 case RT3070_RF_3021: return "RT3021"; 1325 case RT3070_RF_3022: return "RT3022"; 1326 case RT3070_RF_3052: return "RT3052"; 1327 case RT3070_RF_3053: return "RT3053"; 1328 case RT5592_RF_5592: return "RT5592"; 1329 case RT5390_RF_5370: return "RT5370"; 1330 case RT5390_RF_5372: return "RT5372"; 1331 } 1332 return "unknown"; 1333 } 1334 1335 static void 1336 run_rt3593_get_txpower(struct run_softc *sc) 1337 { 1338 uint16_t addr, val; 1339 int i; 1340 1341 /* Read power settings for 2GHz channels. */ 1342 for (i = 0; i < 14; i += 2) { 1343 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1344 RT2860_EEPROM_PWR2GHZ_BASE1; 1345 run_srom_read(sc, addr + i / 2, &val); 1346 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1347 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1348 1349 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1350 RT2860_EEPROM_PWR2GHZ_BASE2; 1351 run_srom_read(sc, addr + i / 2, &val); 1352 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1353 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1354 1355 if (sc->ntxchains == 3) { 1356 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1357 &val); 1358 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1359 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1360 } 1361 } 1362 /* Fix broken Tx power entries. */ 1363 for (i = 0; i < 14; i++) { 1364 if (sc->txpow1[i] > 31) 1365 sc->txpow1[i] = 5; 1366 if (sc->txpow2[i] > 31) 1367 sc->txpow2[i] = 5; 1368 if (sc->ntxchains == 3) { 1369 if (sc->txpow3[i] > 31) 1370 sc->txpow3[i] = 5; 1371 } 1372 } 1373 /* Read power settings for 5GHz channels. */ 1374 for (i = 0; i < 40; i += 2) { 1375 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1376 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1377 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1378 1379 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1380 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1381 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1382 1383 if (sc->ntxchains == 3) { 1384 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1385 &val); 1386 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1387 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1388 } 1389 } 1390 } 1391 1392 static void 1393 run_get_txpower(struct run_softc *sc) 1394 { 1395 uint16_t val; 1396 int i; 1397 1398 /* Read power settings for 2GHz channels. */ 1399 for (i = 0; i < 14; i += 2) { 1400 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1401 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1402 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1403 1404 if (sc->mac_ver != 0x5390) { 1405 run_srom_read(sc, 1406 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1407 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1408 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1409 } 1410 } 1411 /* Fix broken Tx power entries. */ 1412 for (i = 0; i < 14; i++) { 1413 if (sc->mac_ver >= 0x5390) { 1414 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) 1415 sc->txpow1[i] = 5; 1416 } else { 1417 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1418 sc->txpow1[i] = 5; 1419 } 1420 if (sc->mac_ver > 0x5390) { 1421 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) 1422 sc->txpow2[i] = 5; 1423 } else if (sc->mac_ver < 0x5390) { 1424 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1425 sc->txpow2[i] = 5; 1426 } 1427 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1428 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1429 } 1430 /* Read power settings for 5GHz channels. */ 1431 for (i = 0; i < 40; i += 2) { 1432 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1433 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1434 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1435 1436 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1437 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1438 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1439 } 1440 /* Fix broken Tx power entries. */ 1441 for (i = 0; i < 40; i++ ) { 1442 if (sc->mac_ver != 0x5592) { 1443 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1444 sc->txpow1[14 + i] = 5; 1445 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1446 sc->txpow2[14 + i] = 5; 1447 } 1448 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1449 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1450 sc->txpow2[14 + i])); 1451 } 1452 } 1453 1454 static int 1455 run_read_eeprom(struct run_softc *sc) 1456 { 1457 struct ieee80211com *ic = &sc->sc_ic; 1458 int8_t delta_2ghz, delta_5ghz; 1459 uint32_t tmp; 1460 uint16_t val; 1461 int ridx, ant, i; 1462 1463 /* check whether the ROM is eFUSE ROM or EEPROM */ 1464 sc->sc_srom_read = run_eeprom_read_2; 1465 if (sc->mac_ver >= 0x3070) { 1466 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1467 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1468 if (tmp & RT3070_SEL_EFUSE) 1469 sc->sc_srom_read = run_efuse_read_2; 1470 } 1471 1472 /* read ROM version */ 1473 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1474 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1475 1476 /* read MAC address */ 1477 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1478 ic->ic_myaddr[0] = val & 0xff; 1479 ic->ic_myaddr[1] = val >> 8; 1480 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1481 ic->ic_myaddr[2] = val & 0xff; 1482 ic->ic_myaddr[3] = val >> 8; 1483 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1484 ic->ic_myaddr[4] = val & 0xff; 1485 ic->ic_myaddr[5] = val >> 8; 1486 1487 /* read vendor BBP settings */ 1488 for (i = 0; i < 10; i++) { 1489 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1490 sc->bbp[i].val = val & 0xff; 1491 sc->bbp[i].reg = val >> 8; 1492 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 1493 } 1494 1495 /* read vendor RF settings */ 1496 for (i = 0; i < 8; i++) { 1497 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, &val); 1498 sc->rf[i].val = val & 0xff; 1499 sc->rf[i].reg = val >> 8; 1500 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1501 sc->rf[i].val)); 1502 } 1503 1504 /* read RF frequency offset from EEPROM */ 1505 run_srom_read(sc, RT2860_EEPROM_FREQ_LEDS, &val); 1506 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1507 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1508 1509 if ((val >> 8) != 0xff) { 1510 /* read LEDs operating mode */ 1511 sc->leds = val >> 8; 1512 run_srom_read(sc, RT2860_EEPROM_LED1, &sc->led[0]); 1513 run_srom_read(sc, RT2860_EEPROM_LED2, &sc->led[1]); 1514 run_srom_read(sc, RT2860_EEPROM_LED3, &sc->led[2]); 1515 } else { 1516 /* broken EEPROM, use default settings */ 1517 sc->leds = 0x01; 1518 sc->led[0] = 0x5555; 1519 sc->led[1] = 0x2221; 1520 sc->led[2] = 0x5627; /* differs from RT2860 */ 1521 } 1522 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1523 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1524 1525 /* read RF information */ 1526 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1527 if (val == 0xffff) { 1528 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1529 if (sc->mac_ver == 0x3572) { 1530 /* default to RF3052 2T2R */ 1531 sc->rf_rev = RT3070_RF_3052; 1532 sc->ntxchains = 2; 1533 sc->nrxchains = 2; 1534 } else if (sc->mac_ver >= 0x3070) { 1535 /* default to RF3020 1T1R */ 1536 sc->rf_rev = RT3070_RF_3020; 1537 sc->ntxchains = 1; 1538 sc->nrxchains = 1; 1539 } else { 1540 /* default to RF2820 1T2R */ 1541 sc->rf_rev = RT2860_RF_2820; 1542 sc->ntxchains = 1; 1543 sc->nrxchains = 2; 1544 } 1545 } else { 1546 sc->rf_rev = (val >> 8) & 0xf; 1547 sc->ntxchains = (val >> 4) & 0xf; 1548 sc->nrxchains = val & 0xf; 1549 } 1550 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1551 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1552 1553 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1554 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1555 /* check if driver should patch the DAC issue */ 1556 if ((val >> 8) != 0xff) 1557 sc->patch_dac = (val >> 15) & 1; 1558 if ((val & 0xff) != 0xff) { 1559 sc->ext_5ghz_lna = (val >> 3) & 1; 1560 sc->ext_2ghz_lna = (val >> 2) & 1; 1561 /* check if RF supports automatic Tx access gain control */ 1562 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1563 /* check if we have a hardware radio switch */ 1564 sc->rfswitch = val & 1; 1565 } 1566 1567 /* Read Tx power settings. */ 1568 if (sc->mac_ver == 0x3593) 1569 run_rt3593_get_txpower(sc); 1570 else 1571 run_get_txpower(sc); 1572 1573 /* read Tx power compensation for each Tx rate */ 1574 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1575 delta_2ghz = delta_5ghz = 0; 1576 if ((val & 0xff) != 0xff && (val & 0x80)) { 1577 delta_2ghz = val & 0xf; 1578 if (!(val & 0x40)) /* negative number */ 1579 delta_2ghz = -delta_2ghz; 1580 } 1581 val >>= 8; 1582 if ((val & 0xff) != 0xff && (val & 0x80)) { 1583 delta_5ghz = val & 0xf; 1584 if (!(val & 0x40)) /* negative number */ 1585 delta_5ghz = -delta_5ghz; 1586 } 1587 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1588 delta_2ghz, delta_5ghz)); 1589 1590 for (ridx = 0; ridx < 5; ridx++) { 1591 uint32_t reg; 1592 1593 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1594 reg = val; 1595 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1596 reg |= (uint32_t)val << 16; 1597 1598 sc->txpow20mhz[ridx] = reg; 1599 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1600 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1601 1602 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1603 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1604 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1605 } 1606 1607 /* read RSSI offsets and LNA gains from EEPROM */ 1608 run_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ, &val); 1609 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1610 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1611 run_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ, &val); 1612 if (sc->mac_ver >= 0x3070) { 1613 if (sc->mac_ver == 0x3593) { 1614 sc->txmixgain_2ghz = 0; 1615 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1616 } else { 1617 /* 1618 * On RT3070 chips (limited to 2 Rx chains), this ROM 1619 * field contains the Tx mixer gain for the 2GHz band. 1620 */ 1621 if ((val & 0xff) != 0xff) 1622 sc->txmixgain_2ghz = val & 0x7; 1623 } 1624 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1625 } else { 1626 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1627 } 1628 if (sc->mac_ver == 0x3593) 1629 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1630 sc->lna[2] = val >> 8; /* channel group 2 */ 1631 1632 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1633 RT3593_EEPROM_RSSI2_5GHZ, &val); 1634 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1635 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1636 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1637 RT3593_EEPROM_RSSI2_5GHZ, &val); 1638 if (sc->mac_ver == 0x3572) { 1639 /* 1640 * On RT3572 chips (limited to 2 Rx chains), this ROM 1641 * field contains the Tx mixer gain for the 5GHz band. 1642 */ 1643 if ((val & 0xff) != 0xff) 1644 sc->txmixgain_5ghz = val & 0x7; 1645 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1646 } else { 1647 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1648 } 1649 if (sc->mac_ver == 0x3593) { 1650 sc->txmixgain_5ghz = 0; 1651 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1652 } 1653 sc->lna[3] = val >> 8; /* channel group 3 */ 1654 1655 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1656 RT3593_EEPROM_LNA, &val); 1657 sc->lna[0] = val & 0xff; /* channel group 0 */ 1658 sc->lna[1] = val >> 8; /* channel group 1 */ 1659 1660 /* fix broken 5GHz LNA entries */ 1661 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1662 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1663 sc->lna[2] = sc->lna[1]; 1664 } 1665 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1666 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1667 sc->lna[3] = sc->lna[1]; 1668 } 1669 1670 /* fix broken RSSI offset entries */ 1671 for (ant = 0; ant < 3; ant++) { 1672 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1673 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1674 ant + 1, sc->rssi_2ghz[ant])); 1675 sc->rssi_2ghz[ant] = 0; 1676 } 1677 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1678 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1679 ant + 1, sc->rssi_5ghz[ant])); 1680 sc->rssi_5ghz[ant] = 0; 1681 } 1682 } 1683 return 0; 1684 } 1685 1686 static struct ieee80211_node * 1687 run_node_alloc(struct ieee80211_node_table *nt) 1688 { 1689 struct run_node *rn = 1690 malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1691 return rn ? &rn->ni : NULL; 1692 } 1693 1694 static int 1695 run_media_change(struct ifnet *ifp) 1696 { 1697 struct run_softc *sc = ifp->if_softc; 1698 struct ieee80211com *ic = &sc->sc_ic; 1699 uint8_t rate, ridx; 1700 int error; 1701 1702 error = ieee80211_media_change(ifp); 1703 if (error != ENETRESET) 1704 return error; 1705 1706 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1707 rate = ic->ic_sup_rates[ic->ic_curmode]. 1708 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1709 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1710 if (rt2860_rates[ridx].rate == rate) 1711 break; 1712 sc->fixed_ridx = ridx; 1713 } 1714 1715 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1716 run_init(ifp); 1717 1718 return 0; 1719 } 1720 1721 static void 1722 run_next_scan(void *arg) 1723 { 1724 struct run_softc *sc = arg; 1725 1726 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1727 ieee80211_next_scan(&sc->sc_ic); 1728 } 1729 1730 static void 1731 run_task(void *arg) 1732 { 1733 struct run_softc *sc = arg; 1734 struct run_host_cmd_ring *ring = &sc->cmdq; 1735 struct run_host_cmd *cmd; 1736 int s; 1737 1738 /* process host commands */ 1739 s = splusb(); 1740 while (ring->next != ring->cur) { 1741 cmd = &ring->cmd[ring->next]; 1742 splx(s); 1743 /* callback */ 1744 cmd->cb(sc, cmd->data); 1745 s = splusb(); 1746 ring->queued--; 1747 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1748 } 1749 wakeup(ring); 1750 splx(s); 1751 } 1752 1753 static void 1754 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1755 void *arg, int len) 1756 { 1757 struct run_host_cmd_ring *ring = &sc->cmdq; 1758 struct run_host_cmd *cmd; 1759 int s; 1760 1761 if (sc->sc_flags & RUN_DETACHING) 1762 return; 1763 1764 s = splusb(); 1765 cmd = &ring->cmd[ring->cur]; 1766 cmd->cb = cb; 1767 KASSERT(len <= sizeof(cmd->data)); 1768 memcpy(cmd->data, arg, len); 1769 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1770 1771 /* if there is no pending command already, schedule a task */ 1772 if (++ring->queued == 1) 1773 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1774 splx(s); 1775 } 1776 1777 static int 1778 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1779 { 1780 struct run_softc *sc = ic->ic_ifp->if_softc; 1781 struct run_cmd_newstate cmd; 1782 1783 callout_stop(&sc->scan_to); 1784 callout_stop(&sc->calib_to); 1785 1786 /* do it in a process context */ 1787 cmd.state = nstate; 1788 cmd.arg = arg; 1789 run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); 1790 return 0; 1791 } 1792 1793 static void 1794 run_newstate_cb(struct run_softc *sc, void *arg) 1795 { 1796 struct run_cmd_newstate *cmd = arg; 1797 struct ifnet *ifp = &sc->sc_if; 1798 struct ieee80211com *ic = &sc->sc_ic; 1799 enum ieee80211_state ostate; 1800 struct ieee80211_node *ni; 1801 uint32_t tmp, sta[3]; 1802 uint8_t wcid; 1803 int s; 1804 1805 s = splnet(); 1806 ostate = ic->ic_state; 1807 1808 if (ostate == IEEE80211_S_RUN) { 1809 /* turn link LED off */ 1810 run_set_leds(sc, RT2860_LED_RADIO); 1811 } 1812 1813 switch (cmd->state) { 1814 case IEEE80211_S_INIT: 1815 if (ostate == IEEE80211_S_RUN) { 1816 /* abort TSF synchronization */ 1817 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1818 run_write(sc, RT2860_BCN_TIME_CFG, 1819 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1820 RT2860_TBTT_TIMER_EN)); 1821 } 1822 break; 1823 1824 case IEEE80211_S_SCAN: 1825 run_set_chan(sc, ic->ic_curchan); 1826 callout_schedule(&sc->scan_to, hz / 5); 1827 break; 1828 1829 case IEEE80211_S_AUTH: 1830 case IEEE80211_S_ASSOC: 1831 run_set_chan(sc, ic->ic_curchan); 1832 break; 1833 1834 case IEEE80211_S_RUN: 1835 run_set_chan(sc, ic->ic_curchan); 1836 1837 ni = ic->ic_bss; 1838 1839 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1840 run_updateslot(ifp); 1841 run_enable_mrr(sc); 1842 run_set_txpreamble(sc); 1843 run_set_basicrates(sc); 1844 run_set_bssid(sc, ni->ni_bssid); 1845 } 1846 #ifndef IEEE80211_STA_ONLY 1847 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1848 ic->ic_opmode == IEEE80211_M_IBSS) 1849 (void)run_setup_beacon(sc); 1850 #endif 1851 if (ic->ic_opmode == IEEE80211_M_STA) { 1852 /* add BSS entry to the WCID table */ 1853 wcid = RUN_AID2WCID(ni->ni_associd); 1854 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1855 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1856 1857 /* fake a join to init the tx rate */ 1858 run_newassoc(ni, 1); 1859 } 1860 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1861 run_enable_tsf_sync(sc); 1862 1863 /* clear statistic registers used by AMRR */ 1864 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1865 (uint8_t *)sta, sizeof(sta)); 1866 /* start calibration timer */ 1867 callout_schedule(&sc->calib_to, hz); 1868 } 1869 1870 /* turn link LED on */ 1871 run_set_leds(sc, RT2860_LED_RADIO | 1872 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1873 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1874 break; 1875 } 1876 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1877 splx(s); 1878 } 1879 1880 static int 1881 run_updateedca(struct ieee80211com *ic) 1882 { 1883 1884 /* do it in a process context */ 1885 run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); 1886 return 0; 1887 } 1888 1889 /* ARGSUSED */ 1890 static void 1891 run_updateedca_cb(struct run_softc *sc, void *arg) 1892 { 1893 struct ieee80211com *ic = &sc->sc_ic; 1894 int s, aci; 1895 1896 s = splnet(); 1897 /* update MAC TX configuration registers */ 1898 for (aci = 0; aci < WME_NUM_AC; aci++) { 1899 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1900 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 1901 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 1902 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 1903 ic->ic_wme.wme_params[aci].wmep_txopLimit); 1904 } 1905 1906 /* update SCH/DMA registers too */ 1907 run_write(sc, RT2860_WMM_AIFSN_CFG, 1908 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 1909 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 1910 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 1911 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 1912 run_write(sc, RT2860_WMM_CWMIN_CFG, 1913 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 1914 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 1915 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 1916 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 1917 run_write(sc, RT2860_WMM_CWMAX_CFG, 1918 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 1919 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 1920 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 1921 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 1922 run_write(sc, RT2860_WMM_TXOP0_CFG, 1923 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 1924 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 1925 run_write(sc, RT2860_WMM_TXOP1_CFG, 1926 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 1927 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 1928 splx(s); 1929 } 1930 1931 #ifdef RUN_HWCRYPTO 1932 static int 1933 run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, 1934 const uint8_t *mac) 1935 { 1936 struct run_softc *sc = ic->ic_ifp->if_softc; 1937 struct ieee80211_node *ni = ic->ic_bss; 1938 struct run_cmd_key cmd; 1939 1940 /* do it in a process context */ 1941 cmd.key = *k; 1942 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1943 run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); 1944 return 1; 1945 } 1946 1947 static void 1948 run_set_key_cb(struct run_softc *sc, void *arg) 1949 { 1950 #ifndef IEEE80211_STA_ONLY 1951 struct ieee80211com *ic = &sc->sc_ic; 1952 #endif 1953 struct run_cmd_key *cmd = arg; 1954 struct ieee80211_key *k = &cmd->key; 1955 uint32_t attr; 1956 uint16_t base; 1957 uint8_t mode, wcid, iv[8]; 1958 1959 /* map net80211 cipher to RT2860 security mode */ 1960 switch (k->wk_cipher->ic_cipher) { 1961 case IEEE80211_CIPHER_WEP: 1962 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 1963 if (k->wk_keylen == 5) 1964 mode = RT2860_MODE_WEP40; 1965 else 1966 mode = RT2860_MODE_WEP104; 1967 break; 1968 case IEEE80211_CIPHER_TKIP: 1969 mode = RT2860_MODE_TKIP; 1970 break; 1971 case IEEE80211_CIPHER_AES_CCM: 1972 mode = RT2860_MODE_AES_CCMP; 1973 break; 1974 default: 1975 return; 1976 } 1977 1978 if (k->wk_flags & IEEE80211_KEY_GROUP) { 1979 wcid = 0; /* NB: update WCID0 for group keys */ 1980 base = RT2860_SKEY(0, k->wk_keyix); 1981 } else { 1982 wcid = RUN_AID2WCID(cmd->associd); 1983 base = RT2860_PKEY(wcid); 1984 } 1985 1986 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 1987 run_write_region_1(sc, base, k->wk_key, 16); 1988 #ifndef IEEE80211_STA_ONLY 1989 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1990 run_write_region_1(sc, base + 16, &k->wk_key[16], 8); 1991 run_write_region_1(sc, base + 24, &k->wk_key[24], 8); 1992 } else 1993 #endif 1994 { 1995 run_write_region_1(sc, base + 16, &k->wk_key[24], 8); 1996 run_write_region_1(sc, base + 24, &k->wk_key[16], 8); 1997 } 1998 } else { 1999 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 2000 run_write_region_1(sc, base, k->wk_key, 2001 (k->wk_keylen + 1) & ~1); 2002 } 2003 2004 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 2005 (k->wk_flags & IEEE80211_KEY_XMIT)) { 2006 /* set initial packet number in IV+EIV */ 2007 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 2008 memset(iv, 0, sizeof(iv)); 2009 iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; 2010 } else { 2011 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2012 iv[0] = k->wk_keytsc >> 8; 2013 iv[1] = (iv[0] | 0x20) & 0x7f; 2014 iv[2] = k->wk_keytsc; 2015 } else /* CCMP */ { 2016 iv[0] = k->wk_keytsc; 2017 iv[1] = k->wk_keytsc >> 8; 2018 iv[2] = 0; 2019 } 2020 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 2021 iv[4] = k->wk_keytsc >> 16; 2022 iv[5] = k->wk_keytsc >> 24; 2023 iv[6] = k->wk_keytsc >> 32; 2024 iv[7] = k->wk_keytsc >> 40; 2025 } 2026 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2027 } 2028 2029 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2030 /* install group key */ 2031 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2032 attr &= ~(0xf << (k->wk_keyix * 4)); 2033 attr |= mode << (k->wk_keyix * 4); 2034 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2035 } else { 2036 /* install pairwise key */ 2037 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2038 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2039 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2040 } 2041 } 2042 2043 static int 2044 run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 2045 { 2046 struct run_softc *sc = ic->ic_ifp->if_softc; 2047 struct ieee80211_node *ni = ic->ic_bss; 2048 struct run_cmd_key cmd; 2049 2050 /* do it in a process context */ 2051 cmd.key = *k; 2052 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2053 run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); 2054 return 1; 2055 } 2056 2057 static void 2058 run_delete_key_cb(struct run_softc *sc, void *arg) 2059 { 2060 struct run_cmd_key *cmd = arg; 2061 struct ieee80211_key *k = &cmd->key; 2062 uint32_t attr; 2063 uint8_t wcid; 2064 2065 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 2066 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2067 2068 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2069 /* remove group key */ 2070 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2071 attr &= ~(0xf << (k->wk_keyix * 4)); 2072 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2073 2074 } else { 2075 /* remove pairwise key */ 2076 wcid = RUN_AID2WCID(cmd->associd); 2077 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2078 attr &= ~0xf; 2079 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2080 } 2081 } 2082 #endif 2083 2084 static void 2085 run_calibrate_to(void *arg) 2086 { 2087 2088 /* do it in a process context */ 2089 run_do_async(arg, run_calibrate_cb, NULL, 0); 2090 /* next timeout will be rescheduled in the calibration task */ 2091 } 2092 2093 /* ARGSUSED */ 2094 static void 2095 run_calibrate_cb(struct run_softc *sc, void *arg) 2096 { 2097 struct ifnet *ifp = &sc->sc_if; 2098 uint32_t sta[3]; 2099 int s, error; 2100 2101 /* read statistic counters (clear on read) and update AMRR state */ 2102 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2103 sizeof(sta)); 2104 if (error != 0) 2105 goto skip; 2106 2107 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2108 le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, 2109 le32toh(sta[0]) & 0xffff)); 2110 2111 s = splnet(); 2112 /* count failed TX as errors */ 2113 ifp->if_oerrors += le32toh(sta[0]) & 0xffff; 2114 2115 sc->amn.amn_retrycnt = 2116 (le32toh(sta[0]) & 0xffff) + /* failed TX count */ 2117 (le32toh(sta[1]) >> 16); /* TX retransmission count */ 2118 2119 sc->amn.amn_txcnt = 2120 sc->amn.amn_retrycnt + 2121 (le32toh(sta[1]) & 0xffff); /* successful TX count */ 2122 2123 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2124 splx(s); 2125 2126 skip: callout_schedule(&sc->calib_to, hz); 2127 } 2128 2129 static void 2130 run_newassoc(struct ieee80211_node *ni, int isnew) 2131 { 2132 struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; 2133 struct run_node *rn = (void *)ni; 2134 struct ieee80211_rateset *rs = &ni->ni_rates; 2135 uint8_t rate; 2136 int ridx, i, j; 2137 2138 DPRINTF(("new assoc isnew=%d addr=%s\n", 2139 isnew, ether_sprintf(ni->ni_macaddr))); 2140 2141 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2142 /* start at lowest available bit-rate, AMRR will raise */ 2143 ni->ni_txrate = 0; 2144 2145 for (i = 0; i < rs->rs_nrates; i++) { 2146 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2147 /* convert 802.11 rate to hardware rate index */ 2148 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2149 if (rt2860_rates[ridx].rate == rate) 2150 break; 2151 rn->ridx[i] = ridx; 2152 /* determine rate of control response frames */ 2153 for (j = i; j >= 0; j--) { 2154 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2155 rt2860_rates[rn->ridx[i]].phy == 2156 rt2860_rates[rn->ridx[j]].phy) 2157 break; 2158 } 2159 if (j >= 0) { 2160 rn->ctl_ridx[i] = rn->ridx[j]; 2161 } else { 2162 /* no basic rate found, use mandatory one */ 2163 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2164 } 2165 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2166 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2167 } 2168 } 2169 2170 /* 2171 * Return the Rx chain with the highest RSSI for a given frame. 2172 */ 2173 static __inline uint8_t 2174 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2175 { 2176 uint8_t rxchain = 0; 2177 2178 if (sc->nrxchains > 1) { 2179 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2180 rxchain = 1; 2181 if (sc->nrxchains > 2) 2182 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2183 rxchain = 2; 2184 } 2185 return rxchain; 2186 } 2187 2188 static void 2189 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2190 { 2191 struct ieee80211com *ic = &sc->sc_ic; 2192 struct ifnet *ifp = &sc->sc_if; 2193 struct ieee80211_frame *wh; 2194 struct ieee80211_node *ni; 2195 struct rt2870_rxd *rxd; 2196 struct rt2860_rxwi *rxwi; 2197 struct mbuf *m; 2198 uint32_t flags; 2199 uint16_t len, rxwisize, phy; 2200 uint8_t ant, rssi; 2201 int s; 2202 #ifdef RUN_HWCRYPTO 2203 int decrypted = 0; 2204 #endif 2205 2206 rxwi = (struct rt2860_rxwi *)buf; 2207 len = le16toh(rxwi->len) & 0xfff; 2208 if (__predict_false(len > dmalen)) { 2209 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2210 return; 2211 } 2212 /* Rx descriptor is located at the end */ 2213 rxd = (struct rt2870_rxd *)(buf + dmalen); 2214 flags = le32toh(rxd->flags); 2215 2216 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2217 ifp->if_ierrors++; 2218 return; 2219 } 2220 2221 rxwisize = sizeof(struct rt2860_rxwi); 2222 if (sc->mac_ver == 0x5592) 2223 rxwisize += sizeof(uint64_t); 2224 else if (sc->mac_ver == 0x3593) 2225 rxwisize += sizeof(uint32_t); 2226 2227 wh = (struct ieee80211_frame *)(((uint8_t *)rxwi) + rxwisize); 2228 #ifdef RUN_HWCRYPTO 2229 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2230 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2231 decrypted = 1; 2232 } 2233 #endif 2234 2235 if (__predict_false((flags & RT2860_RX_MICERR))) { 2236 /* report MIC failures to net80211 for TKIP */ 2237 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 2238 ifp->if_ierrors++; 2239 return; 2240 } 2241 2242 if (flags & RT2860_RX_L2PAD) { 2243 u_int hdrlen = ieee80211_hdrspace(ic, wh); 2244 ovbcopy(wh, (uint8_t *)wh + 2, hdrlen); 2245 wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); 2246 } 2247 2248 /* could use m_devget but net80211 wants contig mgmt frames */ 2249 MGETHDR(m, M_DONTWAIT, MT_DATA); 2250 if (__predict_false(m == NULL)) { 2251 ifp->if_ierrors++; 2252 return; 2253 } 2254 if (len > MHLEN) { 2255 MCLGET(m, M_DONTWAIT); 2256 if (__predict_false(!(m->m_flags & M_EXT))) { 2257 ifp->if_ierrors++; 2258 m_freem(m); 2259 return; 2260 } 2261 } 2262 /* finalize mbuf */ 2263 m_set_rcvif(m, ifp); 2264 memcpy(mtod(m, void *), wh, len); 2265 m->m_pkthdr.len = m->m_len = len; 2266 2267 ant = run_maxrssi_chain(sc, rxwi); 2268 rssi = rxwi->rssi[ant]; 2269 2270 if (__predict_false(sc->sc_drvbpf != NULL)) { 2271 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2272 2273 tap->wr_flags = 0; 2274 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2275 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2276 tap->wr_antsignal = rssi; 2277 tap->wr_antenna = ant; 2278 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2279 tap->wr_rate = 2; /* in case it can't be found below */ 2280 phy = le16toh(rxwi->phy); 2281 switch (phy & RT2860_PHY_MODE) { 2282 case RT2860_PHY_CCK: 2283 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2284 case 0: tap->wr_rate = 2; break; 2285 case 1: tap->wr_rate = 4; break; 2286 case 2: tap->wr_rate = 11; break; 2287 case 3: tap->wr_rate = 22; break; 2288 } 2289 if (phy & RT2860_PHY_SHPRE) 2290 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2291 break; 2292 case RT2860_PHY_OFDM: 2293 switch (phy & RT2860_PHY_MCS) { 2294 case 0: tap->wr_rate = 12; break; 2295 case 1: tap->wr_rate = 18; break; 2296 case 2: tap->wr_rate = 24; break; 2297 case 3: tap->wr_rate = 36; break; 2298 case 4: tap->wr_rate = 48; break; 2299 case 5: tap->wr_rate = 72; break; 2300 case 6: tap->wr_rate = 96; break; 2301 case 7: tap->wr_rate = 108; break; 2302 } 2303 break; 2304 } 2305 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2306 } 2307 2308 s = splnet(); 2309 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2310 #ifdef RUN_HWCRYPTO 2311 if (decrypted) { 2312 uint32_t icflags = ic->ic_flags; 2313 2314 ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ 2315 ieee80211_input(ic, m, ni, rssi, 0); 2316 ic->ic_flags = icflags; 2317 } else 2318 #endif 2319 ieee80211_input(ic, m, ni, rssi, 0); 2320 2321 /* node is no longer needed */ 2322 ieee80211_free_node(ni); 2323 2324 /* 2325 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 2326 * without calling if_start(). 2327 */ 2328 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 2329 run_start(ifp); 2330 2331 splx(s); 2332 } 2333 2334 static void 2335 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2336 { 2337 struct run_rx_data *data = priv; 2338 struct run_softc *sc = data->sc; 2339 uint8_t *buf; 2340 uint32_t dmalen; 2341 int xferlen; 2342 2343 if (__predict_false(sc->sc_flags & RUN_DETACHING)) 2344 return; 2345 2346 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2347 DPRINTF(("RX status=%d\n", status)); 2348 if (status == USBD_STALLED) 2349 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2350 if (status != USBD_CANCELLED) 2351 goto skip; 2352 return; 2353 } 2354 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2355 2356 if (__predict_false(xferlen < (int)(sizeof(uint32_t) + 2357 sizeof(struct rt2860_rxwi) + sizeof(struct rt2870_rxd)))) { 2358 DPRINTF(("xfer too short %d\n", xferlen)); 2359 goto skip; 2360 } 2361 2362 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2363 buf = data->buf; 2364 while (xferlen > 8) { 2365 dmalen = le32toh(*(uint32_t *)buf) & 0xffff; 2366 2367 if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || 2368 (dmalen & 3) != 0)) { 2369 DPRINTF(("bad DMA length %u (%x)\n", dmalen, dmalen)); 2370 break; 2371 } 2372 if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { 2373 DPRINTF(("bad DMA length %u > %d\n", 2374 dmalen + 8, xferlen)); 2375 break; 2376 } 2377 run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); 2378 buf += dmalen + 8; 2379 xferlen -= dmalen + 8; 2380 } 2381 2382 skip: /* setup a new transfer */ 2383 usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, 2384 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 2385 (void)usbd_transfer(xfer); 2386 } 2387 2388 static void 2389 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2390 { 2391 struct run_tx_data *data = priv; 2392 struct run_softc *sc = data->sc; 2393 struct run_tx_ring *txq = &sc->txq[data->qid]; 2394 struct ifnet *ifp = &sc->sc_if; 2395 int s; 2396 2397 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2398 DPRINTF(("TX status=%d\n", status)); 2399 if (status == USBD_STALLED) 2400 usbd_clear_endpoint_stall_async(txq->pipeh); 2401 ifp->if_oerrors++; 2402 return; 2403 } 2404 2405 s = splnet(); 2406 sc->sc_tx_timer = 0; 2407 ifp->if_opackets++; 2408 if (--txq->queued < RUN_TX_RING_COUNT) { 2409 sc->qfullmsk &= ~(1 << data->qid); 2410 ifp->if_flags &= ~IFF_OACTIVE; 2411 run_start(ifp); 2412 } 2413 splx(s); 2414 } 2415 2416 static int 2417 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2418 { 2419 struct ieee80211com *ic = &sc->sc_ic; 2420 struct run_node *rn = (void *)ni; 2421 struct ieee80211_frame *wh; 2422 #ifndef RUN_HWCRYPTO 2423 struct ieee80211_key *k; 2424 #endif 2425 struct run_tx_ring *ring; 2426 struct run_tx_data *data; 2427 struct rt2870_txd *txd; 2428 struct rt2860_txwi *txwi; 2429 uint16_t dur, mcs; 2430 uint8_t type, tid, qid, qos = 0; 2431 int error, hasqos, ridx, ctl_ridx, xferlen, txwisize; 2432 uint8_t pad; 2433 2434 wh = mtod(m, struct ieee80211_frame *); 2435 2436 #ifndef RUN_HWCRYPTO 2437 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2438 k = ieee80211_crypto_encap(ic, ni, m); 2439 if (k == NULL) { 2440 m_freem(m); 2441 return ENOBUFS; 2442 } 2443 2444 /* packet header may have moved, reset our local pointer */ 2445 wh = mtod(m, struct ieee80211_frame *); 2446 } 2447 #endif 2448 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2449 2450 if ((hasqos = ieee80211_has_qos(wh))) { 2451 qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; 2452 tid = qos & IEEE80211_QOS_TID; 2453 qid = TID_TO_WME_AC(tid); 2454 } else { 2455 tid = 0; 2456 qid = WME_AC_BE; 2457 } 2458 ring = &sc->txq[qid]; 2459 data = &ring->data[ring->cur]; 2460 2461 /* pickup a rate index */ 2462 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2463 type != IEEE80211_FC0_TYPE_DATA) { 2464 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2465 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2466 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2467 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 2468 ridx = sc->fixed_ridx; 2469 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2470 } else { 2471 ridx = rn->ridx[ni->ni_txrate]; 2472 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2473 } 2474 2475 /* get MCS code from rate index */ 2476 mcs = rt2860_rates[ridx].mcs; 2477 2478 txwisize = (sc->mac_ver == 0x5592) ? 2479 sizeof(*txwi) + sizeof(uint32_t) : sizeof(*txwi); 2480 xferlen = txwisize + m->m_pkthdr.len; 2481 /* roundup to 32-bit alignment */ 2482 xferlen = (xferlen + 3) & ~3; 2483 2484 txd = (struct rt2870_txd *)data->buf; 2485 txd->flags = RT2860_TX_QSEL_EDCA; 2486 txd->len = htole16(xferlen); 2487 2488 /* 2489 * Ether both are true or both are false, the header 2490 * are nicely aligned to 32-bit. So, no L2 padding. 2491 */ 2492 if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) 2493 pad = 0; 2494 else 2495 pad = 2; 2496 2497 /* setup TX Wireless Information */ 2498 txwi = (struct rt2860_txwi *)(txd + 1); 2499 txwi->flags = 0; 2500 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2501 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2502 RUN_AID2WCID(ni->ni_associd) : 0xff; 2503 txwi->len = htole16(m->m_pkthdr.len - pad); 2504 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2505 txwi->phy = htole16(RT2860_PHY_CCK); 2506 if (ridx != RT2860_RIDX_CCK1 && 2507 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2508 mcs |= RT2860_PHY_SHPRE; 2509 } else 2510 mcs |= RT2860_PHY_OFDM; 2511 txwi->phy |= htole16(mcs); 2512 2513 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2514 2515 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2516 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 2517 IEEE80211_QOS_ACKPOLICY_NOACK)) { 2518 txwi->xflags |= RT2860_TX_ACK; 2519 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2520 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2521 else 2522 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2523 *(uint16_t *)wh->i_dur = htole16(dur); 2524 } 2525 2526 #ifndef IEEE80211_STA_ONLY 2527 /* ask MAC to insert timestamp into probe responses */ 2528 if ((wh->i_fc[0] & 2529 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2530 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 2531 /* NOTE: beacons do not pass through tx_data() */ 2532 txwi->flags |= RT2860_TX_TS; 2533 #endif 2534 2535 if (__predict_false(sc->sc_drvbpf != NULL)) { 2536 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2537 2538 tap->wt_flags = 0; 2539 tap->wt_rate = rt2860_rates[ridx].rate; 2540 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2541 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2542 tap->wt_hwqueue = qid; 2543 if (mcs & RT2860_PHY_SHPRE) 2544 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2545 2546 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2547 } 2548 2549 m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); 2550 m_freem(m); 2551 2552 xferlen += sizeof(*txd) + 4; 2553 2554 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2555 USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); 2556 error = usbd_transfer(data->xfer); 2557 if (__predict_false(error != USBD_IN_PROGRESS && 2558 error != USBD_NORMAL_COMPLETION)) 2559 return error; 2560 2561 ieee80211_free_node(ni); 2562 2563 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2564 if (++ring->queued >= RUN_TX_RING_COUNT) 2565 sc->qfullmsk |= 1 << qid; 2566 2567 return 0; 2568 } 2569 2570 static void 2571 run_start(struct ifnet *ifp) 2572 { 2573 struct run_softc *sc = ifp->if_softc; 2574 struct ieee80211com *ic = &sc->sc_ic; 2575 struct ether_header *eh; 2576 struct ieee80211_node *ni; 2577 struct mbuf *m; 2578 2579 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2580 return; 2581 2582 for (;;) { 2583 if (sc->qfullmsk != 0) { 2584 ifp->if_flags |= IFF_OACTIVE; 2585 break; 2586 } 2587 /* send pending management frames first */ 2588 IF_DEQUEUE(&ic->ic_mgtq, m); 2589 if (m != NULL) { 2590 ni = M_GETCTX(m, struct ieee80211_node *); 2591 M_CLEARCTX(m); 2592 goto sendit; 2593 } 2594 if (ic->ic_state != IEEE80211_S_RUN) 2595 break; 2596 2597 /* encapsulate and send data frames */ 2598 IFQ_DEQUEUE(&ifp->if_snd, m); 2599 if (m == NULL) 2600 break; 2601 if (m->m_len < (int)sizeof(*eh) && 2602 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2603 ifp->if_oerrors++; 2604 continue; 2605 } 2606 2607 eh = mtod(m, struct ether_header *); 2608 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2609 if (ni == NULL) { 2610 m_freem(m); 2611 ifp->if_oerrors++; 2612 continue; 2613 } 2614 2615 bpf_mtap(ifp, m); 2616 2617 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2618 ieee80211_free_node(ni); 2619 ifp->if_oerrors++; 2620 continue; 2621 } 2622 sendit: 2623 bpf_mtap3(ic->ic_rawbpf, m); 2624 2625 if (run_tx(sc, m, ni) != 0) { 2626 ieee80211_free_node(ni); 2627 ifp->if_oerrors++; 2628 continue; 2629 } 2630 2631 sc->sc_tx_timer = 5; 2632 ifp->if_timer = 1; 2633 } 2634 } 2635 2636 static void 2637 run_watchdog(struct ifnet *ifp) 2638 { 2639 struct run_softc *sc = ifp->if_softc; 2640 struct ieee80211com *ic = &sc->sc_ic; 2641 2642 ifp->if_timer = 0; 2643 2644 if (sc->sc_tx_timer > 0) { 2645 if (--sc->sc_tx_timer == 0) { 2646 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2647 /* run_init(ifp); XXX needs a process context! */ 2648 ifp->if_oerrors++; 2649 return; 2650 } 2651 ifp->if_timer = 1; 2652 } 2653 2654 ieee80211_watchdog(ic); 2655 } 2656 2657 static int 2658 run_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2659 { 2660 struct run_softc *sc = ifp->if_softc; 2661 struct ieee80211com *ic = &sc->sc_ic; 2662 int s, error = 0; 2663 2664 s = splnet(); 2665 2666 switch (cmd) { 2667 case SIOCSIFFLAGS: 2668 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2669 break; 2670 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2671 case IFF_UP|IFF_RUNNING: 2672 break; 2673 case IFF_UP: 2674 run_init(ifp); 2675 break; 2676 case IFF_RUNNING: 2677 run_stop(ifp, 1); 2678 break; 2679 case 0: 2680 break; 2681 } 2682 break; 2683 2684 case SIOCADDMULTI: 2685 case SIOCDELMULTI: 2686 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2687 /* setup multicast filter, etc */ 2688 error = 0; 2689 } 2690 break; 2691 2692 default: 2693 error = ieee80211_ioctl(ic, cmd, data); 2694 break; 2695 } 2696 2697 if (error == ENETRESET) { 2698 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2699 (IFF_UP | IFF_RUNNING)) { 2700 run_init(ifp); 2701 } 2702 error = 0; 2703 } 2704 2705 splx(s); 2706 2707 return error; 2708 } 2709 2710 static void 2711 run_select_chan_group(struct run_softc *sc, int group) 2712 { 2713 uint32_t tmp; 2714 uint8_t agc; 2715 2716 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2717 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2718 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2719 run_bbp_write(sc, 86, 0x00); 2720 2721 if (group == 0) { 2722 if (sc->ext_2ghz_lna) { 2723 run_bbp_write(sc, 82, 0x62); 2724 run_bbp_write(sc, 75, 0x46); 2725 } else { 2726 run_bbp_write(sc, 82, 0x84); 2727 run_bbp_write(sc, 75, 0x50); 2728 } 2729 } else { 2730 if (sc->mac_ver == 0x3572) 2731 run_bbp_write(sc, 82, 0x94); 2732 else 2733 run_bbp_write(sc, 82, 0xf2); 2734 if (sc->ext_5ghz_lna) 2735 run_bbp_write(sc, 75, 0x46); 2736 else 2737 run_bbp_write(sc, 75, 0x50); 2738 } 2739 2740 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2741 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2742 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2743 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2744 2745 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2746 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2747 if (sc->nrxchains > 1) 2748 tmp |= RT2860_LNA_PE1_EN; 2749 if (group == 0) { /* 2GHz */ 2750 tmp |= RT2860_PA_PE_G0_EN; 2751 if (sc->ntxchains > 1) 2752 tmp |= RT2860_PA_PE_G1_EN; 2753 } else { /* 5GHz */ 2754 tmp |= RT2860_PA_PE_A0_EN; 2755 if (sc->ntxchains > 1) 2756 tmp |= RT2860_PA_PE_A1_EN; 2757 } 2758 if (sc->mac_ver == 0x3572) { 2759 run_rt3070_rf_write(sc, 8, 0x00); 2760 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2761 run_rt3070_rf_write(sc, 8, 0x80); 2762 } else 2763 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2764 2765 /* set initial AGC value */ 2766 if (group == 0) { /* 2GHz band */ 2767 if (sc->mac_ver >= 0x3070) 2768 agc = 0x1c + sc->lna[0] * 2; 2769 else 2770 agc = 0x2e + sc->lna[0]; 2771 } else { /* 5GHz band */ 2772 if (sc->mac_ver == 0x3572) 2773 agc = 0x22 + (sc->lna[group] * 5) / 3; 2774 else 2775 agc = 0x32 + (sc->lna[group] * 5) / 3; 2776 } 2777 run_set_agc(sc, agc); 2778 } 2779 2780 static void 2781 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2782 { 2783 const struct rfprog *rfprog = rt2860_rf2850; 2784 uint32_t r2, r3, r4; 2785 int8_t txpow1, txpow2; 2786 int i; 2787 2788 /* find the settings for this channel (we know it exists) */ 2789 for (i = 0; rfprog[i].chan != chan; i++); 2790 2791 r2 = rfprog[i].r2; 2792 if (sc->ntxchains == 1) 2793 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2794 if (sc->nrxchains == 1) 2795 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2796 else if (sc->nrxchains == 2) 2797 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2798 2799 /* use Tx power values from EEPROM */ 2800 txpow1 = sc->txpow1[i]; 2801 txpow2 = sc->txpow2[i]; 2802 if (chan > 14) { 2803 if (txpow1 >= 0) 2804 txpow1 = txpow1 << 1 | 1; 2805 else 2806 txpow1 = (7 + txpow1) << 1; 2807 if (txpow2 >= 0) 2808 txpow2 = txpow2 << 1 | 1; 2809 else 2810 txpow2 = (7 + txpow2) << 1; 2811 } 2812 r3 = rfprog[i].r3 | txpow1 << 7; 2813 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2814 2815 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2816 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2817 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2818 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2819 2820 usbd_delay_ms(sc->sc_udev, 10); 2821 2822 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2823 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2824 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2825 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2826 2827 usbd_delay_ms(sc->sc_udev, 10); 2828 2829 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2830 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2831 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2832 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2833 } 2834 2835 static void 2836 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2837 { 2838 int8_t txpow1, txpow2; 2839 uint8_t rf; 2840 int i; 2841 2842 KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ 2843 2844 /* find the settings for this channel (we know it exists) */ 2845 for (i = 0; rt2860_rf2850[i].chan != chan; i++) 2846 continue; 2847 2848 /* use Tx power values from EEPROM */ 2849 txpow1 = sc->txpow1[i]; 2850 txpow2 = sc->txpow2[i]; 2851 2852 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2853 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2854 run_rt3070_rf_read(sc, 6, &rf); 2855 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2856 run_rt3070_rf_write(sc, 6, rf); 2857 2858 /* set Tx0 power */ 2859 run_rt3070_rf_read(sc, 12, &rf); 2860 rf = (rf & ~0x1f) | txpow1; 2861 run_rt3070_rf_write(sc, 12, rf); 2862 2863 /* set Tx1 power */ 2864 run_rt3070_rf_read(sc, 13, &rf); 2865 rf = (rf & ~0x1f) | txpow2; 2866 run_rt3070_rf_write(sc, 13, rf); 2867 2868 run_rt3070_rf_read(sc, 1, &rf); 2869 rf &= ~0xfc; 2870 if (sc->ntxchains == 1) 2871 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2872 else if (sc->ntxchains == 2) 2873 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2874 if (sc->nrxchains == 1) 2875 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2876 else if (sc->nrxchains == 2) 2877 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2878 run_rt3070_rf_write(sc, 1, rf); 2879 2880 /* set RF offset */ 2881 run_rt3070_rf_read(sc, 23, &rf); 2882 rf = (rf & ~0x7f) | sc->freq; 2883 run_rt3070_rf_write(sc, 23, rf); 2884 2885 /* program RF filter */ 2886 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 2887 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2888 run_rt3070_rf_write(sc, 24, rf); 2889 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 2890 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2891 run_rt3070_rf_write(sc, 31, rf); 2892 2893 /* enable RF tuning */ 2894 run_rt3070_rf_read(sc, 7, &rf); 2895 run_rt3070_rf_write(sc, 7, rf | 0x01); 2896 } 2897 2898 static void 2899 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 2900 { 2901 int8_t txpow1, txpow2; 2902 uint32_t tmp; 2903 uint8_t rf; 2904 int i; 2905 2906 /* find the settings for this channel (we know it exists) */ 2907 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2908 2909 /* use Tx power values from EEPROM */ 2910 txpow1 = sc->txpow1[i]; 2911 txpow2 = sc->txpow2[i]; 2912 2913 if (chan <= 14) { 2914 run_bbp_write(sc, 25, sc->bbp25); 2915 run_bbp_write(sc, 26, sc->bbp26); 2916 } else { 2917 /* enable IQ phase correction */ 2918 run_bbp_write(sc, 25, 0x09); 2919 run_bbp_write(sc, 26, 0xff); 2920 } 2921 2922 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2923 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2924 run_rt3070_rf_read(sc, 6, &rf); 2925 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 2926 rf |= (chan <= 14) ? 0x08 : 0x04; 2927 run_rt3070_rf_write(sc, 6, rf); 2928 2929 /* set PLL mode */ 2930 run_rt3070_rf_read(sc, 5, &rf); 2931 rf &= ~(0x08 | 0x04); 2932 rf |= (chan <= 14) ? 0x04 : 0x08; 2933 run_rt3070_rf_write(sc, 5, rf); 2934 2935 /* set Tx power for chain 0 */ 2936 if (chan <= 14) 2937 rf = 0x60 | txpow1; 2938 else 2939 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 2940 run_rt3070_rf_write(sc, 12, rf); 2941 2942 /* set Tx power for chain 1 */ 2943 if (chan <= 14) 2944 rf = 0x60 | txpow2; 2945 else 2946 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 2947 run_rt3070_rf_write(sc, 13, rf); 2948 2949 /* set Tx/Rx streams */ 2950 run_rt3070_rf_read(sc, 1, &rf); 2951 rf &= ~0xfc; 2952 if (sc->ntxchains == 1) 2953 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2954 else if (sc->ntxchains == 2) 2955 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2956 if (sc->nrxchains == 1) 2957 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2958 else if (sc->nrxchains == 2) 2959 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2960 run_rt3070_rf_write(sc, 1, rf); 2961 2962 /* set RF offset */ 2963 run_rt3070_rf_read(sc, 23, &rf); 2964 rf = (rf & ~0x7f) | sc->freq; 2965 run_rt3070_rf_write(sc, 23, rf); 2966 2967 /* program RF filter */ 2968 rf = sc->rf24_20mhz; 2969 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 2970 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 2971 2972 /* enable RF tuning */ 2973 run_rt3070_rf_read(sc, 7, &rf); 2974 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 2975 run_rt3070_rf_write(sc, 7, rf); 2976 2977 /* TSSI */ 2978 rf = (chan <= 14) ? 0xc3 : 0xc0; 2979 run_rt3070_rf_write(sc, 9, rf); 2980 2981 /* set loop filter 1 */ 2982 run_rt3070_rf_write(sc, 10, 0xf1); 2983 /* set loop filter 2 */ 2984 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 2985 2986 /* set tx_mx2_ic */ 2987 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 2988 /* set tx_mx1_ic */ 2989 if (chan <= 14) 2990 rf = 0x48 | sc->txmixgain_2ghz; 2991 else 2992 rf = 0x78 | sc->txmixgain_5ghz; 2993 run_rt3070_rf_write(sc, 16, rf); 2994 2995 /* set tx_lo1 */ 2996 run_rt3070_rf_write(sc, 17, 0x23); 2997 /* set tx_lo2 */ 2998 if (chan <= 14) 2999 rf = 0x93; 3000 else if (chan <= 64) 3001 rf = 0xb7; 3002 else if (chan <= 128) 3003 rf = 0x74; 3004 else 3005 rf = 0x72; 3006 run_rt3070_rf_write(sc, 19, rf); 3007 3008 /* set rx_lo1 */ 3009 if (chan <= 14) 3010 rf = 0xb3; 3011 else if (chan <= 64) 3012 rf = 0xf6; 3013 else if (chan <= 128) 3014 rf = 0xf4; 3015 else 3016 rf = 0xf3; 3017 run_rt3070_rf_write(sc, 20, rf); 3018 3019 /* set pfd_delay */ 3020 if (chan <= 14) 3021 rf = 0x15; 3022 else if (chan <= 64) 3023 rf = 0x3d; 3024 else 3025 rf = 0x01; 3026 run_rt3070_rf_write(sc, 25, rf); 3027 3028 /* set rx_lo2 */ 3029 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3030 /* set ldo_rf_vc */ 3031 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3032 /* set drv_cc */ 3033 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3034 3035 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3036 tmp &= ~0x8080; 3037 if (chan <= 14) 3038 tmp |= 0x80; 3039 run_write(sc, RT2860_GPIO_CTRL, tmp); 3040 3041 /* enable RF tuning */ 3042 run_rt3070_rf_read(sc, 7, &rf); 3043 run_rt3070_rf_write(sc, 7, rf | 0x01); 3044 3045 usbd_delay_ms(sc->sc_udev, 2); 3046 } 3047 3048 static void 3049 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3050 { 3051 int8_t txpow1, txpow2, txpow3; 3052 uint8_t h20mhz, rf; 3053 int i; 3054 3055 /* find the settings for this channel (we know it exists) */ 3056 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3057 3058 /* use Tx power values from EEPROM */ 3059 txpow1 = sc->txpow1[i]; 3060 txpow2 = sc->txpow2[i]; 3061 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3062 3063 if (chan <= 14) { 3064 run_bbp_write(sc, 25, sc->bbp25); 3065 run_bbp_write(sc, 26, sc->bbp26); 3066 } else { 3067 /* Enable IQ phase correction. */ 3068 run_bbp_write(sc, 25, 0x09); 3069 run_bbp_write(sc, 26, 0xff); 3070 } 3071 3072 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3073 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3074 run_rt3070_rf_read(sc, 11, &rf); 3075 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3076 run_rt3070_rf_write(sc, 11, rf); 3077 3078 /* Set pll_idoh. */ 3079 run_rt3070_rf_read(sc, 11, &rf); 3080 rf &= ~0x4c; 3081 rf |= (chan <= 14) ? 0x44 : 0x48; 3082 run_rt3070_rf_write(sc, 11, rf); 3083 3084 if (chan <= 14) 3085 rf = txpow1 & 0x1f; 3086 else 3087 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3088 run_rt3070_rf_write(sc, 53, rf); 3089 3090 if (chan <= 14) 3091 rf = txpow2 & 0x1f; 3092 else 3093 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3094 run_rt3070_rf_write(sc, 55, rf); 3095 3096 if (chan <= 14) 3097 rf = txpow3 & 0x1f; 3098 else 3099 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3100 run_rt3070_rf_write(sc, 54, rf); 3101 3102 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3103 if (sc->ntxchains == 3) 3104 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3105 else 3106 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3107 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3108 run_rt3070_rf_write(sc, 1, rf); 3109 3110 run_adjust_freq_offset(sc); 3111 3112 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3113 3114 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3115 run_rt3070_rf_read(sc, 30, &rf); 3116 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3117 run_rt3070_rf_write(sc, 30, rf); 3118 3119 run_rt3070_rf_read(sc, 36, &rf); 3120 if (chan <= 14) 3121 rf |= 0x80; 3122 else 3123 rf &= ~0x80; 3124 run_rt3070_rf_write(sc, 36, rf); 3125 3126 /* Set vcolo_bs. */ 3127 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3128 /* Set pfd_delay. */ 3129 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3130 3131 /* Set vco bias current control. */ 3132 run_rt3070_rf_read(sc, 6, &rf); 3133 rf &= ~0xc0; 3134 if (chan <= 14) 3135 rf |= 0x40; 3136 else if (chan <= 128) 3137 rf |= 0x80; 3138 else 3139 rf |= 0x40; 3140 run_rt3070_rf_write(sc, 6, rf); 3141 3142 run_rt3070_rf_read(sc, 30, &rf); 3143 rf = (rf & ~0x18) | 0x10; 3144 run_rt3070_rf_write(sc, 30, rf); 3145 3146 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3147 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3148 3149 run_rt3070_rf_read(sc, 51, &rf); 3150 rf = (rf & ~0x03) | 0x01; 3151 run_rt3070_rf_write(sc, 51, rf); 3152 /* Set tx_mx1_cc. */ 3153 run_rt3070_rf_read(sc, 51, &rf); 3154 rf &= ~0x1c; 3155 rf |= (chan <= 14) ? 0x14 : 0x10; 3156 run_rt3070_rf_write(sc, 51, rf); 3157 /* Set tx_mx1_ic. */ 3158 run_rt3070_rf_read(sc, 51, &rf); 3159 rf &= ~0xe0; 3160 rf |= (chan <= 14) ? 0x60 : 0x40; 3161 run_rt3070_rf_write(sc, 51, rf); 3162 /* Set tx_lo1_ic. */ 3163 run_rt3070_rf_read(sc, 49, &rf); 3164 rf &= ~0x1c; 3165 rf |= (chan <= 14) ? 0x0c : 0x08; 3166 run_rt3070_rf_write(sc, 49, rf); 3167 /* Set tx_lo1_en. */ 3168 run_rt3070_rf_read(sc, 50, &rf); 3169 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3170 /* Set drv_cc. */ 3171 run_rt3070_rf_read(sc, 57, &rf); 3172 rf &= ~0xfc; 3173 rf |= (chan <= 14) ? 0x6c : 0x3c; 3174 run_rt3070_rf_write(sc, 57, rf); 3175 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3176 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3177 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3178 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3179 /* Enable VCO calibration. */ 3180 run_rt3070_rf_read(sc, 3, &rf); 3181 rf &= ~RT5390_VCOCAL; 3182 rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; 3183 run_rt3070_rf_write(sc, 3, rf); 3184 3185 if (chan <= 14) 3186 rf = 0x23; 3187 else if (chan <= 64) 3188 rf = 0x36; 3189 else if (chan <= 128) 3190 rf = 0x32; 3191 else 3192 rf = 0x30; 3193 run_rt3070_rf_write(sc, 39, rf); 3194 if (chan <= 14) 3195 rf = 0xbb; 3196 else if (chan <= 64) 3197 rf = 0xeb; 3198 else if (chan <= 128) 3199 rf = 0xb3; 3200 else 3201 rf = 0x9b; 3202 run_rt3070_rf_write(sc, 45, rf); 3203 3204 /* Set FEQ/AEQ control. */ 3205 run_bbp_write(sc, 105, 0x34); 3206 } 3207 3208 static void 3209 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3210 { 3211 int8_t txpow1, txpow2; 3212 uint8_t rf; 3213 int i; 3214 3215 /* find the settings for this channel (we know it exists) */ 3216 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3217 3218 /* use Tx power values from EEPROM */ 3219 txpow1 = sc->txpow1[i]; 3220 txpow2 = sc->txpow2[i]; 3221 3222 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3223 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3224 run_rt3070_rf_read(sc, 11, &rf); 3225 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3226 run_rt3070_rf_write(sc, 11, rf); 3227 3228 run_rt3070_rf_read(sc, 49, &rf); 3229 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3230 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3231 if ((rf & 0x3f) > 0x27) 3232 rf = (rf & ~0x3f) | 0x27; 3233 run_rt3070_rf_write(sc, 49, rf); 3234 3235 if (sc->mac_ver == 0x5392) { 3236 run_rt3070_rf_read(sc, 50, &rf); 3237 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3238 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3239 if ((rf & 0x3f) > 0x27) 3240 rf = (rf & ~0x3f) | 0x27; 3241 run_rt3070_rf_write(sc, 50, rf); 3242 } 3243 3244 run_rt3070_rf_read(sc, 1, &rf); 3245 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3246 if (sc->mac_ver == 0x5392) 3247 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3248 run_rt3070_rf_write(sc, 1, rf); 3249 3250 if (sc->mac_ver != 0x5392) { 3251 run_rt3070_rf_read(sc, 2, &rf); 3252 rf |= 0x80; 3253 run_rt3070_rf_write(sc, 2, rf); 3254 usbd_delay_ms(sc->sc_udev, 10); 3255 rf &= 0x7f; 3256 run_rt3070_rf_write(sc, 2, rf); 3257 } 3258 3259 run_adjust_freq_offset(sc); 3260 3261 if (sc->mac_ver == 0x5392) { 3262 /* Fix for RT5392C. */ 3263 if (sc->mac_rev >= 0x0223) { 3264 if (chan <= 4) 3265 rf = 0x0f; 3266 else if (chan >= 5 && chan <= 7) 3267 rf = 0x0e; 3268 else 3269 rf = 0x0d; 3270 run_rt3070_rf_write(sc, 23, rf); 3271 3272 if (chan <= 4) 3273 rf = 0x0c; 3274 else if (chan == 5) 3275 rf = 0x0b; 3276 else if (chan >= 6 && chan <= 7) 3277 rf = 0x0a; 3278 else if (chan >= 8 && chan <= 10) 3279 rf = 0x09; 3280 else 3281 rf = 0x08; 3282 run_rt3070_rf_write(sc, 59, rf); 3283 } else { 3284 if (chan <= 11) 3285 rf = 0x0f; 3286 else 3287 rf = 0x0b; 3288 run_rt3070_rf_write(sc, 59, rf); 3289 } 3290 } else { 3291 /* Fix for RT5390F. */ 3292 if (sc->mac_rev >= 0x0502) { 3293 if (chan <= 11) 3294 rf = 0x43; 3295 else 3296 rf = 0x23; 3297 run_rt3070_rf_write(sc, 55, rf); 3298 3299 if (chan <= 11) 3300 rf = 0x0f; 3301 else if (chan == 12) 3302 rf = 0x0d; 3303 else 3304 rf = 0x0b; 3305 run_rt3070_rf_write(sc, 59, rf); 3306 } else { 3307 run_rt3070_rf_write(sc, 55, 0x44); 3308 run_rt3070_rf_write(sc, 59, 0x8f); 3309 } 3310 } 3311 3312 /* Enable VCO calibration. */ 3313 run_rt3070_rf_read(sc, 3, &rf); 3314 rf |= RT5390_VCOCAL; 3315 run_rt3070_rf_write(sc, 3, rf); 3316 } 3317 3318 static void 3319 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3320 { 3321 const struct rt5592_freqs *freqs; 3322 uint32_t tmp; 3323 uint8_t reg, rf, txpow_bound; 3324 int8_t txpow1, txpow2; 3325 int i; 3326 3327 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3328 freqs = (tmp & RT5592_SEL_XTAL) ? 3329 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3330 3331 /* find the settings for this channel (we know it exists) */ 3332 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3333 3334 /* use Tx power values from EEPROM */ 3335 txpow1 = sc->txpow1[i]; 3336 txpow2 = sc->txpow2[i]; 3337 3338 run_read(sc, RT3070_LDO_CFG0, &tmp); 3339 tmp &= ~0x1c000000; 3340 if (chan > 14) 3341 tmp |= 0x14000000; 3342 run_write(sc, RT3070_LDO_CFG0, tmp); 3343 3344 /* N setting. */ 3345 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3346 run_rt3070_rf_read(sc, 9, &rf); 3347 rf &= ~(1 << 4); 3348 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3349 run_rt3070_rf_write(sc, 9, rf); 3350 3351 /* K setting. */ 3352 run_rt3070_rf_read(sc, 9, &rf); 3353 rf &= ~0x0f; 3354 rf |= (freqs->k & 0x0f); 3355 run_rt3070_rf_write(sc, 9, rf); 3356 3357 /* Mode setting. */ 3358 run_rt3070_rf_read(sc, 11, &rf); 3359 rf &= ~0x0c; 3360 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3361 run_rt3070_rf_write(sc, 11, rf); 3362 run_rt3070_rf_read(sc, 9, &rf); 3363 rf &= ~(1 << 7); 3364 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3365 run_rt3070_rf_write(sc, 9, rf); 3366 3367 /* R setting. */ 3368 run_rt3070_rf_read(sc, 11, &rf); 3369 rf &= ~0x03; 3370 rf |= (freqs->r - 0x1); 3371 run_rt3070_rf_write(sc, 11, rf); 3372 3373 if (chan <= 14) { 3374 /* Initialize RF registers for 2GHZ. */ 3375 for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { 3376 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3377 rt5592_2ghz_def_rf[i].val); 3378 } 3379 3380 rf = (chan <= 10) ? 0x07 : 0x06; 3381 run_rt3070_rf_write(sc, 23, rf); 3382 run_rt3070_rf_write(sc, 59, rf); 3383 3384 run_rt3070_rf_write(sc, 55, 0x43); 3385 3386 /* 3387 * RF R49/R50 Tx power ALC code. 3388 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3389 */ 3390 reg = 2; 3391 txpow_bound = 0x27; 3392 } else { 3393 /* Initialize RF registers for 5GHZ. */ 3394 for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { 3395 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3396 rt5592_5ghz_def_rf[i].val); 3397 } 3398 for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { 3399 if (chan >= rt5592_chan_5ghz[i].firstchan && 3400 chan <= rt5592_chan_5ghz[i].lastchan) { 3401 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3402 rt5592_chan_5ghz[i].val); 3403 } 3404 } 3405 3406 /* 3407 * RF R49/R50 Tx power ALC code. 3408 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3409 */ 3410 reg = 3; 3411 txpow_bound = 0x2b; 3412 } 3413 3414 /* RF R49 ch0 Tx power ALC code. */ 3415 run_rt3070_rf_read(sc, 49, &rf); 3416 rf &= ~0xc0; 3417 rf |= (reg << 6); 3418 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3419 if ((rf & 0x3f) > txpow_bound) 3420 rf = (rf & ~0x3f) | txpow_bound; 3421 run_rt3070_rf_write(sc, 49, rf); 3422 3423 /* RF R50 ch1 Tx power ALC code. */ 3424 run_rt3070_rf_read(sc, 50, &rf); 3425 rf &= ~(1 << 7 | 1 << 6); 3426 rf |= (reg << 6); 3427 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3428 if ((rf & 0x3f) > txpow_bound) 3429 rf = (rf & ~0x3f) | txpow_bound; 3430 run_rt3070_rf_write(sc, 50, rf); 3431 3432 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3433 run_rt3070_rf_read(sc, 1, &rf); 3434 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3435 if (sc->ntxchains > 1) 3436 rf |= RT3070_TX1_PD; 3437 if (sc->nrxchains > 1) 3438 rf |= RT3070_RX1_PD; 3439 run_rt3070_rf_write(sc, 1, rf); 3440 3441 run_rt3070_rf_write(sc, 6, 0xe4); 3442 3443 run_rt3070_rf_write(sc, 30, 0x10); 3444 run_rt3070_rf_write(sc, 31, 0x80); 3445 run_rt3070_rf_write(sc, 32, 0x80); 3446 3447 run_adjust_freq_offset(sc); 3448 3449 /* Enable VCO calibration. */ 3450 run_rt3070_rf_read(sc, 3, &rf); 3451 rf |= RT5390_VCOCAL; 3452 run_rt3070_rf_write(sc, 3, rf); 3453 } 3454 3455 static void 3456 run_iq_calib(struct run_softc *sc, u_int chan) 3457 { 3458 uint16_t val; 3459 3460 /* Tx0 IQ gain. */ 3461 run_bbp_write(sc, 158, 0x2c); 3462 if (chan <= 14) 3463 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); 3464 else if (chan <= 64) { 3465 run_efuse_read(sc, 3466 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, 3467 &val, 1); 3468 } else if (chan <= 138) { 3469 run_efuse_read(sc, 3470 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, 3471 &val, 1); 3472 } else if (chan <= 165) { 3473 run_efuse_read(sc, 3474 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 3475 &val, 1); 3476 } else 3477 val = 0; 3478 run_bbp_write(sc, 159, val); 3479 3480 /* Tx0 IQ phase. */ 3481 run_bbp_write(sc, 158, 0x2d); 3482 if (chan <= 14) { 3483 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, 3484 &val, 1); 3485 } else if (chan <= 64) { 3486 run_efuse_read(sc, 3487 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, 3488 &val, 1); 3489 } else if (chan <= 138) { 3490 run_efuse_read(sc, 3491 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, 3492 &val, 1); 3493 } else if (chan <= 165) { 3494 run_efuse_read(sc, 3495 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, 3496 &val, 1); 3497 } else 3498 val = 0; 3499 run_bbp_write(sc, 159, val); 3500 3501 /* Tx1 IQ gain. */ 3502 run_bbp_write(sc, 158, 0x4a); 3503 if (chan <= 14) { 3504 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, 3505 &val, 1); 3506 } else if (chan <= 64) { 3507 run_efuse_read(sc, 3508 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, 3509 &val, 1); 3510 } else if (chan <= 138) { 3511 run_efuse_read(sc, 3512 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, 3513 &val, 1); 3514 } else if (chan <= 165) { 3515 run_efuse_read(sc, 3516 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, 3517 &val, 1); 3518 } else 3519 val = 0; 3520 run_bbp_write(sc, 159, val); 3521 3522 /* Tx1 IQ phase. */ 3523 run_bbp_write(sc, 158, 0x4b); 3524 if (chan <= 14) { 3525 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, 3526 &val, 1); 3527 } else if (chan <= 64) { 3528 run_efuse_read(sc, 3529 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, 3530 &val, 1); 3531 } else if (chan <= 138) { 3532 run_efuse_read(sc, 3533 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, 3534 &val, 1); 3535 } else if (chan <= 165) { 3536 run_efuse_read(sc, 3537 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, 3538 &val, 1); 3539 } else 3540 val = 0; 3541 run_bbp_write(sc, 159, val); 3542 3543 /* RF IQ compensation control. */ 3544 run_bbp_write(sc, 158, 0x04); 3545 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, 3546 &val, 1); 3547 run_bbp_write(sc, 159, val); 3548 3549 /* RF IQ imbalance compensation control. */ 3550 run_bbp_write(sc, 158, 0x03); 3551 run_efuse_read(sc, 3552 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); 3553 run_bbp_write(sc, 159, val); 3554 } 3555 3556 static void 3557 run_set_agc(struct run_softc *sc, uint8_t agc) 3558 { 3559 uint8_t bbp; 3560 3561 if (sc->mac_ver == 0x3572) { 3562 run_bbp_read(sc, 27, &bbp); 3563 bbp &= ~(0x3 << 5); 3564 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3565 run_bbp_write(sc, 66, agc); 3566 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3567 run_bbp_write(sc, 66, agc); 3568 } else 3569 run_bbp_write(sc, 66, agc); 3570 } 3571 3572 static void 3573 run_set_rx_antenna(struct run_softc *sc, int aux) 3574 { 3575 uint32_t tmp; 3576 uint8_t bbp152; 3577 3578 if (sc->rf_rev == RT5390_RF_5370) { 3579 run_bbp_read(sc, 152, &bbp152); 3580 bbp152 &= ~0x80; 3581 if (aux) 3582 bbp152 |= 0x80; 3583 run_bbp_write(sc, 152, bbp152); 3584 } else { 3585 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); 3586 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3587 tmp &= ~0x0808; 3588 if (aux) 3589 tmp |= 0x08; 3590 run_write(sc, RT2860_GPIO_CTRL, tmp); 3591 } 3592 } 3593 3594 static int 3595 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3596 { 3597 struct ieee80211com *ic = &sc->sc_ic; 3598 u_int chan, group; 3599 3600 chan = ieee80211_chan2ieee(ic, c); 3601 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3602 return EINVAL; 3603 3604 if (sc->mac_ver == 0x5592) 3605 run_rt5592_set_chan(sc, chan); 3606 else if (sc->mac_ver >= 0x5390) 3607 run_rt5390_set_chan(sc, chan); 3608 else if (sc->mac_ver == 0x3593) 3609 run_rt3593_set_chan(sc, chan); 3610 else if (sc->mac_ver == 0x3572) 3611 run_rt3572_set_chan(sc, chan); 3612 else if (sc->mac_ver >= 0x3070) 3613 run_rt3070_set_chan(sc, chan); 3614 else 3615 run_rt2870_set_chan(sc, chan); 3616 3617 /* determine channel group */ 3618 if (chan <= 14) 3619 group = 0; 3620 else if (chan <= 64) 3621 group = 1; 3622 else if (chan <= 128) 3623 group = 2; 3624 else 3625 group = 3; 3626 3627 /* XXX necessary only when group has changed! */ 3628 run_select_chan_group(sc, group); 3629 3630 usbd_delay_ms(sc->sc_udev, 10); 3631 3632 /* Perform IQ calibration. */ 3633 if (sc->mac_ver >= 0x5392) 3634 run_iq_calib(sc, chan); 3635 3636 return 0; 3637 } 3638 3639 static void 3640 run_updateprot(struct run_softc *sc) 3641 { 3642 struct ieee80211com *ic = &sc->sc_ic; 3643 uint32_t tmp; 3644 3645 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3646 /* setup protection frame rate (MCS code) */ 3647 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3648 rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : 3649 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3650 3651 /* CCK frames don't require protection */ 3652 run_write(sc, RT2860_CCK_PROT_CFG, tmp); 3653 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3654 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3655 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3656 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3657 tmp |= RT2860_PROT_CTRL_CTS; 3658 } 3659 run_write(sc, RT2860_OFDM_PROT_CFG, tmp); 3660 } 3661 3662 static void 3663 run_enable_tsf_sync(struct run_softc *sc) 3664 { 3665 struct ieee80211com *ic = &sc->sc_ic; 3666 uint32_t tmp; 3667 3668 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3669 tmp &= ~0x1fffff; 3670 tmp |= ic->ic_bss->ni_intval * 16; 3671 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3672 if (ic->ic_opmode == IEEE80211_M_STA) { 3673 /* 3674 * Local TSF is always updated with remote TSF on beacon 3675 * reception. 3676 */ 3677 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3678 } 3679 #ifndef IEEE80211_STA_ONLY 3680 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3681 tmp |= RT2860_BCN_TX_EN; 3682 /* 3683 * Local TSF is updated with remote TSF on beacon reception 3684 * only if the remote TSF is greater than local TSF. 3685 */ 3686 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3687 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3688 tmp |= RT2860_BCN_TX_EN; 3689 /* SYNC with nobody */ 3690 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3691 } 3692 #endif 3693 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3694 } 3695 3696 static void 3697 run_enable_mrr(struct run_softc *sc) 3698 { 3699 #define CCK(mcs) (mcs) 3700 #define OFDM(mcs) (1 << 3 | (mcs)) 3701 run_write(sc, RT2860_LG_FBK_CFG0, 3702 OFDM(6) << 28 | /* 54->48 */ 3703 OFDM(5) << 24 | /* 48->36 */ 3704 OFDM(4) << 20 | /* 36->24 */ 3705 OFDM(3) << 16 | /* 24->18 */ 3706 OFDM(2) << 12 | /* 18->12 */ 3707 OFDM(1) << 8 | /* 12-> 9 */ 3708 OFDM(0) << 4 | /* 9-> 6 */ 3709 OFDM(0)); /* 6-> 6 */ 3710 3711 run_write(sc, RT2860_LG_FBK_CFG1, 3712 CCK(2) << 12 | /* 11->5.5 */ 3713 CCK(1) << 8 | /* 5.5-> 2 */ 3714 CCK(0) << 4 | /* 2-> 1 */ 3715 CCK(0)); /* 1-> 1 */ 3716 #undef OFDM 3717 #undef CCK 3718 } 3719 3720 static void 3721 run_set_txpreamble(struct run_softc *sc) 3722 { 3723 uint32_t tmp; 3724 3725 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3726 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3727 tmp |= RT2860_CCK_SHORT_EN; 3728 else 3729 tmp &= ~RT2860_CCK_SHORT_EN; 3730 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3731 } 3732 3733 static void 3734 run_set_basicrates(struct run_softc *sc) 3735 { 3736 struct ieee80211com *ic = &sc->sc_ic; 3737 3738 /* set basic rates mask */ 3739 if (ic->ic_curmode == IEEE80211_MODE_11B) 3740 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3741 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3742 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3743 else /* 11g */ 3744 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3745 } 3746 3747 static void 3748 run_set_leds(struct run_softc *sc, uint16_t which) 3749 { 3750 3751 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3752 which | (sc->leds & 0x7f)); 3753 } 3754 3755 static void 3756 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3757 { 3758 3759 run_write(sc, RT2860_MAC_BSSID_DW0, 3760 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3761 run_write(sc, RT2860_MAC_BSSID_DW1, 3762 bssid[4] | bssid[5] << 8); 3763 } 3764 3765 static void 3766 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3767 { 3768 3769 run_write(sc, RT2860_MAC_ADDR_DW0, 3770 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3771 run_write(sc, RT2860_MAC_ADDR_DW1, 3772 addr[4] | addr[5] << 8 | 0xff << 16); 3773 } 3774 3775 static void 3776 run_updateslot(struct ifnet *ifp) 3777 { 3778 3779 /* do it in a process context */ 3780 run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); 3781 } 3782 3783 /* ARGSUSED */ 3784 static void 3785 run_updateslot_cb(struct run_softc *sc, void *arg) 3786 { 3787 uint32_t tmp; 3788 3789 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3790 tmp &= ~0xff; 3791 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3792 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3793 } 3794 3795 static int8_t 3796 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3797 { 3798 struct ieee80211com *ic = &sc->sc_ic; 3799 struct ieee80211_channel *c = ic->ic_curchan; 3800 int delta; 3801 3802 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3803 u_int chan = ieee80211_chan2ieee(ic, c); 3804 delta = sc->rssi_5ghz[rxchain]; 3805 3806 /* determine channel group */ 3807 if (chan <= 64) 3808 delta -= sc->lna[1]; 3809 else if (chan <= 128) 3810 delta -= sc->lna[2]; 3811 else 3812 delta -= sc->lna[3]; 3813 } else 3814 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3815 3816 return -12 - delta - rssi; 3817 } 3818 3819 static void 3820 run_rt5390_bbp_init(struct run_softc *sc) 3821 { 3822 u_int i; 3823 uint8_t bbp; 3824 3825 /* Apply maximum likelihood detection for 2 stream case. */ 3826 run_bbp_read(sc, 105, &bbp); 3827 if (sc->nrxchains > 1) 3828 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3829 3830 /* Avoid data lost and CRC error. */ 3831 run_bbp_read(sc, 4, &bbp); 3832 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3833 3834 if (sc->mac_ver == 0x5592) { 3835 for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { 3836 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3837 rt5592_def_bbp[i].val); 3838 } 3839 for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { 3840 run_bbp_write(sc, 195, i + 0x80); 3841 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3842 } 3843 } else { 3844 for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { 3845 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3846 rt5390_def_bbp[i].val); 3847 } 3848 } 3849 if (sc->mac_ver == 0x5392) { 3850 run_bbp_write(sc, 88, 0x90); 3851 run_bbp_write(sc, 95, 0x9a); 3852 run_bbp_write(sc, 98, 0x12); 3853 run_bbp_write(sc, 106, 0x12); 3854 run_bbp_write(sc, 134, 0xd0); 3855 run_bbp_write(sc, 135, 0xf6); 3856 run_bbp_write(sc, 148, 0x84); 3857 } 3858 3859 run_bbp_read(sc, 152, &bbp); 3860 run_bbp_write(sc, 152, bbp | 0x80); 3861 3862 /* Fix BBP254 for RT5592C. */ 3863 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3864 run_bbp_read(sc, 254, &bbp); 3865 run_bbp_write(sc, 254, bbp | 0x80); 3866 } 3867 3868 /* Disable hardware antenna diversity. */ 3869 if (sc->mac_ver == 0x5390) 3870 run_bbp_write(sc, 154, 0); 3871 3872 /* Initialize Rx CCK/OFDM frequency offset report. */ 3873 run_bbp_write(sc, 142, 1); 3874 run_bbp_write(sc, 143, 57); 3875 } 3876 3877 static int 3878 run_bbp_init(struct run_softc *sc) 3879 { 3880 int i, error, ntries; 3881 uint8_t bbp0; 3882 3883 /* wait for BBP to wake up */ 3884 for (ntries = 0; ntries < 20; ntries++) { 3885 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3886 return error; 3887 if (bbp0 != 0 && bbp0 != 0xff) 3888 break; 3889 } 3890 if (ntries == 20) 3891 return ETIMEDOUT; 3892 3893 /* initialize BBP registers to default values */ 3894 if (sc->mac_ver >= 0x5390) 3895 run_rt5390_bbp_init(sc); 3896 else { 3897 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 3898 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3899 rt2860_def_bbp[i].val); 3900 } 3901 } 3902 3903 if (sc->mac_ver == 0x3593) { 3904 run_bbp_write(sc, 79, 0x13); 3905 run_bbp_write(sc, 80, 0x05); 3906 run_bbp_write(sc, 81, 0x33); 3907 run_bbp_write(sc, 86, 0x46); 3908 run_bbp_write(sc, 137, 0x0f); 3909 } 3910 3911 /* fix BBP84 for RT2860E */ 3912 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3913 run_bbp_write(sc, 84, 0x19); 3914 3915 if (sc->mac_ver >= 0x3070) { 3916 run_bbp_write(sc, 79, 0x13); 3917 run_bbp_write(sc, 80, 0x05); 3918 run_bbp_write(sc, 81, 0x33); 3919 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3920 run_bbp_write(sc, 69, 0x16); 3921 run_bbp_write(sc, 73, 0x12); 3922 } 3923 return 0; 3924 } 3925 3926 static int 3927 run_rt3070_rf_init(struct run_softc *sc) 3928 { 3929 uint32_t tmp; 3930 uint8_t rf, target, bbp4; 3931 int i; 3932 3933 run_rt3070_rf_read(sc, 30, &rf); 3934 /* toggle RF R30 bit 7 */ 3935 run_rt3070_rf_write(sc, 30, rf | 0x80); 3936 usbd_delay_ms(sc->sc_udev, 10); 3937 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3938 3939 /* initialize RF registers to default value */ 3940 if (sc->mac_ver == 0x3572) { 3941 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 3942 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3943 rt3572_def_rf[i].val); 3944 } 3945 } else { 3946 for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { 3947 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3948 rt3070_def_rf[i].val); 3949 } 3950 } 3951 if (sc->mac_ver == 0x3572) { 3952 run_rt3070_rf_read(sc, 6, &rf); 3953 run_rt3070_rf_write(sc, 6, rf | 0x40); 3954 run_rt3070_rf_write(sc, 31, 0x14); 3955 3956 run_read(sc, RT3070_LDO_CFG0, &tmp); 3957 tmp &= ~0x1f000000; 3958 if (sc->mac_rev < 0x0211 && sc->patch_dac) 3959 tmp |= 0x0d000000; /* 1.3V */ 3960 else 3961 tmp |= 0x01000000; /* 1.2V */ 3962 run_write(sc, RT3070_LDO_CFG0, tmp); 3963 } else if (sc->mac_ver == 0x3071) { 3964 run_rt3070_rf_read(sc, 6, &rf); 3965 run_rt3070_rf_write(sc, 6, rf | 0x40); 3966 run_rt3070_rf_write(sc, 31, 0x14); 3967 3968 run_read(sc, RT3070_LDO_CFG0, &tmp); 3969 tmp &= ~0x1f000000; 3970 if (sc->mac_rev < 0x0211) 3971 tmp |= 0x0d000000; /* 1.35V */ 3972 else 3973 tmp |= 0x01000000; /* 1.2V */ 3974 run_write(sc, RT3070_LDO_CFG0, tmp); 3975 3976 /* patch LNA_PE_G1 */ 3977 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3978 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3979 } else if (sc->mac_ver == 0x3070) { 3980 /* increase voltage from 1.2V to 1.35V */ 3981 run_read(sc, RT3070_LDO_CFG0, &tmp); 3982 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3983 run_write(sc, RT3070_LDO_CFG0, tmp); 3984 } 3985 3986 /* select 20MHz bandwidth */ 3987 run_rt3070_rf_read(sc, 31, &rf); 3988 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3989 3990 /* calibrate filter for 20MHz bandwidth */ 3991 sc->rf24_20mhz = 0x1f; /* default value */ 3992 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3993 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3994 3995 /* select 40MHz bandwidth */ 3996 run_bbp_read(sc, 4, &bbp4); 3997 run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); 3998 run_rt3070_rf_read(sc, 31, &rf); 3999 run_rt3070_rf_write(sc, 31, rf | 0x20); 4000 4001 /* calibrate filter for 40MHz bandwidth */ 4002 sc->rf24_40mhz = 0x2f; /* default value */ 4003 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 4004 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 4005 4006 /* go back to 20MHz bandwidth */ 4007 run_bbp_read(sc, 4, &bbp4); 4008 run_bbp_write(sc, 4, bbp4 & ~0x18); 4009 4010 if (sc->mac_ver == 0x3572) { 4011 /* save default BBP registers 25 and 26 values */ 4012 run_bbp_read(sc, 25, &sc->bbp25); 4013 run_bbp_read(sc, 26, &sc->bbp26); 4014 } else if (sc->mac_rev < 0x0211) 4015 run_rt3070_rf_write(sc, 27, 0x03); 4016 4017 run_read(sc, RT3070_OPT_14, &tmp); 4018 run_write(sc, RT3070_OPT_14, tmp | 1); 4019 4020 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4021 run_rt3070_rf_read(sc, 17, &rf); 4022 rf &= ~RT3070_TX_LO1; 4023 if ((sc->mac_ver == 0x3070 || 4024 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4025 !sc->ext_2ghz_lna) 4026 rf |= 0x20; /* fix for long range Rx issue */ 4027 if (sc->txmixgain_2ghz >= 1) 4028 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4029 run_rt3070_rf_write(sc, 17, rf); 4030 } 4031 if (sc->mac_ver == 0x3071) { 4032 run_rt3070_rf_read(sc, 1, &rf); 4033 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4034 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4035 run_rt3070_rf_write(sc, 1, rf); 4036 4037 run_rt3070_rf_read(sc, 15, &rf); 4038 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4039 4040 run_rt3070_rf_read(sc, 20, &rf); 4041 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4042 4043 run_rt3070_rf_read(sc, 21, &rf); 4044 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4045 } 4046 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4047 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4048 run_rt3070_rf_read(sc, 27, &rf); 4049 rf &= ~0x77; 4050 if (sc->mac_rev < 0x0211) 4051 rf |= 0x03; 4052 run_rt3070_rf_write(sc, 27, rf); 4053 } 4054 return 0; 4055 } 4056 4057 static int 4058 run_rt3593_rf_init(struct run_softc *sc) 4059 { 4060 uint32_t tmp; 4061 uint8_t rf; 4062 int i; 4063 4064 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4065 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4066 tmp &= ~(1 << 4 | 1 << 7); 4067 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4068 4069 /* Initialize RF registers to default value. */ 4070 for (i = 0; i < __arraycount(rt3593_def_rf); i++) { 4071 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4072 rt3593_def_rf[i].val); 4073 } 4074 4075 /* Toggle RF R2 to initiate calibration. */ 4076 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4077 4078 /* Initialize RF frequency offset. */ 4079 run_adjust_freq_offset(sc); 4080 4081 run_rt3070_rf_read(sc, 18, &rf); 4082 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4083 4084 /* 4085 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4086 * decrease voltage back to 1.2V. 4087 */ 4088 run_read(sc, RT3070_LDO_CFG0, &tmp); 4089 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4090 run_write(sc, RT3070_LDO_CFG0, tmp); 4091 usbd_delay_ms(sc->sc_udev, 1); 4092 tmp = (tmp & ~0x1f000000) | 0x01000000; 4093 run_write(sc, RT3070_LDO_CFG0, tmp); 4094 4095 sc->rf24_20mhz = 0x1f; 4096 sc->rf24_40mhz = 0x2f; 4097 4098 /* Save default BBP registers 25 and 26 values. */ 4099 run_bbp_read(sc, 25, &sc->bbp25); 4100 run_bbp_read(sc, 26, &sc->bbp26); 4101 4102 run_read(sc, RT3070_OPT_14, &tmp); 4103 run_write(sc, RT3070_OPT_14, tmp | 1); 4104 return 0; 4105 } 4106 4107 static int 4108 run_rt5390_rf_init(struct run_softc *sc) 4109 { 4110 uint32_t tmp; 4111 uint8_t rf; 4112 int i; 4113 4114 /* Toggle RF R2 to initiate calibration. */ 4115 if (sc->mac_ver == 0x5390) { 4116 run_rt3070_rf_read(sc, 2, &rf); 4117 run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); 4118 usbd_delay_ms(sc->sc_udev, 10); 4119 run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); 4120 } else { 4121 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4122 usbd_delay_ms(sc->sc_udev, 10); 4123 } 4124 4125 /* Initialize RF registers to default value. */ 4126 if (sc->mac_ver == 0x5592) { 4127 for (i = 0; i < __arraycount(rt5592_def_rf); i++) { 4128 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4129 rt5592_def_rf[i].val); 4130 } 4131 /* Initialize RF frequency offset. */ 4132 run_adjust_freq_offset(sc); 4133 } else if (sc->mac_ver == 0x5392) { 4134 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 4135 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4136 rt5392_def_rf[i].val); 4137 } 4138 if (sc->mac_rev >= 0x0223) { 4139 run_rt3070_rf_write(sc, 23, 0x0f); 4140 run_rt3070_rf_write(sc, 24, 0x3e); 4141 run_rt3070_rf_write(sc, 51, 0x32); 4142 run_rt3070_rf_write(sc, 53, 0x22); 4143 run_rt3070_rf_write(sc, 56, 0xc1); 4144 run_rt3070_rf_write(sc, 59, 0x0f); 4145 } 4146 } else { 4147 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 4148 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4149 rt5390_def_rf[i].val); 4150 } 4151 if (sc->mac_rev >= 0x0502) { 4152 run_rt3070_rf_write(sc, 6, 0xe0); 4153 run_rt3070_rf_write(sc, 25, 0x80); 4154 run_rt3070_rf_write(sc, 46, 0x73); 4155 run_rt3070_rf_write(sc, 53, 0x00); 4156 run_rt3070_rf_write(sc, 56, 0x42); 4157 run_rt3070_rf_write(sc, 61, 0xd1); 4158 } 4159 } 4160 4161 sc->rf24_20mhz = 0x1f; /* default value */ 4162 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4163 4164 if (sc->mac_rev < 0x0211) 4165 run_rt3070_rf_write(sc, 27, 0x3); 4166 4167 run_read(sc, RT3070_OPT_14, &tmp); 4168 run_write(sc, RT3070_OPT_14, tmp | 1); 4169 return 0; 4170 } 4171 4172 static int 4173 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4174 uint8_t *val) 4175 { 4176 uint8_t rf22, rf24; 4177 uint8_t bbp55_pb, bbp55_sb, delta; 4178 int ntries; 4179 4180 /* program filter */ 4181 run_rt3070_rf_read(sc, 24, &rf24); 4182 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4183 run_rt3070_rf_write(sc, 24, rf24); 4184 4185 /* enable baseband loopback mode */ 4186 run_rt3070_rf_read(sc, 22, &rf22); 4187 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4188 4189 /* set power and frequency of passband test tone */ 4190 run_bbp_write(sc, 24, 0x00); 4191 for (ntries = 0; ntries < 100; ntries++) { 4192 /* transmit test tone */ 4193 run_bbp_write(sc, 25, 0x90); 4194 usbd_delay_ms(sc->sc_udev, 10); 4195 /* read received power */ 4196 run_bbp_read(sc, 55, &bbp55_pb); 4197 if (bbp55_pb != 0) 4198 break; 4199 } 4200 if (ntries == 100) 4201 return ETIMEDOUT; 4202 4203 /* set power and frequency of stopband test tone */ 4204 run_bbp_write(sc, 24, 0x06); 4205 for (ntries = 0; ntries < 100; ntries++) { 4206 /* transmit test tone */ 4207 run_bbp_write(sc, 25, 0x90); 4208 usbd_delay_ms(sc->sc_udev, 10); 4209 /* read received power */ 4210 run_bbp_read(sc, 55, &bbp55_sb); 4211 4212 delta = bbp55_pb - bbp55_sb; 4213 if (delta > target) 4214 break; 4215 4216 /* reprogram filter */ 4217 rf24++; 4218 run_rt3070_rf_write(sc, 24, rf24); 4219 } 4220 if (ntries < 100) { 4221 if (rf24 != init) 4222 rf24--; /* backtrack */ 4223 *val = rf24; 4224 run_rt3070_rf_write(sc, 24, rf24); 4225 } 4226 4227 /* restore initial state */ 4228 run_bbp_write(sc, 24, 0x00); 4229 4230 /* disable baseband loopback mode */ 4231 run_rt3070_rf_read(sc, 22, &rf22); 4232 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4233 4234 return 0; 4235 } 4236 4237 static void 4238 run_rt3070_rf_setup(struct run_softc *sc) 4239 { 4240 uint8_t bbp, rf; 4241 int i; 4242 4243 if (sc->mac_ver == 0x3572) { 4244 /* enable DC filter */ 4245 if (sc->mac_rev >= 0x0201) 4246 run_bbp_write(sc, 103, 0xc0); 4247 4248 run_bbp_read(sc, 138, &bbp); 4249 if (sc->ntxchains == 1) 4250 bbp |= 0x20; /* turn off DAC1 */ 4251 if (sc->nrxchains == 1) 4252 bbp &= ~0x02; /* turn off ADC1 */ 4253 run_bbp_write(sc, 138, bbp); 4254 4255 if (sc->mac_rev >= 0x0211) { 4256 /* improve power consumption */ 4257 run_bbp_read(sc, 31, &bbp); 4258 run_bbp_write(sc, 31, bbp & ~0x03); 4259 } 4260 4261 run_rt3070_rf_read(sc, 16, &rf); 4262 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4263 run_rt3070_rf_write(sc, 16, rf); 4264 } else if (sc->mac_ver == 0x3071) { 4265 /* enable DC filter */ 4266 if (sc->mac_rev >= 0x0201) 4267 run_bbp_write(sc, 103, 0xc0); 4268 4269 run_bbp_read(sc, 138, &bbp); 4270 if (sc->ntxchains == 1) 4271 bbp |= 0x20; /* turn off DAC1 */ 4272 if (sc->nrxchains == 1) 4273 bbp &= ~0x02; /* turn off ADC1 */ 4274 run_bbp_write(sc, 138, bbp); 4275 4276 if (sc->mac_rev >= 0x0211) { 4277 /* improve power consumption */ 4278 run_bbp_read(sc, 31, &bbp); 4279 run_bbp_write(sc, 31, bbp & ~0x03); 4280 } 4281 4282 run_write(sc, RT2860_TX_SW_CFG1, 0); 4283 if (sc->mac_rev < 0x0211) { 4284 run_write(sc, RT2860_TX_SW_CFG2, 4285 sc->patch_dac ? 0x2c : 0x0f); 4286 } else 4287 run_write(sc, RT2860_TX_SW_CFG2, 0); 4288 } else if (sc->mac_ver == 0x3070) { 4289 if (sc->mac_rev >= 0x0201) { 4290 /* enable DC filter */ 4291 run_bbp_write(sc, 103, 0xc0); 4292 4293 /* improve power consumption */ 4294 run_bbp_read(sc, 31, &bbp); 4295 run_bbp_write(sc, 31, bbp & ~0x03); 4296 } 4297 4298 if (sc->mac_rev < 0x0211) { 4299 run_write(sc, RT2860_TX_SW_CFG1, 0); 4300 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4301 } else 4302 run_write(sc, RT2860_TX_SW_CFG2, 0); 4303 } 4304 4305 /* initialize RF registers from ROM for >=RT3071*/ 4306 if (sc->mac_ver >= 0x3071) { 4307 for (i = 0; i < 10; i++) { 4308 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4309 continue; 4310 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4311 } 4312 } 4313 } 4314 4315 static void 4316 run_rt3593_rf_setup(struct run_softc *sc) 4317 { 4318 uint8_t bbp, rf; 4319 4320 if (sc->mac_rev >= 0x0211) { 4321 /* Enable DC filter. */ 4322 run_bbp_write(sc, 103, 0xc0); 4323 } 4324 run_write(sc, RT2860_TX_SW_CFG1, 0); 4325 if (sc->mac_rev < 0x0211) { 4326 run_write(sc, RT2860_TX_SW_CFG2, 4327 sc->patch_dac ? 0x2c : 0x0f); 4328 } else 4329 run_write(sc, RT2860_TX_SW_CFG2, 0); 4330 4331 run_rt3070_rf_read(sc, 50, &rf); 4332 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4333 4334 run_rt3070_rf_read(sc, 51, &rf); 4335 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4336 ((sc->txmixgain_2ghz & 0x07) << 2); 4337 run_rt3070_rf_write(sc, 51, rf); 4338 4339 run_rt3070_rf_read(sc, 38, &rf); 4340 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4341 4342 run_rt3070_rf_read(sc, 39, &rf); 4343 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4344 4345 run_rt3070_rf_read(sc, 1, &rf); 4346 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4347 4348 run_rt3070_rf_read(sc, 30, &rf); 4349 rf = (rf & ~0x18) | 0x10; 4350 run_rt3070_rf_write(sc, 30, rf); 4351 4352 /* Apply maximum likelihood detection for 2 stream case. */ 4353 run_bbp_read(sc, 105, &bbp); 4354 if (sc->nrxchains > 1) 4355 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4356 4357 /* Avoid data lost and CRC error. */ 4358 run_bbp_read(sc, 4, &bbp); 4359 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4360 4361 run_bbp_write(sc, 92, 0x02); 4362 run_bbp_write(sc, 82, 0x82); 4363 run_bbp_write(sc, 106, 0x05); 4364 run_bbp_write(sc, 104, 0x92); 4365 run_bbp_write(sc, 88, 0x90); 4366 run_bbp_write(sc, 148, 0xc8); 4367 run_bbp_write(sc, 47, 0x48); 4368 run_bbp_write(sc, 120, 0x50); 4369 4370 run_bbp_write(sc, 163, 0x9d); 4371 4372 /* SNR mapping. */ 4373 run_bbp_write(sc, 142, 0x06); 4374 run_bbp_write(sc, 143, 0xa0); 4375 run_bbp_write(sc, 142, 0x07); 4376 run_bbp_write(sc, 143, 0xa1); 4377 run_bbp_write(sc, 142, 0x08); 4378 run_bbp_write(sc, 143, 0xa2); 4379 4380 run_bbp_write(sc, 31, 0x08); 4381 run_bbp_write(sc, 68, 0x0b); 4382 run_bbp_write(sc, 105, 0x04); 4383 } 4384 4385 static void 4386 run_rt5390_rf_setup(struct run_softc *sc) 4387 { 4388 uint8_t bbp, rf; 4389 4390 if (sc->mac_rev >= 0x0211) { 4391 /* Enable DC filter. */ 4392 run_bbp_write(sc, 103, 0xc0); 4393 4394 if (sc->mac_ver != 0x5592) { 4395 /* Improve power consumption. */ 4396 run_bbp_read(sc, 31, &bbp); 4397 run_bbp_write(sc, 31, bbp & ~0x03); 4398 } 4399 } 4400 4401 run_bbp_read(sc, 138, &bbp); 4402 if (sc->ntxchains == 1) 4403 bbp |= 0x20; /* turn off DAC1 */ 4404 if (sc->nrxchains == 1) 4405 bbp &= ~0x02; /* turn off ADC1 */ 4406 run_bbp_write(sc, 138, bbp); 4407 4408 run_rt3070_rf_read(sc, 38, &rf); 4409 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4410 4411 run_rt3070_rf_read(sc, 39, &rf); 4412 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4413 4414 /* Avoid data lost and CRC error. */ 4415 run_bbp_read(sc, 4, &bbp); 4416 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4417 4418 run_rt3070_rf_read(sc, 30, &rf); 4419 rf = (rf & ~0x18) | 0x10; 4420 run_rt3070_rf_write(sc, 30, rf); 4421 4422 if (sc->mac_ver != 0x5592) { 4423 run_write(sc, RT2860_TX_SW_CFG1, 0); 4424 if (sc->mac_rev < 0x0211) { 4425 run_write(sc, RT2860_TX_SW_CFG2, 4426 sc->patch_dac ? 0x2c : 0x0f); 4427 } else 4428 run_write(sc, RT2860_TX_SW_CFG2, 0); 4429 } 4430 } 4431 4432 static int 4433 run_txrx_enable(struct run_softc *sc) 4434 { 4435 uint32_t tmp; 4436 int error, ntries; 4437 4438 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4439 for (ntries = 0; ntries < 200; ntries++) { 4440 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4441 return error; 4442 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4443 break; 4444 usbd_delay_ms(sc->sc_udev, 50); 4445 } 4446 if (ntries == 200) 4447 return ETIMEDOUT; 4448 4449 usbd_delay_ms(sc->sc_udev, 50); 4450 4451 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4452 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4453 4454 /* enable Rx bulk aggregation (set timeout and limit) */ 4455 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4456 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4457 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4458 4459 /* set Rx filter */ 4460 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4461 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4462 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4463 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4464 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4465 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4466 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4467 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4468 } 4469 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4470 4471 run_write(sc, RT2860_MAC_SYS_CTRL, 4472 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4473 4474 return 0; 4475 } 4476 4477 static int 4478 run_adjust_freq_offset(struct run_softc *sc) 4479 { 4480 uint8_t rf, tmp; 4481 4482 run_rt3070_rf_read(sc, 17, &rf); 4483 tmp = rf; 4484 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4485 rf = MIN(rf, 0x5f); 4486 4487 if (tmp != rf) 4488 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4489 4490 return 0; 4491 } 4492 4493 static int 4494 run_init(struct ifnet *ifp) 4495 { 4496 struct run_softc *sc = ifp->if_softc; 4497 struct ieee80211com *ic = &sc->sc_ic; 4498 uint32_t tmp; 4499 uint8_t bbp1, bbp3; 4500 int i, error, qid, ridx, ntries; 4501 4502 for (ntries = 0; ntries < 100; ntries++) { 4503 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4504 goto fail; 4505 if (tmp != 0 && tmp != 0xffffffff) 4506 break; 4507 usbd_delay_ms(sc->sc_udev, 10); 4508 } 4509 if (ntries == 100) { 4510 error = ETIMEDOUT; 4511 goto fail; 4512 } 4513 4514 if ((sc->sc_flags & RUN_FWLOADED) == 0 && 4515 (error = run_load_microcode(sc)) != 0) { 4516 aprint_error_dev(sc->sc_dev, 4517 "could not load 8051 microcode\n"); 4518 goto fail; 4519 } 4520 4521 if (ifp->if_flags & IFF_RUNNING) 4522 run_stop(ifp, 0); 4523 4524 /* init host command ring */ 4525 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4526 4527 /* init Tx rings (4 EDCAs) */ 4528 for (qid = 0; qid < 4; qid++) { 4529 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4530 goto fail; 4531 } 4532 /* init Rx ring */ 4533 if ((error = run_alloc_rx_ring(sc)) != 0) 4534 goto fail; 4535 4536 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4537 run_set_macaddr(sc, ic->ic_myaddr); 4538 4539 for (ntries = 0; ntries < 100; ntries++) { 4540 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4541 goto fail; 4542 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4543 break; 4544 usbd_delay_ms(sc->sc_udev, 10); 4545 } 4546 if (ntries == 100) { 4547 aprint_error_dev(sc->sc_dev, 4548 "timeout waiting for DMA engine\n"); 4549 error = ETIMEDOUT; 4550 goto fail; 4551 } 4552 tmp &= 0xff0; 4553 tmp |= RT2860_TX_WB_DDONE; 4554 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4555 4556 /* turn off PME_OEN to solve high-current issue */ 4557 run_read(sc, RT2860_SYS_CTRL, &tmp); 4558 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4559 4560 run_write(sc, RT2860_MAC_SYS_CTRL, 4561 RT2860_BBP_HRST | RT2860_MAC_SRST); 4562 run_write(sc, RT2860_USB_DMA_CFG, 0); 4563 4564 if ((error = run_reset(sc)) != 0) { 4565 aprint_error_dev(sc->sc_dev, "could not reset chipset\n"); 4566 goto fail; 4567 } 4568 4569 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4570 4571 /* init Tx power for all Tx rates (from EEPROM) */ 4572 for (ridx = 0; ridx < 5; ridx++) { 4573 if (sc->txpow20mhz[ridx] == 0xffffffff) 4574 continue; 4575 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4576 } 4577 4578 for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) 4579 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4580 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4581 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4582 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4583 4584 if (sc->mac_ver >= 0x5390) { 4585 run_write(sc, RT2860_TX_SW_CFG0, 4586 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4587 if (sc->mac_ver >= 0x5392) { 4588 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4589 if (sc->mac_ver == 0x5592) { 4590 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4591 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4592 } else { 4593 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4594 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4595 } 4596 } 4597 } else if (sc->mac_ver >= 0x3593) { 4598 run_write(sc, RT2860_TX_SW_CFG0, 4599 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4600 } else if (sc->mac_ver >= 0x3070) { 4601 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4602 run_write(sc, RT2860_TX_SW_CFG0, 4603 4 << RT2860_DLY_PAPE_EN_SHIFT); 4604 } 4605 4606 /* wait while MAC is busy */ 4607 for (ntries = 0; ntries < 100; ntries++) { 4608 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4609 goto fail; 4610 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4611 break; 4612 DELAY(1000); 4613 } 4614 if (ntries == 100) { 4615 error = ETIMEDOUT; 4616 goto fail; 4617 } 4618 4619 /* clear Host to MCU mailbox */ 4620 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4621 run_write(sc, RT2860_H2M_MAILBOX, 0); 4622 usbd_delay_ms(sc->sc_udev, 10); 4623 4624 if ((error = run_bbp_init(sc)) != 0) { 4625 aprint_error_dev(sc->sc_dev, "could not initialize BBP\n"); 4626 goto fail; 4627 } 4628 4629 /* abort TSF synchronization */ 4630 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4631 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4632 RT2860_TBTT_TIMER_EN); 4633 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4634 4635 /* clear RX WCID search table */ 4636 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4637 /* clear Pair-wise key table */ 4638 run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); 4639 /* clear IV/EIV table */ 4640 run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); 4641 /* clear WCID attribute table */ 4642 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4643 /* clear shared key table */ 4644 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4645 /* clear shared key mode */ 4646 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4647 4648 /* clear RX WCID search table */ 4649 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4650 /* clear WCID attribute table */ 4651 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4652 4653 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4654 tmp = (tmp & ~0xff) | 0x1e; 4655 run_write(sc, RT2860_US_CYC_CNT, tmp); 4656 4657 if (sc->mac_rev != 0x0101) 4658 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4659 4660 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4661 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4662 4663 /* write vendor-specific BBP values (from EEPROM) */ 4664 if (sc->mac_ver < 0x3593) { 4665 for (i = 0; i < 10; i++) { 4666 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4667 continue; 4668 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4669 } 4670 } 4671 4672 /* select Main antenna for 1T1R devices */ 4673 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4674 run_set_rx_antenna(sc, 0); 4675 4676 /* send LEDs operating mode to microcontroller */ 4677 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4678 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4679 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4680 4681 if (sc->mac_ver >= 0x5390) 4682 run_rt5390_rf_init(sc); 4683 else if (sc->mac_ver == 0x3593) 4684 run_rt3593_rf_init(sc); 4685 else if (sc->mac_ver >= 0x3070) 4686 run_rt3070_rf_init(sc); 4687 4688 /* disable non-existing Rx chains */ 4689 run_bbp_read(sc, 3, &bbp3); 4690 bbp3 &= ~(1 << 3 | 1 << 4); 4691 if (sc->nrxchains == 2) 4692 bbp3 |= 1 << 3; 4693 else if (sc->nrxchains == 3) 4694 bbp3 |= 1 << 4; 4695 run_bbp_write(sc, 3, bbp3); 4696 4697 /* disable non-existing Tx chains */ 4698 run_bbp_read(sc, 1, &bbp1); 4699 if (sc->ntxchains == 1) 4700 bbp1 &= ~(1 << 3 | 1 << 4); 4701 run_bbp_write(sc, 1, bbp1); 4702 4703 if (sc->mac_ver >= 0x5390) 4704 run_rt5390_rf_setup(sc); 4705 else if (sc->mac_ver == 0x3593) 4706 run_rt3593_rf_setup(sc); 4707 else if (sc->mac_ver >= 0x3070) 4708 run_rt3070_rf_setup(sc); 4709 4710 /* select default channel */ 4711 run_set_chan(sc, ic->ic_curchan); 4712 4713 /* setup initial protection mode */ 4714 run_updateprot(sc); 4715 4716 /* turn radio LED on */ 4717 run_set_leds(sc, RT2860_LED_RADIO); 4718 4719 #ifdef RUN_HWCRYPTO 4720 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4721 /* install WEP keys */ 4722 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4723 (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], 4724 NULL); 4725 } 4726 #endif 4727 4728 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4729 struct run_rx_data *data = &sc->rxq.data[i]; 4730 4731 usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, 4732 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 4733 error = usbd_transfer(data->xfer); 4734 if (error != USBD_NORMAL_COMPLETION && 4735 error != USBD_IN_PROGRESS) 4736 goto fail; 4737 } 4738 4739 if ((error = run_txrx_enable(sc)) != 0) 4740 goto fail; 4741 4742 ifp->if_flags &= ~IFF_OACTIVE; 4743 ifp->if_flags |= IFF_RUNNING; 4744 4745 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4746 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4747 else 4748 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4749 4750 if (error != 0) 4751 fail: run_stop(ifp, 1); 4752 return error; 4753 } 4754 4755 static void 4756 run_stop(struct ifnet *ifp, int disable) 4757 { 4758 struct run_softc *sc = ifp->if_softc; 4759 struct ieee80211com *ic = &sc->sc_ic; 4760 uint32_t tmp; 4761 int ntries, qid; 4762 4763 if (ifp->if_flags & IFF_RUNNING) 4764 run_set_leds(sc, 0); /* turn all LEDs off */ 4765 4766 sc->sc_tx_timer = 0; 4767 ifp->if_timer = 0; 4768 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4769 4770 callout_stop(&sc->scan_to); 4771 callout_stop(&sc->calib_to); 4772 4773 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4774 /* wait for all queued asynchronous commands to complete */ 4775 while (sc->cmdq.queued > 0) 4776 tsleep(&sc->cmdq, 0, "cmdq", 0); 4777 4778 /* disable Tx/Rx */ 4779 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4780 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4781 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4782 4783 /* wait for pending Tx to complete */ 4784 for (ntries = 0; ntries < 100; ntries++) { 4785 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4786 break; 4787 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4788 break; 4789 } 4790 DELAY(1000); 4791 run_write(sc, RT2860_USB_DMA_CFG, 0); 4792 4793 /* reset adapter */ 4794 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4795 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4796 4797 /* reset Tx and Rx rings */ 4798 sc->qfullmsk = 0; 4799 for (qid = 0; qid < 4; qid++) 4800 run_free_tx_ring(sc, qid); 4801 run_free_rx_ring(sc); 4802 } 4803 4804 #ifndef IEEE80211_STA_ONLY 4805 static int 4806 run_setup_beacon(struct run_softc *sc) 4807 { 4808 struct ieee80211com *ic = &sc->sc_ic; 4809 struct rt2860_txwi txwi; 4810 struct mbuf *m; 4811 uint16_t txwisize; 4812 int ridx; 4813 4814 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4815 return ENOBUFS; 4816 4817 memset(&txwi, 0, sizeof(txwi)); 4818 txwi.wcid = 0xff; 4819 txwi.len = htole16(m->m_pkthdr.len); 4820 /* send beacons at the lowest available rate */ 4821 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4822 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4823 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4824 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4825 txwi.phy |= htole16(RT2860_PHY_OFDM); 4826 txwi.txop = RT2860_TX_TXOP_HT; 4827 txwi.flags = RT2860_TX_TS; 4828 4829 txwisize = (sc->mac_ver == 0x5592) ? 4830 sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); 4831 run_write_region_1(sc, RT2860_BCN_BASE(0), 4832 (uint8_t *)&txwi, txwisize); 4833 run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, 4834 mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); 4835 4836 m_freem(m); 4837 4838 return 0; 4839 } 4840 #endif 4841 4842 MODULE(MODULE_CLASS_DRIVER, if_run, "bpf"); 4843 4844 #ifdef _MODULE 4845 #include "ioconf.c" 4846 #endif 4847 4848 static int 4849 if_run_modcmd(modcmd_t cmd, void *arg) 4850 { 4851 int error = 0; 4852 4853 switch (cmd) { 4854 case MODULE_CMD_INIT: 4855 #ifdef _MODULE 4856 error = config_init_component(cfdriver_ioconf_run, 4857 cfattach_ioconf_run, cfdata_ioconf_run); 4858 #endif 4859 return error; 4860 case MODULE_CMD_FINI: 4861 #ifdef _MODULE 4862 error = config_fini_component(cfdriver_ioconf_run, 4863 cfattach_ioconf_run, cfdata_ioconf_run); 4864 #endif 4865 return error; 4866 default: 4867 return ENOTTY; 4868 } 4869 } 4870
Indexes created Thu Oct 02 10:09:58 GMT 2025