if_run.c revision 1.16
1 /* $NetBSD: if_run.c,v 1.16 2016/09/16 09:25:30 mlelstv Exp $ */ 2 /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.16 2016/09/16 09:25:30 mlelstv Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/sysctl.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/callout.h> 37 #include <sys/module.h> 38 #include <sys/conf.h> 39 #include <sys/device.h> 40 41 #include <sys/bus.h> 42 #include <machine/endian.h> 43 #include <sys/intr.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_arp.h> 48 #include <net/if_dl.h> 49 #include <net/if_ether.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_amrr.h> 55 #include <net80211/ieee80211_radiotap.h> 56 57 #include <dev/firmload.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbdevs.h> 64 65 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 66 #include <dev/usb/if_runvar.h> 67 68 #ifdef RUN_DEBUG 69 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 70 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 71 int run_debug = 0; 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 78 79 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 80 static const struct usb_devno run_devs[] = { 81 USB_ID(ABOCOM, RT2770), 82 USB_ID(ABOCOM, RT2870), 83 USB_ID(ABOCOM, RT3070), 84 USB_ID(ABOCOM, RT3071), 85 USB_ID(ABOCOM, RT3072), 86 USB_ID(ABOCOM2, RT2870_1), 87 USB_ID(ACCTON, RT2770), 88 USB_ID(ACCTON, RT2870_1), 89 USB_ID(ACCTON, RT2870_2), 90 USB_ID(ACCTON, RT2870_3), 91 USB_ID(ACCTON, RT2870_4), 92 USB_ID(ACCTON, RT2870_5), 93 USB_ID(ACCTON, RT3070), 94 USB_ID(ACCTON, RT3070_1), 95 USB_ID(ACCTON, RT3070_2), 96 USB_ID(ACCTON, RT3070_3), 97 USB_ID(ACCTON, RT3070_4), 98 USB_ID(ACCTON, RT3070_5), 99 USB_ID(ACCTON, RT3070_6), 100 USB_ID(AIRTIES, RT3070), 101 USB_ID(AIRTIES, RT3070_2), 102 USB_ID(ALLWIN, RT2070), 103 USB_ID(ALLWIN, RT2770), 104 USB_ID(ALLWIN, RT2870), 105 USB_ID(ALLWIN, RT3070), 106 USB_ID(ALLWIN, RT3071), 107 USB_ID(ALLWIN, RT3072), 108 USB_ID(ALLWIN, RT3572), 109 USB_ID(AMIGO, RT2870_1), 110 USB_ID(AMIGO, RT2870_2), 111 USB_ID(AMIT, CGWLUSB2GNR), 112 USB_ID(AMIT, RT2870_1), 113 USB_ID(AMIT2, RT2870), 114 USB_ID(ASUSTEK, RT2870_1), 115 USB_ID(ASUSTEK, RT2870_2), 116 USB_ID(ASUSTEK, RT2870_3), 117 USB_ID(ASUSTEK, RT2870_4), 118 USB_ID(ASUSTEK, RT2870_5), 119 USB_ID(ASUSTEK, RT3070), 120 USB_ID(ASUSTEK, RT3070_1), 121 USB_ID(ASUSTEK2, USBN11), 122 USB_ID(AZUREWAVE, RT2870_1), 123 USB_ID(AZUREWAVE, RT2870_2), 124 USB_ID(AZUREWAVE, RT3070), 125 USB_ID(AZUREWAVE, RT3070_2), 126 USB_ID(AZUREWAVE, RT3070_3), 127 USB_ID(AZUREWAVE, RT3070_4), 128 USB_ID(AZUREWAVE, RT3070_5), 129 USB_ID(BELKIN, F5D8053V3), 130 USB_ID(BELKIN, F5D8055), 131 USB_ID(BELKIN, F5D8055V2), 132 USB_ID(BELKIN, F6D4050V1), 133 USB_ID(BELKIN, F6D4050V2), 134 USB_ID(BELKIN, F7D1101V2), 135 USB_ID(BELKIN, RT2870_1), 136 USB_ID(BELKIN, RT2870_2), 137 USB_ID(BEWAN, RT3070), 138 USB_ID(CISCOLINKSYS, AE1000), 139 USB_ID(CISCOLINKSYS, AM10), 140 USB_ID(CISCOLINKSYS2, RT3070), 141 USB_ID(CISCOLINKSYS3, RT3070), 142 USB_ID(CONCEPTRONIC, RT2870_1), 143 USB_ID(CONCEPTRONIC, RT2870_2), 144 USB_ID(CONCEPTRONIC, RT2870_3), 145 USB_ID(CONCEPTRONIC, RT2870_4), 146 USB_ID(CONCEPTRONIC, RT2870_5), 147 USB_ID(CONCEPTRONIC, RT2870_6), 148 USB_ID(CONCEPTRONIC, RT2870_7), 149 USB_ID(CONCEPTRONIC, RT2870_8), 150 USB_ID(CONCEPTRONIC, RT3070_1), 151 USB_ID(CONCEPTRONIC, RT3070_2), 152 USB_ID(CONCEPTRONIC, RT3070_3), 153 USB_ID(COREGA, CGWLUSB300GNM), 154 USB_ID(COREGA, RT2870_1), 155 USB_ID(COREGA, RT2870_2), 156 USB_ID(COREGA, RT2870_3), 157 USB_ID(COREGA, RT3070), 158 USB_ID(CYBERTAN, RT2870), 159 USB_ID(DLINK, RT2870), 160 USB_ID(DLINK, RT3072), 161 USB_ID(DLINK2, DWA130), 162 USB_ID(DLINK2, RT2870_1), 163 USB_ID(DLINK2, RT2870_2), 164 USB_ID(DLINK2, RT3070_1), 165 USB_ID(DLINK2, RT3070_2), 166 USB_ID(DLINK2, RT3070_3), 167 USB_ID(DLINK2, RT3070_4), 168 USB_ID(DLINK2, RT3070_5), 169 USB_ID(DLINK2, RT3072), 170 USB_ID(DLINK2, RT3072_1), 171 USB_ID(DVICO, RT3070), 172 USB_ID(EDIMAX, EW7717), 173 USB_ID(EDIMAX, EW7718), 174 USB_ID(EDIMAX, EW7722UTN), 175 USB_ID(EDIMAX, RT2870_1), 176 USB_ID(ENCORE, RT3070), 177 USB_ID(ENCORE, RT3070_2), 178 USB_ID(ENCORE, RT3070_3), 179 USB_ID(GIGABYTE, GNWB31N), 180 USB_ID(GIGABYTE, GNWB32L), 181 USB_ID(GIGABYTE, RT2870_1), 182 USB_ID(GIGASET, RT3070_1), 183 USB_ID(GIGASET, RT3070_2), 184 USB_ID(GUILLEMOT, HWNU300), 185 USB_ID(HAWKING, HWUN2), 186 USB_ID(HAWKING, RT2870_1), 187 USB_ID(HAWKING, RT2870_2), 188 USB_ID(HAWKING, RT2870_3), 189 USB_ID(HAWKING, RT2870_4), 190 USB_ID(HAWKING, RT2870_5), 191 USB_ID(HAWKING, RT3070), 192 USB_ID(IODATA, RT3072_1), 193 USB_ID(IODATA, RT3072_2), 194 USB_ID(IODATA, RT3072_3), 195 USB_ID(IODATA, RT3072_4), 196 USB_ID(LINKSYS4, RT3070), 197 USB_ID(LINKSYS4, WUSB100), 198 USB_ID(LINKSYS4, WUSB54GC_3), 199 USB_ID(LINKSYS4, WUSB600N), 200 USB_ID(LINKSYS4, WUSB600NV2), 201 USB_ID(LOGITEC, LANW300NU2), 202 USB_ID(LOGITEC, RT2870_1), 203 USB_ID(LOGITEC, RT2870_2), 204 USB_ID(LOGITEC, RT2870_3), 205 USB_ID(LOGITEC, RT3020), 206 USB_ID(MELCO, RT2870_1), 207 USB_ID(MELCO, RT2870_2), 208 USB_ID(MELCO, WLIUCAG300N), 209 USB_ID(MELCO, WLIUCG300N), 210 USB_ID(MELCO, WLIUCG301N), 211 USB_ID(MELCO, WLIUCGN), 212 USB_ID(MELCO, WLIUCGNHP), 213 USB_ID(MELCO, WLIUCGNM), 214 USB_ID(MELCO, WLIUCGNM2T), 215 USB_ID(MOTOROLA4, RT2770), 216 USB_ID(MOTOROLA4, RT3070), 217 USB_ID(MSI, RT3070), 218 USB_ID(MSI, RT3070_2), 219 USB_ID(MSI, RT3070_3), 220 USB_ID(MSI, RT3070_4), 221 USB_ID(MSI, RT3070_5), 222 USB_ID(MSI, RT3070_6), 223 USB_ID(MSI, RT3070_7), 224 USB_ID(MSI, RT3070_8), 225 USB_ID(MSI, RT3070_9), 226 USB_ID(MSI, RT3070_10), 227 USB_ID(MSI, RT3070_11), 228 USB_ID(MSI, RT3070_12), 229 USB_ID(MSI, RT3070_13), 230 USB_ID(MSI, RT3070_14), 231 USB_ID(MSI, RT3070_15), 232 USB_ID(OVISLINK, RT3071), 233 USB_ID(OVISLINK, RT3072), 234 USB_ID(PARA, RT3070), 235 USB_ID(PEGATRON, RT2870), 236 USB_ID(PEGATRON, RT3070), 237 USB_ID(PEGATRON, RT3070_2), 238 USB_ID(PEGATRON, RT3070_3), 239 USB_ID(PEGATRON, RT3072), 240 USB_ID(PHILIPS, RT2870), 241 USB_ID(PLANEX2, GWUS300MINIS), 242 USB_ID(PLANEX2, GWUSMICRO300), 243 USB_ID(PLANEX2, GWUSMICRON), 244 USB_ID(PLANEX2, GWUS300MINIX), 245 USB_ID(PLANEX2, RT3070), 246 USB_ID(QCOM, RT2870), 247 USB_ID(QUANTA, RT3070), 248 USB_ID(RALINK, RT2070), 249 USB_ID(RALINK, RT2770), 250 USB_ID(RALINK, RT2870), 251 USB_ID(RALINK, RT3070), 252 USB_ID(RALINK, RT3071), 253 USB_ID(RALINK, RT3072), 254 USB_ID(RALINK, RT3370), 255 USB_ID(RALINK, RT3572), 256 USB_ID(RALINK, RT5572), 257 USB_ID(RALINK, RT8070), 258 USB_ID(SAMSUNG, RT2870_1), 259 USB_ID(SENAO, RT2870_1), 260 USB_ID(SENAO, RT2870_2), 261 USB_ID(SENAO, RT2870_3), 262 USB_ID(SENAO, RT2870_4), 263 USB_ID(SENAO, RT3070), 264 USB_ID(SENAO, RT3071), 265 USB_ID(SENAO, RT3072), 266 USB_ID(SENAO, RT3072_2), 267 USB_ID(SENAO, RT3072_3), 268 USB_ID(SENAO, RT3072_4), 269 USB_ID(SENAO, RT3072_5), 270 USB_ID(SITECOMEU, RT2870_1), 271 USB_ID(SITECOMEU, RT2870_2), 272 USB_ID(SITECOMEU, RT2870_3), 273 USB_ID(SITECOMEU, RT3070_1), 274 USB_ID(SITECOMEU, RT3072_3), 275 USB_ID(SITECOMEU, RT3072_4), 276 USB_ID(SITECOMEU, RT3072_5), 277 USB_ID(SITECOMEU, WL302), 278 USB_ID(SITECOMEU, WL315), 279 USB_ID(SITECOMEU, WL321), 280 USB_ID(SITECOMEU, WL324), 281 USB_ID(SITECOMEU, WL329), 282 USB_ID(SITECOMEU, WL343), 283 USB_ID(SITECOMEU, WL344), 284 USB_ID(SITECOMEU, WL345), 285 USB_ID(SITECOMEU, WL349V4), 286 USB_ID(SITECOMEU, WL608), 287 USB_ID(SITECOMEU, WLA4000), 288 USB_ID(SITECOMEU, WLA5000), 289 USB_ID(SPARKLAN, RT2870_1), 290 USB_ID(SPARKLAN, RT2870_2), 291 USB_ID(SPARKLAN, RT3070), 292 USB_ID(SWEEX2, LW153), 293 USB_ID(SWEEX2, LW303), 294 USB_ID(SWEEX2, LW313), 295 USB_ID(TOSHIBA, RT3070), 296 USB_ID(UMEDIA, RT2870_1), 297 USB_ID(UMEDIA, TEW645UB), 298 USB_ID(ZCOM, RT2870_1), 299 USB_ID(ZCOM, RT2870_2), 300 USB_ID(ZINWELL, RT2870_1), 301 USB_ID(ZINWELL, RT2870_2), 302 USB_ID(ZINWELL, RT3070), 303 USB_ID(ZINWELL, RT3072), 304 USB_ID(ZINWELL, RT3072_2), 305 USB_ID(ZYXEL, NWD2105), 306 USB_ID(ZYXEL, NWD211AN), 307 USB_ID(ZYXEL, RT2870_1), 308 USB_ID(ZYXEL, RT2870_2), 309 USB_ID(ZYXEL, RT3070), 310 }; 311 312 static int run_match(device_t, cfdata_t, void *); 313 static void run_attach(device_t, device_t, void *); 314 static int run_detach(device_t, int); 315 static int run_activate(device_t, enum devact); 316 317 CFATTACH_DECL_NEW(run, sizeof(struct run_softc), 318 run_match, run_attach, run_detach, run_activate); 319 320 static int run_alloc_rx_ring(struct run_softc *); 321 static void run_free_rx_ring(struct run_softc *); 322 static int run_alloc_tx_ring(struct run_softc *, int); 323 static void run_free_tx_ring(struct run_softc *, int); 324 static int run_load_microcode(struct run_softc *); 325 static int run_reset(struct run_softc *); 326 static int run_read(struct run_softc *, uint16_t, uint32_t *); 327 static int run_read_region_1(struct run_softc *, uint16_t, 328 uint8_t *, int); 329 static int run_write_2(struct run_softc *, uint16_t, uint16_t); 330 static int run_write(struct run_softc *, uint16_t, uint32_t); 331 static int run_write_region_1(struct run_softc *, uint16_t, 332 const uint8_t *, int); 333 static int run_set_region_4(struct run_softc *, uint16_t, 334 uint32_t, int); 335 static int run_efuse_read(struct run_softc *, uint16_t, 336 uint16_t *, int); 337 static int run_efuse_read_2(struct run_softc *, uint16_t, 338 uint16_t *); 339 static int run_eeprom_read_2(struct run_softc *, uint16_t, 340 uint16_t *); 341 static int run_rt2870_rf_write(struct run_softc *, uint8_t, 342 uint32_t); 343 static int run_rt3070_rf_read(struct run_softc *, uint8_t, 344 uint8_t *); 345 static int run_rt3070_rf_write(struct run_softc *, uint8_t, 346 uint8_t); 347 static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 348 static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 349 static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 350 static const char * run_get_rf(int); 351 static void run_rt3593_get_txpower(struct run_softc *); 352 static void run_get_txpower(struct run_softc *); 353 static int run_read_eeprom(struct run_softc *); 354 static struct ieee80211_node * 355 run_node_alloc(struct ieee80211_node_table *); 356 static int run_media_change(struct ifnet *); 357 static void run_next_scan(void *); 358 static void run_task(void *); 359 static void run_do_async(struct run_softc *, 360 void (*)(struct run_softc *, void *), void *, int); 361 static int run_newstate(struct ieee80211com *, 362 enum ieee80211_state, int); 363 static void run_newstate_cb(struct run_softc *, void *); 364 static int run_updateedca(struct ieee80211com *); 365 static void run_updateedca_cb(struct run_softc *, void *); 366 #ifdef RUN_HWCRYPTO 367 static int run_set_key(struct ieee80211com *, 368 const struct ieee80211_key *, const uint8_t *); 369 static void run_set_key_cb(struct run_softc *, void *); 370 static int run_delete_key(struct ieee80211com *, 371 const struct ieee80211_key *); 372 static void run_delete_key_cb(struct run_softc *, void *); 373 #endif 374 static void run_calibrate_to(void *); 375 static void run_calibrate_cb(struct run_softc *, void *); 376 static void run_newassoc(struct ieee80211_node *, int); 377 static void run_rx_frame(struct run_softc *, uint8_t *, int); 378 static void run_rxeof(struct usbd_xfer *, void *, 379 usbd_status); 380 static void run_txeof(struct usbd_xfer *, void *, 381 usbd_status); 382 static int run_tx(struct run_softc *, struct mbuf *, 383 struct ieee80211_node *); 384 static void run_start(struct ifnet *); 385 static void run_watchdog(struct ifnet *); 386 static int run_ioctl(struct ifnet *, u_long, void *); 387 static void run_select_chan_group(struct run_softc *, int); 388 static void run_iq_calib(struct run_softc *, u_int); 389 static void run_set_agc(struct run_softc *, uint8_t); 390 static void run_set_rx_antenna(struct run_softc *, int); 391 static void run_rt2870_set_chan(struct run_softc *, u_int); 392 static void run_rt3070_set_chan(struct run_softc *, u_int); 393 static void run_rt3572_set_chan(struct run_softc *, u_int); 394 static void run_rt3593_set_chan(struct run_softc *, u_int); 395 static void run_rt5390_set_chan(struct run_softc *, u_int); 396 static void run_rt5592_set_chan(struct run_softc *, u_int); 397 static int run_set_chan(struct run_softc *, 398 struct ieee80211_channel *); 399 static void run_updateprot(struct run_softc *); 400 static void run_enable_tsf_sync(struct run_softc *); 401 static void run_enable_mrr(struct run_softc *); 402 static void run_set_txpreamble(struct run_softc *); 403 static void run_set_basicrates(struct run_softc *); 404 static void run_set_leds(struct run_softc *, uint16_t); 405 static void run_set_bssid(struct run_softc *, const uint8_t *); 406 static void run_set_macaddr(struct run_softc *, const uint8_t *); 407 static void run_updateslot(struct ifnet *); 408 static void run_updateslot_cb(struct run_softc *, void *); 409 static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 410 static void run_rt5390_bbp_init(struct run_softc *); 411 static int run_bbp_init(struct run_softc *); 412 static int run_rt3070_rf_init(struct run_softc *); 413 static int run_rt3593_rf_init(struct run_softc *); 414 static int run_rt5390_rf_init(struct run_softc *); 415 static int run_rt3070_filter_calib(struct run_softc *, uint8_t, 416 uint8_t, uint8_t *); 417 static void run_rt3070_rf_setup(struct run_softc *); 418 static void run_rt3593_rf_setup(struct run_softc *); 419 static void run_rt5390_rf_setup(struct run_softc *); 420 static int run_txrx_enable(struct run_softc *); 421 static int run_adjust_freq_offset(struct run_softc *); 422 static int run_init(struct ifnet *); 423 static void run_stop(struct ifnet *, int); 424 #ifndef IEEE80211_STA_ONLY 425 static int run_setup_beacon(struct run_softc *); 426 #endif 427 428 static const struct { 429 uint32_t reg; 430 uint32_t val; 431 } rt2870_def_mac[] = { 432 RT2870_DEF_MAC 433 }; 434 435 static const struct { 436 uint8_t reg; 437 uint8_t val; 438 } rt2860_def_bbp[] = { 439 RT2860_DEF_BBP 440 }, rt5390_def_bbp[] = { 441 RT5390_DEF_BBP 442 }, rt5592_def_bbp[] = { 443 RT5592_DEF_BBP 444 }; 445 446 /* 447 * Default values for BBP register R196 for RT5592. 448 */ 449 static const uint8_t rt5592_bbp_r196[] = { 450 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 451 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 452 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 453 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 454 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 455 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 456 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 457 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 458 0x2e, 0x36, 0x30, 0x6e 459 }; 460 461 static const struct rfprog { 462 uint8_t chan; 463 uint32_t r1, r2, r3, r4; 464 } rt2860_rf2850[] = { 465 RT2860_RF2850 466 }; 467 468 static const struct { 469 uint8_t n, r, k; 470 } rt3070_freqs[] = { 471 RT3070_RF3052 472 }; 473 474 static const struct rt5592_freqs { 475 uint16_t n; 476 uint8_t k, m, r; 477 } rt5592_freqs_20mhz[] = { 478 RT5592_RF5592_20MHZ 479 },rt5592_freqs_40mhz[] = { 480 RT5592_RF5592_40MHZ 481 }; 482 483 static const struct { 484 uint8_t reg; 485 uint8_t val; 486 } rt3070_def_rf[] = { 487 RT3070_DEF_RF 488 }, rt3572_def_rf[] = { 489 RT3572_DEF_RF 490 },rt3593_def_rf[] = { 491 RT3593_DEF_RF 492 },rt5390_def_rf[] = { 493 RT5390_DEF_RF 494 },rt5392_def_rf[] = { 495 RT5392_DEF_RF 496 },rt5592_def_rf[] = { 497 RT5592_DEF_RF 498 },rt5592_2ghz_def_rf[] = { 499 RT5592_2GHZ_DEF_RF 500 },rt5592_5ghz_def_rf[] = { 501 RT5592_5GHZ_DEF_RF 502 }; 503 504 static const struct { 505 u_int firstchan; 506 u_int lastchan; 507 uint8_t reg; 508 uint8_t val; 509 } rt5592_chan_5ghz[] = { 510 RT5592_CHAN_5GHZ 511 }; 512 513 static int 514 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 515 size_t *sizep) 516 { 517 firmware_handle_t fh; 518 int error; 519 520 if ((error = firmware_open(dname, iname, &fh)) != 0) 521 return error; 522 *sizep = firmware_get_size(fh); 523 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 524 firmware_close(fh); 525 return ENOMEM; 526 } 527 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 528 firmware_free(*ucodep, *sizep); 529 firmware_close(fh); 530 531 return error; 532 } 533 534 static int 535 run_match(device_t parent, cfdata_t match, void *aux) 536 { 537 struct usb_attach_arg *uaa = aux; 538 539 return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? 540 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 541 } 542 543 static void 544 run_attach(device_t parent, device_t self, void *aux) 545 { 546 struct run_softc *sc = device_private(self); 547 struct usb_attach_arg *uaa = aux; 548 struct ieee80211com *ic = &sc->sc_ic; 549 struct ifnet *ifp = &sc->sc_if; 550 usb_interface_descriptor_t *id; 551 usb_endpoint_descriptor_t *ed; 552 char *devinfop; 553 int i, nrx, ntx, ntries, error; 554 uint32_t ver; 555 556 aprint_naive("\n"); 557 aprint_normal("\n"); 558 559 sc->sc_dev = self; 560 sc->sc_udev = uaa->uaa_device; 561 562 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 563 aprint_normal_dev(sc->sc_dev, "%s\n", devinfop); 564 usbd_devinfo_free(devinfop); 565 566 error = usbd_set_config_no(sc->sc_udev, 1, 0); 567 if (error != 0) { 568 aprint_error_dev(sc->sc_dev, "failed to set configuration" 569 ", err=%s\n", usbd_errstr(error)); 570 return; 571 } 572 573 /* get the first interface handle */ 574 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 575 if (error != 0) { 576 aprint_error_dev(sc->sc_dev, 577 "could not get interface handle\n"); 578 return; 579 } 580 581 /* 582 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 583 * and 6 for TX (4 EDCAs + HCCA + Prio). 584 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 585 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 586 */ 587 nrx = ntx = 0; 588 id = usbd_get_interface_descriptor(sc->sc_iface); 589 for (i = 0; i < id->bNumEndpoints; i++) { 590 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 591 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 592 continue; 593 594 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 595 sc->rxq.pipe_no = ed->bEndpointAddress; 596 nrx++; 597 } else if (ntx < 4) { 598 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 599 ntx++; 600 } 601 } 602 /* make sure we've got them all */ 603 if (nrx < 1 || ntx < 4) { 604 aprint_error_dev(sc->sc_dev, "missing endpoint\n"); 605 return; 606 } 607 608 usb_init_task(&sc->sc_task, run_task, sc, 0); 609 callout_init(&sc->scan_to, 0); 610 callout_setfunc(&sc->scan_to, run_next_scan, sc); 611 callout_init(&sc->calib_to, 0); 612 callout_setfunc(&sc->calib_to, run_calibrate_to, sc); 613 614 sc->amrr.amrr_min_success_threshold = 1; 615 sc->amrr.amrr_max_success_threshold = 10; 616 617 /* wait for the chip to settle */ 618 for (ntries = 0; ntries < 100; ntries++) { 619 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 620 return; 621 if (ver != 0 && ver != 0xffffffff) 622 break; 623 DELAY(10); 624 } 625 if (ntries == 100) { 626 aprint_error_dev(sc->sc_dev, 627 "timeout waiting for NIC to initialize\n"); 628 return; 629 } 630 sc->mac_ver = ver >> 16; 631 sc->mac_rev = ver & 0xffff; 632 633 /* retrieve RF rev. no and various other things from EEPROM */ 634 run_read_eeprom(sc); 635 636 aprint_error_dev(sc->sc_dev, 637 "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n", 638 sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 639 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 640 641 ic->ic_ifp = ifp; 642 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 643 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 644 ic->ic_state = IEEE80211_S_INIT; 645 646 /* set device capabilities */ 647 ic->ic_caps = 648 IEEE80211_C_MONITOR | /* monitor mode supported */ 649 #ifndef IEEE80211_STA_ONLY 650 IEEE80211_C_IBSS | /* IBSS mode supported */ 651 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 652 #endif 653 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 654 IEEE80211_C_SHSLOT | /* short slot time supported */ 655 #ifdef RUN_HWCRYPTO 656 IEEE80211_C_WEP | /* WEP */ 657 IEEE80211_C_TKIP | /* TKIP */ 658 IEEE80211_C_AES_CCM | /* AES CCMP */ 659 IEEE80211_C_TKIPMIC | /* TKIPMIC */ 660 #endif 661 IEEE80211_C_WME | /* WME */ 662 IEEE80211_C_WPA; /* WPA/RSN */ 663 664 if (sc->rf_rev == RT2860_RF_2750 || 665 sc->rf_rev == RT2860_RF_2850 || 666 sc->rf_rev == RT3070_RF_3052 || 667 sc->rf_rev == RT3070_RF_3053 || 668 sc->rf_rev == RT5592_RF_5592) { 669 /* set supported .11a rates */ 670 ic->ic_sup_rates[IEEE80211_MODE_11A] = 671 ieee80211_std_rateset_11a; 672 673 /* set supported .11a channels */ 674 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 675 uint8_t chan = rt2860_rf2850[i].chan; 676 ic->ic_channels[chan].ic_freq = 677 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 678 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 679 } 680 } 681 682 /* set supported .11b and .11g rates */ 683 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 684 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 685 686 /* set supported .11b and .11g channels (1 through 14) */ 687 for (i = 1; i <= 14; i++) { 688 ic->ic_channels[i].ic_freq = 689 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 690 ic->ic_channels[i].ic_flags = 691 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 692 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 693 } 694 695 ifp->if_softc = sc; 696 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 697 ifp->if_init = run_init; 698 ifp->if_ioctl = run_ioctl; 699 ifp->if_start = run_start; 700 ifp->if_watchdog = run_watchdog; 701 IFQ_SET_READY(&ifp->if_snd); 702 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 703 704 if_attach(ifp); 705 ieee80211_ifattach(ic); 706 ic->ic_node_alloc = run_node_alloc; 707 ic->ic_newassoc = run_newassoc; 708 ic->ic_updateslot = run_updateslot; 709 ic->ic_wme.wme_update = run_updateedca; 710 #ifdef RUN_HWCRYPTO 711 ic->ic_crypto.cs_key_set = run_set_key; 712 ic->ic_crypto.cs_key_delete = run_delete_key; 713 #endif 714 /* override state transition machine */ 715 sc->sc_newstate = ic->ic_newstate; 716 ic->ic_newstate = run_newstate; 717 ieee80211_media_init(ic, run_media_change, ieee80211_media_status); 718 719 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 720 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 721 &sc->sc_drvbpf); 722 723 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 724 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 725 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 726 727 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 728 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 729 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 730 731 ieee80211_announce(ic); 732 733 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 734 735 if (!pmf_device_register(self, NULL, NULL)) 736 aprint_error_dev(self, "couldn't establish power handler\n"); 737 } 738 739 static int 740 run_detach(device_t self, int flags) 741 { 742 struct run_softc *sc = device_private(self); 743 struct ifnet *ifp = &sc->sc_if; 744 struct ieee80211com *ic = &sc->sc_ic; 745 int s; 746 747 if (ifp->if_softc == NULL) 748 return 0; 749 750 pmf_device_deregister(self); 751 752 s = splnet(); 753 754 sc->sc_flags |= RUN_DETACHING; 755 756 if (ifp->if_flags & IFF_RUNNING) { 757 usb_rem_task(sc->sc_udev, &sc->sc_task); 758 run_stop(ifp, 0); 759 } 760 761 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 762 bpf_detach(ifp); 763 ieee80211_ifdetach(ic); 764 if_detach(ifp); 765 766 splx(s); 767 768 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 769 770 callout_stop(&sc->scan_to); 771 callout_stop(&sc->calib_to); 772 773 callout_destroy(&sc->scan_to); 774 callout_destroy(&sc->calib_to); 775 776 return 0; 777 } 778 779 static int 780 run_activate(device_t self, enum devact act) 781 { 782 struct run_softc *sc = device_private(self); 783 784 switch (act) { 785 case DVACT_DEACTIVATE: 786 if_deactivate(sc->sc_ic.ic_ifp); 787 return 0; 788 default: 789 return EOPNOTSUPP; 790 } 791 } 792 793 static int 794 run_alloc_rx_ring(struct run_softc *sc) 795 { 796 struct run_rx_ring *rxq = &sc->rxq; 797 int i, error; 798 799 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 800 if (error != 0) 801 goto fail; 802 803 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 804 struct run_rx_data *data = &rxq->data[i]; 805 806 data->sc = sc; /* backpointer for callbacks */ 807 808 error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, 809 USBD_SHORT_XFER_OK, 0, &data->xfer); 810 if (error) 811 goto fail; 812 813 data->buf = usbd_get_buffer(data->xfer); 814 } 815 if (error != 0) 816 fail: run_free_rx_ring(sc); 817 return error; 818 } 819 820 static void 821 run_free_rx_ring(struct run_softc *sc) 822 { 823 struct run_rx_ring *rxq = &sc->rxq; 824 int i; 825 826 if (rxq->pipeh != NULL) { 827 usbd_abort_pipe(rxq->pipeh); 828 } 829 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 830 if (rxq->data[i].xfer != NULL) 831 usbd_destroy_xfer(rxq->data[i].xfer); 832 rxq->data[i].xfer = NULL; 833 } 834 if (rxq->pipeh != NULL) { 835 usbd_close_pipe(rxq->pipeh); 836 rxq->pipeh = NULL; 837 } 838 } 839 840 static int 841 run_alloc_tx_ring(struct run_softc *sc, int qid) 842 { 843 struct run_tx_ring *txq = &sc->txq[qid]; 844 int i, error; 845 846 txq->cur = txq->queued = 0; 847 848 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 849 if (error != 0) 850 goto fail; 851 852 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 853 struct run_tx_data *data = &txq->data[i]; 854 855 data->sc = sc; /* backpointer for callbacks */ 856 data->qid = qid; 857 858 error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, 859 USBD_FORCE_SHORT_XFER, 0, &data->xfer); 860 if (error) 861 goto fail; 862 863 data->buf = usbd_get_buffer(data->xfer); 864 /* zeroize the TXD + TXWI part */ 865 memset(data->buf, 0, sizeof(struct rt2870_txd) + 866 sizeof(struct rt2860_txwi)); 867 } 868 if (error != 0) 869 fail: run_free_tx_ring(sc, qid); 870 return error; 871 } 872 873 static void 874 run_free_tx_ring(struct run_softc *sc, int qid) 875 { 876 struct run_tx_ring *txq = &sc->txq[qid]; 877 int i; 878 879 if (txq->pipeh != NULL) { 880 usbd_abort_pipe(txq->pipeh); 881 usbd_close_pipe(txq->pipeh); 882 txq->pipeh = NULL; 883 } 884 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 885 if (txq->data[i].xfer != NULL) 886 usbd_destroy_xfer(txq->data[i].xfer); 887 txq->data[i].xfer = NULL; 888 } 889 } 890 891 static int 892 run_load_microcode(struct run_softc *sc) 893 { 894 usb_device_request_t req; 895 const char *fwname; 896 u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ 897 size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ 898 uint32_t tmp; 899 int ntries, error; 900 901 /* RT3071/RT3072 use a different firmware */ 902 if (sc->mac_ver != 0x2860 && 903 sc->mac_ver != 0x2872 && 904 sc->mac_ver != 0x3070) 905 fwname = "run-rt3071"; 906 else 907 fwname = "run-rt2870"; 908 909 if ((error = firmware_load("run", fwname, &ucode, &size)) != 0) { 910 aprint_error_dev(sc->sc_dev, 911 "error %d, could not read firmware %s\n", error, fwname); 912 return error; 913 } 914 if (size != 4096) { 915 aprint_error_dev(sc->sc_dev, 916 "invalid firmware size (should be 4KB)\n"); 917 firmware_free(ucode, size); 918 return EINVAL; 919 } 920 921 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 922 /* write microcode image */ 923 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 924 firmware_free(ucode, size); 925 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 926 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 927 928 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 929 req.bRequest = RT2870_RESET; 930 USETW(req.wValue, 8); 931 USETW(req.wIndex, 0); 932 USETW(req.wLength, 0); 933 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 934 return error; 935 936 usbd_delay_ms(sc->sc_udev, 10); 937 run_write(sc, RT2860_H2M_MAILBOX, 0); 938 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 939 return error; 940 941 /* wait until microcontroller is ready */ 942 for (ntries = 0; ntries < 1000; ntries++) { 943 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 944 return error; 945 if (tmp & RT2860_MCU_READY) 946 break; 947 usbd_delay_ms(sc->sc_udev, 10); 948 } 949 if (ntries == 1000) { 950 aprint_error_dev(sc->sc_dev, 951 "timeout waiting for MCU to initialize\n"); 952 return ETIMEDOUT; 953 } 954 955 sc->sc_flags |= RUN_FWLOADED; 956 957 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 958 return 0; 959 } 960 961 static int 962 run_reset(struct run_softc *sc) 963 { 964 usb_device_request_t req; 965 966 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 967 req.bRequest = RT2870_RESET; 968 USETW(req.wValue, 1); 969 USETW(req.wIndex, 0); 970 USETW(req.wLength, 0); 971 return usbd_do_request(sc->sc_udev, &req, NULL); 972 } 973 974 static int 975 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 976 { 977 uint32_t tmp; 978 int error; 979 980 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 981 if (error == 0) 982 *val = le32toh(tmp); 983 else 984 *val = 0xffffffff; 985 return error; 986 } 987 988 static int 989 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 990 { 991 usb_device_request_t req; 992 993 req.bmRequestType = UT_READ_VENDOR_DEVICE; 994 req.bRequest = RT2870_READ_REGION_1; 995 USETW(req.wValue, 0); 996 USETW(req.wIndex, reg); 997 USETW(req.wLength, len); 998 return usbd_do_request(sc->sc_udev, &req, buf); 999 } 1000 1001 static int 1002 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 1003 { 1004 usb_device_request_t req; 1005 1006 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1007 req.bRequest = RT2870_WRITE_2; 1008 USETW(req.wValue, val); 1009 USETW(req.wIndex, reg); 1010 USETW(req.wLength, 0); 1011 return usbd_do_request(sc->sc_udev, &req, NULL); 1012 } 1013 1014 static int 1015 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 1016 { 1017 int error; 1018 1019 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 1020 error = run_write_2(sc, reg + 2, val >> 16); 1021 return error; 1022 } 1023 1024 static int 1025 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 1026 int len) 1027 { 1028 #if 1 1029 int i, error = 0; 1030 /* 1031 * NB: the WRITE_REGION_1 command is not stable on RT2860. 1032 * We thus issue multiple WRITE_2 commands instead. 1033 */ 1034 KASSERT((len & 1) == 0); 1035 for (i = 0; i < len && error == 0; i += 2) 1036 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 1037 return error; 1038 #else 1039 usb_device_request_t req; 1040 1041 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1042 req.bRequest = RT2870_WRITE_REGION_1; 1043 USETW(req.wValue, 0); 1044 USETW(req.wIndex, reg); 1045 USETW(req.wLength, len); 1046 return usbd_do_request(sc->sc_udev, &req, buf); 1047 #endif 1048 } 1049 1050 static int 1051 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 1052 { 1053 int error = 0; 1054 1055 for (; count > 0 && error == 0; count--, reg += 4) 1056 error = run_write(sc, reg, val); 1057 return error; 1058 } 1059 1060 static int 1061 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) 1062 { 1063 uint32_t tmp; 1064 uint16_t reg; 1065 int error, ntries; 1066 1067 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1068 return error; 1069 1070 if (count == 2) 1071 addr *= 2; 1072 /*- 1073 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1074 * DATA0: F E D C 1075 * DATA1: B A 9 8 1076 * DATA2: 7 6 5 4 1077 * DATA3: 3 2 1 0 1078 */ 1079 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1080 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1081 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1082 for (ntries = 0; ntries < 100; ntries++) { 1083 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1084 return error; 1085 if (!(tmp & RT3070_EFSROM_KICK)) 1086 break; 1087 usbd_delay_ms(sc->sc_udev, 2); 1088 } 1089 if (ntries == 100) 1090 return ETIMEDOUT; 1091 1092 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1093 *val = 0xffff; /* address not found */ 1094 return 0; 1095 } 1096 /* determine to which 32-bit register our 16-bit word belongs */ 1097 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1098 if ((error = run_read(sc, reg, &tmp)) != 0) 1099 return error; 1100 1101 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1102 return 0; 1103 } 1104 1105 /* Read 16-bit from eFUSE ROM for RT3xxxx. */ 1106 static int 1107 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1108 { 1109 return (run_efuse_read(sc, addr, val, 2)); 1110 } 1111 1112 static int 1113 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1114 { 1115 usb_device_request_t req; 1116 uint16_t tmp; 1117 int error; 1118 1119 addr *= 2; 1120 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1121 req.bRequest = RT2870_EEPROM_READ; 1122 USETW(req.wValue, 0); 1123 USETW(req.wIndex, addr); 1124 USETW(req.wLength, sizeof(tmp)); 1125 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1126 if (error == 0) 1127 *val = le16toh(tmp); 1128 else 1129 *val = 0xffff; 1130 return error; 1131 } 1132 1133 static __inline int 1134 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1135 { 1136 1137 /* either eFUSE ROM or EEPROM */ 1138 return sc->sc_srom_read(sc, addr, val); 1139 } 1140 1141 static int 1142 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1143 { 1144 uint32_t tmp; 1145 int error, ntries; 1146 1147 for (ntries = 0; ntries < 10; ntries++) { 1148 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1149 return error; 1150 if (!(tmp & RT2860_RF_REG_CTRL)) 1151 break; 1152 } 1153 if (ntries == 10) 1154 return ETIMEDOUT; 1155 1156 /* RF registers are 24-bit on the RT2860 */ 1157 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1158 (val & 0x3fffff) << 2 | (reg & 3); 1159 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1160 } 1161 1162 static int 1163 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1164 { 1165 uint32_t tmp; 1166 int error, ntries; 1167 1168 for (ntries = 0; ntries < 100; ntries++) { 1169 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1170 return error; 1171 if (!(tmp & RT3070_RF_KICK)) 1172 break; 1173 } 1174 if (ntries == 100) 1175 return ETIMEDOUT; 1176 1177 tmp = RT3070_RF_KICK | reg << 8; 1178 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1179 return error; 1180 1181 for (ntries = 0; ntries < 100; ntries++) { 1182 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1183 return error; 1184 if (!(tmp & RT3070_RF_KICK)) 1185 break; 1186 } 1187 if (ntries == 100) 1188 return ETIMEDOUT; 1189 1190 *val = tmp & 0xff; 1191 return 0; 1192 } 1193 1194 static int 1195 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1196 { 1197 uint32_t tmp; 1198 int error, ntries; 1199 1200 for (ntries = 0; ntries < 10; ntries++) { 1201 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1202 return error; 1203 if (!(tmp & RT3070_RF_KICK)) 1204 break; 1205 } 1206 if (ntries == 10) 1207 return ETIMEDOUT; 1208 1209 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1210 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1211 } 1212 1213 static int 1214 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1215 { 1216 uint32_t tmp; 1217 int ntries, error; 1218 1219 for (ntries = 0; ntries < 10; ntries++) { 1220 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1221 return error; 1222 if (!(tmp & RT2860_BBP_CSR_KICK)) 1223 break; 1224 } 1225 if (ntries == 10) 1226 return ETIMEDOUT; 1227 1228 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1229 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1230 return error; 1231 1232 for (ntries = 0; ntries < 10; ntries++) { 1233 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1234 return error; 1235 if (!(tmp & RT2860_BBP_CSR_KICK)) 1236 break; 1237 } 1238 if (ntries == 10) 1239 return ETIMEDOUT; 1240 1241 *val = tmp & 0xff; 1242 return 0; 1243 } 1244 1245 static int 1246 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1247 { 1248 uint32_t tmp; 1249 int ntries, error; 1250 1251 for (ntries = 0; ntries < 10; ntries++) { 1252 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1253 return error; 1254 if (!(tmp & RT2860_BBP_CSR_KICK)) 1255 break; 1256 } 1257 if (ntries == 10) 1258 return ETIMEDOUT; 1259 1260 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1261 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1262 } 1263 1264 /* 1265 * Send a command to the 8051 microcontroller unit. 1266 */ 1267 static int 1268 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1269 { 1270 uint32_t tmp; 1271 int error, ntries; 1272 1273 for (ntries = 0; ntries < 100; ntries++) { 1274 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1275 return error; 1276 if (!(tmp & RT2860_H2M_BUSY)) 1277 break; 1278 } 1279 if (ntries == 100) 1280 return ETIMEDOUT; 1281 1282 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1283 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1284 error = run_write(sc, RT2860_HOST_CMD, cmd); 1285 return error; 1286 } 1287 1288 /* 1289 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1290 * Used to adjust per-rate Tx power registers. 1291 */ 1292 static __inline uint32_t 1293 b4inc(uint32_t b32, int8_t delta) 1294 { 1295 int8_t i, b4; 1296 1297 for (i = 0; i < 8; i++) { 1298 b4 = b32 & 0xf; 1299 b4 += delta; 1300 if (b4 < 0) 1301 b4 = 0; 1302 else if (b4 > 0xf) 1303 b4 = 0xf; 1304 b32 = b32 >> 4 | b4 << 28; 1305 } 1306 return b32; 1307 } 1308 1309 static const char * 1310 run_get_rf(int rev) 1311 { 1312 switch (rev) { 1313 case RT2860_RF_2820: return "RT2820"; 1314 case RT2860_RF_2850: return "RT2850"; 1315 case RT2860_RF_2720: return "RT2720"; 1316 case RT2860_RF_2750: return "RT2750"; 1317 case RT3070_RF_3020: return "RT3020"; 1318 case RT3070_RF_2020: return "RT2020"; 1319 case RT3070_RF_3021: return "RT3021"; 1320 case RT3070_RF_3022: return "RT3022"; 1321 case RT3070_RF_3052: return "RT3052"; 1322 case RT3070_RF_3053: return "RT3053"; 1323 case RT5592_RF_5592: return "RT5592"; 1324 case RT5390_RF_5370: return "RT5370"; 1325 case RT5390_RF_5372: return "RT5372"; 1326 } 1327 return "unknown"; 1328 } 1329 1330 static void 1331 run_rt3593_get_txpower(struct run_softc *sc) 1332 { 1333 uint16_t addr, val; 1334 int i; 1335 1336 /* Read power settings for 2GHz channels. */ 1337 for (i = 0; i < 14; i += 2) { 1338 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1339 RT2860_EEPROM_PWR2GHZ_BASE1; 1340 run_srom_read(sc, addr + i / 2, &val); 1341 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1342 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1343 1344 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1345 RT2860_EEPROM_PWR2GHZ_BASE2; 1346 run_srom_read(sc, addr + i / 2, &val); 1347 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1348 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1349 1350 if (sc->ntxchains == 3) { 1351 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1352 &val); 1353 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1354 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1355 } 1356 } 1357 /* Fix broken Tx power entries. */ 1358 for (i = 0; i < 14; i++) { 1359 if (sc->txpow1[i] > 31) 1360 sc->txpow1[i] = 5; 1361 if (sc->txpow2[i] > 31) 1362 sc->txpow2[i] = 5; 1363 if (sc->ntxchains == 3) { 1364 if (sc->txpow3[i] > 31) 1365 sc->txpow3[i] = 5; 1366 } 1367 } 1368 /* Read power settings for 5GHz channels. */ 1369 for (i = 0; i < 40; i += 2) { 1370 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1371 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1372 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1373 1374 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1375 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1376 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1377 1378 if (sc->ntxchains == 3) { 1379 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1380 &val); 1381 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1382 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1383 } 1384 } 1385 } 1386 1387 static void 1388 run_get_txpower(struct run_softc *sc) 1389 { 1390 uint16_t val; 1391 int i; 1392 1393 /* Read power settings for 2GHz channels. */ 1394 for (i = 0; i < 14; i += 2) { 1395 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1396 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1397 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1398 1399 if (sc->mac_ver != 0x5390) { 1400 run_srom_read(sc, 1401 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1402 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1403 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1404 } 1405 } 1406 /* Fix broken Tx power entries. */ 1407 for (i = 0; i < 14; i++) { 1408 if (sc->mac_ver >= 0x5390) { 1409 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) 1410 sc->txpow1[i] = 5; 1411 } else { 1412 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1413 sc->txpow1[i] = 5; 1414 } 1415 if (sc->mac_ver > 0x5390) { 1416 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) 1417 sc->txpow2[i] = 5; 1418 } else if (sc->mac_ver < 0x5390) { 1419 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1420 sc->txpow2[i] = 5; 1421 } 1422 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1423 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1424 } 1425 /* Read power settings for 5GHz channels. */ 1426 for (i = 0; i < 40; i += 2) { 1427 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1428 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1429 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1430 1431 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1432 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1433 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1434 } 1435 /* Fix broken Tx power entries. */ 1436 for (i = 0; i < 40; i++ ) { 1437 if (sc->mac_ver != 0x5592) { 1438 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1439 sc->txpow1[14 + i] = 5; 1440 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1441 sc->txpow2[14 + i] = 5; 1442 } 1443 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1444 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1445 sc->txpow2[14 + i])); 1446 } 1447 } 1448 1449 static int 1450 run_read_eeprom(struct run_softc *sc) 1451 { 1452 struct ieee80211com *ic = &sc->sc_ic; 1453 int8_t delta_2ghz, delta_5ghz; 1454 uint32_t tmp; 1455 uint16_t val; 1456 int ridx, ant, i; 1457 1458 /* check whether the ROM is eFUSE ROM or EEPROM */ 1459 sc->sc_srom_read = run_eeprom_read_2; 1460 if (sc->mac_ver >= 0x3070) { 1461 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1462 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1463 if (tmp & RT3070_SEL_EFUSE) 1464 sc->sc_srom_read = run_efuse_read_2; 1465 } 1466 1467 /* read ROM version */ 1468 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1469 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1470 1471 /* read MAC address */ 1472 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1473 ic->ic_myaddr[0] = val & 0xff; 1474 ic->ic_myaddr[1] = val >> 8; 1475 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1476 ic->ic_myaddr[2] = val & 0xff; 1477 ic->ic_myaddr[3] = val >> 8; 1478 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1479 ic->ic_myaddr[4] = val & 0xff; 1480 ic->ic_myaddr[5] = val >> 8; 1481 1482 /* read vendor BBP settings */ 1483 for (i = 0; i < 10; i++) { 1484 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1485 sc->bbp[i].val = val & 0xff; 1486 sc->bbp[i].reg = val >> 8; 1487 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 1488 } 1489 1490 /* read vendor RF settings */ 1491 for (i = 0; i < 8; i++) { 1492 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, &val); 1493 sc->rf[i].val = val & 0xff; 1494 sc->rf[i].reg = val >> 8; 1495 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1496 sc->rf[i].val)); 1497 } 1498 1499 /* read RF frequency offset from EEPROM */ 1500 run_srom_read(sc, RT2860_EEPROM_FREQ_LEDS, &val); 1501 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1502 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1503 1504 if ((val >> 8) != 0xff) { 1505 /* read LEDs operating mode */ 1506 sc->leds = val >> 8; 1507 run_srom_read(sc, RT2860_EEPROM_LED1, &sc->led[0]); 1508 run_srom_read(sc, RT2860_EEPROM_LED2, &sc->led[1]); 1509 run_srom_read(sc, RT2860_EEPROM_LED3, &sc->led[2]); 1510 } else { 1511 /* broken EEPROM, use default settings */ 1512 sc->leds = 0x01; 1513 sc->led[0] = 0x5555; 1514 sc->led[1] = 0x2221; 1515 sc->led[2] = 0x5627; /* differs from RT2860 */ 1516 } 1517 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1518 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1519 1520 /* read RF information */ 1521 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1522 if (val == 0xffff) { 1523 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1524 if (sc->mac_ver == 0x3572) { 1525 /* default to RF3052 2T2R */ 1526 sc->rf_rev = RT3070_RF_3052; 1527 sc->ntxchains = 2; 1528 sc->nrxchains = 2; 1529 } else if (sc->mac_ver >= 0x3070) { 1530 /* default to RF3020 1T1R */ 1531 sc->rf_rev = RT3070_RF_3020; 1532 sc->ntxchains = 1; 1533 sc->nrxchains = 1; 1534 } else { 1535 /* default to RF2820 1T2R */ 1536 sc->rf_rev = RT2860_RF_2820; 1537 sc->ntxchains = 1; 1538 sc->nrxchains = 2; 1539 } 1540 } else { 1541 sc->rf_rev = (val >> 8) & 0xf; 1542 sc->ntxchains = (val >> 4) & 0xf; 1543 sc->nrxchains = val & 0xf; 1544 } 1545 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1546 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1547 1548 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1549 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1550 /* check if driver should patch the DAC issue */ 1551 if ((val >> 8) != 0xff) 1552 sc->patch_dac = (val >> 15) & 1; 1553 if ((val & 0xff) != 0xff) { 1554 sc->ext_5ghz_lna = (val >> 3) & 1; 1555 sc->ext_2ghz_lna = (val >> 2) & 1; 1556 /* check if RF supports automatic Tx access gain control */ 1557 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1558 /* check if we have a hardware radio switch */ 1559 sc->rfswitch = val & 1; 1560 } 1561 1562 /* Read Tx power settings. */ 1563 if (sc->mac_ver == 0x3593) 1564 run_rt3593_get_txpower(sc); 1565 else 1566 run_get_txpower(sc); 1567 1568 /* read Tx power compensation for each Tx rate */ 1569 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1570 delta_2ghz = delta_5ghz = 0; 1571 if ((val & 0xff) != 0xff && (val & 0x80)) { 1572 delta_2ghz = val & 0xf; 1573 if (!(val & 0x40)) /* negative number */ 1574 delta_2ghz = -delta_2ghz; 1575 } 1576 val >>= 8; 1577 if ((val & 0xff) != 0xff && (val & 0x80)) { 1578 delta_5ghz = val & 0xf; 1579 if (!(val & 0x40)) /* negative number */ 1580 delta_5ghz = -delta_5ghz; 1581 } 1582 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1583 delta_2ghz, delta_5ghz)); 1584 1585 for (ridx = 0; ridx < 5; ridx++) { 1586 uint32_t reg; 1587 1588 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1589 reg = val; 1590 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1591 reg |= (uint32_t)val << 16; 1592 1593 sc->txpow20mhz[ridx] = reg; 1594 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1595 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1596 1597 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1598 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1599 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1600 } 1601 1602 /* read RSSI offsets and LNA gains from EEPROM */ 1603 run_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ, &val); 1604 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1605 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1606 run_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ, &val); 1607 if (sc->mac_ver >= 0x3070) { 1608 if (sc->mac_ver == 0x3593) { 1609 sc->txmixgain_2ghz = 0; 1610 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1611 } else { 1612 /* 1613 * On RT3070 chips (limited to 2 Rx chains), this ROM 1614 * field contains the Tx mixer gain for the 2GHz band. 1615 */ 1616 if ((val & 0xff) != 0xff) 1617 sc->txmixgain_2ghz = val & 0x7; 1618 } 1619 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1620 } else { 1621 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1622 } 1623 if (sc->mac_ver == 0x3593) 1624 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1625 sc->lna[2] = val >> 8; /* channel group 2 */ 1626 1627 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1628 RT3593_EEPROM_RSSI2_5GHZ, &val); 1629 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1630 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1631 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1632 RT3593_EEPROM_RSSI2_5GHZ, &val); 1633 if (sc->mac_ver == 0x3572) { 1634 /* 1635 * On RT3572 chips (limited to 2 Rx chains), this ROM 1636 * field contains the Tx mixer gain for the 5GHz band. 1637 */ 1638 if ((val & 0xff) != 0xff) 1639 sc->txmixgain_5ghz = val & 0x7; 1640 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1641 } else { 1642 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1643 } 1644 if (sc->mac_ver == 0x3593) { 1645 sc->txmixgain_5ghz = 0; 1646 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1647 } 1648 sc->lna[3] = val >> 8; /* channel group 3 */ 1649 1650 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1651 RT3593_EEPROM_LNA, &val); 1652 sc->lna[0] = val & 0xff; /* channel group 0 */ 1653 sc->lna[1] = val >> 8; /* channel group 1 */ 1654 1655 /* fix broken 5GHz LNA entries */ 1656 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1657 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1658 sc->lna[2] = sc->lna[1]; 1659 } 1660 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1661 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1662 sc->lna[3] = sc->lna[1]; 1663 } 1664 1665 /* fix broken RSSI offset entries */ 1666 for (ant = 0; ant < 3; ant++) { 1667 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1668 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1669 ant + 1, sc->rssi_2ghz[ant])); 1670 sc->rssi_2ghz[ant] = 0; 1671 } 1672 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1673 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1674 ant + 1, sc->rssi_5ghz[ant])); 1675 sc->rssi_5ghz[ant] = 0; 1676 } 1677 } 1678 return 0; 1679 } 1680 1681 static struct ieee80211_node * 1682 run_node_alloc(struct ieee80211_node_table *nt) 1683 { 1684 struct run_node *rn = 1685 malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1686 return rn ? &rn->ni : NULL; 1687 } 1688 1689 static int 1690 run_media_change(struct ifnet *ifp) 1691 { 1692 struct run_softc *sc = ifp->if_softc; 1693 struct ieee80211com *ic = &sc->sc_ic; 1694 uint8_t rate, ridx; 1695 int error; 1696 1697 error = ieee80211_media_change(ifp); 1698 if (error != ENETRESET) 1699 return error; 1700 1701 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1702 rate = ic->ic_sup_rates[ic->ic_curmode]. 1703 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1704 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1705 if (rt2860_rates[ridx].rate == rate) 1706 break; 1707 sc->fixed_ridx = ridx; 1708 } 1709 1710 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1711 run_init(ifp); 1712 1713 return 0; 1714 } 1715 1716 static void 1717 run_next_scan(void *arg) 1718 { 1719 struct run_softc *sc = arg; 1720 1721 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1722 ieee80211_next_scan(&sc->sc_ic); 1723 } 1724 1725 static void 1726 run_task(void *arg) 1727 { 1728 struct run_softc *sc = arg; 1729 struct run_host_cmd_ring *ring = &sc->cmdq; 1730 struct run_host_cmd *cmd; 1731 int s; 1732 1733 /* process host commands */ 1734 s = splusb(); 1735 while (ring->next != ring->cur) { 1736 cmd = &ring->cmd[ring->next]; 1737 splx(s); 1738 /* callback */ 1739 cmd->cb(sc, cmd->data); 1740 s = splusb(); 1741 ring->queued--; 1742 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1743 } 1744 wakeup(ring); 1745 splx(s); 1746 } 1747 1748 static void 1749 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1750 void *arg, int len) 1751 { 1752 struct run_host_cmd_ring *ring = &sc->cmdq; 1753 struct run_host_cmd *cmd; 1754 int s; 1755 1756 if (sc->sc_flags & RUN_DETACHING) 1757 return; 1758 1759 s = splusb(); 1760 cmd = &ring->cmd[ring->cur]; 1761 cmd->cb = cb; 1762 KASSERT(len <= sizeof(cmd->data)); 1763 memcpy(cmd->data, arg, len); 1764 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1765 1766 /* if there is no pending command already, schedule a task */ 1767 if (++ring->queued == 1) 1768 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1769 splx(s); 1770 } 1771 1772 static int 1773 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1774 { 1775 struct run_softc *sc = ic->ic_ifp->if_softc; 1776 struct run_cmd_newstate cmd; 1777 1778 callout_stop(&sc->scan_to); 1779 callout_stop(&sc->calib_to); 1780 1781 /* do it in a process context */ 1782 cmd.state = nstate; 1783 cmd.arg = arg; 1784 run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); 1785 return 0; 1786 } 1787 1788 static void 1789 run_newstate_cb(struct run_softc *sc, void *arg) 1790 { 1791 struct run_cmd_newstate *cmd = arg; 1792 struct ifnet *ifp = &sc->sc_if; 1793 struct ieee80211com *ic = &sc->sc_ic; 1794 enum ieee80211_state ostate; 1795 struct ieee80211_node *ni; 1796 uint32_t tmp, sta[3]; 1797 uint8_t wcid; 1798 int s; 1799 1800 s = splnet(); 1801 ostate = ic->ic_state; 1802 1803 if (ostate == IEEE80211_S_RUN) { 1804 /* turn link LED off */ 1805 run_set_leds(sc, RT2860_LED_RADIO); 1806 } 1807 1808 switch (cmd->state) { 1809 case IEEE80211_S_INIT: 1810 if (ostate == IEEE80211_S_RUN) { 1811 /* abort TSF synchronization */ 1812 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1813 run_write(sc, RT2860_BCN_TIME_CFG, 1814 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1815 RT2860_TBTT_TIMER_EN)); 1816 } 1817 break; 1818 1819 case IEEE80211_S_SCAN: 1820 run_set_chan(sc, ic->ic_curchan); 1821 callout_schedule(&sc->scan_to, hz / 5); 1822 break; 1823 1824 case IEEE80211_S_AUTH: 1825 case IEEE80211_S_ASSOC: 1826 run_set_chan(sc, ic->ic_curchan); 1827 break; 1828 1829 case IEEE80211_S_RUN: 1830 run_set_chan(sc, ic->ic_curchan); 1831 1832 ni = ic->ic_bss; 1833 1834 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1835 run_updateslot(ifp); 1836 run_enable_mrr(sc); 1837 run_set_txpreamble(sc); 1838 run_set_basicrates(sc); 1839 run_set_bssid(sc, ni->ni_bssid); 1840 } 1841 #ifndef IEEE80211_STA_ONLY 1842 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1843 ic->ic_opmode == IEEE80211_M_IBSS) 1844 (void)run_setup_beacon(sc); 1845 #endif 1846 if (ic->ic_opmode == IEEE80211_M_STA) { 1847 /* add BSS entry to the WCID table */ 1848 wcid = RUN_AID2WCID(ni->ni_associd); 1849 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1850 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1851 1852 /* fake a join to init the tx rate */ 1853 run_newassoc(ni, 1); 1854 } 1855 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1856 run_enable_tsf_sync(sc); 1857 1858 /* clear statistic registers used by AMRR */ 1859 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1860 (uint8_t *)sta, sizeof(sta)); 1861 /* start calibration timer */ 1862 callout_schedule(&sc->calib_to, hz); 1863 } 1864 1865 /* turn link LED on */ 1866 run_set_leds(sc, RT2860_LED_RADIO | 1867 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1868 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1869 break; 1870 } 1871 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1872 splx(s); 1873 } 1874 1875 static int 1876 run_updateedca(struct ieee80211com *ic) 1877 { 1878 1879 /* do it in a process context */ 1880 run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); 1881 return 0; 1882 } 1883 1884 /* ARGSUSED */ 1885 static void 1886 run_updateedca_cb(struct run_softc *sc, void *arg) 1887 { 1888 struct ieee80211com *ic = &sc->sc_ic; 1889 int s, aci; 1890 1891 s = splnet(); 1892 /* update MAC TX configuration registers */ 1893 for (aci = 0; aci < WME_NUM_AC; aci++) { 1894 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1895 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 1896 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 1897 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 1898 ic->ic_wme.wme_params[aci].wmep_txopLimit); 1899 } 1900 1901 /* update SCH/DMA registers too */ 1902 run_write(sc, RT2860_WMM_AIFSN_CFG, 1903 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 1904 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 1905 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 1906 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 1907 run_write(sc, RT2860_WMM_CWMIN_CFG, 1908 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 1909 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 1910 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 1911 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 1912 run_write(sc, RT2860_WMM_CWMAX_CFG, 1913 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 1914 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 1915 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 1916 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 1917 run_write(sc, RT2860_WMM_TXOP0_CFG, 1918 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 1919 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 1920 run_write(sc, RT2860_WMM_TXOP1_CFG, 1921 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 1922 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 1923 splx(s); 1924 } 1925 1926 #ifdef RUN_HWCRYPTO 1927 static int 1928 run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, 1929 const uint8_t *mac) 1930 { 1931 struct run_softc *sc = ic->ic_ifp->if_softc; 1932 struct ieee80211_node *ni = ic->ic_bss; 1933 struct run_cmd_key cmd; 1934 1935 /* do it in a process context */ 1936 cmd.key = *k; 1937 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1938 run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); 1939 return 1; 1940 } 1941 1942 static void 1943 run_set_key_cb(struct run_softc *sc, void *arg) 1944 { 1945 #ifndef IEEE80211_STA_ONLY 1946 struct ieee80211com *ic = &sc->sc_ic; 1947 #endif 1948 struct run_cmd_key *cmd = arg; 1949 struct ieee80211_key *k = &cmd->key; 1950 uint32_t attr; 1951 uint16_t base; 1952 uint8_t mode, wcid, iv[8]; 1953 1954 /* map net80211 cipher to RT2860 security mode */ 1955 switch (k->wk_cipher->ic_cipher) { 1956 case IEEE80211_CIPHER_WEP: 1957 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 1958 if (k->wk_keylen == 5) 1959 mode = RT2860_MODE_WEP40; 1960 else 1961 mode = RT2860_MODE_WEP104; 1962 break; 1963 case IEEE80211_CIPHER_TKIP: 1964 mode = RT2860_MODE_TKIP; 1965 break; 1966 case IEEE80211_CIPHER_AES_CCM: 1967 mode = RT2860_MODE_AES_CCMP; 1968 break; 1969 default: 1970 return; 1971 } 1972 1973 if (k->wk_flags & IEEE80211_KEY_GROUP) { 1974 wcid = 0; /* NB: update WCID0 for group keys */ 1975 base = RT2860_SKEY(0, k->wk_keyix); 1976 } else { 1977 wcid = RUN_AID2WCID(cmd->associd); 1978 base = RT2860_PKEY(wcid); 1979 } 1980 1981 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 1982 run_write_region_1(sc, base, k->wk_key, 16); 1983 #ifndef IEEE80211_STA_ONLY 1984 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1985 run_write_region_1(sc, base + 16, &k->wk_key[16], 8); 1986 run_write_region_1(sc, base + 24, &k->wk_key[24], 8); 1987 } else 1988 #endif 1989 { 1990 run_write_region_1(sc, base + 16, &k->wk_key[24], 8); 1991 run_write_region_1(sc, base + 24, &k->wk_key[16], 8); 1992 } 1993 } else { 1994 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 1995 run_write_region_1(sc, base, k->wk_key, 1996 (k->wk_keylen + 1) & ~1); 1997 } 1998 1999 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 2000 (k->wk_flags & IEEE80211_KEY_XMIT)) { 2001 /* set initial packet number in IV+EIV */ 2002 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 2003 memset(iv, 0, sizeof(iv)); 2004 iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; 2005 } else { 2006 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2007 iv[0] = k->wk_keytsc >> 8; 2008 iv[1] = (iv[0] | 0x20) & 0x7f; 2009 iv[2] = k->wk_keytsc; 2010 } else /* CCMP */ { 2011 iv[0] = k->wk_keytsc; 2012 iv[1] = k->wk_keytsc >> 8; 2013 iv[2] = 0; 2014 } 2015 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 2016 iv[4] = k->wk_keytsc >> 16; 2017 iv[5] = k->wk_keytsc >> 24; 2018 iv[6] = k->wk_keytsc >> 32; 2019 iv[7] = k->wk_keytsc >> 40; 2020 } 2021 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2022 } 2023 2024 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2025 /* install group key */ 2026 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2027 attr &= ~(0xf << (k->wk_keyix * 4)); 2028 attr |= mode << (k->wk_keyix * 4); 2029 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2030 } else { 2031 /* install pairwise key */ 2032 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2033 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2034 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2035 } 2036 } 2037 2038 static int 2039 run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 2040 { 2041 struct run_softc *sc = ic->ic_ifp->if_softc; 2042 struct ieee80211_node *ni = ic->ic_bss; 2043 struct run_cmd_key cmd; 2044 2045 /* do it in a process context */ 2046 cmd.key = *k; 2047 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2048 run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); 2049 return 1; 2050 } 2051 2052 static void 2053 run_delete_key_cb(struct run_softc *sc, void *arg) 2054 { 2055 struct run_cmd_key *cmd = arg; 2056 struct ieee80211_key *k = &cmd->key; 2057 uint32_t attr; 2058 uint8_t wcid; 2059 2060 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 2061 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2062 2063 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2064 /* remove group key */ 2065 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2066 attr &= ~(0xf << (k->wk_keyix * 4)); 2067 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2068 2069 } else { 2070 /* remove pairwise key */ 2071 wcid = RUN_AID2WCID(cmd->associd); 2072 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2073 attr &= ~0xf; 2074 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2075 } 2076 } 2077 #endif 2078 2079 static void 2080 run_calibrate_to(void *arg) 2081 { 2082 2083 /* do it in a process context */ 2084 run_do_async(arg, run_calibrate_cb, NULL, 0); 2085 /* next timeout will be rescheduled in the calibration task */ 2086 } 2087 2088 /* ARGSUSED */ 2089 static void 2090 run_calibrate_cb(struct run_softc *sc, void *arg) 2091 { 2092 struct ifnet *ifp = &sc->sc_if; 2093 uint32_t sta[3]; 2094 int s, error; 2095 2096 /* read statistic counters (clear on read) and update AMRR state */ 2097 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2098 sizeof(sta)); 2099 if (error != 0) 2100 goto skip; 2101 2102 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2103 le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, 2104 le32toh(sta[0]) & 0xffff)); 2105 2106 s = splnet(); 2107 /* count failed TX as errors */ 2108 ifp->if_oerrors += le32toh(sta[0]) & 0xffff; 2109 2110 sc->amn.amn_retrycnt = 2111 (le32toh(sta[0]) & 0xffff) + /* failed TX count */ 2112 (le32toh(sta[1]) >> 16); /* TX retransmission count */ 2113 2114 sc->amn.amn_txcnt = 2115 sc->amn.amn_retrycnt + 2116 (le32toh(sta[1]) & 0xffff); /* successful TX count */ 2117 2118 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2119 splx(s); 2120 2121 skip: callout_schedule(&sc->calib_to, hz); 2122 } 2123 2124 static void 2125 run_newassoc(struct ieee80211_node *ni, int isnew) 2126 { 2127 struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; 2128 struct run_node *rn = (void *)ni; 2129 struct ieee80211_rateset *rs = &ni->ni_rates; 2130 uint8_t rate; 2131 int ridx, i, j; 2132 2133 DPRINTF(("new assoc isnew=%d addr=%s\n", 2134 isnew, ether_sprintf(ni->ni_macaddr))); 2135 2136 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2137 /* start at lowest available bit-rate, AMRR will raise */ 2138 ni->ni_txrate = 0; 2139 2140 for (i = 0; i < rs->rs_nrates; i++) { 2141 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2142 /* convert 802.11 rate to hardware rate index */ 2143 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2144 if (rt2860_rates[ridx].rate == rate) 2145 break; 2146 rn->ridx[i] = ridx; 2147 /* determine rate of control response frames */ 2148 for (j = i; j >= 0; j--) { 2149 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2150 rt2860_rates[rn->ridx[i]].phy == 2151 rt2860_rates[rn->ridx[j]].phy) 2152 break; 2153 } 2154 if (j >= 0) { 2155 rn->ctl_ridx[i] = rn->ridx[j]; 2156 } else { 2157 /* no basic rate found, use mandatory one */ 2158 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2159 } 2160 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2161 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2162 } 2163 } 2164 2165 /* 2166 * Return the Rx chain with the highest RSSI for a given frame. 2167 */ 2168 static __inline uint8_t 2169 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2170 { 2171 uint8_t rxchain = 0; 2172 2173 if (sc->nrxchains > 1) { 2174 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2175 rxchain = 1; 2176 if (sc->nrxchains > 2) 2177 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2178 rxchain = 2; 2179 } 2180 return rxchain; 2181 } 2182 2183 static void 2184 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2185 { 2186 struct ieee80211com *ic = &sc->sc_ic; 2187 struct ifnet *ifp = &sc->sc_if; 2188 struct ieee80211_frame *wh; 2189 struct ieee80211_node *ni; 2190 struct rt2870_rxd *rxd; 2191 struct rt2860_rxwi *rxwi; 2192 struct mbuf *m; 2193 uint32_t flags; 2194 uint16_t len, rxwisize, phy; 2195 uint8_t ant, rssi; 2196 int s; 2197 #ifdef RUN_HWCRYPTO 2198 int decrypted = 0; 2199 #endif 2200 2201 rxwi = (struct rt2860_rxwi *)buf; 2202 len = le16toh(rxwi->len) & 0xfff; 2203 if (__predict_false(len > dmalen)) { 2204 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2205 return; 2206 } 2207 /* Rx descriptor is located at the end */ 2208 rxd = (struct rt2870_rxd *)(buf + dmalen); 2209 flags = le32toh(rxd->flags); 2210 2211 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2212 ifp->if_ierrors++; 2213 return; 2214 } 2215 2216 rxwisize = sizeof(struct rt2860_rxwi); 2217 if (sc->mac_ver == 0x5592) 2218 rxwisize += sizeof(uint64_t); 2219 else if (sc->mac_ver == 0x3593) 2220 rxwisize += sizeof(uint32_t); 2221 2222 wh = (struct ieee80211_frame *)(((uint8_t *)rxwi) + rxwisize); 2223 #ifdef RUN_HWCRYPTO 2224 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2225 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2226 decrypted = 1; 2227 } 2228 #endif 2229 2230 if (__predict_false((flags & RT2860_RX_MICERR))) { 2231 /* report MIC failures to net80211 for TKIP */ 2232 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 2233 ifp->if_ierrors++; 2234 return; 2235 } 2236 2237 if (flags & RT2860_RX_L2PAD) { 2238 u_int hdrlen = ieee80211_hdrspace(ic, wh); 2239 ovbcopy(wh, (uint8_t *)wh + 2, hdrlen); 2240 wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); 2241 } 2242 2243 /* could use m_devget but net80211 wants contig mgmt frames */ 2244 MGETHDR(m, M_DONTWAIT, MT_DATA); 2245 if (__predict_false(m == NULL)) { 2246 ifp->if_ierrors++; 2247 return; 2248 } 2249 if (len > MHLEN) { 2250 MCLGET(m, M_DONTWAIT); 2251 if (__predict_false(!(m->m_flags & M_EXT))) { 2252 ifp->if_ierrors++; 2253 m_freem(m); 2254 return; 2255 } 2256 } 2257 /* finalize mbuf */ 2258 m_set_rcvif(m, ifp); 2259 memcpy(mtod(m, void *), wh, len); 2260 m->m_pkthdr.len = m->m_len = len; 2261 2262 ant = run_maxrssi_chain(sc, rxwi); 2263 rssi = rxwi->rssi[ant]; 2264 2265 if (__predict_false(sc->sc_drvbpf != NULL)) { 2266 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2267 2268 tap->wr_flags = 0; 2269 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2270 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2271 tap->wr_antsignal = rssi; 2272 tap->wr_antenna = ant; 2273 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2274 tap->wr_rate = 2; /* in case it can't be found below */ 2275 phy = le16toh(rxwi->phy); 2276 switch (phy & RT2860_PHY_MODE) { 2277 case RT2860_PHY_CCK: 2278 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2279 case 0: tap->wr_rate = 2; break; 2280 case 1: tap->wr_rate = 4; break; 2281 case 2: tap->wr_rate = 11; break; 2282 case 3: tap->wr_rate = 22; break; 2283 } 2284 if (phy & RT2860_PHY_SHPRE) 2285 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2286 break; 2287 case RT2860_PHY_OFDM: 2288 switch (phy & RT2860_PHY_MCS) { 2289 case 0: tap->wr_rate = 12; break; 2290 case 1: tap->wr_rate = 18; break; 2291 case 2: tap->wr_rate = 24; break; 2292 case 3: tap->wr_rate = 36; break; 2293 case 4: tap->wr_rate = 48; break; 2294 case 5: tap->wr_rate = 72; break; 2295 case 6: tap->wr_rate = 96; break; 2296 case 7: tap->wr_rate = 108; break; 2297 } 2298 break; 2299 } 2300 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 2301 } 2302 2303 s = splnet(); 2304 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2305 #ifdef RUN_HWCRYPTO 2306 if (decrypted) { 2307 uint32_t icflags = ic->ic_flags; 2308 2309 ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ 2310 ieee80211_input(ic, m, ni, rssi, 0); 2311 ic->ic_flags = icflags; 2312 } else 2313 #endif 2314 ieee80211_input(ic, m, ni, rssi, 0); 2315 2316 /* node is no longer needed */ 2317 ieee80211_free_node(ni); 2318 2319 /* 2320 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 2321 * without calling if_start(). 2322 */ 2323 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 2324 run_start(ifp); 2325 2326 splx(s); 2327 } 2328 2329 static void 2330 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2331 { 2332 struct run_rx_data *data = priv; 2333 struct run_softc *sc = data->sc; 2334 uint8_t *buf; 2335 uint32_t dmalen; 2336 int xferlen; 2337 2338 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2339 DPRINTF(("RX status=%d\n", status)); 2340 if (status == USBD_STALLED) 2341 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2342 if (status != USBD_CANCELLED) 2343 goto skip; 2344 return; 2345 } 2346 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2347 2348 if (__predict_false(xferlen < (int)(sizeof(uint32_t) + 2349 sizeof(struct rt2860_rxwi) + sizeof(struct rt2870_rxd)))) { 2350 DPRINTF(("xfer too short %d\n", xferlen)); 2351 goto skip; 2352 } 2353 2354 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2355 buf = data->buf; 2356 while (xferlen > 8) { 2357 dmalen = le32toh(*(uint32_t *)buf) & 0xffff; 2358 2359 if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || 2360 (dmalen & 3) != 0)) { 2361 DPRINTF(("bad DMA length %u (%x)\n", dmalen, dmalen)); 2362 break; 2363 } 2364 if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { 2365 DPRINTF(("bad DMA length %u > %d\n", 2366 dmalen + 8, xferlen)); 2367 break; 2368 } 2369 run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); 2370 buf += dmalen + 8; 2371 xferlen -= dmalen + 8; 2372 } 2373 2374 skip: /* setup a new transfer */ 2375 usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, 2376 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 2377 (void)usbd_transfer(data->xfer); 2378 } 2379 2380 static void 2381 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2382 { 2383 struct run_tx_data *data = priv; 2384 struct run_softc *sc = data->sc; 2385 struct run_tx_ring *txq = &sc->txq[data->qid]; 2386 struct ifnet *ifp = &sc->sc_if; 2387 int s; 2388 2389 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2390 DPRINTF(("TX status=%d\n", status)); 2391 if (status == USBD_STALLED) 2392 usbd_clear_endpoint_stall_async(txq->pipeh); 2393 ifp->if_oerrors++; 2394 return; 2395 } 2396 2397 s = splnet(); 2398 sc->sc_tx_timer = 0; 2399 ifp->if_opackets++; 2400 if (--txq->queued < RUN_TX_RING_COUNT) { 2401 sc->qfullmsk &= ~(1 << data->qid); 2402 ifp->if_flags &= ~IFF_OACTIVE; 2403 run_start(ifp); 2404 } 2405 splx(s); 2406 } 2407 2408 static int 2409 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2410 { 2411 struct ieee80211com *ic = &sc->sc_ic; 2412 struct run_node *rn = (void *)ni; 2413 struct ieee80211_frame *wh; 2414 #ifndef RUN_HWCRYPTO 2415 struct ieee80211_key *k; 2416 #endif 2417 struct run_tx_ring *ring; 2418 struct run_tx_data *data; 2419 struct rt2870_txd *txd; 2420 struct rt2860_txwi *txwi; 2421 uint16_t dur; 2422 uint8_t type, mcs, tid, qid, qos = 0; 2423 int error, hasqos, ridx, ctl_ridx, xferlen, txwisize; 2424 uint8_t pad; 2425 2426 wh = mtod(m, struct ieee80211_frame *); 2427 2428 #ifndef RUN_HWCRYPTO 2429 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2430 k = ieee80211_crypto_encap(ic, ni, m); 2431 if (k == NULL) { 2432 m_freem(m); 2433 return ENOBUFS; 2434 } 2435 2436 /* packet header may have moved, reset our local pointer */ 2437 wh = mtod(m, struct ieee80211_frame *); 2438 } 2439 #endif 2440 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2441 2442 if ((hasqos = ieee80211_has_qos(wh))) { 2443 qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; 2444 tid = qos & IEEE80211_QOS_TID; 2445 qid = TID_TO_WME_AC(tid); 2446 } else { 2447 tid = 0; 2448 qid = WME_AC_BE; 2449 } 2450 ring = &sc->txq[qid]; 2451 data = &ring->data[ring->cur]; 2452 2453 /* pickup a rate index */ 2454 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2455 type != IEEE80211_FC0_TYPE_DATA) { 2456 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2457 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2458 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2459 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 2460 ridx = sc->fixed_ridx; 2461 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2462 } else { 2463 ridx = rn->ridx[ni->ni_txrate]; 2464 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2465 } 2466 2467 /* get MCS code from rate index */ 2468 mcs = rt2860_rates[ridx].mcs; 2469 2470 txwisize = (sc->mac_ver == 0x5592) ? 2471 sizeof(*txwi) + sizeof(uint32_t) : sizeof(*txwi); 2472 xferlen = txwisize + m->m_pkthdr.len; 2473 /* roundup to 32-bit alignment */ 2474 xferlen = (xferlen + 3) & ~3; 2475 2476 txd = (struct rt2870_txd *)data->buf; 2477 txd->flags = RT2860_TX_QSEL_EDCA; 2478 txd->len = htole16(xferlen); 2479 2480 /* 2481 * Ether both are true or both are false, the header 2482 * are nicely aligned to 32-bit. So, no L2 padding. 2483 */ 2484 if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) 2485 pad = 0; 2486 else 2487 pad = 2; 2488 2489 /* setup TX Wireless Information */ 2490 txwi = (struct rt2860_txwi *)(txd + 1); 2491 txwi->flags = 0; 2492 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2493 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2494 RUN_AID2WCID(ni->ni_associd) : 0xff; 2495 txwi->len = htole16(m->m_pkthdr.len - pad); 2496 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2497 txwi->phy = htole16(RT2860_PHY_CCK); 2498 if (ridx != RT2860_RIDX_CCK1 && 2499 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2500 mcs |= RT2860_PHY_SHPRE; 2501 } else 2502 mcs |= RT2860_PHY_OFDM; 2503 txwi->phy |= htole16(mcs); 2504 2505 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2506 2507 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2508 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 2509 IEEE80211_QOS_ACKPOLICY_NOACK)) { 2510 txwi->xflags |= RT2860_TX_ACK; 2511 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2512 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2513 else 2514 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2515 *(uint16_t *)wh->i_dur = htole16(dur); 2516 } 2517 2518 #ifndef IEEE80211_STA_ONLY 2519 /* ask MAC to insert timestamp into probe responses */ 2520 if ((wh->i_fc[0] & 2521 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2522 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 2523 /* NOTE: beacons do not pass through tx_data() */ 2524 txwi->flags |= RT2860_TX_TS; 2525 #endif 2526 2527 if (__predict_false(sc->sc_drvbpf != NULL)) { 2528 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2529 2530 tap->wt_flags = 0; 2531 tap->wt_rate = rt2860_rates[ridx].rate; 2532 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2533 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2534 tap->wt_hwqueue = qid; 2535 if (mcs & RT2860_PHY_SHPRE) 2536 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2537 2538 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2539 } 2540 2541 m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); 2542 m_freem(m); 2543 2544 xferlen += sizeof(*txd) + 4; 2545 2546 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2547 USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); 2548 error = usbd_transfer(data->xfer); 2549 if (__predict_false(error != USBD_IN_PROGRESS && 2550 error != USBD_NORMAL_COMPLETION)) 2551 return error; 2552 2553 ieee80211_free_node(ni); 2554 2555 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2556 if (++ring->queued >= RUN_TX_RING_COUNT) 2557 sc->qfullmsk |= 1 << qid; 2558 2559 return 0; 2560 } 2561 2562 static void 2563 run_start(struct ifnet *ifp) 2564 { 2565 struct run_softc *sc = ifp->if_softc; 2566 struct ieee80211com *ic = &sc->sc_ic; 2567 struct ether_header *eh; 2568 struct ieee80211_node *ni; 2569 struct mbuf *m; 2570 2571 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2572 return; 2573 2574 for (;;) { 2575 if (sc->qfullmsk != 0) { 2576 ifp->if_flags |= IFF_OACTIVE; 2577 break; 2578 } 2579 /* send pending management frames first */ 2580 IF_DEQUEUE(&ic->ic_mgtq, m); 2581 if (m != NULL) { 2582 ni = M_GETCTX(m, struct ieee80211_node *); 2583 M_CLEARCTX(m); 2584 goto sendit; 2585 } 2586 if (ic->ic_state != IEEE80211_S_RUN) 2587 break; 2588 2589 /* encapsulate and send data frames */ 2590 IFQ_DEQUEUE(&ifp->if_snd, m); 2591 if (m == NULL) 2592 break; 2593 if (m->m_len < (int)sizeof(*eh) && 2594 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2595 ifp->if_oerrors++; 2596 continue; 2597 } 2598 2599 eh = mtod(m, struct ether_header *); 2600 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2601 if (ni == NULL) { 2602 m_freem(m); 2603 ifp->if_oerrors++; 2604 continue; 2605 } 2606 2607 bpf_mtap(ifp, m); 2608 2609 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2610 ieee80211_free_node(ni); 2611 ifp->if_oerrors++; 2612 continue; 2613 } 2614 sendit: 2615 bpf_mtap3(ic->ic_rawbpf, m); 2616 2617 if (run_tx(sc, m, ni) != 0) { 2618 ieee80211_free_node(ni); 2619 ifp->if_oerrors++; 2620 continue; 2621 } 2622 2623 sc->sc_tx_timer = 5; 2624 ifp->if_timer = 1; 2625 } 2626 } 2627 2628 static void 2629 run_watchdog(struct ifnet *ifp) 2630 { 2631 struct run_softc *sc = ifp->if_softc; 2632 struct ieee80211com *ic = &sc->sc_ic; 2633 2634 ifp->if_timer = 0; 2635 2636 if (sc->sc_tx_timer > 0) { 2637 if (--sc->sc_tx_timer == 0) { 2638 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2639 /* run_init(ifp); XXX needs a process context! */ 2640 ifp->if_oerrors++; 2641 return; 2642 } 2643 ifp->if_timer = 1; 2644 } 2645 2646 ieee80211_watchdog(ic); 2647 } 2648 2649 static int 2650 run_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2651 { 2652 struct run_softc *sc = ifp->if_softc; 2653 struct ieee80211com *ic = &sc->sc_ic; 2654 int s, error = 0; 2655 2656 s = splnet(); 2657 2658 switch (cmd) { 2659 case SIOCSIFFLAGS: 2660 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2661 break; 2662 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2663 case IFF_UP|IFF_RUNNING: 2664 break; 2665 case IFF_UP: 2666 run_init(ifp); 2667 break; 2668 case IFF_RUNNING: 2669 run_stop(ifp, 1); 2670 break; 2671 case 0: 2672 break; 2673 } 2674 break; 2675 2676 case SIOCADDMULTI: 2677 case SIOCDELMULTI: 2678 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2679 /* setup multicast filter, etc */ 2680 error = 0; 2681 } 2682 break; 2683 2684 default: 2685 error = ieee80211_ioctl(ic, cmd, data); 2686 break; 2687 } 2688 2689 if (error == ENETRESET) { 2690 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2691 (IFF_UP | IFF_RUNNING)) { 2692 run_init(ifp); 2693 } 2694 error = 0; 2695 } 2696 2697 splx(s); 2698 2699 return error; 2700 } 2701 2702 static void 2703 run_select_chan_group(struct run_softc *sc, int group) 2704 { 2705 uint32_t tmp; 2706 uint8_t agc; 2707 2708 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2709 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2710 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2711 run_bbp_write(sc, 86, 0x00); 2712 2713 if (group == 0) { 2714 if (sc->ext_2ghz_lna) { 2715 run_bbp_write(sc, 82, 0x62); 2716 run_bbp_write(sc, 75, 0x46); 2717 } else { 2718 run_bbp_write(sc, 82, 0x84); 2719 run_bbp_write(sc, 75, 0x50); 2720 } 2721 } else { 2722 if (sc->mac_ver == 0x3572) 2723 run_bbp_write(sc, 82, 0x94); 2724 else 2725 run_bbp_write(sc, 82, 0xf2); 2726 if (sc->ext_5ghz_lna) 2727 run_bbp_write(sc, 75, 0x46); 2728 else 2729 run_bbp_write(sc, 75, 0x50); 2730 } 2731 2732 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2733 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2734 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2735 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2736 2737 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2738 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2739 if (sc->nrxchains > 1) 2740 tmp |= RT2860_LNA_PE1_EN; 2741 if (group == 0) { /* 2GHz */ 2742 tmp |= RT2860_PA_PE_G0_EN; 2743 if (sc->ntxchains > 1) 2744 tmp |= RT2860_PA_PE_G1_EN; 2745 } else { /* 5GHz */ 2746 tmp |= RT2860_PA_PE_A0_EN; 2747 if (sc->ntxchains > 1) 2748 tmp |= RT2860_PA_PE_A1_EN; 2749 } 2750 if (sc->mac_ver == 0x3572) { 2751 run_rt3070_rf_write(sc, 8, 0x00); 2752 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2753 run_rt3070_rf_write(sc, 8, 0x80); 2754 } else 2755 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2756 2757 /* set initial AGC value */ 2758 if (group == 0) { /* 2GHz band */ 2759 if (sc->mac_ver >= 0x3070) 2760 agc = 0x1c + sc->lna[0] * 2; 2761 else 2762 agc = 0x2e + sc->lna[0]; 2763 } else { /* 5GHz band */ 2764 if (sc->mac_ver == 0x3572) 2765 agc = 0x22 + (sc->lna[group] * 5) / 3; 2766 else 2767 agc = 0x32 + (sc->lna[group] * 5) / 3; 2768 } 2769 run_set_agc(sc, agc); 2770 } 2771 2772 static void 2773 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2774 { 2775 const struct rfprog *rfprog = rt2860_rf2850; 2776 uint32_t r2, r3, r4; 2777 int8_t txpow1, txpow2; 2778 int i; 2779 2780 /* find the settings for this channel (we know it exists) */ 2781 for (i = 0; rfprog[i].chan != chan; i++); 2782 2783 r2 = rfprog[i].r2; 2784 if (sc->ntxchains == 1) 2785 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2786 if (sc->nrxchains == 1) 2787 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2788 else if (sc->nrxchains == 2) 2789 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2790 2791 /* use Tx power values from EEPROM */ 2792 txpow1 = sc->txpow1[i]; 2793 txpow2 = sc->txpow2[i]; 2794 if (chan > 14) { 2795 if (txpow1 >= 0) 2796 txpow1 = txpow1 << 1 | 1; 2797 else 2798 txpow1 = (7 + txpow1) << 1; 2799 if (txpow2 >= 0) 2800 txpow2 = txpow2 << 1 | 1; 2801 else 2802 txpow2 = (7 + txpow2) << 1; 2803 } 2804 r3 = rfprog[i].r3 | txpow1 << 7; 2805 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2806 2807 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2808 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2809 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2810 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2811 2812 usbd_delay_ms(sc->sc_udev, 10); 2813 2814 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2815 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2816 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2817 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2818 2819 usbd_delay_ms(sc->sc_udev, 10); 2820 2821 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2822 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2823 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2824 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2825 } 2826 2827 static void 2828 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2829 { 2830 int8_t txpow1, txpow2; 2831 uint8_t rf; 2832 int i; 2833 2834 KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ 2835 2836 /* find the settings for this channel (we know it exists) */ 2837 for (i = 0; rt2860_rf2850[i].chan != chan; i++) 2838 continue; 2839 2840 /* use Tx power values from EEPROM */ 2841 txpow1 = sc->txpow1[i]; 2842 txpow2 = sc->txpow2[i]; 2843 2844 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2845 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2846 run_rt3070_rf_read(sc, 6, &rf); 2847 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2848 run_rt3070_rf_write(sc, 6, rf); 2849 2850 /* set Tx0 power */ 2851 run_rt3070_rf_read(sc, 12, &rf); 2852 rf = (rf & ~0x1f) | txpow1; 2853 run_rt3070_rf_write(sc, 12, rf); 2854 2855 /* set Tx1 power */ 2856 run_rt3070_rf_read(sc, 13, &rf); 2857 rf = (rf & ~0x1f) | txpow2; 2858 run_rt3070_rf_write(sc, 13, rf); 2859 2860 run_rt3070_rf_read(sc, 1, &rf); 2861 rf &= ~0xfc; 2862 if (sc->ntxchains == 1) 2863 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2864 else if (sc->ntxchains == 2) 2865 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2866 if (sc->nrxchains == 1) 2867 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2868 else if (sc->nrxchains == 2) 2869 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2870 run_rt3070_rf_write(sc, 1, rf); 2871 2872 /* set RF offset */ 2873 run_rt3070_rf_read(sc, 23, &rf); 2874 rf = (rf & ~0x7f) | sc->freq; 2875 run_rt3070_rf_write(sc, 23, rf); 2876 2877 /* program RF filter */ 2878 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 2879 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2880 run_rt3070_rf_write(sc, 24, rf); 2881 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 2882 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2883 run_rt3070_rf_write(sc, 31, rf); 2884 2885 /* enable RF tuning */ 2886 run_rt3070_rf_read(sc, 7, &rf); 2887 run_rt3070_rf_write(sc, 7, rf | 0x01); 2888 } 2889 2890 static void 2891 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 2892 { 2893 int8_t txpow1, txpow2; 2894 uint32_t tmp; 2895 uint8_t rf; 2896 int i; 2897 2898 /* find the settings for this channel (we know it exists) */ 2899 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2900 2901 /* use Tx power values from EEPROM */ 2902 txpow1 = sc->txpow1[i]; 2903 txpow2 = sc->txpow2[i]; 2904 2905 if (chan <= 14) { 2906 run_bbp_write(sc, 25, sc->bbp25); 2907 run_bbp_write(sc, 26, sc->bbp26); 2908 } else { 2909 /* enable IQ phase correction */ 2910 run_bbp_write(sc, 25, 0x09); 2911 run_bbp_write(sc, 26, 0xff); 2912 } 2913 2914 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2915 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2916 run_rt3070_rf_read(sc, 6, &rf); 2917 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 2918 rf |= (chan <= 14) ? 0x08 : 0x04; 2919 run_rt3070_rf_write(sc, 6, rf); 2920 2921 /* set PLL mode */ 2922 run_rt3070_rf_read(sc, 5, &rf); 2923 rf &= ~(0x08 | 0x04); 2924 rf |= (chan <= 14) ? 0x04 : 0x08; 2925 run_rt3070_rf_write(sc, 5, rf); 2926 2927 /* set Tx power for chain 0 */ 2928 if (chan <= 14) 2929 rf = 0x60 | txpow1; 2930 else 2931 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 2932 run_rt3070_rf_write(sc, 12, rf); 2933 2934 /* set Tx power for chain 1 */ 2935 if (chan <= 14) 2936 rf = 0x60 | txpow2; 2937 else 2938 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 2939 run_rt3070_rf_write(sc, 13, rf); 2940 2941 /* set Tx/Rx streams */ 2942 run_rt3070_rf_read(sc, 1, &rf); 2943 rf &= ~0xfc; 2944 if (sc->ntxchains == 1) 2945 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2946 else if (sc->ntxchains == 2) 2947 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2948 if (sc->nrxchains == 1) 2949 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2950 else if (sc->nrxchains == 2) 2951 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2952 run_rt3070_rf_write(sc, 1, rf); 2953 2954 /* set RF offset */ 2955 run_rt3070_rf_read(sc, 23, &rf); 2956 rf = (rf & ~0x7f) | sc->freq; 2957 run_rt3070_rf_write(sc, 23, rf); 2958 2959 /* program RF filter */ 2960 rf = sc->rf24_20mhz; 2961 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 2962 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 2963 2964 /* enable RF tuning */ 2965 run_rt3070_rf_read(sc, 7, &rf); 2966 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 2967 run_rt3070_rf_write(sc, 7, rf); 2968 2969 /* TSSI */ 2970 rf = (chan <= 14) ? 0xc3 : 0xc0; 2971 run_rt3070_rf_write(sc, 9, rf); 2972 2973 /* set loop filter 1 */ 2974 run_rt3070_rf_write(sc, 10, 0xf1); 2975 /* set loop filter 2 */ 2976 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 2977 2978 /* set tx_mx2_ic */ 2979 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 2980 /* set tx_mx1_ic */ 2981 if (chan <= 14) 2982 rf = 0x48 | sc->txmixgain_2ghz; 2983 else 2984 rf = 0x78 | sc->txmixgain_5ghz; 2985 run_rt3070_rf_write(sc, 16, rf); 2986 2987 /* set tx_lo1 */ 2988 run_rt3070_rf_write(sc, 17, 0x23); 2989 /* set tx_lo2 */ 2990 if (chan <= 14) 2991 rf = 0x93; 2992 else if (chan <= 64) 2993 rf = 0xb7; 2994 else if (chan <= 128) 2995 rf = 0x74; 2996 else 2997 rf = 0x72; 2998 run_rt3070_rf_write(sc, 19, rf); 2999 3000 /* set rx_lo1 */ 3001 if (chan <= 14) 3002 rf = 0xb3; 3003 else if (chan <= 64) 3004 rf = 0xf6; 3005 else if (chan <= 128) 3006 rf = 0xf4; 3007 else 3008 rf = 0xf3; 3009 run_rt3070_rf_write(sc, 20, rf); 3010 3011 /* set pfd_delay */ 3012 if (chan <= 14) 3013 rf = 0x15; 3014 else if (chan <= 64) 3015 rf = 0x3d; 3016 else 3017 rf = 0x01; 3018 run_rt3070_rf_write(sc, 25, rf); 3019 3020 /* set rx_lo2 */ 3021 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3022 /* set ldo_rf_vc */ 3023 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3024 /* set drv_cc */ 3025 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3026 3027 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3028 tmp &= ~0x8080; 3029 if (chan <= 14) 3030 tmp |= 0x80; 3031 run_write(sc, RT2860_GPIO_CTRL, tmp); 3032 3033 /* enable RF tuning */ 3034 run_rt3070_rf_read(sc, 7, &rf); 3035 run_rt3070_rf_write(sc, 7, rf | 0x01); 3036 3037 usbd_delay_ms(sc->sc_udev, 2); 3038 } 3039 3040 static void 3041 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3042 { 3043 int8_t txpow1, txpow2, txpow3; 3044 uint8_t h20mhz, rf; 3045 int i; 3046 3047 /* find the settings for this channel (we know it exists) */ 3048 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3049 3050 /* use Tx power values from EEPROM */ 3051 txpow1 = sc->txpow1[i]; 3052 txpow2 = sc->txpow2[i]; 3053 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3054 3055 if (chan <= 14) { 3056 run_bbp_write(sc, 25, sc->bbp25); 3057 run_bbp_write(sc, 26, sc->bbp26); 3058 } else { 3059 /* Enable IQ phase correction. */ 3060 run_bbp_write(sc, 25, 0x09); 3061 run_bbp_write(sc, 26, 0xff); 3062 } 3063 3064 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3065 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3066 run_rt3070_rf_read(sc, 11, &rf); 3067 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3068 run_rt3070_rf_write(sc, 11, rf); 3069 3070 /* Set pll_idoh. */ 3071 run_rt3070_rf_read(sc, 11, &rf); 3072 rf &= ~0x4c; 3073 rf |= (chan <= 14) ? 0x44 : 0x48; 3074 run_rt3070_rf_write(sc, 11, rf); 3075 3076 if (chan <= 14) 3077 rf = txpow1 & 0x1f; 3078 else 3079 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3080 run_rt3070_rf_write(sc, 53, rf); 3081 3082 if (chan <= 14) 3083 rf = txpow2 & 0x1f; 3084 else 3085 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3086 run_rt3070_rf_write(sc, 55, rf); 3087 3088 if (chan <= 14) 3089 rf = txpow3 & 0x1f; 3090 else 3091 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3092 run_rt3070_rf_write(sc, 54, rf); 3093 3094 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3095 if (sc->ntxchains == 3) 3096 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3097 else 3098 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3099 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3100 run_rt3070_rf_write(sc, 1, rf); 3101 3102 run_adjust_freq_offset(sc); 3103 3104 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3105 3106 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3107 run_rt3070_rf_read(sc, 30, &rf); 3108 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3109 run_rt3070_rf_write(sc, 30, rf); 3110 3111 run_rt3070_rf_read(sc, 36, &rf); 3112 if (chan <= 14) 3113 rf |= 0x80; 3114 else 3115 rf &= ~0x80; 3116 run_rt3070_rf_write(sc, 36, rf); 3117 3118 /* Set vcolo_bs. */ 3119 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3120 /* Set pfd_delay. */ 3121 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3122 3123 /* Set vco bias current control. */ 3124 run_rt3070_rf_read(sc, 6, &rf); 3125 rf &= ~0xc0; 3126 if (chan <= 14) 3127 rf |= 0x40; 3128 else if (chan <= 128) 3129 rf |= 0x80; 3130 else 3131 rf |= 0x40; 3132 run_rt3070_rf_write(sc, 6, rf); 3133 3134 run_rt3070_rf_read(sc, 30, &rf); 3135 rf = (rf & ~0x18) | 0x10; 3136 run_rt3070_rf_write(sc, 30, rf); 3137 3138 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3139 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3140 3141 run_rt3070_rf_read(sc, 51, &rf); 3142 rf = (rf & ~0x03) | 0x01; 3143 run_rt3070_rf_write(sc, 51, rf); 3144 /* Set tx_mx1_cc. */ 3145 run_rt3070_rf_read(sc, 51, &rf); 3146 rf &= ~0x1c; 3147 rf |= (chan <= 14) ? 0x14 : 0x10; 3148 run_rt3070_rf_write(sc, 51, rf); 3149 /* Set tx_mx1_ic. */ 3150 run_rt3070_rf_read(sc, 51, &rf); 3151 rf &= ~0xe0; 3152 rf |= (chan <= 14) ? 0x60 : 0x40; 3153 run_rt3070_rf_write(sc, 51, rf); 3154 /* Set tx_lo1_ic. */ 3155 run_rt3070_rf_read(sc, 49, &rf); 3156 rf &= ~0x1c; 3157 rf |= (chan <= 14) ? 0x0c : 0x08; 3158 run_rt3070_rf_write(sc, 49, rf); 3159 /* Set tx_lo1_en. */ 3160 run_rt3070_rf_read(sc, 50, &rf); 3161 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3162 /* Set drv_cc. */ 3163 run_rt3070_rf_read(sc, 57, &rf); 3164 rf &= ~0xfc; 3165 rf |= (chan <= 14) ? 0x6c : 0x3c; 3166 run_rt3070_rf_write(sc, 57, rf); 3167 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3168 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3169 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3170 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3171 /* Enable VCO calibration. */ 3172 run_rt3070_rf_read(sc, 3, &rf); 3173 rf &= ~RT5390_VCOCAL; 3174 rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; 3175 run_rt3070_rf_write(sc, 3, rf); 3176 3177 if (chan <= 14) 3178 rf = 0x23; 3179 else if (chan <= 64) 3180 rf = 0x36; 3181 else if (chan <= 128) 3182 rf = 0x32; 3183 else 3184 rf = 0x30; 3185 run_rt3070_rf_write(sc, 39, rf); 3186 if (chan <= 14) 3187 rf = 0xbb; 3188 else if (chan <= 64) 3189 rf = 0xeb; 3190 else if (chan <= 128) 3191 rf = 0xb3; 3192 else 3193 rf = 0x9b; 3194 run_rt3070_rf_write(sc, 45, rf); 3195 3196 /* Set FEQ/AEQ control. */ 3197 run_bbp_write(sc, 105, 0x34); 3198 } 3199 3200 static void 3201 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3202 { 3203 int8_t txpow1, txpow2; 3204 uint8_t rf; 3205 int i; 3206 3207 /* find the settings for this channel (we know it exists) */ 3208 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3209 3210 /* use Tx power values from EEPROM */ 3211 txpow1 = sc->txpow1[i]; 3212 txpow2 = sc->txpow2[i]; 3213 3214 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3215 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3216 run_rt3070_rf_read(sc, 11, &rf); 3217 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3218 run_rt3070_rf_write(sc, 11, rf); 3219 3220 run_rt3070_rf_read(sc, 49, &rf); 3221 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3222 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3223 if ((rf & 0x3f) > 0x27) 3224 rf = (rf & ~0x3f) | 0x27; 3225 run_rt3070_rf_write(sc, 49, rf); 3226 3227 if (sc->mac_ver == 0x5392) { 3228 run_rt3070_rf_read(sc, 50, &rf); 3229 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3230 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3231 if ((rf & 0x3f) > 0x27) 3232 rf = (rf & ~0x3f) | 0x27; 3233 run_rt3070_rf_write(sc, 50, rf); 3234 } 3235 3236 run_rt3070_rf_read(sc, 1, &rf); 3237 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3238 if (sc->mac_ver == 0x5392) 3239 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3240 run_rt3070_rf_write(sc, 1, rf); 3241 3242 if (sc->mac_ver != 0x5392) { 3243 run_rt3070_rf_read(sc, 2, &rf); 3244 rf |= 0x80; 3245 run_rt3070_rf_write(sc, 2, rf); 3246 usbd_delay_ms(sc->sc_udev, 10); 3247 rf &= 0x7f; 3248 run_rt3070_rf_write(sc, 2, rf); 3249 } 3250 3251 run_adjust_freq_offset(sc); 3252 3253 if (sc->mac_ver == 0x5392) { 3254 /* Fix for RT5392C. */ 3255 if (sc->mac_rev >= 0x0223) { 3256 if (chan <= 4) 3257 rf = 0x0f; 3258 else if (chan >= 5 && chan <= 7) 3259 rf = 0x0e; 3260 else 3261 rf = 0x0d; 3262 run_rt3070_rf_write(sc, 23, rf); 3263 3264 if (chan <= 4) 3265 rf = 0x0c; 3266 else if (chan == 5) 3267 rf = 0x0b; 3268 else if (chan >= 6 && chan <= 7) 3269 rf = 0x0a; 3270 else if (chan >= 8 && chan <= 10) 3271 rf = 0x09; 3272 else 3273 rf = 0x08; 3274 run_rt3070_rf_write(sc, 59, rf); 3275 } else { 3276 if (chan <= 11) 3277 rf = 0x0f; 3278 else 3279 rf = 0x0b; 3280 run_rt3070_rf_write(sc, 59, rf); 3281 } 3282 } else { 3283 /* Fix for RT5390F. */ 3284 if (sc->mac_rev >= 0x0502) { 3285 if (chan <= 11) 3286 rf = 0x43; 3287 else 3288 rf = 0x23; 3289 run_rt3070_rf_write(sc, 55, rf); 3290 3291 if (chan <= 11) 3292 rf = 0x0f; 3293 else if (chan == 12) 3294 rf = 0x0d; 3295 else 3296 rf = 0x0b; 3297 run_rt3070_rf_write(sc, 59, rf); 3298 } else { 3299 run_rt3070_rf_write(sc, 55, 0x44); 3300 run_rt3070_rf_write(sc, 59, 0x8f); 3301 } 3302 } 3303 3304 /* Enable VCO calibration. */ 3305 run_rt3070_rf_read(sc, 3, &rf); 3306 rf |= RT5390_VCOCAL; 3307 run_rt3070_rf_write(sc, 3, rf); 3308 } 3309 3310 static void 3311 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3312 { 3313 const struct rt5592_freqs *freqs; 3314 uint32_t tmp; 3315 uint8_t reg, rf, txpow_bound; 3316 int8_t txpow1, txpow2; 3317 int i; 3318 3319 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3320 freqs = (tmp & RT5592_SEL_XTAL) ? 3321 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3322 3323 /* find the settings for this channel (we know it exists) */ 3324 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3325 3326 /* use Tx power values from EEPROM */ 3327 txpow1 = sc->txpow1[i]; 3328 txpow2 = sc->txpow2[i]; 3329 3330 run_read(sc, RT3070_LDO_CFG0, &tmp); 3331 tmp &= ~0x1c000000; 3332 if (chan > 14) 3333 tmp |= 0x14000000; 3334 run_write(sc, RT3070_LDO_CFG0, tmp); 3335 3336 /* N setting. */ 3337 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3338 run_rt3070_rf_read(sc, 9, &rf); 3339 rf &= ~(1 << 4); 3340 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3341 run_rt3070_rf_write(sc, 9, rf); 3342 3343 /* K setting. */ 3344 run_rt3070_rf_read(sc, 9, &rf); 3345 rf &= ~0x0f; 3346 rf |= (freqs->k & 0x0f); 3347 run_rt3070_rf_write(sc, 9, rf); 3348 3349 /* Mode setting. */ 3350 run_rt3070_rf_read(sc, 11, &rf); 3351 rf &= ~0x0c; 3352 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3353 run_rt3070_rf_write(sc, 11, rf); 3354 run_rt3070_rf_read(sc, 9, &rf); 3355 rf &= ~(1 << 7); 3356 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3357 run_rt3070_rf_write(sc, 9, rf); 3358 3359 /* R setting. */ 3360 run_rt3070_rf_read(sc, 11, &rf); 3361 rf &= ~0x03; 3362 rf |= (freqs->r - 0x1); 3363 run_rt3070_rf_write(sc, 11, rf); 3364 3365 if (chan <= 14) { 3366 /* Initialize RF registers for 2GHZ. */ 3367 for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { 3368 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3369 rt5592_2ghz_def_rf[i].val); 3370 } 3371 3372 rf = (chan <= 10) ? 0x07 : 0x06; 3373 run_rt3070_rf_write(sc, 23, rf); 3374 run_rt3070_rf_write(sc, 59, rf); 3375 3376 run_rt3070_rf_write(sc, 55, 0x43); 3377 3378 /* 3379 * RF R49/R50 Tx power ALC code. 3380 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3381 */ 3382 reg = 2; 3383 txpow_bound = 0x27; 3384 } else { 3385 /* Initialize RF registers for 5GHZ. */ 3386 for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { 3387 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3388 rt5592_5ghz_def_rf[i].val); 3389 } 3390 for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { 3391 if (chan >= rt5592_chan_5ghz[i].firstchan && 3392 chan <= rt5592_chan_5ghz[i].lastchan) { 3393 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3394 rt5592_chan_5ghz[i].val); 3395 } 3396 } 3397 3398 /* 3399 * RF R49/R50 Tx power ALC code. 3400 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3401 */ 3402 reg = 3; 3403 txpow_bound = 0x2b; 3404 } 3405 3406 /* RF R49 ch0 Tx power ALC code. */ 3407 run_rt3070_rf_read(sc, 49, &rf); 3408 rf &= ~0xc0; 3409 rf |= (reg << 6); 3410 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3411 if ((rf & 0x3f) > txpow_bound) 3412 rf = (rf & ~0x3f) | txpow_bound; 3413 run_rt3070_rf_write(sc, 49, rf); 3414 3415 /* RF R50 ch1 Tx power ALC code. */ 3416 run_rt3070_rf_read(sc, 50, &rf); 3417 rf &= ~(1 << 7 | 1 << 6); 3418 rf |= (reg << 6); 3419 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3420 if ((rf & 0x3f) > txpow_bound) 3421 rf = (rf & ~0x3f) | txpow_bound; 3422 run_rt3070_rf_write(sc, 50, rf); 3423 3424 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3425 run_rt3070_rf_read(sc, 1, &rf); 3426 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3427 if (sc->ntxchains > 1) 3428 rf |= RT3070_TX1_PD; 3429 if (sc->nrxchains > 1) 3430 rf |= RT3070_RX1_PD; 3431 run_rt3070_rf_write(sc, 1, rf); 3432 3433 run_rt3070_rf_write(sc, 6, 0xe4); 3434 3435 run_rt3070_rf_write(sc, 30, 0x10); 3436 run_rt3070_rf_write(sc, 31, 0x80); 3437 run_rt3070_rf_write(sc, 32, 0x80); 3438 3439 run_adjust_freq_offset(sc); 3440 3441 /* Enable VCO calibration. */ 3442 run_rt3070_rf_read(sc, 3, &rf); 3443 rf |= RT5390_VCOCAL; 3444 run_rt3070_rf_write(sc, 3, rf); 3445 } 3446 3447 static void 3448 run_iq_calib(struct run_softc *sc, u_int chan) 3449 { 3450 uint16_t val; 3451 3452 /* Tx0 IQ gain. */ 3453 run_bbp_write(sc, 158, 0x2c); 3454 if (chan <= 14) 3455 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); 3456 else if (chan <= 64) { 3457 run_efuse_read(sc, 3458 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, 3459 &val, 1); 3460 } else if (chan <= 138) { 3461 run_efuse_read(sc, 3462 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, 3463 &val, 1); 3464 } else if (chan <= 165) { 3465 run_efuse_read(sc, 3466 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 3467 &val, 1); 3468 } else 3469 val = 0; 3470 run_bbp_write(sc, 159, val); 3471 3472 /* Tx0 IQ phase. */ 3473 run_bbp_write(sc, 158, 0x2d); 3474 if (chan <= 14) { 3475 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, 3476 &val, 1); 3477 } else if (chan <= 64) { 3478 run_efuse_read(sc, 3479 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, 3480 &val, 1); 3481 } else if (chan <= 138) { 3482 run_efuse_read(sc, 3483 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, 3484 &val, 1); 3485 } else if (chan <= 165) { 3486 run_efuse_read(sc, 3487 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, 3488 &val, 1); 3489 } else 3490 val = 0; 3491 run_bbp_write(sc, 159, val); 3492 3493 /* Tx1 IQ gain. */ 3494 run_bbp_write(sc, 158, 0x4a); 3495 if (chan <= 14) { 3496 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, 3497 &val, 1); 3498 } else if (chan <= 64) { 3499 run_efuse_read(sc, 3500 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, 3501 &val, 1); 3502 } else if (chan <= 138) { 3503 run_efuse_read(sc, 3504 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, 3505 &val, 1); 3506 } else if (chan <= 165) { 3507 run_efuse_read(sc, 3508 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, 3509 &val, 1); 3510 } else 3511 val = 0; 3512 run_bbp_write(sc, 159, val); 3513 3514 /* Tx1 IQ phase. */ 3515 run_bbp_write(sc, 158, 0x4b); 3516 if (chan <= 14) { 3517 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, 3518 &val, 1); 3519 } else if (chan <= 64) { 3520 run_efuse_read(sc, 3521 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, 3522 &val, 1); 3523 } else if (chan <= 138) { 3524 run_efuse_read(sc, 3525 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, 3526 &val, 1); 3527 } else if (chan <= 165) { 3528 run_efuse_read(sc, 3529 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, 3530 &val, 1); 3531 } else 3532 val = 0; 3533 run_bbp_write(sc, 159, val); 3534 3535 /* RF IQ compensation control. */ 3536 run_bbp_write(sc, 158, 0x04); 3537 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, 3538 &val, 1); 3539 run_bbp_write(sc, 159, val); 3540 3541 /* RF IQ imbalance compensation control. */ 3542 run_bbp_write(sc, 158, 0x03); 3543 run_efuse_read(sc, 3544 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); 3545 run_bbp_write(sc, 159, val); 3546 } 3547 3548 static void 3549 run_set_agc(struct run_softc *sc, uint8_t agc) 3550 { 3551 uint8_t bbp; 3552 3553 if (sc->mac_ver == 0x3572) { 3554 run_bbp_read(sc, 27, &bbp); 3555 bbp &= ~(0x3 << 5); 3556 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3557 run_bbp_write(sc, 66, agc); 3558 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3559 run_bbp_write(sc, 66, agc); 3560 } else 3561 run_bbp_write(sc, 66, agc); 3562 } 3563 3564 static void 3565 run_set_rx_antenna(struct run_softc *sc, int aux) 3566 { 3567 uint32_t tmp; 3568 uint8_t bbp152; 3569 3570 if (sc->rf_rev == RT5390_RF_5370) { 3571 run_bbp_read(sc, 152, &bbp152); 3572 bbp152 &= ~0x80; 3573 if (aux) 3574 bbp152 |= 0x80; 3575 run_bbp_write(sc, 152, bbp152); 3576 } else { 3577 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); 3578 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3579 tmp &= ~0x0808; 3580 if (aux) 3581 tmp |= 0x08; 3582 run_write(sc, RT2860_GPIO_CTRL, tmp); 3583 } 3584 } 3585 3586 static int 3587 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3588 { 3589 struct ieee80211com *ic = &sc->sc_ic; 3590 u_int chan, group; 3591 3592 chan = ieee80211_chan2ieee(ic, c); 3593 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3594 return EINVAL; 3595 3596 if (sc->mac_ver == 0x5592) 3597 run_rt5592_set_chan(sc, chan); 3598 else if (sc->mac_ver >= 0x5390) 3599 run_rt5390_set_chan(sc, chan); 3600 else if (sc->mac_ver == 0x3593) 3601 run_rt3593_set_chan(sc, chan); 3602 else if (sc->mac_ver == 0x3572) 3603 run_rt3572_set_chan(sc, chan); 3604 else if (sc->mac_ver >= 0x3070) 3605 run_rt3070_set_chan(sc, chan); 3606 else 3607 run_rt2870_set_chan(sc, chan); 3608 3609 /* determine channel group */ 3610 if (chan <= 14) 3611 group = 0; 3612 else if (chan <= 64) 3613 group = 1; 3614 else if (chan <= 128) 3615 group = 2; 3616 else 3617 group = 3; 3618 3619 /* XXX necessary only when group has changed! */ 3620 run_select_chan_group(sc, group); 3621 3622 usbd_delay_ms(sc->sc_udev, 10); 3623 3624 /* Perform IQ calibration. */ 3625 if (sc->mac_ver >= 0x5392) 3626 run_iq_calib(sc, chan); 3627 3628 return 0; 3629 } 3630 3631 static void 3632 run_updateprot(struct run_softc *sc) 3633 { 3634 struct ieee80211com *ic = &sc->sc_ic; 3635 uint32_t tmp; 3636 3637 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3638 /* setup protection frame rate (MCS code) */ 3639 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3640 rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : 3641 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3642 3643 /* CCK frames don't require protection */ 3644 run_write(sc, RT2860_CCK_PROT_CFG, tmp); 3645 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3646 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3647 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3648 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3649 tmp |= RT2860_PROT_CTRL_CTS; 3650 } 3651 run_write(sc, RT2860_OFDM_PROT_CFG, tmp); 3652 } 3653 3654 static void 3655 run_enable_tsf_sync(struct run_softc *sc) 3656 { 3657 struct ieee80211com *ic = &sc->sc_ic; 3658 uint32_t tmp; 3659 3660 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3661 tmp &= ~0x1fffff; 3662 tmp |= ic->ic_bss->ni_intval * 16; 3663 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3664 if (ic->ic_opmode == IEEE80211_M_STA) { 3665 /* 3666 * Local TSF is always updated with remote TSF on beacon 3667 * reception. 3668 */ 3669 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3670 } 3671 #ifndef IEEE80211_STA_ONLY 3672 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3673 tmp |= RT2860_BCN_TX_EN; 3674 /* 3675 * Local TSF is updated with remote TSF on beacon reception 3676 * only if the remote TSF is greater than local TSF. 3677 */ 3678 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3679 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3680 tmp |= RT2860_BCN_TX_EN; 3681 /* SYNC with nobody */ 3682 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3683 } 3684 #endif 3685 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3686 } 3687 3688 static void 3689 run_enable_mrr(struct run_softc *sc) 3690 { 3691 #define CCK(mcs) (mcs) 3692 #define OFDM(mcs) (1 << 3 | (mcs)) 3693 run_write(sc, RT2860_LG_FBK_CFG0, 3694 OFDM(6) << 28 | /* 54->48 */ 3695 OFDM(5) << 24 | /* 48->36 */ 3696 OFDM(4) << 20 | /* 36->24 */ 3697 OFDM(3) << 16 | /* 24->18 */ 3698 OFDM(2) << 12 | /* 18->12 */ 3699 OFDM(1) << 8 | /* 12-> 9 */ 3700 OFDM(0) << 4 | /* 9-> 6 */ 3701 OFDM(0)); /* 6-> 6 */ 3702 3703 run_write(sc, RT2860_LG_FBK_CFG1, 3704 CCK(2) << 12 | /* 11->5.5 */ 3705 CCK(1) << 8 | /* 5.5-> 2 */ 3706 CCK(0) << 4 | /* 2-> 1 */ 3707 CCK(0)); /* 1-> 1 */ 3708 #undef OFDM 3709 #undef CCK 3710 } 3711 3712 static void 3713 run_set_txpreamble(struct run_softc *sc) 3714 { 3715 uint32_t tmp; 3716 3717 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3718 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3719 tmp |= RT2860_CCK_SHORT_EN; 3720 else 3721 tmp &= ~RT2860_CCK_SHORT_EN; 3722 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3723 } 3724 3725 static void 3726 run_set_basicrates(struct run_softc *sc) 3727 { 3728 struct ieee80211com *ic = &sc->sc_ic; 3729 3730 /* set basic rates mask */ 3731 if (ic->ic_curmode == IEEE80211_MODE_11B) 3732 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3733 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3734 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3735 else /* 11g */ 3736 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3737 } 3738 3739 static void 3740 run_set_leds(struct run_softc *sc, uint16_t which) 3741 { 3742 3743 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3744 which | (sc->leds & 0x7f)); 3745 } 3746 3747 static void 3748 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3749 { 3750 3751 run_write(sc, RT2860_MAC_BSSID_DW0, 3752 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3753 run_write(sc, RT2860_MAC_BSSID_DW1, 3754 bssid[4] | bssid[5] << 8); 3755 } 3756 3757 static void 3758 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3759 { 3760 3761 run_write(sc, RT2860_MAC_ADDR_DW0, 3762 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3763 run_write(sc, RT2860_MAC_ADDR_DW1, 3764 addr[4] | addr[5] << 8 | 0xff << 16); 3765 } 3766 3767 static void 3768 run_updateslot(struct ifnet *ifp) 3769 { 3770 3771 /* do it in a process context */ 3772 run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); 3773 } 3774 3775 /* ARGSUSED */ 3776 static void 3777 run_updateslot_cb(struct run_softc *sc, void *arg) 3778 { 3779 uint32_t tmp; 3780 3781 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3782 tmp &= ~0xff; 3783 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3784 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3785 } 3786 3787 static int8_t 3788 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3789 { 3790 struct ieee80211com *ic = &sc->sc_ic; 3791 struct ieee80211_channel *c = ic->ic_curchan; 3792 int delta; 3793 3794 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3795 u_int chan = ieee80211_chan2ieee(ic, c); 3796 delta = sc->rssi_5ghz[rxchain]; 3797 3798 /* determine channel group */ 3799 if (chan <= 64) 3800 delta -= sc->lna[1]; 3801 else if (chan <= 128) 3802 delta -= sc->lna[2]; 3803 else 3804 delta -= sc->lna[3]; 3805 } else 3806 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3807 3808 return -12 - delta - rssi; 3809 } 3810 3811 static void 3812 run_rt5390_bbp_init(struct run_softc *sc) 3813 { 3814 u_int i; 3815 uint8_t bbp; 3816 3817 /* Apply maximum likelihood detection for 2 stream case. */ 3818 run_bbp_read(sc, 105, &bbp); 3819 if (sc->nrxchains > 1) 3820 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3821 3822 /* Avoid data lost and CRC error. */ 3823 run_bbp_read(sc, 4, &bbp); 3824 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3825 3826 if (sc->mac_ver == 0x5592) { 3827 for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { 3828 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3829 rt5592_def_bbp[i].val); 3830 } 3831 for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { 3832 run_bbp_write(sc, 195, i + 0x80); 3833 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3834 } 3835 } else { 3836 for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { 3837 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3838 rt5390_def_bbp[i].val); 3839 } 3840 } 3841 if (sc->mac_ver == 0x5392) { 3842 run_bbp_write(sc, 88, 0x90); 3843 run_bbp_write(sc, 95, 0x9a); 3844 run_bbp_write(sc, 98, 0x12); 3845 run_bbp_write(sc, 106, 0x12); 3846 run_bbp_write(sc, 134, 0xd0); 3847 run_bbp_write(sc, 135, 0xf6); 3848 run_bbp_write(sc, 148, 0x84); 3849 } 3850 3851 run_bbp_read(sc, 152, &bbp); 3852 run_bbp_write(sc, 152, bbp | 0x80); 3853 3854 /* Fix BBP254 for RT5592C. */ 3855 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3856 run_bbp_read(sc, 254, &bbp); 3857 run_bbp_write(sc, 254, bbp | 0x80); 3858 } 3859 3860 /* Disable hardware antenna diversity. */ 3861 if (sc->mac_ver == 0x5390) 3862 run_bbp_write(sc, 154, 0); 3863 3864 /* Initialize Rx CCK/OFDM frequency offset report. */ 3865 run_bbp_write(sc, 142, 1); 3866 run_bbp_write(sc, 143, 57); 3867 } 3868 3869 static int 3870 run_bbp_init(struct run_softc *sc) 3871 { 3872 int i, error, ntries; 3873 uint8_t bbp0; 3874 3875 /* wait for BBP to wake up */ 3876 for (ntries = 0; ntries < 20; ntries++) { 3877 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3878 return error; 3879 if (bbp0 != 0 && bbp0 != 0xff) 3880 break; 3881 } 3882 if (ntries == 20) 3883 return ETIMEDOUT; 3884 3885 /* initialize BBP registers to default values */ 3886 if (sc->mac_ver >= 0x5390) 3887 run_rt5390_bbp_init(sc); 3888 else { 3889 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 3890 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3891 rt2860_def_bbp[i].val); 3892 } 3893 } 3894 3895 if (sc->mac_ver == 0x3593) { 3896 run_bbp_write(sc, 79, 0x13); 3897 run_bbp_write(sc, 80, 0x05); 3898 run_bbp_write(sc, 81, 0x33); 3899 run_bbp_write(sc, 86, 0x46); 3900 run_bbp_write(sc, 137, 0x0f); 3901 } 3902 3903 /* fix BBP84 for RT2860E */ 3904 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3905 run_bbp_write(sc, 84, 0x19); 3906 3907 if (sc->mac_ver >= 0x3070) { 3908 run_bbp_write(sc, 79, 0x13); 3909 run_bbp_write(sc, 80, 0x05); 3910 run_bbp_write(sc, 81, 0x33); 3911 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3912 run_bbp_write(sc, 69, 0x16); 3913 run_bbp_write(sc, 73, 0x12); 3914 } 3915 return 0; 3916 } 3917 3918 static int 3919 run_rt3070_rf_init(struct run_softc *sc) 3920 { 3921 uint32_t tmp; 3922 uint8_t rf, target, bbp4; 3923 int i; 3924 3925 run_rt3070_rf_read(sc, 30, &rf); 3926 /* toggle RF R30 bit 7 */ 3927 run_rt3070_rf_write(sc, 30, rf | 0x80); 3928 usbd_delay_ms(sc->sc_udev, 10); 3929 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3930 3931 /* initialize RF registers to default value */ 3932 if (sc->mac_ver == 0x3572) { 3933 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 3934 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3935 rt3572_def_rf[i].val); 3936 } 3937 } else { 3938 for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { 3939 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3940 rt3070_def_rf[i].val); 3941 } 3942 } 3943 if (sc->mac_ver == 0x3572) { 3944 run_rt3070_rf_read(sc, 6, &rf); 3945 run_rt3070_rf_write(sc, 6, rf | 0x40); 3946 run_rt3070_rf_write(sc, 31, 0x14); 3947 3948 run_read(sc, RT3070_LDO_CFG0, &tmp); 3949 tmp &= ~0x1f000000; 3950 if (sc->mac_rev < 0x0211 && sc->patch_dac) 3951 tmp |= 0x0d000000; /* 1.3V */ 3952 else 3953 tmp |= 0x01000000; /* 1.2V */ 3954 run_write(sc, RT3070_LDO_CFG0, tmp); 3955 } else if (sc->mac_ver == 0x3071) { 3956 run_rt3070_rf_read(sc, 6, &rf); 3957 run_rt3070_rf_write(sc, 6, rf | 0x40); 3958 run_rt3070_rf_write(sc, 31, 0x14); 3959 3960 run_read(sc, RT3070_LDO_CFG0, &tmp); 3961 tmp &= ~0x1f000000; 3962 if (sc->mac_rev < 0x0211) 3963 tmp |= 0x0d000000; /* 1.35V */ 3964 else 3965 tmp |= 0x01000000; /* 1.2V */ 3966 run_write(sc, RT3070_LDO_CFG0, tmp); 3967 3968 /* patch LNA_PE_G1 */ 3969 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3970 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3971 } else if (sc->mac_ver == 0x3070) { 3972 /* increase voltage from 1.2V to 1.35V */ 3973 run_read(sc, RT3070_LDO_CFG0, &tmp); 3974 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3975 run_write(sc, RT3070_LDO_CFG0, tmp); 3976 } 3977 3978 /* select 20MHz bandwidth */ 3979 run_rt3070_rf_read(sc, 31, &rf); 3980 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3981 3982 /* calibrate filter for 20MHz bandwidth */ 3983 sc->rf24_20mhz = 0x1f; /* default value */ 3984 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3985 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3986 3987 /* select 40MHz bandwidth */ 3988 run_bbp_read(sc, 4, &bbp4); 3989 run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); 3990 run_rt3070_rf_read(sc, 31, &rf); 3991 run_rt3070_rf_write(sc, 31, rf | 0x20); 3992 3993 /* calibrate filter for 40MHz bandwidth */ 3994 sc->rf24_40mhz = 0x2f; /* default value */ 3995 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 3996 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 3997 3998 /* go back to 20MHz bandwidth */ 3999 run_bbp_read(sc, 4, &bbp4); 4000 run_bbp_write(sc, 4, bbp4 & ~0x18); 4001 4002 if (sc->mac_ver == 0x3572) { 4003 /* save default BBP registers 25 and 26 values */ 4004 run_bbp_read(sc, 25, &sc->bbp25); 4005 run_bbp_read(sc, 26, &sc->bbp26); 4006 } else if (sc->mac_rev < 0x0211) 4007 run_rt3070_rf_write(sc, 27, 0x03); 4008 4009 run_read(sc, RT3070_OPT_14, &tmp); 4010 run_write(sc, RT3070_OPT_14, tmp | 1); 4011 4012 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4013 run_rt3070_rf_read(sc, 17, &rf); 4014 rf &= ~RT3070_TX_LO1; 4015 if ((sc->mac_ver == 0x3070 || 4016 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4017 !sc->ext_2ghz_lna) 4018 rf |= 0x20; /* fix for long range Rx issue */ 4019 if (sc->txmixgain_2ghz >= 1) 4020 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4021 run_rt3070_rf_write(sc, 17, rf); 4022 } 4023 if (sc->mac_ver == 0x3071) { 4024 run_rt3070_rf_read(sc, 1, &rf); 4025 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4026 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4027 run_rt3070_rf_write(sc, 1, rf); 4028 4029 run_rt3070_rf_read(sc, 15, &rf); 4030 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4031 4032 run_rt3070_rf_read(sc, 20, &rf); 4033 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4034 4035 run_rt3070_rf_read(sc, 21, &rf); 4036 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4037 } 4038 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4039 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4040 run_rt3070_rf_read(sc, 27, &rf); 4041 rf &= ~0x77; 4042 if (sc->mac_rev < 0x0211) 4043 rf |= 0x03; 4044 run_rt3070_rf_write(sc, 27, rf); 4045 } 4046 return 0; 4047 } 4048 4049 static int 4050 run_rt3593_rf_init(struct run_softc *sc) 4051 { 4052 uint32_t tmp; 4053 uint8_t rf; 4054 int i; 4055 4056 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4057 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4058 tmp &= ~(1 << 4 | 1 << 7); 4059 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4060 4061 /* Initialize RF registers to default value. */ 4062 for (i = 0; i < __arraycount(rt3593_def_rf); i++) { 4063 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4064 rt3593_def_rf[i].val); 4065 } 4066 4067 /* Toggle RF R2 to initiate calibration. */ 4068 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4069 4070 /* Initialize RF frequency offset. */ 4071 run_adjust_freq_offset(sc); 4072 4073 run_rt3070_rf_read(sc, 18, &rf); 4074 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4075 4076 /* 4077 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4078 * decrease voltage back to 1.2V. 4079 */ 4080 run_read(sc, RT3070_LDO_CFG0, &tmp); 4081 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4082 run_write(sc, RT3070_LDO_CFG0, tmp); 4083 usbd_delay_ms(sc->sc_udev, 1); 4084 tmp = (tmp & ~0x1f000000) | 0x01000000; 4085 run_write(sc, RT3070_LDO_CFG0, tmp); 4086 4087 sc->rf24_20mhz = 0x1f; 4088 sc->rf24_40mhz = 0x2f; 4089 4090 /* Save default BBP registers 25 and 26 values. */ 4091 run_bbp_read(sc, 25, &sc->bbp25); 4092 run_bbp_read(sc, 26, &sc->bbp26); 4093 4094 run_read(sc, RT3070_OPT_14, &tmp); 4095 run_write(sc, RT3070_OPT_14, tmp | 1); 4096 return (0); 4097 } 4098 4099 static int 4100 run_rt5390_rf_init(struct run_softc *sc) 4101 { 4102 uint32_t tmp; 4103 uint8_t rf; 4104 int i; 4105 4106 /* Toggle RF R2 to initiate calibration. */ 4107 if (sc->mac_ver == 0x5390) { 4108 run_rt3070_rf_read(sc, 2, &rf); 4109 run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); 4110 usbd_delay_ms(sc->sc_udev, 10); 4111 run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); 4112 } else { 4113 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4114 usbd_delay_ms(sc->sc_udev, 10); 4115 } 4116 4117 /* Initialize RF registers to default value. */ 4118 if (sc->mac_ver == 0x5592) { 4119 for (i = 0; i < __arraycount(rt5592_def_rf); i++) { 4120 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4121 rt5592_def_rf[i].val); 4122 } 4123 /* Initialize RF frequency offset. */ 4124 run_adjust_freq_offset(sc); 4125 } else if (sc->mac_ver == 0x5392) { 4126 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 4127 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4128 rt5392_def_rf[i].val); 4129 } 4130 if (sc->mac_rev >= 0x0223) { 4131 run_rt3070_rf_write(sc, 23, 0x0f); 4132 run_rt3070_rf_write(sc, 24, 0x3e); 4133 run_rt3070_rf_write(sc, 51, 0x32); 4134 run_rt3070_rf_write(sc, 53, 0x22); 4135 run_rt3070_rf_write(sc, 56, 0xc1); 4136 run_rt3070_rf_write(sc, 59, 0x0f); 4137 } 4138 } else { 4139 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 4140 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4141 rt5390_def_rf[i].val); 4142 } 4143 if (sc->mac_rev >= 0x0502) { 4144 run_rt3070_rf_write(sc, 6, 0xe0); 4145 run_rt3070_rf_write(sc, 25, 0x80); 4146 run_rt3070_rf_write(sc, 46, 0x73); 4147 run_rt3070_rf_write(sc, 53, 0x00); 4148 run_rt3070_rf_write(sc, 56, 0x42); 4149 run_rt3070_rf_write(sc, 61, 0xd1); 4150 } 4151 } 4152 4153 sc->rf24_20mhz = 0x1f; /* default value */ 4154 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4155 4156 if (sc->mac_rev < 0x0211) 4157 run_rt3070_rf_write(sc, 27, 0x3); 4158 4159 run_read(sc, RT3070_OPT_14, &tmp); 4160 run_write(sc, RT3070_OPT_14, tmp | 1); 4161 return (0); 4162 } 4163 4164 static int 4165 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4166 uint8_t *val) 4167 { 4168 uint8_t rf22, rf24; 4169 uint8_t bbp55_pb, bbp55_sb, delta; 4170 int ntries; 4171 4172 /* program filter */ 4173 run_rt3070_rf_read(sc, 24, &rf24); 4174 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4175 run_rt3070_rf_write(sc, 24, rf24); 4176 4177 /* enable baseband loopback mode */ 4178 run_rt3070_rf_read(sc, 22, &rf22); 4179 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4180 4181 /* set power and frequency of passband test tone */ 4182 run_bbp_write(sc, 24, 0x00); 4183 for (ntries = 0; ntries < 100; ntries++) { 4184 /* transmit test tone */ 4185 run_bbp_write(sc, 25, 0x90); 4186 usbd_delay_ms(sc->sc_udev, 10); 4187 /* read received power */ 4188 run_bbp_read(sc, 55, &bbp55_pb); 4189 if (bbp55_pb != 0) 4190 break; 4191 } 4192 if (ntries == 100) 4193 return ETIMEDOUT; 4194 4195 /* set power and frequency of stopband test tone */ 4196 run_bbp_write(sc, 24, 0x06); 4197 for (ntries = 0; ntries < 100; ntries++) { 4198 /* transmit test tone */ 4199 run_bbp_write(sc, 25, 0x90); 4200 usbd_delay_ms(sc->sc_udev, 10); 4201 /* read received power */ 4202 run_bbp_read(sc, 55, &bbp55_sb); 4203 4204 delta = bbp55_pb - bbp55_sb; 4205 if (delta > target) 4206 break; 4207 4208 /* reprogram filter */ 4209 rf24++; 4210 run_rt3070_rf_write(sc, 24, rf24); 4211 } 4212 if (ntries < 100) { 4213 if (rf24 != init) 4214 rf24--; /* backtrack */ 4215 *val = rf24; 4216 run_rt3070_rf_write(sc, 24, rf24); 4217 } 4218 4219 /* restore initial state */ 4220 run_bbp_write(sc, 24, 0x00); 4221 4222 /* disable baseband loopback mode */ 4223 run_rt3070_rf_read(sc, 22, &rf22); 4224 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4225 4226 return 0; 4227 } 4228 4229 static void 4230 run_rt3070_rf_setup(struct run_softc *sc) 4231 { 4232 uint8_t bbp, rf; 4233 int i; 4234 4235 if (sc->mac_ver == 0x3572) { 4236 /* enable DC filter */ 4237 if (sc->mac_rev >= 0x0201) 4238 run_bbp_write(sc, 103, 0xc0); 4239 4240 run_bbp_read(sc, 138, &bbp); 4241 if (sc->ntxchains == 1) 4242 bbp |= 0x20; /* turn off DAC1 */ 4243 if (sc->nrxchains == 1) 4244 bbp &= ~0x02; /* turn off ADC1 */ 4245 run_bbp_write(sc, 138, bbp); 4246 4247 if (sc->mac_rev >= 0x0211) { 4248 /* improve power consumption */ 4249 run_bbp_read(sc, 31, &bbp); 4250 run_bbp_write(sc, 31, bbp & ~0x03); 4251 } 4252 4253 run_rt3070_rf_read(sc, 16, &rf); 4254 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4255 run_rt3070_rf_write(sc, 16, rf); 4256 } else if (sc->mac_ver == 0x3071) { 4257 /* enable DC filter */ 4258 if (sc->mac_rev >= 0x0201) 4259 run_bbp_write(sc, 103, 0xc0); 4260 4261 run_bbp_read(sc, 138, &bbp); 4262 if (sc->ntxchains == 1) 4263 bbp |= 0x20; /* turn off DAC1 */ 4264 if (sc->nrxchains == 1) 4265 bbp &= ~0x02; /* turn off ADC1 */ 4266 run_bbp_write(sc, 138, bbp); 4267 4268 if (sc->mac_rev >= 0x0211) { 4269 /* improve power consumption */ 4270 run_bbp_read(sc, 31, &bbp); 4271 run_bbp_write(sc, 31, bbp & ~0x03); 4272 } 4273 4274 run_write(sc, RT2860_TX_SW_CFG1, 0); 4275 if (sc->mac_rev < 0x0211) { 4276 run_write(sc, RT2860_TX_SW_CFG2, 4277 sc->patch_dac ? 0x2c : 0x0f); 4278 } else 4279 run_write(sc, RT2860_TX_SW_CFG2, 0); 4280 } else if (sc->mac_ver == 0x3070) { 4281 if (sc->mac_rev >= 0x0201) { 4282 /* enable DC filter */ 4283 run_bbp_write(sc, 103, 0xc0); 4284 4285 /* improve power consumption */ 4286 run_bbp_read(sc, 31, &bbp); 4287 run_bbp_write(sc, 31, bbp & ~0x03); 4288 } 4289 4290 if (sc->mac_rev < 0x0211) { 4291 run_write(sc, RT2860_TX_SW_CFG1, 0); 4292 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4293 } else 4294 run_write(sc, RT2860_TX_SW_CFG2, 0); 4295 } 4296 4297 /* initialize RF registers from ROM for >=RT3071*/ 4298 if (sc->mac_ver >= 0x3071) { 4299 for (i = 0; i < 10; i++) { 4300 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4301 continue; 4302 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4303 } 4304 } 4305 } 4306 4307 static void 4308 run_rt3593_rf_setup(struct run_softc *sc) 4309 { 4310 uint8_t bbp, rf; 4311 4312 if (sc->mac_rev >= 0x0211) { 4313 /* Enable DC filter. */ 4314 run_bbp_write(sc, 103, 0xc0); 4315 } 4316 run_write(sc, RT2860_TX_SW_CFG1, 0); 4317 if (sc->mac_rev < 0x0211) { 4318 run_write(sc, RT2860_TX_SW_CFG2, 4319 sc->patch_dac ? 0x2c : 0x0f); 4320 } else 4321 run_write(sc, RT2860_TX_SW_CFG2, 0); 4322 4323 run_rt3070_rf_read(sc, 50, &rf); 4324 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4325 4326 run_rt3070_rf_read(sc, 51, &rf); 4327 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4328 ((sc->txmixgain_2ghz & 0x07) << 2); 4329 run_rt3070_rf_write(sc, 51, rf); 4330 4331 run_rt3070_rf_read(sc, 38, &rf); 4332 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4333 4334 run_rt3070_rf_read(sc, 39, &rf); 4335 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4336 4337 run_rt3070_rf_read(sc, 1, &rf); 4338 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4339 4340 run_rt3070_rf_read(sc, 30, &rf); 4341 rf = (rf & ~0x18) | 0x10; 4342 run_rt3070_rf_write(sc, 30, rf); 4343 4344 /* Apply maximum likelihood detection for 2 stream case. */ 4345 run_bbp_read(sc, 105, &bbp); 4346 if (sc->nrxchains > 1) 4347 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4348 4349 /* Avoid data lost and CRC error. */ 4350 run_bbp_read(sc, 4, &bbp); 4351 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4352 4353 run_bbp_write(sc, 92, 0x02); 4354 run_bbp_write(sc, 82, 0x82); 4355 run_bbp_write(sc, 106, 0x05); 4356 run_bbp_write(sc, 104, 0x92); 4357 run_bbp_write(sc, 88, 0x90); 4358 run_bbp_write(sc, 148, 0xc8); 4359 run_bbp_write(sc, 47, 0x48); 4360 run_bbp_write(sc, 120, 0x50); 4361 4362 run_bbp_write(sc, 163, 0x9d); 4363 4364 /* SNR mapping. */ 4365 run_bbp_write(sc, 142, 0x06); 4366 run_bbp_write(sc, 143, 0xa0); 4367 run_bbp_write(sc, 142, 0x07); 4368 run_bbp_write(sc, 143, 0xa1); 4369 run_bbp_write(sc, 142, 0x08); 4370 run_bbp_write(sc, 143, 0xa2); 4371 4372 run_bbp_write(sc, 31, 0x08); 4373 run_bbp_write(sc, 68, 0x0b); 4374 run_bbp_write(sc, 105, 0x04); 4375 } 4376 4377 static void 4378 run_rt5390_rf_setup(struct run_softc *sc) 4379 { 4380 uint8_t bbp, rf; 4381 4382 if (sc->mac_rev >= 0x0211) { 4383 /* Enable DC filter. */ 4384 run_bbp_write(sc, 103, 0xc0); 4385 4386 if (sc->mac_ver != 0x5592) { 4387 /* Improve power consumption. */ 4388 run_bbp_read(sc, 31, &bbp); 4389 run_bbp_write(sc, 31, bbp & ~0x03); 4390 } 4391 } 4392 4393 run_bbp_read(sc, 138, &bbp); 4394 if (sc->ntxchains == 1) 4395 bbp |= 0x20; /* turn off DAC1 */ 4396 if (sc->nrxchains == 1) 4397 bbp &= ~0x02; /* turn off ADC1 */ 4398 run_bbp_write(sc, 138, bbp); 4399 4400 run_rt3070_rf_read(sc, 38, &rf); 4401 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4402 4403 run_rt3070_rf_read(sc, 39, &rf); 4404 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4405 4406 /* Avoid data lost and CRC error. */ 4407 run_bbp_read(sc, 4, &bbp); 4408 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4409 4410 run_rt3070_rf_read(sc, 30, &rf); 4411 rf = (rf & ~0x18) | 0x10; 4412 run_rt3070_rf_write(sc, 30, rf); 4413 4414 if (sc->mac_ver != 0x5592) { 4415 run_write(sc, RT2860_TX_SW_CFG1, 0); 4416 if (sc->mac_rev < 0x0211) { 4417 run_write(sc, RT2860_TX_SW_CFG2, 4418 sc->patch_dac ? 0x2c : 0x0f); 4419 } else 4420 run_write(sc, RT2860_TX_SW_CFG2, 0); 4421 } 4422 } 4423 4424 static int 4425 run_txrx_enable(struct run_softc *sc) 4426 { 4427 uint32_t tmp; 4428 int error, ntries; 4429 4430 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4431 for (ntries = 0; ntries < 200; ntries++) { 4432 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4433 return error; 4434 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4435 break; 4436 usbd_delay_ms(sc->sc_udev, 50); 4437 } 4438 if (ntries == 200) 4439 return ETIMEDOUT; 4440 4441 usbd_delay_ms(sc->sc_udev, 50); 4442 4443 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4444 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4445 4446 /* enable Rx bulk aggregation (set timeout and limit) */ 4447 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4448 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4449 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4450 4451 /* set Rx filter */ 4452 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4453 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4454 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4455 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4456 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4457 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4458 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4459 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4460 } 4461 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4462 4463 run_write(sc, RT2860_MAC_SYS_CTRL, 4464 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4465 4466 return 0; 4467 } 4468 4469 static int 4470 run_adjust_freq_offset(struct run_softc *sc) 4471 { 4472 uint8_t rf, tmp; 4473 4474 run_rt3070_rf_read(sc, 17, &rf); 4475 tmp = rf; 4476 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4477 rf = MIN(rf, 0x5f); 4478 4479 if (tmp != rf) 4480 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4481 4482 return (0); 4483 } 4484 4485 static int 4486 run_init(struct ifnet *ifp) 4487 { 4488 struct run_softc *sc = ifp->if_softc; 4489 struct ieee80211com *ic = &sc->sc_ic; 4490 uint32_t tmp; 4491 uint8_t bbp1, bbp3; 4492 int i, error, qid, ridx, ntries; 4493 4494 for (ntries = 0; ntries < 100; ntries++) { 4495 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4496 goto fail; 4497 if (tmp != 0 && tmp != 0xffffffff) 4498 break; 4499 usbd_delay_ms(sc->sc_udev, 10); 4500 } 4501 if (ntries == 100) { 4502 error = ETIMEDOUT; 4503 goto fail; 4504 } 4505 4506 if ((sc->sc_flags & RUN_FWLOADED) == 0 && 4507 (error = run_load_microcode(sc)) != 0) { 4508 aprint_error_dev(sc->sc_dev, 4509 "could not load 8051 microcode\n"); 4510 goto fail; 4511 } 4512 4513 if (ifp->if_flags & IFF_RUNNING) 4514 run_stop(ifp, 0); 4515 4516 /* init host command ring */ 4517 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4518 4519 /* init Tx rings (4 EDCAs) */ 4520 for (qid = 0; qid < 4; qid++) { 4521 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4522 goto fail; 4523 } 4524 /* init Rx ring */ 4525 if ((error = run_alloc_rx_ring(sc)) != 0) 4526 goto fail; 4527 4528 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4529 run_set_macaddr(sc, ic->ic_myaddr); 4530 4531 for (ntries = 0; ntries < 100; ntries++) { 4532 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4533 goto fail; 4534 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4535 break; 4536 usbd_delay_ms(sc->sc_udev, 10); 4537 } 4538 if (ntries == 100) { 4539 aprint_error_dev(sc->sc_dev, 4540 "timeout waiting for DMA engine\n"); 4541 error = ETIMEDOUT; 4542 goto fail; 4543 } 4544 tmp &= 0xff0; 4545 tmp |= RT2860_TX_WB_DDONE; 4546 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4547 4548 /* turn off PME_OEN to solve high-current issue */ 4549 run_read(sc, RT2860_SYS_CTRL, &tmp); 4550 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4551 4552 run_write(sc, RT2860_MAC_SYS_CTRL, 4553 RT2860_BBP_HRST | RT2860_MAC_SRST); 4554 run_write(sc, RT2860_USB_DMA_CFG, 0); 4555 4556 if ((error = run_reset(sc)) != 0) { 4557 aprint_error_dev(sc->sc_dev, "could not reset chipset\n"); 4558 goto fail; 4559 } 4560 4561 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4562 4563 /* init Tx power for all Tx rates (from EEPROM) */ 4564 for (ridx = 0; ridx < 5; ridx++) { 4565 if (sc->txpow20mhz[ridx] == 0xffffffff) 4566 continue; 4567 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4568 } 4569 4570 for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) 4571 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4572 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4573 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4574 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4575 4576 if (sc->mac_ver >= 0x5390) { 4577 run_write(sc, RT2860_TX_SW_CFG0, 4578 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4579 if (sc->mac_ver >= 0x5392) { 4580 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4581 if (sc->mac_ver == 0x5592) { 4582 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4583 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4584 } else { 4585 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4586 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4587 } 4588 } 4589 } else if (sc->mac_ver >= 0x3593) { 4590 run_write(sc, RT2860_TX_SW_CFG0, 4591 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4592 } else if (sc->mac_ver >= 0x3070) { 4593 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4594 run_write(sc, RT2860_TX_SW_CFG0, 4595 4 << RT2860_DLY_PAPE_EN_SHIFT); 4596 } 4597 4598 /* wait while MAC is busy */ 4599 for (ntries = 0; ntries < 100; ntries++) { 4600 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4601 goto fail; 4602 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4603 break; 4604 DELAY(1000); 4605 } 4606 if (ntries == 100) { 4607 error = ETIMEDOUT; 4608 goto fail; 4609 } 4610 4611 /* clear Host to MCU mailbox */ 4612 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4613 run_write(sc, RT2860_H2M_MAILBOX, 0); 4614 usbd_delay_ms(sc->sc_udev, 10); 4615 4616 if ((error = run_bbp_init(sc)) != 0) { 4617 aprint_error_dev(sc->sc_dev, "could not initialize BBP\n"); 4618 goto fail; 4619 } 4620 4621 /* abort TSF synchronization */ 4622 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4623 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4624 RT2860_TBTT_TIMER_EN); 4625 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4626 4627 /* clear RX WCID search table */ 4628 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4629 /* clear Pair-wise key table */ 4630 run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); 4631 /* clear IV/EIV table */ 4632 run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); 4633 /* clear WCID attribute table */ 4634 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4635 /* clear shared key table */ 4636 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4637 /* clear shared key mode */ 4638 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4639 4640 /* clear RX WCID search table */ 4641 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4642 /* clear WCID attribute table */ 4643 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4644 4645 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4646 tmp = (tmp & ~0xff) | 0x1e; 4647 run_write(sc, RT2860_US_CYC_CNT, tmp); 4648 4649 if (sc->mac_rev != 0x0101) 4650 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4651 4652 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4653 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4654 4655 /* write vendor-specific BBP values (from EEPROM) */ 4656 if (sc->mac_ver < 0x3593) { 4657 for (i = 0; i < 10; i++) { 4658 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4659 continue; 4660 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4661 } 4662 } 4663 4664 /* select Main antenna for 1T1R devices */ 4665 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4666 run_set_rx_antenna(sc, 0); 4667 4668 /* send LEDs operating mode to microcontroller */ 4669 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4670 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4671 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4672 4673 if (sc->mac_ver >= 0x5390) 4674 run_rt5390_rf_init(sc); 4675 else if (sc->mac_ver == 0x3593) 4676 run_rt3593_rf_init(sc); 4677 else if (sc->mac_ver >= 0x3070) 4678 run_rt3070_rf_init(sc); 4679 4680 /* disable non-existing Rx chains */ 4681 run_bbp_read(sc, 3, &bbp3); 4682 bbp3 &= ~(1 << 3 | 1 << 4); 4683 if (sc->nrxchains == 2) 4684 bbp3 |= 1 << 3; 4685 else if (sc->nrxchains == 3) 4686 bbp3 |= 1 << 4; 4687 run_bbp_write(sc, 3, bbp3); 4688 4689 /* disable non-existing Tx chains */ 4690 run_bbp_read(sc, 1, &bbp1); 4691 if (sc->ntxchains == 1) 4692 bbp1 &= ~(1 << 3 | 1 << 4); 4693 run_bbp_write(sc, 1, bbp1); 4694 4695 if (sc->mac_ver >= 0x5390) 4696 run_rt5390_rf_setup(sc); 4697 else if (sc->mac_ver == 0x3593) 4698 run_rt3593_rf_setup(sc); 4699 else if (sc->mac_ver >= 0x3070) 4700 run_rt3070_rf_setup(sc); 4701 4702 /* select default channel */ 4703 run_set_chan(sc, ic->ic_curchan); 4704 4705 /* setup initial protection mode */ 4706 run_updateprot(sc); 4707 4708 /* turn radio LED on */ 4709 run_set_leds(sc, RT2860_LED_RADIO); 4710 4711 #ifdef RUN_HWCRYPTO 4712 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4713 /* install WEP keys */ 4714 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4715 (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], 4716 NULL); 4717 } 4718 #endif 4719 4720 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4721 struct run_rx_data *data = &sc->rxq.data[i]; 4722 4723 usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, 4724 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 4725 error = usbd_transfer(data->xfer); 4726 if (error != USBD_NORMAL_COMPLETION && 4727 error != USBD_IN_PROGRESS) 4728 goto fail; 4729 } 4730 4731 if ((error = run_txrx_enable(sc)) != 0) 4732 goto fail; 4733 4734 ifp->if_flags &= ~IFF_OACTIVE; 4735 ifp->if_flags |= IFF_RUNNING; 4736 4737 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4738 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4739 else 4740 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4741 4742 if (error != 0) 4743 fail: run_stop(ifp, 1); 4744 return error; 4745 } 4746 4747 static void 4748 run_stop(struct ifnet *ifp, int disable) 4749 { 4750 struct run_softc *sc = ifp->if_softc; 4751 struct ieee80211com *ic = &sc->sc_ic; 4752 uint32_t tmp; 4753 int ntries, qid; 4754 4755 if (ifp->if_flags & IFF_RUNNING) 4756 run_set_leds(sc, 0); /* turn all LEDs off */ 4757 4758 sc->sc_tx_timer = 0; 4759 ifp->if_timer = 0; 4760 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4761 4762 callout_stop(&sc->scan_to); 4763 callout_stop(&sc->calib_to); 4764 4765 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4766 /* wait for all queued asynchronous commands to complete */ 4767 while (sc->cmdq.queued > 0) 4768 tsleep(&sc->cmdq, 0, "cmdq", 0); 4769 4770 /* disable Tx/Rx */ 4771 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4772 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4773 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4774 4775 /* wait for pending Tx to complete */ 4776 for (ntries = 0; ntries < 100; ntries++) { 4777 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4778 break; 4779 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4780 break; 4781 } 4782 DELAY(1000); 4783 run_write(sc, RT2860_USB_DMA_CFG, 0); 4784 4785 /* reset adapter */ 4786 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4787 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4788 4789 /* reset Tx and Rx rings */ 4790 sc->qfullmsk = 0; 4791 for (qid = 0; qid < 4; qid++) 4792 run_free_tx_ring(sc, qid); 4793 run_free_rx_ring(sc); 4794 } 4795 4796 #ifndef IEEE80211_STA_ONLY 4797 static int 4798 run_setup_beacon(struct run_softc *sc) 4799 { 4800 struct ieee80211com *ic = &sc->sc_ic; 4801 struct rt2860_txwi txwi; 4802 struct mbuf *m; 4803 uint16_t txwisize; 4804 int ridx; 4805 4806 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4807 return ENOBUFS; 4808 4809 memset(&txwi, 0, sizeof(txwi)); 4810 txwi.wcid = 0xff; 4811 txwi.len = htole16(m->m_pkthdr.len); 4812 /* send beacons at the lowest available rate */ 4813 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4814 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4815 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4816 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4817 txwi.phy |= htole16(RT2860_PHY_OFDM); 4818 txwi.txop = RT2860_TX_TXOP_HT; 4819 txwi.flags = RT2860_TX_TS; 4820 4821 txwisize = (sc->mac_ver == 0x5592) ? 4822 sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); 4823 run_write_region_1(sc, RT2860_BCN_BASE(0), 4824 (uint8_t *)&txwi, txwisize); 4825 run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, 4826 mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); 4827 4828 m_freem(m); 4829 4830 return 0; 4831 } 4832 #endif 4833 4834 MODULE(MODULE_CLASS_DRIVER, if_run, "bpf"); 4835 4836 #ifdef _MODULE 4837 #include "ioconf.c" 4838 #endif 4839 4840 static int 4841 if_run_modcmd(modcmd_t cmd, void *arg) 4842 { 4843 int error = 0; 4844 4845 switch (cmd) { 4846 case MODULE_CMD_INIT: 4847 #ifdef _MODULE 4848 error = config_init_component(cfdriver_ioconf_run, 4849 cfattach_ioconf_run, cfdata_ioconf_run); 4850 #endif 4851 return error; 4852 case MODULE_CMD_FINI: 4853 #ifdef _MODULE 4854 error = config_fini_component(cfdriver_ioconf_run, 4855 cfattach_ioconf_run, cfdata_ioconf_run); 4856 #endif 4857 return error; 4858 default: 4859 return ENOTTY; 4860 } 4861 } 4862
Indexes created Thu Oct 02 10:09:58 GMT 2025