if_run.c revision 1.31
1 /* $NetBSD: if_run.c,v 1.31 2018/11/29 18:53:42 jakllsch Exp $ */ 2 /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.31 2018/11/29 18:53:42 jakllsch Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_usb.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/device.h> 44 45 #include <sys/bus.h> 46 #include <machine/endian.h> 47 #include <sys/intr.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_ether.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #include <net80211/ieee80211_var.h> 58 #include <net80211/ieee80211_amrr.h> 59 #include <net80211/ieee80211_radiotap.h> 60 61 #include <dev/firmload.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 #include <dev/usb/usbdivar.h> 66 #include <dev/usb/usbdi_util.h> 67 #include <dev/usb/usbdevs.h> 68 69 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 70 #include <dev/usb/if_runvar.h> 71 72 #ifdef RUN_DEBUG 73 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 74 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 75 int run_debug = 0; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n, x) 79 #endif 80 81 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 82 83 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 84 static const struct usb_devno run_devs[] = { 85 USB_ID(ABOCOM, RT2770), 86 USB_ID(ABOCOM, RT2870), 87 USB_ID(ABOCOM, RT3070), 88 USB_ID(ABOCOM, RT3071), 89 USB_ID(ABOCOM, RT3072), 90 USB_ID(ABOCOM2, RT2870_1), 91 USB_ID(ACCTON, RT2770), 92 USB_ID(ACCTON, RT2870_1), 93 USB_ID(ACCTON, RT2870_2), 94 USB_ID(ACCTON, RT2870_3), 95 USB_ID(ACCTON, RT2870_4), 96 USB_ID(ACCTON, RT2870_5), 97 USB_ID(ACCTON, RT3070), 98 USB_ID(ACCTON, RT3070_1), 99 USB_ID(ACCTON, RT3070_2), 100 USB_ID(ACCTON, RT3070_3), 101 USB_ID(ACCTON, RT3070_4), 102 USB_ID(ACCTON, RT3070_5), 103 USB_ID(ACCTON, RT3070_6), 104 USB_ID(AIRTIES, RT3070), 105 USB_ID(AIRTIES, RT3070_2), 106 USB_ID(ALLWIN, RT2070), 107 USB_ID(ALLWIN, RT2770), 108 USB_ID(ALLWIN, RT2870), 109 USB_ID(ALLWIN, RT3070), 110 USB_ID(ALLWIN, RT3071), 111 USB_ID(ALLWIN, RT3072), 112 USB_ID(ALLWIN, RT3572), 113 USB_ID(AMIGO, RT2870_1), 114 USB_ID(AMIGO, RT2870_2), 115 USB_ID(AMIT, CGWLUSB2GNR), 116 USB_ID(AMIT, RT2870_1), 117 USB_ID(AMIT2, RT2870), 118 USB_ID(ASUSTEK, RT2870_1), 119 USB_ID(ASUSTEK, RT2870_2), 120 USB_ID(ASUSTEK, RT2870_3), 121 USB_ID(ASUSTEK, RT2870_4), 122 USB_ID(ASUSTEK, RT2870_5), 123 USB_ID(ASUSTEK, RT3070), 124 USB_ID(ASUSTEK, RT3070_1), 125 USB_ID(ASUSTEK2, USBN11), 126 USB_ID(AZUREWAVE, RT2870_1), 127 USB_ID(AZUREWAVE, RT2870_2), 128 USB_ID(AZUREWAVE, RT3070), 129 USB_ID(AZUREWAVE, RT3070_2), 130 USB_ID(AZUREWAVE, RT3070_3), 131 USB_ID(AZUREWAVE, RT3070_4), 132 USB_ID(AZUREWAVE, RT3070_5), 133 USB_ID(BELKIN, F5D8053V3), 134 USB_ID(BELKIN, F5D8055), 135 USB_ID(BELKIN, F5D8055V2), 136 USB_ID(BELKIN, F6D4050V1), 137 USB_ID(BELKIN, F6D4050V2), 138 USB_ID(BELKIN, F7D1101V2), 139 USB_ID(BELKIN, RT2870_1), 140 USB_ID(BELKIN, RT2870_2), 141 USB_ID(BEWAN, RT3070), 142 USB_ID(CISCOLINKSYS, AE1000), 143 USB_ID(CISCOLINKSYS, AM10), 144 USB_ID(CISCOLINKSYS2, RT3070), 145 USB_ID(CISCOLINKSYS3, RT3070), 146 USB_ID(CONCEPTRONIC, RT2870_1), 147 USB_ID(CONCEPTRONIC, RT2870_2), 148 USB_ID(CONCEPTRONIC, RT2870_3), 149 USB_ID(CONCEPTRONIC, RT2870_4), 150 USB_ID(CONCEPTRONIC, RT2870_5), 151 USB_ID(CONCEPTRONIC, RT2870_6), 152 USB_ID(CONCEPTRONIC, RT2870_7), 153 USB_ID(CONCEPTRONIC, RT2870_8), 154 USB_ID(CONCEPTRONIC, RT3070_1), 155 USB_ID(CONCEPTRONIC, RT3070_2), 156 USB_ID(CONCEPTRONIC, RT3070_3), 157 USB_ID(COREGA, CGWLUSB300GNM), 158 USB_ID(COREGA, RT2870_1), 159 USB_ID(COREGA, RT2870_2), 160 USB_ID(COREGA, RT2870_3), 161 USB_ID(COREGA, RT3070), 162 USB_ID(CYBERTAN, RT2870), 163 USB_ID(DLINK, RT2870), 164 USB_ID(DLINK, RT3072), 165 USB_ID(DLINK2, DWA130), 166 USB_ID(DLINK2, RT2870_1), 167 USB_ID(DLINK2, RT2870_2), 168 USB_ID(DLINK2, RT3070_1), 169 USB_ID(DLINK2, RT3070_2), 170 USB_ID(DLINK2, RT3070_3), 171 USB_ID(DLINK2, RT3070_4), 172 USB_ID(DLINK2, RT3070_5), 173 USB_ID(DLINK2, RT3072), 174 USB_ID(DLINK2, RT3072_1), 175 USB_ID(DVICO, RT3070), 176 USB_ID(EDIMAX, EW7717), 177 USB_ID(EDIMAX, EW7718), 178 USB_ID(EDIMAX, EW7722UTN), 179 USB_ID(EDIMAX, RT2870_1), 180 USB_ID(ENCORE, RT3070), 181 USB_ID(ENCORE, RT3070_2), 182 USB_ID(ENCORE, RT3070_3), 183 USB_ID(GIGABYTE, GNWB31N), 184 USB_ID(GIGABYTE, GNWB32L), 185 USB_ID(GIGABYTE, RT2870_1), 186 USB_ID(GIGASET, RT3070_1), 187 USB_ID(GIGASET, RT3070_2), 188 USB_ID(GUILLEMOT, HWNU300), 189 USB_ID(HAWKING, HWUN2), 190 USB_ID(HAWKING, RT2870_1), 191 USB_ID(HAWKING, RT2870_2), 192 USB_ID(HAWKING, RT2870_3), 193 USB_ID(HAWKING, RT2870_4), 194 USB_ID(HAWKING, RT2870_5), 195 USB_ID(HAWKING, RT3070), 196 USB_ID(IODATA, RT3072_1), 197 USB_ID(IODATA, RT3072_2), 198 USB_ID(IODATA, RT3072_3), 199 USB_ID(IODATA, RT3072_4), 200 USB_ID(LINKSYS4, RT3070), 201 USB_ID(LINKSYS4, WUSB100), 202 USB_ID(LINKSYS4, WUSB54GC_3), 203 USB_ID(LINKSYS4, WUSB600N), 204 USB_ID(LINKSYS4, WUSB600NV2), 205 USB_ID(LOGITEC, LANW300NU2), 206 USB_ID(LOGITEC, RT2870_1), 207 USB_ID(LOGITEC, RT2870_2), 208 USB_ID(LOGITEC, RT2870_3), 209 USB_ID(LOGITEC, RT3020), 210 USB_ID(MELCO, RT2870_1), 211 USB_ID(MELCO, RT2870_2), 212 USB_ID(MELCO, WLIUCAG300N), 213 USB_ID(MELCO, WLIUCG300N), 214 USB_ID(MELCO, WLIUCG301N), 215 USB_ID(MELCO, WLIUCGN), 216 USB_ID(MELCO, WLIUCGNHP), 217 USB_ID(MELCO, WLIUCGNM), 218 USB_ID(MELCO, WLIUCGNM2T), 219 USB_ID(MOTOROLA4, RT2770), 220 USB_ID(MOTOROLA4, RT3070), 221 USB_ID(MSI, RT3070), 222 USB_ID(MSI, RT3070_2), 223 USB_ID(MSI, RT3070_3), 224 USB_ID(MSI, RT3070_4), 225 USB_ID(MSI, RT3070_5), 226 USB_ID(MSI, RT3070_6), 227 USB_ID(MSI, RT3070_7), 228 USB_ID(MSI, RT3070_8), 229 USB_ID(MSI, RT3070_9), 230 USB_ID(MSI, RT3070_10), 231 USB_ID(MSI, RT3070_11), 232 USB_ID(MSI, RT3070_12), 233 USB_ID(MSI, RT3070_13), 234 USB_ID(MSI, RT3070_14), 235 USB_ID(MSI, RT3070_15), 236 USB_ID(OVISLINK, RT3071), 237 USB_ID(OVISLINK, RT3072), 238 USB_ID(PARA, RT3070), 239 USB_ID(PEGATRON, RT2870), 240 USB_ID(PEGATRON, RT3070), 241 USB_ID(PEGATRON, RT3070_2), 242 USB_ID(PEGATRON, RT3070_3), 243 USB_ID(PEGATRON, RT3072), 244 USB_ID(PHILIPS, RT2870), 245 USB_ID(PLANEX2, GWUS300MINIS), 246 USB_ID(PLANEX2, GWUSMICRO300), 247 USB_ID(PLANEX2, GWUSMICRON), 248 USB_ID(PLANEX2, GWUS300MINIX), 249 USB_ID(PLANEX2, RT3070), 250 USB_ID(QCOM, RT2870), 251 USB_ID(QUANTA, RT3070), 252 USB_ID(RALINK, RT2070), 253 USB_ID(RALINK, RT2770), 254 USB_ID(RALINK, RT2870), 255 USB_ID(RALINK, RT3070), 256 USB_ID(RALINK, RT3071), 257 USB_ID(RALINK, RT3072), 258 USB_ID(RALINK, RT3370), 259 USB_ID(RALINK, RT3572), 260 USB_ID(RALINK, RT5370), 261 USB_ID(RALINK, RT5572), 262 USB_ID(RALINK, RT8070), 263 USB_ID(SAMSUNG, RT2870_1), 264 USB_ID(SENAO, RT2870_1), 265 USB_ID(SENAO, RT2870_2), 266 USB_ID(SENAO, RT2870_3), 267 USB_ID(SENAO, RT2870_4), 268 USB_ID(SENAO, RT3070), 269 USB_ID(SENAO, RT3071), 270 USB_ID(SENAO, RT3072), 271 USB_ID(SENAO, RT3072_2), 272 USB_ID(SENAO, RT3072_3), 273 USB_ID(SENAO, RT3072_4), 274 USB_ID(SENAO, RT3072_5), 275 USB_ID(SITECOMEU, RT2870_1), 276 USB_ID(SITECOMEU, RT2870_2), 277 USB_ID(SITECOMEU, RT2870_3), 278 USB_ID(SITECOMEU, RT3070_1), 279 USB_ID(SITECOMEU, RT3072_3), 280 USB_ID(SITECOMEU, RT3072_4), 281 USB_ID(SITECOMEU, RT3072_5), 282 USB_ID(SITECOMEU, WL302), 283 USB_ID(SITECOMEU, WL315), 284 USB_ID(SITECOMEU, WL321), 285 USB_ID(SITECOMEU, WL324), 286 USB_ID(SITECOMEU, WL329), 287 USB_ID(SITECOMEU, WL343), 288 USB_ID(SITECOMEU, WL344), 289 USB_ID(SITECOMEU, WL345), 290 USB_ID(SITECOMEU, WL349V4), 291 USB_ID(SITECOMEU, WL608), 292 USB_ID(SITECOMEU, WLA4000), 293 USB_ID(SITECOMEU, WLA5000), 294 USB_ID(SPARKLAN, RT2870_1), 295 USB_ID(SPARKLAN, RT2870_2), 296 USB_ID(SPARKLAN, RT3070), 297 USB_ID(SWEEX2, LW153), 298 USB_ID(SWEEX2, LW303), 299 USB_ID(SWEEX2, LW313), 300 USB_ID(TOSHIBA, RT3070), 301 USB_ID(UMEDIA, RT2870_1), 302 USB_ID(UMEDIA, TEW645UB), 303 USB_ID(ZCOM, RT2870_1), 304 USB_ID(ZCOM, RT2870_2), 305 USB_ID(ZINWELL, RT2870_1), 306 USB_ID(ZINWELL, RT2870_2), 307 USB_ID(ZINWELL, RT3070), 308 USB_ID(ZINWELL, RT3072), 309 USB_ID(ZINWELL, RT3072_2), 310 USB_ID(ZYXEL, NWD2105), 311 USB_ID(ZYXEL, NWD211AN), 312 USB_ID(ZYXEL, RT2870_1), 313 USB_ID(ZYXEL, RT2870_2), 314 USB_ID(ZYXEL, RT3070), 315 }; 316 317 static int run_match(device_t, cfdata_t, void *); 318 static void run_attach(device_t, device_t, void *); 319 static int run_detach(device_t, int); 320 static int run_activate(device_t, enum devact); 321 322 CFATTACH_DECL_NEW(run, sizeof(struct run_softc), 323 run_match, run_attach, run_detach, run_activate); 324 325 static int run_alloc_rx_ring(struct run_softc *); 326 static void run_free_rx_ring(struct run_softc *); 327 static int run_alloc_tx_ring(struct run_softc *, int); 328 static void run_free_tx_ring(struct run_softc *, int); 329 static int run_load_microcode(struct run_softc *); 330 static int run_reset(struct run_softc *); 331 static int run_read(struct run_softc *, uint16_t, uint32_t *); 332 static int run_read_region_1(struct run_softc *, uint16_t, 333 uint8_t *, int); 334 static int run_write_2(struct run_softc *, uint16_t, uint16_t); 335 static int run_write(struct run_softc *, uint16_t, uint32_t); 336 static int run_write_region_1(struct run_softc *, uint16_t, 337 const uint8_t *, int); 338 static int run_set_region_4(struct run_softc *, uint16_t, 339 uint32_t, int); 340 static int run_efuse_read(struct run_softc *, uint16_t, 341 uint16_t *, int); 342 static int run_efuse_read_2(struct run_softc *, uint16_t, 343 uint16_t *); 344 static int run_eeprom_read_2(struct run_softc *, uint16_t, 345 uint16_t *); 346 static int run_rt2870_rf_write(struct run_softc *, uint8_t, 347 uint32_t); 348 static int run_rt3070_rf_read(struct run_softc *, uint8_t, 349 uint8_t *); 350 static int run_rt3070_rf_write(struct run_softc *, uint8_t, 351 uint8_t); 352 static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 353 static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 354 static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 355 static const char * run_get_rf(int); 356 static void run_rt3593_get_txpower(struct run_softc *); 357 static void run_get_txpower(struct run_softc *); 358 static int run_read_eeprom(struct run_softc *); 359 static struct ieee80211_node * 360 run_node_alloc(struct ieee80211_node_table *); 361 static int run_media_change(struct ifnet *); 362 static void run_next_scan(void *); 363 static void run_task(void *); 364 static void run_do_async(struct run_softc *, 365 void (*)(struct run_softc *, void *), void *, int); 366 static int run_newstate(struct ieee80211com *, 367 enum ieee80211_state, int); 368 static void run_newstate_cb(struct run_softc *, void *); 369 static int run_updateedca(struct ieee80211com *); 370 static void run_updateedca_cb(struct run_softc *, void *); 371 #ifdef RUN_HWCRYPTO 372 static int run_set_key(struct ieee80211com *, 373 const struct ieee80211_key *, const uint8_t *); 374 static void run_set_key_cb(struct run_softc *, void *); 375 static int run_delete_key(struct ieee80211com *, 376 const struct ieee80211_key *); 377 static void run_delete_key_cb(struct run_softc *, void *); 378 #endif 379 static void run_calibrate_to(void *); 380 static void run_calibrate_cb(struct run_softc *, void *); 381 static void run_newassoc(struct ieee80211_node *, int); 382 static void run_rx_frame(struct run_softc *, uint8_t *, int); 383 static void run_rxeof(struct usbd_xfer *, void *, 384 usbd_status); 385 static void run_txeof(struct usbd_xfer *, void *, 386 usbd_status); 387 static int run_tx(struct run_softc *, struct mbuf *, 388 struct ieee80211_node *); 389 static void run_start(struct ifnet *); 390 static void run_watchdog(struct ifnet *); 391 static int run_ioctl(struct ifnet *, u_long, void *); 392 static void run_select_chan_group(struct run_softc *, int); 393 static void run_iq_calib(struct run_softc *, u_int); 394 static void run_set_agc(struct run_softc *, uint8_t); 395 static void run_set_rx_antenna(struct run_softc *, int); 396 static void run_rt2870_set_chan(struct run_softc *, u_int); 397 static void run_rt3070_set_chan(struct run_softc *, u_int); 398 static void run_rt3572_set_chan(struct run_softc *, u_int); 399 static void run_rt3593_set_chan(struct run_softc *, u_int); 400 static void run_rt5390_set_chan(struct run_softc *, u_int); 401 static void run_rt5592_set_chan(struct run_softc *, u_int); 402 static int run_set_chan(struct run_softc *, 403 struct ieee80211_channel *); 404 static void run_updateprot(struct run_softc *); 405 static void run_enable_tsf_sync(struct run_softc *); 406 static void run_enable_mrr(struct run_softc *); 407 static void run_set_txpreamble(struct run_softc *); 408 static void run_set_basicrates(struct run_softc *); 409 static void run_set_leds(struct run_softc *, uint16_t); 410 static void run_set_bssid(struct run_softc *, const uint8_t *); 411 static void run_set_macaddr(struct run_softc *, const uint8_t *); 412 static void run_updateslot(struct ifnet *); 413 static void run_updateslot_cb(struct run_softc *, void *); 414 static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 415 static void run_rt5390_bbp_init(struct run_softc *); 416 static int run_bbp_init(struct run_softc *); 417 static int run_rt3070_rf_init(struct run_softc *); 418 static int run_rt3593_rf_init(struct run_softc *); 419 static int run_rt5390_rf_init(struct run_softc *); 420 static int run_rt3070_filter_calib(struct run_softc *, uint8_t, 421 uint8_t, uint8_t *); 422 static void run_rt3070_rf_setup(struct run_softc *); 423 static void run_rt3593_rf_setup(struct run_softc *); 424 static void run_rt5390_rf_setup(struct run_softc *); 425 static int run_txrx_enable(struct run_softc *); 426 static int run_adjust_freq_offset(struct run_softc *); 427 static int run_init(struct ifnet *); 428 static void run_stop(struct ifnet *, int); 429 #ifndef IEEE80211_STA_ONLY 430 static int run_setup_beacon(struct run_softc *); 431 #endif 432 433 static const struct { 434 uint32_t reg; 435 uint32_t val; 436 } rt2870_def_mac[] = { 437 RT2870_DEF_MAC 438 }; 439 440 static const struct { 441 uint8_t reg; 442 uint8_t val; 443 } rt2860_def_bbp[] = { 444 RT2860_DEF_BBP 445 }, rt5390_def_bbp[] = { 446 RT5390_DEF_BBP 447 }, rt5592_def_bbp[] = { 448 RT5592_DEF_BBP 449 }; 450 451 /* 452 * Default values for BBP register R196 for RT5592. 453 */ 454 static const uint8_t rt5592_bbp_r196[] = { 455 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 456 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 457 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 458 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 459 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 460 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 462 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 463 0x2e, 0x36, 0x30, 0x6e 464 }; 465 466 static const struct rfprog { 467 uint8_t chan; 468 uint32_t r1, r2, r3, r4; 469 } rt2860_rf2850[] = { 470 RT2860_RF2850 471 }; 472 473 static const struct { 474 uint8_t n, r, k; 475 } rt3070_freqs[] = { 476 RT3070_RF3052 477 }; 478 479 static const struct rt5592_freqs { 480 uint16_t n; 481 uint8_t k, m, r; 482 } rt5592_freqs_20mhz[] = { 483 RT5592_RF5592_20MHZ 484 },rt5592_freqs_40mhz[] = { 485 RT5592_RF5592_40MHZ 486 }; 487 488 static const struct { 489 uint8_t reg; 490 uint8_t val; 491 } rt3070_def_rf[] = { 492 RT3070_DEF_RF 493 }, rt3572_def_rf[] = { 494 RT3572_DEF_RF 495 },rt3593_def_rf[] = { 496 RT3593_DEF_RF 497 },rt5390_def_rf[] = { 498 RT5390_DEF_RF 499 },rt5392_def_rf[] = { 500 RT5392_DEF_RF 501 },rt5592_def_rf[] = { 502 RT5592_DEF_RF 503 },rt5592_2ghz_def_rf[] = { 504 RT5592_2GHZ_DEF_RF 505 },rt5592_5ghz_def_rf[] = { 506 RT5592_5GHZ_DEF_RF 507 }; 508 509 static const struct { 510 u_int firstchan; 511 u_int lastchan; 512 uint8_t reg; 513 uint8_t val; 514 } rt5592_chan_5ghz[] = { 515 RT5592_CHAN_5GHZ 516 }; 517 518 static int 519 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 520 size_t *sizep) 521 { 522 firmware_handle_t fh; 523 int error; 524 525 if ((error = firmware_open(dname, iname, &fh)) != 0) 526 return error; 527 *sizep = firmware_get_size(fh); 528 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 529 firmware_close(fh); 530 return ENOMEM; 531 } 532 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 533 firmware_free(*ucodep, *sizep); 534 firmware_close(fh); 535 536 return error; 537 } 538 539 static int 540 run_match(device_t parent, cfdata_t match, void *aux) 541 { 542 struct usb_attach_arg *uaa = aux; 543 544 return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? 545 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 546 } 547 548 static void 549 run_attach(device_t parent, device_t self, void *aux) 550 { 551 struct run_softc *sc = device_private(self); 552 struct usb_attach_arg *uaa = aux; 553 struct ieee80211com *ic = &sc->sc_ic; 554 struct ifnet *ifp = &sc->sc_if; 555 usb_interface_descriptor_t *id; 556 usb_endpoint_descriptor_t *ed; 557 char *devinfop; 558 int i, nrx, ntx, ntries, error; 559 uint32_t ver; 560 561 aprint_naive("\n"); 562 aprint_normal("\n"); 563 564 sc->sc_dev = self; 565 sc->sc_udev = uaa->uaa_device; 566 567 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 568 aprint_normal_dev(sc->sc_dev, "%s\n", devinfop); 569 usbd_devinfo_free(devinfop); 570 571 error = usbd_set_config_no(sc->sc_udev, 1, 0); 572 if (error != 0) { 573 aprint_error_dev(sc->sc_dev, "failed to set configuration" 574 ", err=%s\n", usbd_errstr(error)); 575 return; 576 } 577 578 /* get the first interface handle */ 579 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 580 if (error != 0) { 581 aprint_error_dev(sc->sc_dev, 582 "could not get interface handle\n"); 583 return; 584 } 585 586 /* 587 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 588 * and 6 for TX (4 EDCAs + HCCA + Prio). 589 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 590 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 591 */ 592 nrx = ntx = 0; 593 id = usbd_get_interface_descriptor(sc->sc_iface); 594 for (i = 0; i < id->bNumEndpoints; i++) { 595 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 596 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 597 continue; 598 599 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 600 sc->rxq.pipe_no = ed->bEndpointAddress; 601 nrx++; 602 } else if (ntx < RUN_MAXEPOUT) { 603 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 604 ntx++; 605 } 606 } 607 /* make sure we've got them all */ 608 if (nrx < 1 || ntx < RUN_MAXEPOUT) { 609 aprint_error_dev(sc->sc_dev, "missing endpoint\n"); 610 return; 611 } 612 613 usb_init_task(&sc->sc_task, run_task, sc, 0); 614 callout_init(&sc->scan_to, 0); 615 callout_setfunc(&sc->scan_to, run_next_scan, sc); 616 callout_init(&sc->calib_to, 0); 617 callout_setfunc(&sc->calib_to, run_calibrate_to, sc); 618 619 sc->amrr.amrr_min_success_threshold = 1; 620 sc->amrr.amrr_max_success_threshold = 10; 621 622 /* wait for the chip to settle */ 623 for (ntries = 0; ntries < 100; ntries++) { 624 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 625 return; 626 if (ver != 0 && ver != 0xffffffff) 627 break; 628 DELAY(10); 629 } 630 if (ntries == 100) { 631 aprint_error_dev(sc->sc_dev, 632 "timeout waiting for NIC to initialize\n"); 633 return; 634 } 635 sc->mac_ver = ver >> 16; 636 sc->mac_rev = ver & 0xffff; 637 638 /* retrieve RF rev. no and various other things from EEPROM */ 639 run_read_eeprom(sc); 640 641 aprint_verbose_dev(sc->sc_dev, 642 "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n", 643 sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 644 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 645 646 ic->ic_ifp = ifp; 647 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 648 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 649 ic->ic_state = IEEE80211_S_INIT; 650 651 /* set device capabilities */ 652 ic->ic_caps = 653 IEEE80211_C_MONITOR | /* monitor mode supported */ 654 #ifndef IEEE80211_STA_ONLY 655 IEEE80211_C_IBSS | /* IBSS mode supported */ 656 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 657 #endif 658 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 659 IEEE80211_C_SHSLOT | /* short slot time supported */ 660 #ifdef RUN_HWCRYPTO 661 IEEE80211_C_WEP | /* WEP */ 662 IEEE80211_C_TKIP | /* TKIP */ 663 IEEE80211_C_AES_CCM | /* AES CCMP */ 664 IEEE80211_C_TKIPMIC | /* TKIPMIC */ 665 #endif 666 IEEE80211_C_WME | /* WME */ 667 IEEE80211_C_WPA; /* WPA/RSN */ 668 669 if (sc->rf_rev == RT2860_RF_2750 || 670 sc->rf_rev == RT2860_RF_2850 || 671 sc->rf_rev == RT3070_RF_3052 || 672 sc->rf_rev == RT3070_RF_3053 || 673 sc->rf_rev == RT5592_RF_5592) { 674 /* set supported .11a rates */ 675 ic->ic_sup_rates[IEEE80211_MODE_11A] = 676 ieee80211_std_rateset_11a; 677 678 /* set supported .11a channels */ 679 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 680 uint8_t chan = rt2860_rf2850[i].chan; 681 ic->ic_channels[chan].ic_freq = 682 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 683 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 684 } 685 } 686 687 /* set supported .11b and .11g rates */ 688 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 689 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 690 691 /* set supported .11b and .11g channels (1 through 14) */ 692 for (i = 1; i <= 14; i++) { 693 ic->ic_channels[i].ic_freq = 694 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 695 ic->ic_channels[i].ic_flags = 696 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 697 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 698 } 699 700 ifp->if_softc = sc; 701 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 702 ifp->if_init = run_init; 703 ifp->if_ioctl = run_ioctl; 704 ifp->if_start = run_start; 705 ifp->if_watchdog = run_watchdog; 706 IFQ_SET_READY(&ifp->if_snd); 707 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 708 709 if_attach(ifp); 710 ieee80211_ifattach(ic); 711 ic->ic_node_alloc = run_node_alloc; 712 ic->ic_newassoc = run_newassoc; 713 ic->ic_updateslot = run_updateslot; 714 ic->ic_wme.wme_update = run_updateedca; 715 #ifdef RUN_HWCRYPTO 716 ic->ic_crypto.cs_key_set = run_set_key; 717 ic->ic_crypto.cs_key_delete = run_delete_key; 718 #endif 719 /* override state transition machine */ 720 sc->sc_newstate = ic->ic_newstate; 721 ic->ic_newstate = run_newstate; 722 ieee80211_media_init(ic, run_media_change, ieee80211_media_status); 723 724 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 725 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 726 &sc->sc_drvbpf); 727 728 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 729 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 730 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 731 732 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 733 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 734 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 735 736 ieee80211_announce(ic); 737 738 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 739 740 if (!pmf_device_register(self, NULL, NULL)) 741 aprint_error_dev(self, "couldn't establish power handler\n"); 742 } 743 744 static int 745 run_detach(device_t self, int flags) 746 { 747 struct run_softc *sc = device_private(self); 748 struct ifnet *ifp = &sc->sc_if; 749 struct ieee80211com *ic = &sc->sc_ic; 750 int s; 751 752 if (ifp->if_softc == NULL) 753 return 0; 754 755 pmf_device_deregister(self); 756 757 s = splusb(); 758 759 sc->sc_flags |= RUN_DETACHING; 760 761 if (ifp->if_flags & IFF_RUNNING) { 762 run_stop(ifp, 0); 763 callout_halt(&sc->scan_to, NULL); 764 callout_halt(&sc->calib_to, NULL); 765 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 766 NULL); 767 } 768 769 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 770 bpf_detach(ifp); 771 ieee80211_ifdetach(ic); 772 if_detach(ifp); 773 774 splx(s); 775 776 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 777 778 callout_stop(&sc->scan_to); 779 callout_stop(&sc->calib_to); 780 781 callout_destroy(&sc->scan_to); 782 callout_destroy(&sc->calib_to); 783 784 return 0; 785 } 786 787 static int 788 run_activate(device_t self, enum devact act) 789 { 790 struct run_softc *sc = device_private(self); 791 792 switch (act) { 793 case DVACT_DEACTIVATE: 794 if_deactivate(sc->sc_ic.ic_ifp); 795 return 0; 796 default: 797 return EOPNOTSUPP; 798 } 799 } 800 801 static int 802 run_alloc_rx_ring(struct run_softc *sc) 803 { 804 struct run_rx_ring *rxq = &sc->rxq; 805 int i, error; 806 807 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 808 if (error != 0) 809 goto fail; 810 811 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 812 struct run_rx_data *data = &rxq->data[i]; 813 814 data->sc = sc; /* backpointer for callbacks */ 815 816 error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, 817 0, 0, &data->xfer); 818 if (error) 819 goto fail; 820 821 data->buf = usbd_get_buffer(data->xfer); 822 } 823 if (error != 0) 824 fail: run_free_rx_ring(sc); 825 return error; 826 } 827 828 static void 829 run_free_rx_ring(struct run_softc *sc) 830 { 831 struct run_rx_ring *rxq = &sc->rxq; 832 int i; 833 834 if (rxq->pipeh != NULL) { 835 usbd_abort_pipe(rxq->pipeh); 836 } 837 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 838 if (rxq->data[i].xfer != NULL) 839 usbd_destroy_xfer(rxq->data[i].xfer); 840 rxq->data[i].xfer = NULL; 841 } 842 if (rxq->pipeh != NULL) { 843 usbd_close_pipe(rxq->pipeh); 844 rxq->pipeh = NULL; 845 } 846 } 847 848 static int 849 run_alloc_tx_ring(struct run_softc *sc, int qid) 850 { 851 struct run_tx_ring *txq = &sc->txq[qid]; 852 int i, error; 853 854 txq->cur = txq->queued = 0; 855 856 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 857 if (error != 0) 858 goto fail; 859 860 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 861 struct run_tx_data *data = &txq->data[i]; 862 863 data->sc = sc; /* backpointer for callbacks */ 864 data->qid = qid; 865 866 error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, 867 USBD_FORCE_SHORT_XFER, 0, &data->xfer); 868 if (error) 869 goto fail; 870 871 data->buf = usbd_get_buffer(data->xfer); 872 /* zeroize the TXD + TXWI part */ 873 memset(data->buf, 0, sizeof(struct rt2870_txd) + 874 sizeof(struct rt2860_txwi)); 875 } 876 if (error != 0) 877 fail: run_free_tx_ring(sc, qid); 878 return error; 879 } 880 881 static void 882 run_free_tx_ring(struct run_softc *sc, int qid) 883 { 884 struct run_tx_ring *txq = &sc->txq[qid]; 885 int i; 886 887 if (txq->pipeh != NULL) { 888 usbd_abort_pipe(txq->pipeh); 889 usbd_close_pipe(txq->pipeh); 890 txq->pipeh = NULL; 891 } 892 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 893 if (txq->data[i].xfer != NULL) 894 usbd_destroy_xfer(txq->data[i].xfer); 895 txq->data[i].xfer = NULL; 896 } 897 } 898 899 static int 900 run_load_microcode(struct run_softc *sc) 901 { 902 usb_device_request_t req; 903 const char *fwname; 904 u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ 905 size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ 906 uint32_t tmp; 907 int ntries, error; 908 909 /* RT3071/RT3072 use a different firmware */ 910 if (sc->mac_ver != 0x2860 && 911 sc->mac_ver != 0x2872 && 912 sc->mac_ver != 0x3070) 913 fwname = "run-rt3071"; 914 else 915 fwname = "run-rt2870"; 916 917 if ((error = firmware_load("run", fwname, &ucode, &size)) != 0) { 918 device_printf(sc->sc_dev, 919 "error %d, could not read firmware %s\n", error, fwname); 920 return error; 921 } 922 if (size != 4096) { 923 device_printf(sc->sc_dev, 924 "invalid firmware size (should be 4KB)\n"); 925 firmware_free(ucode, size); 926 return EINVAL; 927 } 928 929 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 930 /* write microcode image */ 931 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 932 firmware_free(ucode, size); 933 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 934 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 935 936 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 937 req.bRequest = RT2870_RESET; 938 USETW(req.wValue, 8); 939 USETW(req.wIndex, 0); 940 USETW(req.wLength, 0); 941 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 942 return error; 943 944 usbd_delay_ms(sc->sc_udev, 10); 945 run_write(sc, RT2860_H2M_MAILBOX, 0); 946 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 947 return error; 948 949 /* wait until microcontroller is ready */ 950 for (ntries = 0; ntries < 1000; ntries++) { 951 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 952 return error; 953 if (tmp & RT2860_MCU_READY) 954 break; 955 usbd_delay_ms(sc->sc_udev, 10); 956 } 957 if (ntries == 1000) { 958 device_printf(sc->sc_dev, 959 "timeout waiting for MCU to initialize\n"); 960 return ETIMEDOUT; 961 } 962 963 sc->sc_flags |= RUN_FWLOADED; 964 965 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 966 return 0; 967 } 968 969 static int 970 run_reset(struct run_softc *sc) 971 { 972 usb_device_request_t req; 973 974 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 975 req.bRequest = RT2870_RESET; 976 USETW(req.wValue, 1); 977 USETW(req.wIndex, 0); 978 USETW(req.wLength, 0); 979 return usbd_do_request(sc->sc_udev, &req, NULL); 980 } 981 982 static int 983 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 984 { 985 uint32_t tmp; 986 int error; 987 988 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 989 if (error == 0) 990 *val = le32toh(tmp); 991 else 992 *val = 0xffffffff; 993 return error; 994 } 995 996 static int 997 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 998 { 999 usb_device_request_t req; 1000 1001 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1002 req.bRequest = RT2870_READ_REGION_1; 1003 USETW(req.wValue, 0); 1004 USETW(req.wIndex, reg); 1005 USETW(req.wLength, len); 1006 return usbd_do_request(sc->sc_udev, &req, buf); 1007 } 1008 1009 static int 1010 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 1011 { 1012 usb_device_request_t req; 1013 1014 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1015 req.bRequest = RT2870_WRITE_2; 1016 USETW(req.wValue, val); 1017 USETW(req.wIndex, reg); 1018 USETW(req.wLength, 0); 1019 return usbd_do_request(sc->sc_udev, &req, NULL); 1020 } 1021 1022 static int 1023 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 1024 { 1025 int error; 1026 1027 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 1028 error = run_write_2(sc, reg + 2, val >> 16); 1029 return error; 1030 } 1031 1032 static int 1033 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 1034 int len) 1035 { 1036 #if 1 1037 int i, error = 0; 1038 /* 1039 * NB: the WRITE_REGION_1 command is not stable on RT2860. 1040 * We thus issue multiple WRITE_2 commands instead. 1041 */ 1042 KASSERT((len & 1) == 0); 1043 for (i = 0; i < len && error == 0; i += 2) 1044 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 1045 return error; 1046 #else 1047 usb_device_request_t req; 1048 1049 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1050 req.bRequest = RT2870_WRITE_REGION_1; 1051 USETW(req.wValue, 0); 1052 USETW(req.wIndex, reg); 1053 USETW(req.wLength, len); 1054 return usbd_do_request(sc->sc_udev, &req, buf); 1055 #endif 1056 } 1057 1058 static int 1059 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 1060 { 1061 int error = 0; 1062 1063 for (; count > 0 && error == 0; count--, reg += 4) 1064 error = run_write(sc, reg, val); 1065 return error; 1066 } 1067 1068 static int 1069 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) 1070 { 1071 uint32_t tmp; 1072 uint16_t reg; 1073 int error, ntries; 1074 1075 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1076 return error; 1077 1078 if (count == 2) 1079 addr *= 2; 1080 /*- 1081 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1082 * DATA0: F E D C 1083 * DATA1: B A 9 8 1084 * DATA2: 7 6 5 4 1085 * DATA3: 3 2 1 0 1086 */ 1087 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1088 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1089 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1090 for (ntries = 0; ntries < 100; ntries++) { 1091 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1092 return error; 1093 if (!(tmp & RT3070_EFSROM_KICK)) 1094 break; 1095 usbd_delay_ms(sc->sc_udev, 2); 1096 } 1097 if (ntries == 100) 1098 return ETIMEDOUT; 1099 1100 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1101 *val = 0xffff; /* address not found */ 1102 return 0; 1103 } 1104 /* determine to which 32-bit register our 16-bit word belongs */ 1105 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1106 if ((error = run_read(sc, reg, &tmp)) != 0) 1107 return error; 1108 1109 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1110 return 0; 1111 } 1112 1113 /* Read 16-bit from eFUSE ROM for RT3xxxx. */ 1114 static int 1115 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1116 { 1117 return (run_efuse_read(sc, addr, val, 2)); 1118 } 1119 1120 static int 1121 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1122 { 1123 usb_device_request_t req; 1124 uint16_t tmp; 1125 int error; 1126 1127 addr *= 2; 1128 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1129 req.bRequest = RT2870_EEPROM_READ; 1130 USETW(req.wValue, 0); 1131 USETW(req.wIndex, addr); 1132 USETW(req.wLength, sizeof(tmp)); 1133 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1134 if (error == 0) 1135 *val = le16toh(tmp); 1136 else 1137 *val = 0xffff; 1138 return error; 1139 } 1140 1141 static __inline int 1142 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1143 { 1144 1145 /* either eFUSE ROM or EEPROM */ 1146 return sc->sc_srom_read(sc, addr, val); 1147 } 1148 1149 static int 1150 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1151 { 1152 uint32_t tmp; 1153 int error, ntries; 1154 1155 for (ntries = 0; ntries < 10; ntries++) { 1156 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1157 return error; 1158 if (!(tmp & RT2860_RF_REG_CTRL)) 1159 break; 1160 } 1161 if (ntries == 10) 1162 return ETIMEDOUT; 1163 1164 /* RF registers are 24-bit on the RT2860 */ 1165 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1166 (val & 0x3fffff) << 2 | (reg & 3); 1167 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1168 } 1169 1170 static int 1171 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1172 { 1173 uint32_t tmp; 1174 int error, ntries; 1175 1176 for (ntries = 0; ntries < 100; ntries++) { 1177 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1178 return error; 1179 if (!(tmp & RT3070_RF_KICK)) 1180 break; 1181 } 1182 if (ntries == 100) 1183 return ETIMEDOUT; 1184 1185 tmp = RT3070_RF_KICK | reg << 8; 1186 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1187 return error; 1188 1189 for (ntries = 0; ntries < 100; ntries++) { 1190 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1191 return error; 1192 if (!(tmp & RT3070_RF_KICK)) 1193 break; 1194 } 1195 if (ntries == 100) 1196 return ETIMEDOUT; 1197 1198 *val = tmp & 0xff; 1199 return 0; 1200 } 1201 1202 static int 1203 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1204 { 1205 uint32_t tmp; 1206 int error, ntries; 1207 1208 for (ntries = 0; ntries < 10; ntries++) { 1209 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1210 return error; 1211 if (!(tmp & RT3070_RF_KICK)) 1212 break; 1213 } 1214 if (ntries == 10) 1215 return ETIMEDOUT; 1216 1217 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1218 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1219 } 1220 1221 static int 1222 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1223 { 1224 uint32_t tmp; 1225 int ntries, error; 1226 1227 for (ntries = 0; ntries < 10; ntries++) { 1228 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1229 return error; 1230 if (!(tmp & RT2860_BBP_CSR_KICK)) 1231 break; 1232 } 1233 if (ntries == 10) 1234 return ETIMEDOUT; 1235 1236 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1237 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1238 return error; 1239 1240 for (ntries = 0; ntries < 10; ntries++) { 1241 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1242 return error; 1243 if (!(tmp & RT2860_BBP_CSR_KICK)) 1244 break; 1245 } 1246 if (ntries == 10) 1247 return ETIMEDOUT; 1248 1249 *val = tmp & 0xff; 1250 return 0; 1251 } 1252 1253 static int 1254 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1255 { 1256 uint32_t tmp; 1257 int ntries, error; 1258 1259 for (ntries = 0; ntries < 10; ntries++) { 1260 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1261 return error; 1262 if (!(tmp & RT2860_BBP_CSR_KICK)) 1263 break; 1264 } 1265 if (ntries == 10) 1266 return ETIMEDOUT; 1267 1268 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1269 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1270 } 1271 1272 /* 1273 * Send a command to the 8051 microcontroller unit. 1274 */ 1275 static int 1276 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1277 { 1278 uint32_t tmp; 1279 int error, ntries; 1280 1281 for (ntries = 0; ntries < 100; ntries++) { 1282 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1283 return error; 1284 if (!(tmp & RT2860_H2M_BUSY)) 1285 break; 1286 } 1287 if (ntries == 100) 1288 return ETIMEDOUT; 1289 1290 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1291 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1292 error = run_write(sc, RT2860_HOST_CMD, cmd); 1293 return error; 1294 } 1295 1296 /* 1297 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1298 * Used to adjust per-rate Tx power registers. 1299 */ 1300 static __inline uint32_t 1301 b4inc(uint32_t b32, int8_t delta) 1302 { 1303 int8_t i, b4; 1304 1305 for (i = 0; i < 8; i++) { 1306 b4 = b32 & 0xf; 1307 b4 += delta; 1308 if (b4 < 0) 1309 b4 = 0; 1310 else if (b4 > 0xf) 1311 b4 = 0xf; 1312 b32 = b32 >> 4 | b4 << 28; 1313 } 1314 return b32; 1315 } 1316 1317 static const char * 1318 run_get_rf(int rev) 1319 { 1320 switch (rev) { 1321 case RT2860_RF_2820: return "RT2820"; 1322 case RT2860_RF_2850: return "RT2850"; 1323 case RT2860_RF_2720: return "RT2720"; 1324 case RT2860_RF_2750: return "RT2750"; 1325 case RT3070_RF_3020: return "RT3020"; 1326 case RT3070_RF_2020: return "RT2020"; 1327 case RT3070_RF_3021: return "RT3021"; 1328 case RT3070_RF_3022: return "RT3022"; 1329 case RT3070_RF_3052: return "RT3052"; 1330 case RT3070_RF_3053: return "RT3053"; 1331 case RT5592_RF_5592: return "RT5592"; 1332 case RT5390_RF_5370: return "RT5370"; 1333 case RT5390_RF_5372: return "RT5372"; 1334 } 1335 return "unknown"; 1336 } 1337 1338 static void 1339 run_rt3593_get_txpower(struct run_softc *sc) 1340 { 1341 uint16_t addr, val; 1342 int i; 1343 1344 /* Read power settings for 2GHz channels. */ 1345 for (i = 0; i < 14; i += 2) { 1346 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1347 RT2860_EEPROM_PWR2GHZ_BASE1; 1348 run_srom_read(sc, addr + i / 2, &val); 1349 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1350 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1351 1352 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1353 RT2860_EEPROM_PWR2GHZ_BASE2; 1354 run_srom_read(sc, addr + i / 2, &val); 1355 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1356 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1357 1358 if (sc->ntxchains == 3) { 1359 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1360 &val); 1361 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1362 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1363 } 1364 } 1365 /* Fix broken Tx power entries. */ 1366 for (i = 0; i < 14; i++) { 1367 if (sc->txpow1[i] > 31) 1368 sc->txpow1[i] = 5; 1369 if (sc->txpow2[i] > 31) 1370 sc->txpow2[i] = 5; 1371 if (sc->ntxchains == 3) { 1372 if (sc->txpow3[i] > 31) 1373 sc->txpow3[i] = 5; 1374 } 1375 } 1376 /* Read power settings for 5GHz channels. */ 1377 for (i = 0; i < 40; i += 2) { 1378 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1379 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1380 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1381 1382 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1383 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1384 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1385 1386 if (sc->ntxchains == 3) { 1387 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1388 &val); 1389 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1390 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1391 } 1392 } 1393 } 1394 1395 static void 1396 run_get_txpower(struct run_softc *sc) 1397 { 1398 uint16_t val; 1399 int i; 1400 1401 /* Read power settings for 2GHz channels. */ 1402 for (i = 0; i < 14; i += 2) { 1403 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1404 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1405 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1406 1407 if (sc->mac_ver != 0x5390) { 1408 run_srom_read(sc, 1409 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1410 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1411 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1412 } 1413 } 1414 /* Fix broken Tx power entries. */ 1415 for (i = 0; i < 14; i++) { 1416 if (sc->mac_ver >= 0x5390) { 1417 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) 1418 sc->txpow1[i] = 5; 1419 } else { 1420 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1421 sc->txpow1[i] = 5; 1422 } 1423 if (sc->mac_ver > 0x5390) { 1424 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) 1425 sc->txpow2[i] = 5; 1426 } else if (sc->mac_ver < 0x5390) { 1427 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1428 sc->txpow2[i] = 5; 1429 } 1430 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1431 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1432 } 1433 /* Read power settings for 5GHz channels. */ 1434 for (i = 0; i < 40; i += 2) { 1435 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1436 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1437 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1438 1439 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1440 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1441 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1442 } 1443 /* Fix broken Tx power entries. */ 1444 for (i = 0; i < 40; i++ ) { 1445 if (sc->mac_ver != 0x5592) { 1446 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1447 sc->txpow1[14 + i] = 5; 1448 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1449 sc->txpow2[14 + i] = 5; 1450 } 1451 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1452 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1453 sc->txpow2[14 + i])); 1454 } 1455 } 1456 1457 static int 1458 run_read_eeprom(struct run_softc *sc) 1459 { 1460 struct ieee80211com *ic = &sc->sc_ic; 1461 int8_t delta_2ghz, delta_5ghz; 1462 uint32_t tmp; 1463 uint16_t val; 1464 int ridx, ant, i; 1465 1466 /* check whether the ROM is eFUSE ROM or EEPROM */ 1467 sc->sc_srom_read = run_eeprom_read_2; 1468 if (sc->mac_ver >= 0x3070) { 1469 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1470 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1471 if (tmp & RT3070_SEL_EFUSE) 1472 sc->sc_srom_read = run_efuse_read_2; 1473 } 1474 1475 /* read ROM version */ 1476 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1477 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1478 1479 /* read MAC address */ 1480 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1481 ic->ic_myaddr[0] = val & 0xff; 1482 ic->ic_myaddr[1] = val >> 8; 1483 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1484 ic->ic_myaddr[2] = val & 0xff; 1485 ic->ic_myaddr[3] = val >> 8; 1486 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1487 ic->ic_myaddr[4] = val & 0xff; 1488 ic->ic_myaddr[5] = val >> 8; 1489 1490 /* read vendor BBP settings */ 1491 for (i = 0; i < 10; i++) { 1492 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1493 sc->bbp[i].val = val & 0xff; 1494 sc->bbp[i].reg = val >> 8; 1495 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 1496 } 1497 1498 /* read vendor RF settings */ 1499 for (i = 0; i < 8; i++) { 1500 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, &val); 1501 sc->rf[i].val = val & 0xff; 1502 sc->rf[i].reg = val >> 8; 1503 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1504 sc->rf[i].val)); 1505 } 1506 1507 /* read RF frequency offset from EEPROM */ 1508 run_srom_read(sc, RT2860_EEPROM_FREQ_LEDS, &val); 1509 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1510 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1511 1512 if ((val >> 8) != 0xff) { 1513 /* read LEDs operating mode */ 1514 sc->leds = val >> 8; 1515 run_srom_read(sc, RT2860_EEPROM_LED1, &sc->led[0]); 1516 run_srom_read(sc, RT2860_EEPROM_LED2, &sc->led[1]); 1517 run_srom_read(sc, RT2860_EEPROM_LED3, &sc->led[2]); 1518 } else { 1519 /* broken EEPROM, use default settings */ 1520 sc->leds = 0x01; 1521 sc->led[0] = 0x5555; 1522 sc->led[1] = 0x2221; 1523 sc->led[2] = 0x5627; /* differs from RT2860 */ 1524 } 1525 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1526 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1527 1528 /* read RF information */ 1529 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1530 if (val == 0xffff) { 1531 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1532 if (sc->mac_ver == 0x3572) { 1533 /* default to RF3052 2T2R */ 1534 sc->rf_rev = RT3070_RF_3052; 1535 sc->ntxchains = 2; 1536 sc->nrxchains = 2; 1537 } else if (sc->mac_ver >= 0x3070) { 1538 /* default to RF3020 1T1R */ 1539 sc->rf_rev = RT3070_RF_3020; 1540 sc->ntxchains = 1; 1541 sc->nrxchains = 1; 1542 } else { 1543 /* default to RF2820 1T2R */ 1544 sc->rf_rev = RT2860_RF_2820; 1545 sc->ntxchains = 1; 1546 sc->nrxchains = 2; 1547 } 1548 } else { 1549 sc->rf_rev = (val >> 8) & 0xf; 1550 sc->ntxchains = (val >> 4) & 0xf; 1551 sc->nrxchains = val & 0xf; 1552 } 1553 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1554 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1555 1556 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1557 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1558 /* check if driver should patch the DAC issue */ 1559 if ((val >> 8) != 0xff) 1560 sc->patch_dac = (val >> 15) & 1; 1561 if ((val & 0xff) != 0xff) { 1562 sc->ext_5ghz_lna = (val >> 3) & 1; 1563 sc->ext_2ghz_lna = (val >> 2) & 1; 1564 /* check if RF supports automatic Tx access gain control */ 1565 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1566 /* check if we have a hardware radio switch */ 1567 sc->rfswitch = val & 1; 1568 } 1569 1570 /* Read Tx power settings. */ 1571 if (sc->mac_ver == 0x3593) 1572 run_rt3593_get_txpower(sc); 1573 else 1574 run_get_txpower(sc); 1575 1576 /* read Tx power compensation for each Tx rate */ 1577 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1578 delta_2ghz = delta_5ghz = 0; 1579 if ((val & 0xff) != 0xff && (val & 0x80)) { 1580 delta_2ghz = val & 0xf; 1581 if (!(val & 0x40)) /* negative number */ 1582 delta_2ghz = -delta_2ghz; 1583 } 1584 val >>= 8; 1585 if ((val & 0xff) != 0xff && (val & 0x80)) { 1586 delta_5ghz = val & 0xf; 1587 if (!(val & 0x40)) /* negative number */ 1588 delta_5ghz = -delta_5ghz; 1589 } 1590 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1591 delta_2ghz, delta_5ghz)); 1592 1593 for (ridx = 0; ridx < 5; ridx++) { 1594 uint32_t reg; 1595 1596 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1597 reg = val; 1598 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1599 reg |= (uint32_t)val << 16; 1600 1601 sc->txpow20mhz[ridx] = reg; 1602 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1603 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1604 1605 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1606 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1607 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1608 } 1609 1610 /* read RSSI offsets and LNA gains from EEPROM */ 1611 run_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ, &val); 1612 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1613 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1614 run_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ, &val); 1615 if (sc->mac_ver >= 0x3070) { 1616 if (sc->mac_ver == 0x3593) { 1617 sc->txmixgain_2ghz = 0; 1618 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1619 } else { 1620 /* 1621 * On RT3070 chips (limited to 2 Rx chains), this ROM 1622 * field contains the Tx mixer gain for the 2GHz band. 1623 */ 1624 if ((val & 0xff) != 0xff) 1625 sc->txmixgain_2ghz = val & 0x7; 1626 } 1627 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1628 } else { 1629 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1630 } 1631 if (sc->mac_ver == 0x3593) 1632 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1633 sc->lna[2] = val >> 8; /* channel group 2 */ 1634 1635 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1636 RT3593_EEPROM_RSSI2_5GHZ, &val); 1637 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1638 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1639 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1640 RT3593_EEPROM_RSSI2_5GHZ, &val); 1641 if (sc->mac_ver == 0x3572) { 1642 /* 1643 * On RT3572 chips (limited to 2 Rx chains), this ROM 1644 * field contains the Tx mixer gain for the 5GHz band. 1645 */ 1646 if ((val & 0xff) != 0xff) 1647 sc->txmixgain_5ghz = val & 0x7; 1648 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1649 } else { 1650 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1651 } 1652 if (sc->mac_ver == 0x3593) { 1653 sc->txmixgain_5ghz = 0; 1654 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1655 } 1656 sc->lna[3] = val >> 8; /* channel group 3 */ 1657 1658 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1659 RT3593_EEPROM_LNA, &val); 1660 sc->lna[0] = val & 0xff; /* channel group 0 */ 1661 sc->lna[1] = val >> 8; /* channel group 1 */ 1662 1663 /* fix broken 5GHz LNA entries */ 1664 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1665 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1666 sc->lna[2] = sc->lna[1]; 1667 } 1668 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1669 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1670 sc->lna[3] = sc->lna[1]; 1671 } 1672 1673 /* fix broken RSSI offset entries */ 1674 for (ant = 0; ant < 3; ant++) { 1675 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1676 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1677 ant + 1, sc->rssi_2ghz[ant])); 1678 sc->rssi_2ghz[ant] = 0; 1679 } 1680 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1681 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1682 ant + 1, sc->rssi_5ghz[ant])); 1683 sc->rssi_5ghz[ant] = 0; 1684 } 1685 } 1686 return 0; 1687 } 1688 1689 static struct ieee80211_node * 1690 run_node_alloc(struct ieee80211_node_table *nt) 1691 { 1692 struct run_node *rn = 1693 malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1694 return rn ? &rn->ni : NULL; 1695 } 1696 1697 static int 1698 run_media_change(struct ifnet *ifp) 1699 { 1700 struct run_softc *sc = ifp->if_softc; 1701 struct ieee80211com *ic = &sc->sc_ic; 1702 uint8_t rate, ridx; 1703 int error; 1704 1705 error = ieee80211_media_change(ifp); 1706 if (error != ENETRESET) 1707 return error; 1708 1709 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1710 rate = ic->ic_sup_rates[ic->ic_curmode]. 1711 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1712 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1713 if (rt2860_rates[ridx].rate == rate) 1714 break; 1715 sc->fixed_ridx = ridx; 1716 } 1717 1718 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1719 run_init(ifp); 1720 1721 return 0; 1722 } 1723 1724 static void 1725 run_next_scan(void *arg) 1726 { 1727 struct run_softc *sc = arg; 1728 1729 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1730 ieee80211_next_scan(&sc->sc_ic); 1731 } 1732 1733 static void 1734 run_task(void *arg) 1735 { 1736 struct run_softc *sc = arg; 1737 struct run_host_cmd_ring *ring = &sc->cmdq; 1738 struct run_host_cmd *cmd; 1739 int s; 1740 1741 /* process host commands */ 1742 s = splusb(); 1743 while (ring->next != ring->cur) { 1744 cmd = &ring->cmd[ring->next]; 1745 splx(s); 1746 /* callback */ 1747 cmd->cb(sc, cmd->data); 1748 s = splusb(); 1749 ring->queued--; 1750 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1751 } 1752 wakeup(ring); 1753 splx(s); 1754 } 1755 1756 static void 1757 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1758 void *arg, int len) 1759 { 1760 struct run_host_cmd_ring *ring = &sc->cmdq; 1761 struct run_host_cmd *cmd; 1762 int s; 1763 1764 if (sc->sc_flags & RUN_DETACHING) 1765 return; 1766 1767 s = splusb(); 1768 cmd = &ring->cmd[ring->cur]; 1769 cmd->cb = cb; 1770 KASSERT(len <= sizeof(cmd->data)); 1771 memcpy(cmd->data, arg, len); 1772 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1773 1774 /* if there is no pending command already, schedule a task */ 1775 if (++ring->queued == 1) 1776 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1777 splx(s); 1778 } 1779 1780 static int 1781 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1782 { 1783 struct run_softc *sc = ic->ic_ifp->if_softc; 1784 struct run_cmd_newstate cmd; 1785 1786 callout_stop(&sc->scan_to); 1787 callout_stop(&sc->calib_to); 1788 1789 /* do it in a process context */ 1790 cmd.state = nstate; 1791 cmd.arg = arg; 1792 run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); 1793 return 0; 1794 } 1795 1796 static void 1797 run_newstate_cb(struct run_softc *sc, void *arg) 1798 { 1799 struct run_cmd_newstate *cmd = arg; 1800 struct ifnet *ifp = &sc->sc_if; 1801 struct ieee80211com *ic = &sc->sc_ic; 1802 enum ieee80211_state ostate; 1803 struct ieee80211_node *ni; 1804 uint32_t tmp, sta[3]; 1805 uint8_t wcid; 1806 int s; 1807 1808 s = splnet(); 1809 ostate = ic->ic_state; 1810 1811 if (ostate == IEEE80211_S_RUN) { 1812 /* turn link LED off */ 1813 run_set_leds(sc, RT2860_LED_RADIO); 1814 } 1815 1816 switch (cmd->state) { 1817 case IEEE80211_S_INIT: 1818 if (ostate == IEEE80211_S_RUN) { 1819 /* abort TSF synchronization */ 1820 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1821 run_write(sc, RT2860_BCN_TIME_CFG, 1822 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1823 RT2860_TBTT_TIMER_EN)); 1824 } 1825 break; 1826 1827 case IEEE80211_S_SCAN: 1828 run_set_chan(sc, ic->ic_curchan); 1829 callout_schedule(&sc->scan_to, hz / 5); 1830 break; 1831 1832 case IEEE80211_S_AUTH: 1833 case IEEE80211_S_ASSOC: 1834 run_set_chan(sc, ic->ic_curchan); 1835 break; 1836 1837 case IEEE80211_S_RUN: 1838 run_set_chan(sc, ic->ic_curchan); 1839 1840 ni = ic->ic_bss; 1841 1842 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1843 run_updateslot(ifp); 1844 run_enable_mrr(sc); 1845 run_set_txpreamble(sc); 1846 run_set_basicrates(sc); 1847 run_set_bssid(sc, ni->ni_bssid); 1848 } 1849 #ifndef IEEE80211_STA_ONLY 1850 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1851 ic->ic_opmode == IEEE80211_M_IBSS) 1852 (void)run_setup_beacon(sc); 1853 #endif 1854 if (ic->ic_opmode == IEEE80211_M_STA) { 1855 /* add BSS entry to the WCID table */ 1856 wcid = RUN_AID2WCID(ni->ni_associd); 1857 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1858 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1859 1860 /* fake a join to init the tx rate */ 1861 run_newassoc(ni, 1); 1862 } 1863 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1864 run_enable_tsf_sync(sc); 1865 1866 /* clear statistic registers used by AMRR */ 1867 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1868 (uint8_t *)sta, sizeof(sta)); 1869 /* start calibration timer */ 1870 callout_schedule(&sc->calib_to, hz); 1871 } 1872 1873 /* turn link LED on */ 1874 run_set_leds(sc, RT2860_LED_RADIO | 1875 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1876 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1877 break; 1878 } 1879 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1880 splx(s); 1881 } 1882 1883 static int 1884 run_updateedca(struct ieee80211com *ic) 1885 { 1886 1887 /* do it in a process context */ 1888 run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); 1889 return 0; 1890 } 1891 1892 /* ARGSUSED */ 1893 static void 1894 run_updateedca_cb(struct run_softc *sc, void *arg) 1895 { 1896 struct ieee80211com *ic = &sc->sc_ic; 1897 int s, aci; 1898 1899 s = splnet(); 1900 /* update MAC TX configuration registers */ 1901 for (aci = 0; aci < WME_NUM_AC; aci++) { 1902 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1903 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 1904 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 1905 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 1906 ic->ic_wme.wme_params[aci].wmep_txopLimit); 1907 } 1908 1909 /* update SCH/DMA registers too */ 1910 run_write(sc, RT2860_WMM_AIFSN_CFG, 1911 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 1912 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 1913 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 1914 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 1915 run_write(sc, RT2860_WMM_CWMIN_CFG, 1916 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 1917 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 1918 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 1919 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 1920 run_write(sc, RT2860_WMM_CWMAX_CFG, 1921 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 1922 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 1923 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 1924 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 1925 run_write(sc, RT2860_WMM_TXOP0_CFG, 1926 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 1927 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 1928 run_write(sc, RT2860_WMM_TXOP1_CFG, 1929 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 1930 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 1931 splx(s); 1932 } 1933 1934 #ifdef RUN_HWCRYPTO 1935 static int 1936 run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, 1937 const uint8_t *mac) 1938 { 1939 struct run_softc *sc = ic->ic_ifp->if_softc; 1940 struct ieee80211_node *ni = ic->ic_bss; 1941 struct run_cmd_key cmd; 1942 1943 /* do it in a process context */ 1944 cmd.key = *k; 1945 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1946 run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); 1947 return 1; 1948 } 1949 1950 static void 1951 run_set_key_cb(struct run_softc *sc, void *arg) 1952 { 1953 #ifndef IEEE80211_STA_ONLY 1954 struct ieee80211com *ic = &sc->sc_ic; 1955 #endif 1956 struct run_cmd_key *cmd = arg; 1957 struct ieee80211_key *k = &cmd->key; 1958 uint32_t attr; 1959 uint16_t base; 1960 uint8_t mode, wcid, iv[8]; 1961 1962 /* map net80211 cipher to RT2860 security mode */ 1963 switch (k->wk_cipher->ic_cipher) { 1964 case IEEE80211_CIPHER_WEP: 1965 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 1966 if (k->wk_keylen == 5) 1967 mode = RT2860_MODE_WEP40; 1968 else 1969 mode = RT2860_MODE_WEP104; 1970 break; 1971 case IEEE80211_CIPHER_TKIP: 1972 mode = RT2860_MODE_TKIP; 1973 break; 1974 case IEEE80211_CIPHER_AES_CCM: 1975 mode = RT2860_MODE_AES_CCMP; 1976 break; 1977 default: 1978 return; 1979 } 1980 1981 if (k->wk_flags & IEEE80211_KEY_GROUP) { 1982 wcid = 0; /* NB: update WCID0 for group keys */ 1983 base = RT2860_SKEY(0, k->wk_keyix); 1984 } else { 1985 wcid = RUN_AID2WCID(cmd->associd); 1986 base = RT2860_PKEY(wcid); 1987 } 1988 1989 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 1990 run_write_region_1(sc, base, k->wk_key, 16); 1991 #ifndef IEEE80211_STA_ONLY 1992 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1993 run_write_region_1(sc, base + 16, &k->wk_key[16], 8); 1994 run_write_region_1(sc, base + 24, &k->wk_key[24], 8); 1995 } else 1996 #endif 1997 { 1998 run_write_region_1(sc, base + 16, &k->wk_key[24], 8); 1999 run_write_region_1(sc, base + 24, &k->wk_key[16], 8); 2000 } 2001 } else { 2002 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 2003 run_write_region_1(sc, base, k->wk_key, 2004 (k->wk_keylen + 1) & ~1); 2005 } 2006 2007 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 2008 (k->wk_flags & IEEE80211_KEY_XMIT)) { 2009 /* set initial packet number in IV+EIV */ 2010 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 2011 memset(iv, 0, sizeof(iv)); 2012 iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; 2013 } else { 2014 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2015 iv[0] = k->wk_keytsc >> 8; 2016 iv[1] = (iv[0] | 0x20) & 0x7f; 2017 iv[2] = k->wk_keytsc; 2018 } else /* CCMP */ { 2019 iv[0] = k->wk_keytsc; 2020 iv[1] = k->wk_keytsc >> 8; 2021 iv[2] = 0; 2022 } 2023 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 2024 iv[4] = k->wk_keytsc >> 16; 2025 iv[5] = k->wk_keytsc >> 24; 2026 iv[6] = k->wk_keytsc >> 32; 2027 iv[7] = k->wk_keytsc >> 40; 2028 } 2029 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2030 } 2031 2032 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2033 /* install group key */ 2034 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2035 attr &= ~(0xf << (k->wk_keyix * 4)); 2036 attr |= mode << (k->wk_keyix * 4); 2037 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2038 } else { 2039 /* install pairwise key */ 2040 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2041 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2042 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2043 } 2044 } 2045 2046 static int 2047 run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 2048 { 2049 struct run_softc *sc = ic->ic_ifp->if_softc; 2050 struct ieee80211_node *ni = ic->ic_bss; 2051 struct run_cmd_key cmd; 2052 2053 /* do it in a process context */ 2054 cmd.key = *k; 2055 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2056 run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); 2057 return 1; 2058 } 2059 2060 static void 2061 run_delete_key_cb(struct run_softc *sc, void *arg) 2062 { 2063 struct run_cmd_key *cmd = arg; 2064 struct ieee80211_key *k = &cmd->key; 2065 uint32_t attr; 2066 uint8_t wcid; 2067 2068 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 2069 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2070 2071 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2072 /* remove group key */ 2073 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2074 attr &= ~(0xf << (k->wk_keyix * 4)); 2075 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2076 2077 } else { 2078 /* remove pairwise key */ 2079 wcid = RUN_AID2WCID(cmd->associd); 2080 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2081 attr &= ~0xf; 2082 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2083 } 2084 } 2085 #endif 2086 2087 static void 2088 run_calibrate_to(void *arg) 2089 { 2090 2091 /* do it in a process context */ 2092 run_do_async(arg, run_calibrate_cb, NULL, 0); 2093 /* next timeout will be rescheduled in the calibration task */ 2094 } 2095 2096 /* ARGSUSED */ 2097 static void 2098 run_calibrate_cb(struct run_softc *sc, void *arg) 2099 { 2100 struct ifnet *ifp = &sc->sc_if; 2101 uint32_t sta[3]; 2102 int s, error; 2103 2104 /* read statistic counters (clear on read) and update AMRR state */ 2105 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2106 sizeof(sta)); 2107 if (error != 0) 2108 goto skip; 2109 2110 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2111 le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, 2112 le32toh(sta[0]) & 0xffff)); 2113 2114 s = splnet(); 2115 /* count failed TX as errors */ 2116 ifp->if_oerrors += le32toh(sta[0]) & 0xffff; 2117 2118 sc->amn.amn_retrycnt = 2119 (le32toh(sta[0]) & 0xffff) + /* failed TX count */ 2120 (le32toh(sta[1]) >> 16); /* TX retransmission count */ 2121 2122 sc->amn.amn_txcnt = 2123 sc->amn.amn_retrycnt + 2124 (le32toh(sta[1]) & 0xffff); /* successful TX count */ 2125 2126 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2127 splx(s); 2128 2129 skip: callout_schedule(&sc->calib_to, hz); 2130 } 2131 2132 static void 2133 run_newassoc(struct ieee80211_node *ni, int isnew) 2134 { 2135 struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; 2136 struct run_node *rn = (void *)ni; 2137 struct ieee80211_rateset *rs = &ni->ni_rates; 2138 uint8_t rate; 2139 int ridx, i, j; 2140 2141 DPRINTF(("new assoc isnew=%d addr=%s\n", 2142 isnew, ether_sprintf(ni->ni_macaddr))); 2143 2144 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2145 /* start at lowest available bit-rate, AMRR will raise */ 2146 ni->ni_txrate = 0; 2147 2148 for (i = 0; i < rs->rs_nrates; i++) { 2149 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2150 /* convert 802.11 rate to hardware rate index */ 2151 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2152 if (rt2860_rates[ridx].rate == rate) 2153 break; 2154 rn->ridx[i] = ridx; 2155 /* determine rate of control response frames */ 2156 for (j = i; j >= 0; j--) { 2157 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2158 rt2860_rates[rn->ridx[i]].phy == 2159 rt2860_rates[rn->ridx[j]].phy) 2160 break; 2161 } 2162 if (j >= 0) { 2163 rn->ctl_ridx[i] = rn->ridx[j]; 2164 } else { 2165 /* no basic rate found, use mandatory one */ 2166 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2167 } 2168 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2169 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2170 } 2171 } 2172 2173 /* 2174 * Return the Rx chain with the highest RSSI for a given frame. 2175 */ 2176 static __inline uint8_t 2177 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2178 { 2179 uint8_t rxchain = 0; 2180 2181 if (sc->nrxchains > 1) { 2182 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2183 rxchain = 1; 2184 if (sc->nrxchains > 2) 2185 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2186 rxchain = 2; 2187 } 2188 return rxchain; 2189 } 2190 2191 static void 2192 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2193 { 2194 struct ieee80211com *ic = &sc->sc_ic; 2195 struct ifnet *ifp = &sc->sc_if; 2196 struct ieee80211_frame *wh; 2197 struct ieee80211_node *ni; 2198 struct rt2870_rxd *rxd; 2199 struct rt2860_rxwi *rxwi; 2200 struct mbuf *m; 2201 uint32_t flags; 2202 uint16_t len, rxwisize, phy; 2203 uint8_t ant, rssi; 2204 int s; 2205 #ifdef RUN_HWCRYPTO 2206 int decrypted = 0; 2207 #endif 2208 2209 rxwi = (struct rt2860_rxwi *)buf; 2210 len = le16toh(rxwi->len) & 0xfff; 2211 if (__predict_false(len > dmalen)) { 2212 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2213 return; 2214 } 2215 /* Rx descriptor is located at the end */ 2216 rxd = (struct rt2870_rxd *)(buf + dmalen); 2217 flags = le32toh(rxd->flags); 2218 2219 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2220 ifp->if_ierrors++; 2221 return; 2222 } 2223 2224 rxwisize = sizeof(struct rt2860_rxwi); 2225 if (sc->mac_ver == 0x5592) 2226 rxwisize += sizeof(uint64_t); 2227 else if (sc->mac_ver == 0x3593) 2228 rxwisize += sizeof(uint32_t); 2229 2230 wh = (struct ieee80211_frame *)(((uint8_t *)rxwi) + rxwisize); 2231 #ifdef RUN_HWCRYPTO 2232 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2233 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2234 decrypted = 1; 2235 } 2236 #endif 2237 2238 if (__predict_false((flags & RT2860_RX_MICERR))) { 2239 /* report MIC failures to net80211 for TKIP */ 2240 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 2241 ifp->if_ierrors++; 2242 return; 2243 } 2244 2245 if (flags & RT2860_RX_L2PAD) { 2246 u_int hdrlen = ieee80211_hdrspace(ic, wh); 2247 memmove((uint8_t *)wh + 2, wh, hdrlen); 2248 wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); 2249 } 2250 2251 /* could use m_devget but net80211 wants contig mgmt frames */ 2252 MGETHDR(m, M_DONTWAIT, MT_DATA); 2253 if (__predict_false(m == NULL)) { 2254 ifp->if_ierrors++; 2255 return; 2256 } 2257 if (len > MHLEN) { 2258 MCLGET(m, M_DONTWAIT); 2259 if (__predict_false(!(m->m_flags & M_EXT))) { 2260 ifp->if_ierrors++; 2261 m_freem(m); 2262 return; 2263 } 2264 } 2265 /* finalize mbuf */ 2266 m_set_rcvif(m, ifp); 2267 memcpy(mtod(m, void *), wh, len); 2268 m->m_pkthdr.len = m->m_len = len; 2269 2270 ant = run_maxrssi_chain(sc, rxwi); 2271 rssi = rxwi->rssi[ant]; 2272 2273 if (__predict_false(sc->sc_drvbpf != NULL)) { 2274 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2275 2276 tap->wr_flags = 0; 2277 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2278 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2279 tap->wr_antsignal = rssi; 2280 tap->wr_antenna = ant; 2281 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2282 tap->wr_rate = 2; /* in case it can't be found below */ 2283 phy = le16toh(rxwi->phy); 2284 switch (phy & RT2860_PHY_MODE) { 2285 case RT2860_PHY_CCK: 2286 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2287 case 0: tap->wr_rate = 2; break; 2288 case 1: tap->wr_rate = 4; break; 2289 case 2: tap->wr_rate = 11; break; 2290 case 3: tap->wr_rate = 22; break; 2291 } 2292 if (phy & RT2860_PHY_SHPRE) 2293 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2294 break; 2295 case RT2860_PHY_OFDM: 2296 switch (phy & RT2860_PHY_MCS) { 2297 case 0: tap->wr_rate = 12; break; 2298 case 1: tap->wr_rate = 18; break; 2299 case 2: tap->wr_rate = 24; break; 2300 case 3: tap->wr_rate = 36; break; 2301 case 4: tap->wr_rate = 48; break; 2302 case 5: tap->wr_rate = 72; break; 2303 case 6: tap->wr_rate = 96; break; 2304 case 7: tap->wr_rate = 108; break; 2305 } 2306 break; 2307 } 2308 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2309 } 2310 2311 s = splnet(); 2312 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2313 #ifdef RUN_HWCRYPTO 2314 if (decrypted) { 2315 uint32_t icflags = ic->ic_flags; 2316 2317 ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ 2318 ieee80211_input(ic, m, ni, rssi, 0); 2319 ic->ic_flags = icflags; 2320 } else 2321 #endif 2322 ieee80211_input(ic, m, ni, rssi, 0); 2323 2324 /* node is no longer needed */ 2325 ieee80211_free_node(ni); 2326 2327 /* 2328 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 2329 * without calling if_start(). 2330 */ 2331 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 2332 run_start(ifp); 2333 2334 splx(s); 2335 } 2336 2337 static void 2338 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2339 { 2340 struct run_rx_data *data = priv; 2341 struct run_softc *sc = data->sc; 2342 uint8_t *buf; 2343 uint32_t dmalen; 2344 int xferlen; 2345 2346 if (__predict_false(sc->sc_flags & RUN_DETACHING)) 2347 return; 2348 2349 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2350 DPRINTF(("RX status=%d\n", status)); 2351 if (status == USBD_STALLED) 2352 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2353 if (status != USBD_CANCELLED) 2354 goto skip; 2355 return; 2356 } 2357 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2358 2359 if (__predict_false(xferlen < (int)(sizeof(uint32_t) + 2360 sizeof(struct rt2860_rxwi) + sizeof(struct rt2870_rxd)))) { 2361 DPRINTF(("xfer too short %d\n", xferlen)); 2362 goto skip; 2363 } 2364 2365 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2366 buf = data->buf; 2367 while (xferlen > 8) { 2368 dmalen = le32toh(*(uint32_t *)buf) & 0xffff; 2369 2370 if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || 2371 (dmalen & 3) != 0)) { 2372 DPRINTF(("bad DMA length %u (%x)\n", dmalen, dmalen)); 2373 break; 2374 } 2375 if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { 2376 DPRINTF(("bad DMA length %u > %d\n", 2377 dmalen + 8, xferlen)); 2378 break; 2379 } 2380 run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); 2381 buf += dmalen + 8; 2382 xferlen -= dmalen + 8; 2383 } 2384 2385 skip: /* setup a new transfer */ 2386 usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, 2387 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 2388 (void)usbd_transfer(xfer); 2389 } 2390 2391 static void 2392 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2393 { 2394 struct run_tx_data *data = priv; 2395 struct run_softc *sc = data->sc; 2396 struct run_tx_ring *txq = &sc->txq[data->qid]; 2397 struct ifnet *ifp = &sc->sc_if; 2398 int s; 2399 2400 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2401 DPRINTF(("TX status=%d\n", status)); 2402 if (status == USBD_STALLED) 2403 usbd_clear_endpoint_stall_async(txq->pipeh); 2404 ifp->if_oerrors++; 2405 return; 2406 } 2407 2408 s = splnet(); 2409 sc->sc_tx_timer = 0; 2410 ifp->if_opackets++; 2411 if (--txq->queued < RUN_TX_RING_COUNT) { 2412 sc->qfullmsk &= ~(1 << data->qid); 2413 ifp->if_flags &= ~IFF_OACTIVE; 2414 run_start(ifp); 2415 } 2416 splx(s); 2417 } 2418 2419 static int 2420 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2421 { 2422 struct ieee80211com *ic = &sc->sc_ic; 2423 struct run_node *rn = (void *)ni; 2424 struct ieee80211_frame *wh; 2425 #ifndef RUN_HWCRYPTO 2426 struct ieee80211_key *k; 2427 #endif 2428 struct run_tx_ring *ring; 2429 struct run_tx_data *data; 2430 struct rt2870_txd *txd; 2431 struct rt2860_txwi *txwi; 2432 uint16_t dur, mcs; 2433 uint8_t type, tid, qid, qos = 0; 2434 int error, hasqos, ridx, ctl_ridx, xferlen, txwisize; 2435 uint8_t pad; 2436 2437 wh = mtod(m, struct ieee80211_frame *); 2438 2439 #ifndef RUN_HWCRYPTO 2440 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2441 k = ieee80211_crypto_encap(ic, ni, m); 2442 if (k == NULL) { 2443 m_freem(m); 2444 return ENOBUFS; 2445 } 2446 2447 /* packet header may have moved, reset our local pointer */ 2448 wh = mtod(m, struct ieee80211_frame *); 2449 } 2450 #endif 2451 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2452 2453 if ((hasqos = ieee80211_has_qos(wh))) { 2454 qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; 2455 tid = qos & IEEE80211_QOS_TID; 2456 qid = TID_TO_WME_AC(tid); 2457 } else { 2458 tid = 0; 2459 qid = WME_AC_BE; 2460 } 2461 ring = &sc->txq[qid]; 2462 data = &ring->data[ring->cur]; 2463 2464 /* pickup a rate index */ 2465 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2466 type != IEEE80211_FC0_TYPE_DATA) { 2467 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2468 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2469 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2470 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 2471 ridx = sc->fixed_ridx; 2472 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2473 } else { 2474 ridx = rn->ridx[ni->ni_txrate]; 2475 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2476 } 2477 2478 /* get MCS code from rate index */ 2479 mcs = rt2860_rates[ridx].mcs; 2480 2481 txwisize = (sc->mac_ver == 0x5592) ? 2482 sizeof(*txwi) + sizeof(uint32_t) : sizeof(*txwi); 2483 xferlen = txwisize + m->m_pkthdr.len; 2484 /* roundup to 32-bit alignment */ 2485 xferlen = (xferlen + 3) & ~3; 2486 2487 txd = (struct rt2870_txd *)data->buf; 2488 txd->flags = RT2860_TX_QSEL_EDCA; 2489 txd->len = htole16(xferlen); 2490 2491 /* 2492 * Ether both are true or both are false, the header 2493 * are nicely aligned to 32-bit. So, no L2 padding. 2494 */ 2495 if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) 2496 pad = 0; 2497 else 2498 pad = 2; 2499 2500 /* setup TX Wireless Information */ 2501 txwi = (struct rt2860_txwi *)(txd + 1); 2502 txwi->flags = 0; 2503 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2504 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2505 RUN_AID2WCID(ni->ni_associd) : 0xff; 2506 txwi->len = htole16(m->m_pkthdr.len - pad); 2507 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2508 txwi->phy = htole16(RT2860_PHY_CCK); 2509 if (ridx != RT2860_RIDX_CCK1 && 2510 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2511 mcs |= RT2860_PHY_SHPRE; 2512 } else 2513 mcs |= RT2860_PHY_OFDM; 2514 txwi->phy |= htole16(mcs); 2515 2516 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2517 2518 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2519 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 2520 IEEE80211_QOS_ACKPOLICY_NOACK)) { 2521 txwi->xflags |= RT2860_TX_ACK; 2522 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2523 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2524 else 2525 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2526 *(uint16_t *)wh->i_dur = htole16(dur); 2527 } 2528 2529 #ifndef IEEE80211_STA_ONLY 2530 /* ask MAC to insert timestamp into probe responses */ 2531 if ((wh->i_fc[0] & 2532 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2533 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 2534 /* NOTE: beacons do not pass through tx_data() */ 2535 txwi->flags |= RT2860_TX_TS; 2536 #endif 2537 2538 if (__predict_false(sc->sc_drvbpf != NULL)) { 2539 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2540 2541 tap->wt_flags = 0; 2542 tap->wt_rate = rt2860_rates[ridx].rate; 2543 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2544 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2545 tap->wt_hwqueue = qid; 2546 if (mcs & RT2860_PHY_SHPRE) 2547 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2548 2549 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2550 } 2551 2552 m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); 2553 m_freem(m); 2554 2555 xferlen += sizeof(*txd) + 4; 2556 2557 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2558 USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); 2559 error = usbd_transfer(data->xfer); 2560 if (__predict_false(error != USBD_IN_PROGRESS && 2561 error != USBD_NORMAL_COMPLETION)) 2562 return error; 2563 2564 ieee80211_free_node(ni); 2565 2566 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2567 if (++ring->queued >= RUN_TX_RING_COUNT) 2568 sc->qfullmsk |= 1 << qid; 2569 2570 return 0; 2571 } 2572 2573 static void 2574 run_start(struct ifnet *ifp) 2575 { 2576 struct run_softc *sc = ifp->if_softc; 2577 struct ieee80211com *ic = &sc->sc_ic; 2578 struct ether_header *eh; 2579 struct ieee80211_node *ni; 2580 struct mbuf *m; 2581 2582 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2583 return; 2584 2585 for (;;) { 2586 if (sc->qfullmsk != 0) { 2587 ifp->if_flags |= IFF_OACTIVE; 2588 break; 2589 } 2590 /* send pending management frames first */ 2591 IF_DEQUEUE(&ic->ic_mgtq, m); 2592 if (m != NULL) { 2593 ni = M_GETCTX(m, struct ieee80211_node *); 2594 M_CLEARCTX(m); 2595 goto sendit; 2596 } 2597 if (ic->ic_state != IEEE80211_S_RUN) 2598 break; 2599 2600 /* encapsulate and send data frames */ 2601 IFQ_DEQUEUE(&ifp->if_snd, m); 2602 if (m == NULL) 2603 break; 2604 if (m->m_len < (int)sizeof(*eh) && 2605 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2606 ifp->if_oerrors++; 2607 continue; 2608 } 2609 2610 eh = mtod(m, struct ether_header *); 2611 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2612 if (ni == NULL) { 2613 m_freem(m); 2614 ifp->if_oerrors++; 2615 continue; 2616 } 2617 2618 bpf_mtap(ifp, m, BPF_D_OUT); 2619 2620 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2621 ieee80211_free_node(ni); 2622 ifp->if_oerrors++; 2623 continue; 2624 } 2625 sendit: 2626 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2627 2628 if (run_tx(sc, m, ni) != 0) { 2629 ieee80211_free_node(ni); 2630 ifp->if_oerrors++; 2631 continue; 2632 } 2633 2634 sc->sc_tx_timer = 5; 2635 ifp->if_timer = 1; 2636 } 2637 } 2638 2639 static void 2640 run_watchdog(struct ifnet *ifp) 2641 { 2642 struct run_softc *sc = ifp->if_softc; 2643 struct ieee80211com *ic = &sc->sc_ic; 2644 2645 ifp->if_timer = 0; 2646 2647 if (sc->sc_tx_timer > 0) { 2648 if (--sc->sc_tx_timer == 0) { 2649 device_printf(sc->sc_dev, "device timeout\n"); 2650 /* run_init(ifp); XXX needs a process context! */ 2651 ifp->if_oerrors++; 2652 return; 2653 } 2654 ifp->if_timer = 1; 2655 } 2656 2657 ieee80211_watchdog(ic); 2658 } 2659 2660 static int 2661 run_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2662 { 2663 struct run_softc *sc = ifp->if_softc; 2664 struct ieee80211com *ic = &sc->sc_ic; 2665 int s, error = 0; 2666 2667 s = splnet(); 2668 2669 switch (cmd) { 2670 case SIOCSIFFLAGS: 2671 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2672 break; 2673 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2674 case IFF_UP|IFF_RUNNING: 2675 break; 2676 case IFF_UP: 2677 run_init(ifp); 2678 break; 2679 case IFF_RUNNING: 2680 run_stop(ifp, 1); 2681 break; 2682 case 0: 2683 break; 2684 } 2685 break; 2686 2687 case SIOCADDMULTI: 2688 case SIOCDELMULTI: 2689 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2690 /* setup multicast filter, etc */ 2691 error = 0; 2692 } 2693 break; 2694 2695 default: 2696 error = ieee80211_ioctl(ic, cmd, data); 2697 break; 2698 } 2699 2700 if (error == ENETRESET) { 2701 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2702 (IFF_UP | IFF_RUNNING)) { 2703 run_init(ifp); 2704 } 2705 error = 0; 2706 } 2707 2708 splx(s); 2709 2710 return error; 2711 } 2712 2713 static void 2714 run_select_chan_group(struct run_softc *sc, int group) 2715 { 2716 uint32_t tmp; 2717 uint8_t agc; 2718 2719 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2720 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2721 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2722 run_bbp_write(sc, 86, 0x00); 2723 2724 if (group == 0) { 2725 if (sc->ext_2ghz_lna) { 2726 run_bbp_write(sc, 82, 0x62); 2727 run_bbp_write(sc, 75, 0x46); 2728 } else { 2729 run_bbp_write(sc, 82, 0x84); 2730 run_bbp_write(sc, 75, 0x50); 2731 } 2732 } else { 2733 if (sc->mac_ver == 0x3572) 2734 run_bbp_write(sc, 82, 0x94); 2735 else 2736 run_bbp_write(sc, 82, 0xf2); 2737 if (sc->ext_5ghz_lna) 2738 run_bbp_write(sc, 75, 0x46); 2739 else 2740 run_bbp_write(sc, 75, 0x50); 2741 } 2742 2743 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2744 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2745 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2746 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2747 2748 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2749 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2750 if (sc->nrxchains > 1) 2751 tmp |= RT2860_LNA_PE1_EN; 2752 if (group == 0) { /* 2GHz */ 2753 tmp |= RT2860_PA_PE_G0_EN; 2754 if (sc->ntxchains > 1) 2755 tmp |= RT2860_PA_PE_G1_EN; 2756 } else { /* 5GHz */ 2757 tmp |= RT2860_PA_PE_A0_EN; 2758 if (sc->ntxchains > 1) 2759 tmp |= RT2860_PA_PE_A1_EN; 2760 } 2761 if (sc->mac_ver == 0x3572) { 2762 run_rt3070_rf_write(sc, 8, 0x00); 2763 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2764 run_rt3070_rf_write(sc, 8, 0x80); 2765 } else 2766 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2767 2768 /* set initial AGC value */ 2769 if (group == 0) { /* 2GHz band */ 2770 if (sc->mac_ver >= 0x3070) 2771 agc = 0x1c + sc->lna[0] * 2; 2772 else 2773 agc = 0x2e + sc->lna[0]; 2774 } else { /* 5GHz band */ 2775 if (sc->mac_ver == 0x3572) 2776 agc = 0x22 + (sc->lna[group] * 5) / 3; 2777 else 2778 agc = 0x32 + (sc->lna[group] * 5) / 3; 2779 } 2780 run_set_agc(sc, agc); 2781 } 2782 2783 static void 2784 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2785 { 2786 const struct rfprog *rfprog = rt2860_rf2850; 2787 uint32_t r2, r3, r4; 2788 int8_t txpow1, txpow2; 2789 int i; 2790 2791 /* find the settings for this channel (we know it exists) */ 2792 for (i = 0; rfprog[i].chan != chan; i++); 2793 2794 r2 = rfprog[i].r2; 2795 if (sc->ntxchains == 1) 2796 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2797 if (sc->nrxchains == 1) 2798 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2799 else if (sc->nrxchains == 2) 2800 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2801 2802 /* use Tx power values from EEPROM */ 2803 txpow1 = sc->txpow1[i]; 2804 txpow2 = sc->txpow2[i]; 2805 if (chan > 14) { 2806 if (txpow1 >= 0) 2807 txpow1 = txpow1 << 1 | 1; 2808 else 2809 txpow1 = (7 + txpow1) << 1; 2810 if (txpow2 >= 0) 2811 txpow2 = txpow2 << 1 | 1; 2812 else 2813 txpow2 = (7 + txpow2) << 1; 2814 } 2815 r3 = rfprog[i].r3 | txpow1 << 7; 2816 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2817 2818 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2819 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2820 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2821 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2822 2823 usbd_delay_ms(sc->sc_udev, 10); 2824 2825 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2826 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2827 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2828 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2829 2830 usbd_delay_ms(sc->sc_udev, 10); 2831 2832 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2833 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2834 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2835 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2836 } 2837 2838 static void 2839 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2840 { 2841 int8_t txpow1, txpow2; 2842 uint8_t rf; 2843 int i; 2844 2845 KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ 2846 2847 /* find the settings for this channel (we know it exists) */ 2848 for (i = 0; rt2860_rf2850[i].chan != chan; i++) 2849 continue; 2850 2851 /* use Tx power values from EEPROM */ 2852 txpow1 = sc->txpow1[i]; 2853 txpow2 = sc->txpow2[i]; 2854 2855 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2856 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2857 run_rt3070_rf_read(sc, 6, &rf); 2858 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2859 run_rt3070_rf_write(sc, 6, rf); 2860 2861 /* set Tx0 power */ 2862 run_rt3070_rf_read(sc, 12, &rf); 2863 rf = (rf & ~0x1f) | txpow1; 2864 run_rt3070_rf_write(sc, 12, rf); 2865 2866 /* set Tx1 power */ 2867 run_rt3070_rf_read(sc, 13, &rf); 2868 rf = (rf & ~0x1f) | txpow2; 2869 run_rt3070_rf_write(sc, 13, rf); 2870 2871 run_rt3070_rf_read(sc, 1, &rf); 2872 rf &= ~0xfc; 2873 if (sc->ntxchains == 1) 2874 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2875 else if (sc->ntxchains == 2) 2876 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2877 if (sc->nrxchains == 1) 2878 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2879 else if (sc->nrxchains == 2) 2880 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2881 run_rt3070_rf_write(sc, 1, rf); 2882 2883 /* set RF offset */ 2884 run_rt3070_rf_read(sc, 23, &rf); 2885 rf = (rf & ~0x7f) | sc->freq; 2886 run_rt3070_rf_write(sc, 23, rf); 2887 2888 /* program RF filter */ 2889 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 2890 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2891 run_rt3070_rf_write(sc, 24, rf); 2892 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 2893 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2894 run_rt3070_rf_write(sc, 31, rf); 2895 2896 /* enable RF tuning */ 2897 run_rt3070_rf_read(sc, 7, &rf); 2898 run_rt3070_rf_write(sc, 7, rf | 0x01); 2899 } 2900 2901 static void 2902 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 2903 { 2904 int8_t txpow1, txpow2; 2905 uint32_t tmp; 2906 uint8_t rf; 2907 int i; 2908 2909 /* find the settings for this channel (we know it exists) */ 2910 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2911 2912 /* use Tx power values from EEPROM */ 2913 txpow1 = sc->txpow1[i]; 2914 txpow2 = sc->txpow2[i]; 2915 2916 if (chan <= 14) { 2917 run_bbp_write(sc, 25, sc->bbp25); 2918 run_bbp_write(sc, 26, sc->bbp26); 2919 } else { 2920 /* enable IQ phase correction */ 2921 run_bbp_write(sc, 25, 0x09); 2922 run_bbp_write(sc, 26, 0xff); 2923 } 2924 2925 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2926 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 2927 run_rt3070_rf_read(sc, 6, &rf); 2928 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 2929 rf |= (chan <= 14) ? 0x08 : 0x04; 2930 run_rt3070_rf_write(sc, 6, rf); 2931 2932 /* set PLL mode */ 2933 run_rt3070_rf_read(sc, 5, &rf); 2934 rf &= ~(0x08 | 0x04); 2935 rf |= (chan <= 14) ? 0x04 : 0x08; 2936 run_rt3070_rf_write(sc, 5, rf); 2937 2938 /* set Tx power for chain 0 */ 2939 if (chan <= 14) 2940 rf = 0x60 | txpow1; 2941 else 2942 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 2943 run_rt3070_rf_write(sc, 12, rf); 2944 2945 /* set Tx power for chain 1 */ 2946 if (chan <= 14) 2947 rf = 0x60 | txpow2; 2948 else 2949 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 2950 run_rt3070_rf_write(sc, 13, rf); 2951 2952 /* set Tx/Rx streams */ 2953 run_rt3070_rf_read(sc, 1, &rf); 2954 rf &= ~0xfc; 2955 if (sc->ntxchains == 1) 2956 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2957 else if (sc->ntxchains == 2) 2958 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2959 if (sc->nrxchains == 1) 2960 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2961 else if (sc->nrxchains == 2) 2962 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2963 run_rt3070_rf_write(sc, 1, rf); 2964 2965 /* set RF offset */ 2966 run_rt3070_rf_read(sc, 23, &rf); 2967 rf = (rf & ~0x7f) | sc->freq; 2968 run_rt3070_rf_write(sc, 23, rf); 2969 2970 /* program RF filter */ 2971 rf = sc->rf24_20mhz; 2972 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 2973 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 2974 2975 /* enable RF tuning */ 2976 run_rt3070_rf_read(sc, 7, &rf); 2977 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 2978 run_rt3070_rf_write(sc, 7, rf); 2979 2980 /* TSSI */ 2981 rf = (chan <= 14) ? 0xc3 : 0xc0; 2982 run_rt3070_rf_write(sc, 9, rf); 2983 2984 /* set loop filter 1 */ 2985 run_rt3070_rf_write(sc, 10, 0xf1); 2986 /* set loop filter 2 */ 2987 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 2988 2989 /* set tx_mx2_ic */ 2990 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 2991 /* set tx_mx1_ic */ 2992 if (chan <= 14) 2993 rf = 0x48 | sc->txmixgain_2ghz; 2994 else 2995 rf = 0x78 | sc->txmixgain_5ghz; 2996 run_rt3070_rf_write(sc, 16, rf); 2997 2998 /* set tx_lo1 */ 2999 run_rt3070_rf_write(sc, 17, 0x23); 3000 /* set tx_lo2 */ 3001 if (chan <= 14) 3002 rf = 0x93; 3003 else if (chan <= 64) 3004 rf = 0xb7; 3005 else if (chan <= 128) 3006 rf = 0x74; 3007 else 3008 rf = 0x72; 3009 run_rt3070_rf_write(sc, 19, rf); 3010 3011 /* set rx_lo1 */ 3012 if (chan <= 14) 3013 rf = 0xb3; 3014 else if (chan <= 64) 3015 rf = 0xf6; 3016 else if (chan <= 128) 3017 rf = 0xf4; 3018 else 3019 rf = 0xf3; 3020 run_rt3070_rf_write(sc, 20, rf); 3021 3022 /* set pfd_delay */ 3023 if (chan <= 14) 3024 rf = 0x15; 3025 else if (chan <= 64) 3026 rf = 0x3d; 3027 else 3028 rf = 0x01; 3029 run_rt3070_rf_write(sc, 25, rf); 3030 3031 /* set rx_lo2 */ 3032 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3033 /* set ldo_rf_vc */ 3034 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3035 /* set drv_cc */ 3036 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3037 3038 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3039 tmp &= ~0x8080; 3040 if (chan <= 14) 3041 tmp |= 0x80; 3042 run_write(sc, RT2860_GPIO_CTRL, tmp); 3043 3044 /* enable RF tuning */ 3045 run_rt3070_rf_read(sc, 7, &rf); 3046 run_rt3070_rf_write(sc, 7, rf | 0x01); 3047 3048 usbd_delay_ms(sc->sc_udev, 2); 3049 } 3050 3051 static void 3052 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3053 { 3054 int8_t txpow1, txpow2, txpow3; 3055 uint8_t h20mhz, rf; 3056 int i; 3057 3058 /* find the settings for this channel (we know it exists) */ 3059 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3060 3061 /* use Tx power values from EEPROM */ 3062 txpow1 = sc->txpow1[i]; 3063 txpow2 = sc->txpow2[i]; 3064 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3065 3066 if (chan <= 14) { 3067 run_bbp_write(sc, 25, sc->bbp25); 3068 run_bbp_write(sc, 26, sc->bbp26); 3069 } else { 3070 /* Enable IQ phase correction. */ 3071 run_bbp_write(sc, 25, 0x09); 3072 run_bbp_write(sc, 26, 0xff); 3073 } 3074 3075 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3076 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3077 run_rt3070_rf_read(sc, 11, &rf); 3078 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3079 run_rt3070_rf_write(sc, 11, rf); 3080 3081 /* Set pll_idoh. */ 3082 run_rt3070_rf_read(sc, 11, &rf); 3083 rf &= ~0x4c; 3084 rf |= (chan <= 14) ? 0x44 : 0x48; 3085 run_rt3070_rf_write(sc, 11, rf); 3086 3087 if (chan <= 14) 3088 rf = txpow1 & 0x1f; 3089 else 3090 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3091 run_rt3070_rf_write(sc, 53, rf); 3092 3093 if (chan <= 14) 3094 rf = txpow2 & 0x1f; 3095 else 3096 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3097 run_rt3070_rf_write(sc, 55, rf); 3098 3099 if (chan <= 14) 3100 rf = txpow3 & 0x1f; 3101 else 3102 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3103 run_rt3070_rf_write(sc, 54, rf); 3104 3105 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3106 if (sc->ntxchains == 3) 3107 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3108 else 3109 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3110 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3111 run_rt3070_rf_write(sc, 1, rf); 3112 3113 run_adjust_freq_offset(sc); 3114 3115 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3116 3117 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3118 run_rt3070_rf_read(sc, 30, &rf); 3119 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3120 run_rt3070_rf_write(sc, 30, rf); 3121 3122 run_rt3070_rf_read(sc, 36, &rf); 3123 if (chan <= 14) 3124 rf |= 0x80; 3125 else 3126 rf &= ~0x80; 3127 run_rt3070_rf_write(sc, 36, rf); 3128 3129 /* Set vcolo_bs. */ 3130 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3131 /* Set pfd_delay. */ 3132 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3133 3134 /* Set vco bias current control. */ 3135 run_rt3070_rf_read(sc, 6, &rf); 3136 rf &= ~0xc0; 3137 if (chan <= 14) 3138 rf |= 0x40; 3139 else if (chan <= 128) 3140 rf |= 0x80; 3141 else 3142 rf |= 0x40; 3143 run_rt3070_rf_write(sc, 6, rf); 3144 3145 run_rt3070_rf_read(sc, 30, &rf); 3146 rf = (rf & ~0x18) | 0x10; 3147 run_rt3070_rf_write(sc, 30, rf); 3148 3149 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3150 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3151 3152 run_rt3070_rf_read(sc, 51, &rf); 3153 rf = (rf & ~0x03) | 0x01; 3154 run_rt3070_rf_write(sc, 51, rf); 3155 /* Set tx_mx1_cc. */ 3156 run_rt3070_rf_read(sc, 51, &rf); 3157 rf &= ~0x1c; 3158 rf |= (chan <= 14) ? 0x14 : 0x10; 3159 run_rt3070_rf_write(sc, 51, rf); 3160 /* Set tx_mx1_ic. */ 3161 run_rt3070_rf_read(sc, 51, &rf); 3162 rf &= ~0xe0; 3163 rf |= (chan <= 14) ? 0x60 : 0x40; 3164 run_rt3070_rf_write(sc, 51, rf); 3165 /* Set tx_lo1_ic. */ 3166 run_rt3070_rf_read(sc, 49, &rf); 3167 rf &= ~0x1c; 3168 rf |= (chan <= 14) ? 0x0c : 0x08; 3169 run_rt3070_rf_write(sc, 49, rf); 3170 /* Set tx_lo1_en. */ 3171 run_rt3070_rf_read(sc, 50, &rf); 3172 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3173 /* Set drv_cc. */ 3174 run_rt3070_rf_read(sc, 57, &rf); 3175 rf &= ~0xfc; 3176 rf |= (chan <= 14) ? 0x6c : 0x3c; 3177 run_rt3070_rf_write(sc, 57, rf); 3178 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3179 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3180 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3181 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3182 /* Enable VCO calibration. */ 3183 run_rt3070_rf_read(sc, 3, &rf); 3184 rf &= ~RT5390_VCOCAL; 3185 rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; 3186 run_rt3070_rf_write(sc, 3, rf); 3187 3188 if (chan <= 14) 3189 rf = 0x23; 3190 else if (chan <= 64) 3191 rf = 0x36; 3192 else if (chan <= 128) 3193 rf = 0x32; 3194 else 3195 rf = 0x30; 3196 run_rt3070_rf_write(sc, 39, rf); 3197 if (chan <= 14) 3198 rf = 0xbb; 3199 else if (chan <= 64) 3200 rf = 0xeb; 3201 else if (chan <= 128) 3202 rf = 0xb3; 3203 else 3204 rf = 0x9b; 3205 run_rt3070_rf_write(sc, 45, rf); 3206 3207 /* Set FEQ/AEQ control. */ 3208 run_bbp_write(sc, 105, 0x34); 3209 } 3210 3211 static void 3212 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3213 { 3214 int8_t txpow1, txpow2; 3215 uint8_t rf; 3216 int i; 3217 3218 /* find the settings for this channel (we know it exists) */ 3219 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3220 3221 /* use Tx power values from EEPROM */ 3222 txpow1 = sc->txpow1[i]; 3223 txpow2 = sc->txpow2[i]; 3224 3225 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3226 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3227 run_rt3070_rf_read(sc, 11, &rf); 3228 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3229 run_rt3070_rf_write(sc, 11, rf); 3230 3231 run_rt3070_rf_read(sc, 49, &rf); 3232 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3233 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3234 if ((rf & 0x3f) > 0x27) 3235 rf = (rf & ~0x3f) | 0x27; 3236 run_rt3070_rf_write(sc, 49, rf); 3237 3238 if (sc->mac_ver == 0x5392) { 3239 run_rt3070_rf_read(sc, 50, &rf); 3240 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3241 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3242 if ((rf & 0x3f) > 0x27) 3243 rf = (rf & ~0x3f) | 0x27; 3244 run_rt3070_rf_write(sc, 50, rf); 3245 } 3246 3247 run_rt3070_rf_read(sc, 1, &rf); 3248 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3249 if (sc->mac_ver == 0x5392) 3250 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3251 run_rt3070_rf_write(sc, 1, rf); 3252 3253 if (sc->mac_ver != 0x5392) { 3254 run_rt3070_rf_read(sc, 2, &rf); 3255 rf |= 0x80; 3256 run_rt3070_rf_write(sc, 2, rf); 3257 usbd_delay_ms(sc->sc_udev, 10); 3258 rf &= 0x7f; 3259 run_rt3070_rf_write(sc, 2, rf); 3260 } 3261 3262 run_adjust_freq_offset(sc); 3263 3264 if (sc->mac_ver == 0x5392) { 3265 /* Fix for RT5392C. */ 3266 if (sc->mac_rev >= 0x0223) { 3267 if (chan <= 4) 3268 rf = 0x0f; 3269 else if (chan >= 5 && chan <= 7) 3270 rf = 0x0e; 3271 else 3272 rf = 0x0d; 3273 run_rt3070_rf_write(sc, 23, rf); 3274 3275 if (chan <= 4) 3276 rf = 0x0c; 3277 else if (chan == 5) 3278 rf = 0x0b; 3279 else if (chan >= 6 && chan <= 7) 3280 rf = 0x0a; 3281 else if (chan >= 8 && chan <= 10) 3282 rf = 0x09; 3283 else 3284 rf = 0x08; 3285 run_rt3070_rf_write(sc, 59, rf); 3286 } else { 3287 if (chan <= 11) 3288 rf = 0x0f; 3289 else 3290 rf = 0x0b; 3291 run_rt3070_rf_write(sc, 59, rf); 3292 } 3293 } else { 3294 /* Fix for RT5390F. */ 3295 if (sc->mac_rev >= 0x0502) { 3296 if (chan <= 11) 3297 rf = 0x43; 3298 else 3299 rf = 0x23; 3300 run_rt3070_rf_write(sc, 55, rf); 3301 3302 if (chan <= 11) 3303 rf = 0x0f; 3304 else if (chan == 12) 3305 rf = 0x0d; 3306 else 3307 rf = 0x0b; 3308 run_rt3070_rf_write(sc, 59, rf); 3309 } else { 3310 run_rt3070_rf_write(sc, 55, 0x44); 3311 run_rt3070_rf_write(sc, 59, 0x8f); 3312 } 3313 } 3314 3315 /* Enable VCO calibration. */ 3316 run_rt3070_rf_read(sc, 3, &rf); 3317 rf |= RT5390_VCOCAL; 3318 run_rt3070_rf_write(sc, 3, rf); 3319 } 3320 3321 static void 3322 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3323 { 3324 const struct rt5592_freqs *freqs; 3325 uint32_t tmp; 3326 uint8_t reg, rf, txpow_bound; 3327 int8_t txpow1, txpow2; 3328 int i; 3329 3330 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3331 freqs = (tmp & RT5592_SEL_XTAL) ? 3332 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3333 3334 /* find the settings for this channel (we know it exists) */ 3335 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3336 3337 /* use Tx power values from EEPROM */ 3338 txpow1 = sc->txpow1[i]; 3339 txpow2 = sc->txpow2[i]; 3340 3341 run_read(sc, RT3070_LDO_CFG0, &tmp); 3342 tmp &= ~0x1c000000; 3343 if (chan > 14) 3344 tmp |= 0x14000000; 3345 run_write(sc, RT3070_LDO_CFG0, tmp); 3346 3347 /* N setting. */ 3348 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3349 run_rt3070_rf_read(sc, 9, &rf); 3350 rf &= ~(1 << 4); 3351 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3352 run_rt3070_rf_write(sc, 9, rf); 3353 3354 /* K setting. */ 3355 run_rt3070_rf_read(sc, 9, &rf); 3356 rf &= ~0x0f; 3357 rf |= (freqs->k & 0x0f); 3358 run_rt3070_rf_write(sc, 9, rf); 3359 3360 /* Mode setting. */ 3361 run_rt3070_rf_read(sc, 11, &rf); 3362 rf &= ~0x0c; 3363 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3364 run_rt3070_rf_write(sc, 11, rf); 3365 run_rt3070_rf_read(sc, 9, &rf); 3366 rf &= ~(1 << 7); 3367 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3368 run_rt3070_rf_write(sc, 9, rf); 3369 3370 /* R setting. */ 3371 run_rt3070_rf_read(sc, 11, &rf); 3372 rf &= ~0x03; 3373 rf |= (freqs->r - 0x1); 3374 run_rt3070_rf_write(sc, 11, rf); 3375 3376 if (chan <= 14) { 3377 /* Initialize RF registers for 2GHZ. */ 3378 for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { 3379 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3380 rt5592_2ghz_def_rf[i].val); 3381 } 3382 3383 rf = (chan <= 10) ? 0x07 : 0x06; 3384 run_rt3070_rf_write(sc, 23, rf); 3385 run_rt3070_rf_write(sc, 59, rf); 3386 3387 run_rt3070_rf_write(sc, 55, 0x43); 3388 3389 /* 3390 * RF R49/R50 Tx power ALC code. 3391 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3392 */ 3393 reg = 2; 3394 txpow_bound = 0x27; 3395 } else { 3396 /* Initialize RF registers for 5GHZ. */ 3397 for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { 3398 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3399 rt5592_5ghz_def_rf[i].val); 3400 } 3401 for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { 3402 if (chan >= rt5592_chan_5ghz[i].firstchan && 3403 chan <= rt5592_chan_5ghz[i].lastchan) { 3404 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3405 rt5592_chan_5ghz[i].val); 3406 } 3407 } 3408 3409 /* 3410 * RF R49/R50 Tx power ALC code. 3411 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3412 */ 3413 reg = 3; 3414 txpow_bound = 0x2b; 3415 } 3416 3417 /* RF R49 ch0 Tx power ALC code. */ 3418 run_rt3070_rf_read(sc, 49, &rf); 3419 rf &= ~0xc0; 3420 rf |= (reg << 6); 3421 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3422 if ((rf & 0x3f) > txpow_bound) 3423 rf = (rf & ~0x3f) | txpow_bound; 3424 run_rt3070_rf_write(sc, 49, rf); 3425 3426 /* RF R50 ch1 Tx power ALC code. */ 3427 run_rt3070_rf_read(sc, 50, &rf); 3428 rf &= ~(1 << 7 | 1 << 6); 3429 rf |= (reg << 6); 3430 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3431 if ((rf & 0x3f) > txpow_bound) 3432 rf = (rf & ~0x3f) | txpow_bound; 3433 run_rt3070_rf_write(sc, 50, rf); 3434 3435 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3436 run_rt3070_rf_read(sc, 1, &rf); 3437 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3438 if (sc->ntxchains > 1) 3439 rf |= RT3070_TX1_PD; 3440 if (sc->nrxchains > 1) 3441 rf |= RT3070_RX1_PD; 3442 run_rt3070_rf_write(sc, 1, rf); 3443 3444 run_rt3070_rf_write(sc, 6, 0xe4); 3445 3446 run_rt3070_rf_write(sc, 30, 0x10); 3447 run_rt3070_rf_write(sc, 31, 0x80); 3448 run_rt3070_rf_write(sc, 32, 0x80); 3449 3450 run_adjust_freq_offset(sc); 3451 3452 /* Enable VCO calibration. */ 3453 run_rt3070_rf_read(sc, 3, &rf); 3454 rf |= RT5390_VCOCAL; 3455 run_rt3070_rf_write(sc, 3, rf); 3456 } 3457 3458 static void 3459 run_iq_calib(struct run_softc *sc, u_int chan) 3460 { 3461 uint16_t val; 3462 3463 /* Tx0 IQ gain. */ 3464 run_bbp_write(sc, 158, 0x2c); 3465 if (chan <= 14) 3466 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); 3467 else if (chan <= 64) { 3468 run_efuse_read(sc, 3469 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, 3470 &val, 1); 3471 } else if (chan <= 138) { 3472 run_efuse_read(sc, 3473 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, 3474 &val, 1); 3475 } else if (chan <= 165) { 3476 run_efuse_read(sc, 3477 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 3478 &val, 1); 3479 } else 3480 val = 0; 3481 run_bbp_write(sc, 159, val); 3482 3483 /* Tx0 IQ phase. */ 3484 run_bbp_write(sc, 158, 0x2d); 3485 if (chan <= 14) { 3486 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, 3487 &val, 1); 3488 } else if (chan <= 64) { 3489 run_efuse_read(sc, 3490 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, 3491 &val, 1); 3492 } else if (chan <= 138) { 3493 run_efuse_read(sc, 3494 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, 3495 &val, 1); 3496 } else if (chan <= 165) { 3497 run_efuse_read(sc, 3498 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, 3499 &val, 1); 3500 } else 3501 val = 0; 3502 run_bbp_write(sc, 159, val); 3503 3504 /* Tx1 IQ gain. */ 3505 run_bbp_write(sc, 158, 0x4a); 3506 if (chan <= 14) { 3507 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, 3508 &val, 1); 3509 } else if (chan <= 64) { 3510 run_efuse_read(sc, 3511 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, 3512 &val, 1); 3513 } else if (chan <= 138) { 3514 run_efuse_read(sc, 3515 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, 3516 &val, 1); 3517 } else if (chan <= 165) { 3518 run_efuse_read(sc, 3519 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, 3520 &val, 1); 3521 } else 3522 val = 0; 3523 run_bbp_write(sc, 159, val); 3524 3525 /* Tx1 IQ phase. */ 3526 run_bbp_write(sc, 158, 0x4b); 3527 if (chan <= 14) { 3528 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, 3529 &val, 1); 3530 } else if (chan <= 64) { 3531 run_efuse_read(sc, 3532 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, 3533 &val, 1); 3534 } else if (chan <= 138) { 3535 run_efuse_read(sc, 3536 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, 3537 &val, 1); 3538 } else if (chan <= 165) { 3539 run_efuse_read(sc, 3540 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, 3541 &val, 1); 3542 } else 3543 val = 0; 3544 run_bbp_write(sc, 159, val); 3545 3546 /* RF IQ compensation control. */ 3547 run_bbp_write(sc, 158, 0x04); 3548 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, 3549 &val, 1); 3550 run_bbp_write(sc, 159, val); 3551 3552 /* RF IQ imbalance compensation control. */ 3553 run_bbp_write(sc, 158, 0x03); 3554 run_efuse_read(sc, 3555 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); 3556 run_bbp_write(sc, 159, val); 3557 } 3558 3559 static void 3560 run_set_agc(struct run_softc *sc, uint8_t agc) 3561 { 3562 uint8_t bbp; 3563 3564 if (sc->mac_ver == 0x3572) { 3565 run_bbp_read(sc, 27, &bbp); 3566 bbp &= ~(0x3 << 5); 3567 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3568 run_bbp_write(sc, 66, agc); 3569 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3570 run_bbp_write(sc, 66, agc); 3571 } else 3572 run_bbp_write(sc, 66, agc); 3573 } 3574 3575 static void 3576 run_set_rx_antenna(struct run_softc *sc, int aux) 3577 { 3578 uint32_t tmp; 3579 uint8_t bbp152; 3580 3581 if (sc->rf_rev == RT5390_RF_5370) { 3582 run_bbp_read(sc, 152, &bbp152); 3583 bbp152 &= ~0x80; 3584 if (aux) 3585 bbp152 |= 0x80; 3586 run_bbp_write(sc, 152, bbp152); 3587 } else { 3588 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); 3589 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3590 tmp &= ~0x0808; 3591 if (aux) 3592 tmp |= 0x08; 3593 run_write(sc, RT2860_GPIO_CTRL, tmp); 3594 } 3595 } 3596 3597 static int 3598 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3599 { 3600 struct ieee80211com *ic = &sc->sc_ic; 3601 u_int chan, group; 3602 3603 chan = ieee80211_chan2ieee(ic, c); 3604 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3605 return EINVAL; 3606 3607 if (sc->mac_ver == 0x5592) 3608 run_rt5592_set_chan(sc, chan); 3609 else if (sc->mac_ver >= 0x5390) 3610 run_rt5390_set_chan(sc, chan); 3611 else if (sc->mac_ver == 0x3593) 3612 run_rt3593_set_chan(sc, chan); 3613 else if (sc->mac_ver == 0x3572) 3614 run_rt3572_set_chan(sc, chan); 3615 else if (sc->mac_ver >= 0x3070) 3616 run_rt3070_set_chan(sc, chan); 3617 else 3618 run_rt2870_set_chan(sc, chan); 3619 3620 /* determine channel group */ 3621 if (chan <= 14) 3622 group = 0; 3623 else if (chan <= 64) 3624 group = 1; 3625 else if (chan <= 128) 3626 group = 2; 3627 else 3628 group = 3; 3629 3630 /* XXX necessary only when group has changed! */ 3631 run_select_chan_group(sc, group); 3632 3633 usbd_delay_ms(sc->sc_udev, 10); 3634 3635 /* Perform IQ calibration. */ 3636 if (sc->mac_ver >= 0x5392) 3637 run_iq_calib(sc, chan); 3638 3639 return 0; 3640 } 3641 3642 static void 3643 run_updateprot(struct run_softc *sc) 3644 { 3645 struct ieee80211com *ic = &sc->sc_ic; 3646 uint32_t tmp; 3647 3648 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3649 /* setup protection frame rate (MCS code) */ 3650 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3651 rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : 3652 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3653 3654 /* CCK frames don't require protection */ 3655 run_write(sc, RT2860_CCK_PROT_CFG, tmp); 3656 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3657 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3658 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3659 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3660 tmp |= RT2860_PROT_CTRL_CTS; 3661 } 3662 run_write(sc, RT2860_OFDM_PROT_CFG, tmp); 3663 } 3664 3665 static void 3666 run_enable_tsf_sync(struct run_softc *sc) 3667 { 3668 struct ieee80211com *ic = &sc->sc_ic; 3669 uint32_t tmp; 3670 3671 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3672 tmp &= ~0x1fffff; 3673 tmp |= ic->ic_bss->ni_intval * 16; 3674 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3675 if (ic->ic_opmode == IEEE80211_M_STA) { 3676 /* 3677 * Local TSF is always updated with remote TSF on beacon 3678 * reception. 3679 */ 3680 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3681 } 3682 #ifndef IEEE80211_STA_ONLY 3683 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3684 tmp |= RT2860_BCN_TX_EN; 3685 /* 3686 * Local TSF is updated with remote TSF on beacon reception 3687 * only if the remote TSF is greater than local TSF. 3688 */ 3689 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3690 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3691 tmp |= RT2860_BCN_TX_EN; 3692 /* SYNC with nobody */ 3693 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3694 } 3695 #endif 3696 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3697 } 3698 3699 static void 3700 run_enable_mrr(struct run_softc *sc) 3701 { 3702 #define CCK(mcs) (mcs) 3703 #define OFDM(mcs) (1 << 3 | (mcs)) 3704 run_write(sc, RT2860_LG_FBK_CFG0, 3705 OFDM(6) << 28 | /* 54->48 */ 3706 OFDM(5) << 24 | /* 48->36 */ 3707 OFDM(4) << 20 | /* 36->24 */ 3708 OFDM(3) << 16 | /* 24->18 */ 3709 OFDM(2) << 12 | /* 18->12 */ 3710 OFDM(1) << 8 | /* 12-> 9 */ 3711 OFDM(0) << 4 | /* 9-> 6 */ 3712 OFDM(0)); /* 6-> 6 */ 3713 3714 run_write(sc, RT2860_LG_FBK_CFG1, 3715 CCK(2) << 12 | /* 11->5.5 */ 3716 CCK(1) << 8 | /* 5.5-> 2 */ 3717 CCK(0) << 4 | /* 2-> 1 */ 3718 CCK(0)); /* 1-> 1 */ 3719 #undef OFDM 3720 #undef CCK 3721 } 3722 3723 static void 3724 run_set_txpreamble(struct run_softc *sc) 3725 { 3726 uint32_t tmp; 3727 3728 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3729 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3730 tmp |= RT2860_CCK_SHORT_EN; 3731 else 3732 tmp &= ~RT2860_CCK_SHORT_EN; 3733 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3734 } 3735 3736 static void 3737 run_set_basicrates(struct run_softc *sc) 3738 { 3739 struct ieee80211com *ic = &sc->sc_ic; 3740 3741 /* set basic rates mask */ 3742 if (ic->ic_curmode == IEEE80211_MODE_11B) 3743 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3744 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3745 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3746 else /* 11g */ 3747 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3748 } 3749 3750 static void 3751 run_set_leds(struct run_softc *sc, uint16_t which) 3752 { 3753 3754 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3755 which | (sc->leds & 0x7f)); 3756 } 3757 3758 static void 3759 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3760 { 3761 3762 run_write(sc, RT2860_MAC_BSSID_DW0, 3763 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3764 run_write(sc, RT2860_MAC_BSSID_DW1, 3765 bssid[4] | bssid[5] << 8); 3766 } 3767 3768 static void 3769 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3770 { 3771 3772 run_write(sc, RT2860_MAC_ADDR_DW0, 3773 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3774 run_write(sc, RT2860_MAC_ADDR_DW1, 3775 addr[4] | addr[5] << 8 | 0xff << 16); 3776 } 3777 3778 static void 3779 run_updateslot(struct ifnet *ifp) 3780 { 3781 3782 /* do it in a process context */ 3783 run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); 3784 } 3785 3786 /* ARGSUSED */ 3787 static void 3788 run_updateslot_cb(struct run_softc *sc, void *arg) 3789 { 3790 uint32_t tmp; 3791 3792 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3793 tmp &= ~0xff; 3794 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3795 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3796 } 3797 3798 static int8_t 3799 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3800 { 3801 struct ieee80211com *ic = &sc->sc_ic; 3802 struct ieee80211_channel *c = ic->ic_curchan; 3803 int delta; 3804 3805 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3806 u_int chan = ieee80211_chan2ieee(ic, c); 3807 delta = sc->rssi_5ghz[rxchain]; 3808 3809 /* determine channel group */ 3810 if (chan <= 64) 3811 delta -= sc->lna[1]; 3812 else if (chan <= 128) 3813 delta -= sc->lna[2]; 3814 else 3815 delta -= sc->lna[3]; 3816 } else 3817 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3818 3819 return -12 - delta - rssi; 3820 } 3821 3822 static void 3823 run_rt5390_bbp_init(struct run_softc *sc) 3824 { 3825 u_int i; 3826 uint8_t bbp; 3827 3828 /* Apply maximum likelihood detection for 2 stream case. */ 3829 run_bbp_read(sc, 105, &bbp); 3830 if (sc->nrxchains > 1) 3831 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3832 3833 /* Avoid data lost and CRC error. */ 3834 run_bbp_read(sc, 4, &bbp); 3835 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3836 3837 if (sc->mac_ver == 0x5592) { 3838 for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { 3839 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3840 rt5592_def_bbp[i].val); 3841 } 3842 for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { 3843 run_bbp_write(sc, 195, i + 0x80); 3844 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3845 } 3846 } else { 3847 for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { 3848 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3849 rt5390_def_bbp[i].val); 3850 } 3851 } 3852 if (sc->mac_ver == 0x5392) { 3853 run_bbp_write(sc, 88, 0x90); 3854 run_bbp_write(sc, 95, 0x9a); 3855 run_bbp_write(sc, 98, 0x12); 3856 run_bbp_write(sc, 106, 0x12); 3857 run_bbp_write(sc, 134, 0xd0); 3858 run_bbp_write(sc, 135, 0xf6); 3859 run_bbp_write(sc, 148, 0x84); 3860 } 3861 3862 run_bbp_read(sc, 152, &bbp); 3863 run_bbp_write(sc, 152, bbp | 0x80); 3864 3865 /* Fix BBP254 for RT5592C. */ 3866 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3867 run_bbp_read(sc, 254, &bbp); 3868 run_bbp_write(sc, 254, bbp | 0x80); 3869 } 3870 3871 /* Disable hardware antenna diversity. */ 3872 if (sc->mac_ver == 0x5390) 3873 run_bbp_write(sc, 154, 0); 3874 3875 /* Initialize Rx CCK/OFDM frequency offset report. */ 3876 run_bbp_write(sc, 142, 1); 3877 run_bbp_write(sc, 143, 57); 3878 } 3879 3880 static int 3881 run_bbp_init(struct run_softc *sc) 3882 { 3883 int i, error, ntries; 3884 uint8_t bbp0; 3885 3886 /* wait for BBP to wake up */ 3887 for (ntries = 0; ntries < 20; ntries++) { 3888 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3889 return error; 3890 if (bbp0 != 0 && bbp0 != 0xff) 3891 break; 3892 } 3893 if (ntries == 20) 3894 return ETIMEDOUT; 3895 3896 /* initialize BBP registers to default values */ 3897 if (sc->mac_ver >= 0x5390) 3898 run_rt5390_bbp_init(sc); 3899 else { 3900 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 3901 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3902 rt2860_def_bbp[i].val); 3903 } 3904 } 3905 3906 if (sc->mac_ver == 0x3593) { 3907 run_bbp_write(sc, 79, 0x13); 3908 run_bbp_write(sc, 80, 0x05); 3909 run_bbp_write(sc, 81, 0x33); 3910 run_bbp_write(sc, 86, 0x46); 3911 run_bbp_write(sc, 137, 0x0f); 3912 } 3913 3914 /* fix BBP84 for RT2860E */ 3915 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3916 run_bbp_write(sc, 84, 0x19); 3917 3918 if (sc->mac_ver >= 0x3070) { 3919 run_bbp_write(sc, 79, 0x13); 3920 run_bbp_write(sc, 80, 0x05); 3921 run_bbp_write(sc, 81, 0x33); 3922 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3923 run_bbp_write(sc, 69, 0x16); 3924 run_bbp_write(sc, 73, 0x12); 3925 } 3926 return 0; 3927 } 3928 3929 static int 3930 run_rt3070_rf_init(struct run_softc *sc) 3931 { 3932 uint32_t tmp; 3933 uint8_t rf, target, bbp4; 3934 int i; 3935 3936 run_rt3070_rf_read(sc, 30, &rf); 3937 /* toggle RF R30 bit 7 */ 3938 run_rt3070_rf_write(sc, 30, rf | 0x80); 3939 usbd_delay_ms(sc->sc_udev, 10); 3940 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3941 3942 /* initialize RF registers to default value */ 3943 if (sc->mac_ver == 0x3572) { 3944 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 3945 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3946 rt3572_def_rf[i].val); 3947 } 3948 } else { 3949 for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { 3950 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3951 rt3070_def_rf[i].val); 3952 } 3953 } 3954 if (sc->mac_ver == 0x3572) { 3955 run_rt3070_rf_read(sc, 6, &rf); 3956 run_rt3070_rf_write(sc, 6, rf | 0x40); 3957 run_rt3070_rf_write(sc, 31, 0x14); 3958 3959 run_read(sc, RT3070_LDO_CFG0, &tmp); 3960 tmp &= ~0x1f000000; 3961 if (sc->mac_rev < 0x0211 && sc->patch_dac) 3962 tmp |= 0x0d000000; /* 1.3V */ 3963 else 3964 tmp |= 0x01000000; /* 1.2V */ 3965 run_write(sc, RT3070_LDO_CFG0, tmp); 3966 } else if (sc->mac_ver == 0x3071) { 3967 run_rt3070_rf_read(sc, 6, &rf); 3968 run_rt3070_rf_write(sc, 6, rf | 0x40); 3969 run_rt3070_rf_write(sc, 31, 0x14); 3970 3971 run_read(sc, RT3070_LDO_CFG0, &tmp); 3972 tmp &= ~0x1f000000; 3973 if (sc->mac_rev < 0x0211) 3974 tmp |= 0x0d000000; /* 1.35V */ 3975 else 3976 tmp |= 0x01000000; /* 1.2V */ 3977 run_write(sc, RT3070_LDO_CFG0, tmp); 3978 3979 /* patch LNA_PE_G1 */ 3980 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3981 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3982 } else if (sc->mac_ver == 0x3070) { 3983 /* increase voltage from 1.2V to 1.35V */ 3984 run_read(sc, RT3070_LDO_CFG0, &tmp); 3985 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3986 run_write(sc, RT3070_LDO_CFG0, tmp); 3987 } 3988 3989 /* select 20MHz bandwidth */ 3990 run_rt3070_rf_read(sc, 31, &rf); 3991 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3992 3993 /* calibrate filter for 20MHz bandwidth */ 3994 sc->rf24_20mhz = 0x1f; /* default value */ 3995 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3996 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3997 3998 /* select 40MHz bandwidth */ 3999 run_bbp_read(sc, 4, &bbp4); 4000 run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); 4001 run_rt3070_rf_read(sc, 31, &rf); 4002 run_rt3070_rf_write(sc, 31, rf | 0x20); 4003 4004 /* calibrate filter for 40MHz bandwidth */ 4005 sc->rf24_40mhz = 0x2f; /* default value */ 4006 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 4007 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 4008 4009 /* go back to 20MHz bandwidth */ 4010 run_bbp_read(sc, 4, &bbp4); 4011 run_bbp_write(sc, 4, bbp4 & ~0x18); 4012 4013 if (sc->mac_ver == 0x3572) { 4014 /* save default BBP registers 25 and 26 values */ 4015 run_bbp_read(sc, 25, &sc->bbp25); 4016 run_bbp_read(sc, 26, &sc->bbp26); 4017 } else if (sc->mac_rev < 0x0211) 4018 run_rt3070_rf_write(sc, 27, 0x03); 4019 4020 run_read(sc, RT3070_OPT_14, &tmp); 4021 run_write(sc, RT3070_OPT_14, tmp | 1); 4022 4023 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4024 run_rt3070_rf_read(sc, 17, &rf); 4025 rf &= ~RT3070_TX_LO1; 4026 if ((sc->mac_ver == 0x3070 || 4027 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4028 !sc->ext_2ghz_lna) 4029 rf |= 0x20; /* fix for long range Rx issue */ 4030 if (sc->txmixgain_2ghz >= 1) 4031 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4032 run_rt3070_rf_write(sc, 17, rf); 4033 } 4034 if (sc->mac_ver == 0x3071) { 4035 run_rt3070_rf_read(sc, 1, &rf); 4036 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4037 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4038 run_rt3070_rf_write(sc, 1, rf); 4039 4040 run_rt3070_rf_read(sc, 15, &rf); 4041 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4042 4043 run_rt3070_rf_read(sc, 20, &rf); 4044 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4045 4046 run_rt3070_rf_read(sc, 21, &rf); 4047 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4048 } 4049 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4050 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4051 run_rt3070_rf_read(sc, 27, &rf); 4052 rf &= ~0x77; 4053 if (sc->mac_rev < 0x0211) 4054 rf |= 0x03; 4055 run_rt3070_rf_write(sc, 27, rf); 4056 } 4057 return 0; 4058 } 4059 4060 static int 4061 run_rt3593_rf_init(struct run_softc *sc) 4062 { 4063 uint32_t tmp; 4064 uint8_t rf; 4065 int i; 4066 4067 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4068 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4069 tmp &= ~(1 << 4 | 1 << 7); 4070 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4071 4072 /* Initialize RF registers to default value. */ 4073 for (i = 0; i < __arraycount(rt3593_def_rf); i++) { 4074 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4075 rt3593_def_rf[i].val); 4076 } 4077 4078 /* Toggle RF R2 to initiate calibration. */ 4079 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4080 4081 /* Initialize RF frequency offset. */ 4082 run_adjust_freq_offset(sc); 4083 4084 run_rt3070_rf_read(sc, 18, &rf); 4085 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4086 4087 /* 4088 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4089 * decrease voltage back to 1.2V. 4090 */ 4091 run_read(sc, RT3070_LDO_CFG0, &tmp); 4092 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4093 run_write(sc, RT3070_LDO_CFG0, tmp); 4094 usbd_delay_ms(sc->sc_udev, 1); 4095 tmp = (tmp & ~0x1f000000) | 0x01000000; 4096 run_write(sc, RT3070_LDO_CFG0, tmp); 4097 4098 sc->rf24_20mhz = 0x1f; 4099 sc->rf24_40mhz = 0x2f; 4100 4101 /* Save default BBP registers 25 and 26 values. */ 4102 run_bbp_read(sc, 25, &sc->bbp25); 4103 run_bbp_read(sc, 26, &sc->bbp26); 4104 4105 run_read(sc, RT3070_OPT_14, &tmp); 4106 run_write(sc, RT3070_OPT_14, tmp | 1); 4107 return (0); 4108 } 4109 4110 static int 4111 run_rt5390_rf_init(struct run_softc *sc) 4112 { 4113 uint32_t tmp; 4114 uint8_t rf; 4115 int i; 4116 4117 /* Toggle RF R2 to initiate calibration. */ 4118 if (sc->mac_ver == 0x5390) { 4119 run_rt3070_rf_read(sc, 2, &rf); 4120 run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); 4121 usbd_delay_ms(sc->sc_udev, 10); 4122 run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); 4123 } else { 4124 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4125 usbd_delay_ms(sc->sc_udev, 10); 4126 } 4127 4128 /* Initialize RF registers to default value. */ 4129 if (sc->mac_ver == 0x5592) { 4130 for (i = 0; i < __arraycount(rt5592_def_rf); i++) { 4131 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4132 rt5592_def_rf[i].val); 4133 } 4134 /* Initialize RF frequency offset. */ 4135 run_adjust_freq_offset(sc); 4136 } else if (sc->mac_ver == 0x5392) { 4137 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 4138 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4139 rt5392_def_rf[i].val); 4140 } 4141 if (sc->mac_rev >= 0x0223) { 4142 run_rt3070_rf_write(sc, 23, 0x0f); 4143 run_rt3070_rf_write(sc, 24, 0x3e); 4144 run_rt3070_rf_write(sc, 51, 0x32); 4145 run_rt3070_rf_write(sc, 53, 0x22); 4146 run_rt3070_rf_write(sc, 56, 0xc1); 4147 run_rt3070_rf_write(sc, 59, 0x0f); 4148 } 4149 } else { 4150 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 4151 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4152 rt5390_def_rf[i].val); 4153 } 4154 if (sc->mac_rev >= 0x0502) { 4155 run_rt3070_rf_write(sc, 6, 0xe0); 4156 run_rt3070_rf_write(sc, 25, 0x80); 4157 run_rt3070_rf_write(sc, 46, 0x73); 4158 run_rt3070_rf_write(sc, 53, 0x00); 4159 run_rt3070_rf_write(sc, 56, 0x42); 4160 run_rt3070_rf_write(sc, 61, 0xd1); 4161 } 4162 } 4163 4164 sc->rf24_20mhz = 0x1f; /* default value */ 4165 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4166 4167 if (sc->mac_rev < 0x0211) 4168 run_rt3070_rf_write(sc, 27, 0x3); 4169 4170 run_read(sc, RT3070_OPT_14, &tmp); 4171 run_write(sc, RT3070_OPT_14, tmp | 1); 4172 return (0); 4173 } 4174 4175 static int 4176 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4177 uint8_t *val) 4178 { 4179 uint8_t rf22, rf24; 4180 uint8_t bbp55_pb, bbp55_sb, delta; 4181 int ntries; 4182 4183 /* program filter */ 4184 run_rt3070_rf_read(sc, 24, &rf24); 4185 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4186 run_rt3070_rf_write(sc, 24, rf24); 4187 4188 /* enable baseband loopback mode */ 4189 run_rt3070_rf_read(sc, 22, &rf22); 4190 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4191 4192 /* set power and frequency of passband test tone */ 4193 run_bbp_write(sc, 24, 0x00); 4194 for (ntries = 0; ntries < 100; ntries++) { 4195 /* transmit test tone */ 4196 run_bbp_write(sc, 25, 0x90); 4197 usbd_delay_ms(sc->sc_udev, 10); 4198 /* read received power */ 4199 run_bbp_read(sc, 55, &bbp55_pb); 4200 if (bbp55_pb != 0) 4201 break; 4202 } 4203 if (ntries == 100) 4204 return ETIMEDOUT; 4205 4206 /* set power and frequency of stopband test tone */ 4207 run_bbp_write(sc, 24, 0x06); 4208 for (ntries = 0; ntries < 100; ntries++) { 4209 /* transmit test tone */ 4210 run_bbp_write(sc, 25, 0x90); 4211 usbd_delay_ms(sc->sc_udev, 10); 4212 /* read received power */ 4213 run_bbp_read(sc, 55, &bbp55_sb); 4214 4215 delta = bbp55_pb - bbp55_sb; 4216 if (delta > target) 4217 break; 4218 4219 /* reprogram filter */ 4220 rf24++; 4221 run_rt3070_rf_write(sc, 24, rf24); 4222 } 4223 if (ntries < 100) { 4224 if (rf24 != init) 4225 rf24--; /* backtrack */ 4226 *val = rf24; 4227 run_rt3070_rf_write(sc, 24, rf24); 4228 } 4229 4230 /* restore initial state */ 4231 run_bbp_write(sc, 24, 0x00); 4232 4233 /* disable baseband loopback mode */ 4234 run_rt3070_rf_read(sc, 22, &rf22); 4235 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4236 4237 return 0; 4238 } 4239 4240 static void 4241 run_rt3070_rf_setup(struct run_softc *sc) 4242 { 4243 uint8_t bbp, rf; 4244 int i; 4245 4246 if (sc->mac_ver == 0x3572) { 4247 /* enable DC filter */ 4248 if (sc->mac_rev >= 0x0201) 4249 run_bbp_write(sc, 103, 0xc0); 4250 4251 run_bbp_read(sc, 138, &bbp); 4252 if (sc->ntxchains == 1) 4253 bbp |= 0x20; /* turn off DAC1 */ 4254 if (sc->nrxchains == 1) 4255 bbp &= ~0x02; /* turn off ADC1 */ 4256 run_bbp_write(sc, 138, bbp); 4257 4258 if (sc->mac_rev >= 0x0211) { 4259 /* improve power consumption */ 4260 run_bbp_read(sc, 31, &bbp); 4261 run_bbp_write(sc, 31, bbp & ~0x03); 4262 } 4263 4264 run_rt3070_rf_read(sc, 16, &rf); 4265 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4266 run_rt3070_rf_write(sc, 16, rf); 4267 } else if (sc->mac_ver == 0x3071) { 4268 /* enable DC filter */ 4269 if (sc->mac_rev >= 0x0201) 4270 run_bbp_write(sc, 103, 0xc0); 4271 4272 run_bbp_read(sc, 138, &bbp); 4273 if (sc->ntxchains == 1) 4274 bbp |= 0x20; /* turn off DAC1 */ 4275 if (sc->nrxchains == 1) 4276 bbp &= ~0x02; /* turn off ADC1 */ 4277 run_bbp_write(sc, 138, bbp); 4278 4279 if (sc->mac_rev >= 0x0211) { 4280 /* improve power consumption */ 4281 run_bbp_read(sc, 31, &bbp); 4282 run_bbp_write(sc, 31, bbp & ~0x03); 4283 } 4284 4285 run_write(sc, RT2860_TX_SW_CFG1, 0); 4286 if (sc->mac_rev < 0x0211) { 4287 run_write(sc, RT2860_TX_SW_CFG2, 4288 sc->patch_dac ? 0x2c : 0x0f); 4289 } else 4290 run_write(sc, RT2860_TX_SW_CFG2, 0); 4291 } else if (sc->mac_ver == 0x3070) { 4292 if (sc->mac_rev >= 0x0201) { 4293 /* enable DC filter */ 4294 run_bbp_write(sc, 103, 0xc0); 4295 4296 /* improve power consumption */ 4297 run_bbp_read(sc, 31, &bbp); 4298 run_bbp_write(sc, 31, bbp & ~0x03); 4299 } 4300 4301 if (sc->mac_rev < 0x0211) { 4302 run_write(sc, RT2860_TX_SW_CFG1, 0); 4303 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4304 } else 4305 run_write(sc, RT2860_TX_SW_CFG2, 0); 4306 } 4307 4308 /* initialize RF registers from ROM for >=RT3071*/ 4309 if (sc->mac_ver >= 0x3071) { 4310 for (i = 0; i < 10; i++) { 4311 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4312 continue; 4313 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4314 } 4315 } 4316 } 4317 4318 static void 4319 run_rt3593_rf_setup(struct run_softc *sc) 4320 { 4321 uint8_t bbp, rf; 4322 4323 if (sc->mac_rev >= 0x0211) { 4324 /* Enable DC filter. */ 4325 run_bbp_write(sc, 103, 0xc0); 4326 } 4327 run_write(sc, RT2860_TX_SW_CFG1, 0); 4328 if (sc->mac_rev < 0x0211) { 4329 run_write(sc, RT2860_TX_SW_CFG2, 4330 sc->patch_dac ? 0x2c : 0x0f); 4331 } else 4332 run_write(sc, RT2860_TX_SW_CFG2, 0); 4333 4334 run_rt3070_rf_read(sc, 50, &rf); 4335 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4336 4337 run_rt3070_rf_read(sc, 51, &rf); 4338 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4339 ((sc->txmixgain_2ghz & 0x07) << 2); 4340 run_rt3070_rf_write(sc, 51, rf); 4341 4342 run_rt3070_rf_read(sc, 38, &rf); 4343 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4344 4345 run_rt3070_rf_read(sc, 39, &rf); 4346 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4347 4348 run_rt3070_rf_read(sc, 1, &rf); 4349 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4350 4351 run_rt3070_rf_read(sc, 30, &rf); 4352 rf = (rf & ~0x18) | 0x10; 4353 run_rt3070_rf_write(sc, 30, rf); 4354 4355 /* Apply maximum likelihood detection for 2 stream case. */ 4356 run_bbp_read(sc, 105, &bbp); 4357 if (sc->nrxchains > 1) 4358 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4359 4360 /* Avoid data lost and CRC error. */ 4361 run_bbp_read(sc, 4, &bbp); 4362 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4363 4364 run_bbp_write(sc, 92, 0x02); 4365 run_bbp_write(sc, 82, 0x82); 4366 run_bbp_write(sc, 106, 0x05); 4367 run_bbp_write(sc, 104, 0x92); 4368 run_bbp_write(sc, 88, 0x90); 4369 run_bbp_write(sc, 148, 0xc8); 4370 run_bbp_write(sc, 47, 0x48); 4371 run_bbp_write(sc, 120, 0x50); 4372 4373 run_bbp_write(sc, 163, 0x9d); 4374 4375 /* SNR mapping. */ 4376 run_bbp_write(sc, 142, 0x06); 4377 run_bbp_write(sc, 143, 0xa0); 4378 run_bbp_write(sc, 142, 0x07); 4379 run_bbp_write(sc, 143, 0xa1); 4380 run_bbp_write(sc, 142, 0x08); 4381 run_bbp_write(sc, 143, 0xa2); 4382 4383 run_bbp_write(sc, 31, 0x08); 4384 run_bbp_write(sc, 68, 0x0b); 4385 run_bbp_write(sc, 105, 0x04); 4386 } 4387 4388 static void 4389 run_rt5390_rf_setup(struct run_softc *sc) 4390 { 4391 uint8_t bbp, rf; 4392 4393 if (sc->mac_rev >= 0x0211) { 4394 /* Enable DC filter. */ 4395 run_bbp_write(sc, 103, 0xc0); 4396 4397 if (sc->mac_ver != 0x5592) { 4398 /* Improve power consumption. */ 4399 run_bbp_read(sc, 31, &bbp); 4400 run_bbp_write(sc, 31, bbp & ~0x03); 4401 } 4402 } 4403 4404 run_bbp_read(sc, 138, &bbp); 4405 if (sc->ntxchains == 1) 4406 bbp |= 0x20; /* turn off DAC1 */ 4407 if (sc->nrxchains == 1) 4408 bbp &= ~0x02; /* turn off ADC1 */ 4409 run_bbp_write(sc, 138, bbp); 4410 4411 run_rt3070_rf_read(sc, 38, &rf); 4412 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4413 4414 run_rt3070_rf_read(sc, 39, &rf); 4415 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4416 4417 /* Avoid data lost and CRC error. */ 4418 run_bbp_read(sc, 4, &bbp); 4419 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4420 4421 run_rt3070_rf_read(sc, 30, &rf); 4422 rf = (rf & ~0x18) | 0x10; 4423 run_rt3070_rf_write(sc, 30, rf); 4424 4425 if (sc->mac_ver != 0x5592) { 4426 run_write(sc, RT2860_TX_SW_CFG1, 0); 4427 if (sc->mac_rev < 0x0211) { 4428 run_write(sc, RT2860_TX_SW_CFG2, 4429 sc->patch_dac ? 0x2c : 0x0f); 4430 } else 4431 run_write(sc, RT2860_TX_SW_CFG2, 0); 4432 } 4433 } 4434 4435 static int 4436 run_txrx_enable(struct run_softc *sc) 4437 { 4438 uint32_t tmp; 4439 int error, ntries; 4440 4441 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4442 for (ntries = 0; ntries < 200; ntries++) { 4443 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4444 return error; 4445 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4446 break; 4447 usbd_delay_ms(sc->sc_udev, 50); 4448 } 4449 if (ntries == 200) 4450 return ETIMEDOUT; 4451 4452 usbd_delay_ms(sc->sc_udev, 50); 4453 4454 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4455 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4456 4457 /* enable Rx bulk aggregation (set timeout and limit) */ 4458 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4459 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4460 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4461 4462 /* set Rx filter */ 4463 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4464 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4465 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4466 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4467 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4468 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4469 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4470 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4471 } 4472 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4473 4474 run_write(sc, RT2860_MAC_SYS_CTRL, 4475 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4476 4477 return 0; 4478 } 4479 4480 static int 4481 run_adjust_freq_offset(struct run_softc *sc) 4482 { 4483 uint8_t rf, tmp; 4484 4485 run_rt3070_rf_read(sc, 17, &rf); 4486 tmp = rf; 4487 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4488 rf = MIN(rf, 0x5f); 4489 4490 if (tmp != rf) 4491 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4492 4493 return (0); 4494 } 4495 4496 static int 4497 run_init(struct ifnet *ifp) 4498 { 4499 struct run_softc *sc = ifp->if_softc; 4500 struct ieee80211com *ic = &sc->sc_ic; 4501 uint32_t tmp; 4502 uint8_t bbp1, bbp3; 4503 int i, error, qid, ridx, ntries; 4504 4505 for (ntries = 0; ntries < 100; ntries++) { 4506 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4507 goto fail; 4508 if (tmp != 0 && tmp != 0xffffffff) 4509 break; 4510 usbd_delay_ms(sc->sc_udev, 10); 4511 } 4512 if (ntries == 100) { 4513 error = ETIMEDOUT; 4514 goto fail; 4515 } 4516 4517 if ((sc->sc_flags & RUN_FWLOADED) == 0 && 4518 (error = run_load_microcode(sc)) != 0) { 4519 device_printf(sc->sc_dev, 4520 "could not load 8051 microcode\n"); 4521 goto fail; 4522 } 4523 4524 if (ifp->if_flags & IFF_RUNNING) 4525 run_stop(ifp, 0); 4526 4527 /* init host command ring */ 4528 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4529 4530 /* init Tx rings (4 EDCAs) */ 4531 for (qid = 0; qid < 4; qid++) { 4532 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4533 goto fail; 4534 } 4535 /* init Rx ring */ 4536 if ((error = run_alloc_rx_ring(sc)) != 0) 4537 goto fail; 4538 4539 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4540 run_set_macaddr(sc, ic->ic_myaddr); 4541 4542 for (ntries = 0; ntries < 100; ntries++) { 4543 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4544 goto fail; 4545 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4546 break; 4547 usbd_delay_ms(sc->sc_udev, 10); 4548 } 4549 if (ntries == 100) { 4550 device_printf(sc->sc_dev, 4551 "timeout waiting for DMA engine\n"); 4552 error = ETIMEDOUT; 4553 goto fail; 4554 } 4555 tmp &= 0xff0; 4556 tmp |= RT2860_TX_WB_DDONE; 4557 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4558 4559 /* turn off PME_OEN to solve high-current issue */ 4560 run_read(sc, RT2860_SYS_CTRL, &tmp); 4561 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4562 4563 run_write(sc, RT2860_MAC_SYS_CTRL, 4564 RT2860_BBP_HRST | RT2860_MAC_SRST); 4565 run_write(sc, RT2860_USB_DMA_CFG, 0); 4566 4567 if ((error = run_reset(sc)) != 0) { 4568 device_printf(sc->sc_dev, "could not reset chipset\n"); 4569 goto fail; 4570 } 4571 4572 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4573 4574 /* init Tx power for all Tx rates (from EEPROM) */ 4575 for (ridx = 0; ridx < 5; ridx++) { 4576 if (sc->txpow20mhz[ridx] == 0xffffffff) 4577 continue; 4578 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4579 } 4580 4581 for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) 4582 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4583 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4584 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4585 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4586 4587 if (sc->mac_ver >= 0x5390) { 4588 run_write(sc, RT2860_TX_SW_CFG0, 4589 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4590 if (sc->mac_ver >= 0x5392) { 4591 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4592 if (sc->mac_ver == 0x5592) { 4593 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4594 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4595 } else { 4596 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4597 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4598 } 4599 } 4600 } else if (sc->mac_ver >= 0x3593) { 4601 run_write(sc, RT2860_TX_SW_CFG0, 4602 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4603 } else if (sc->mac_ver >= 0x3070) { 4604 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4605 run_write(sc, RT2860_TX_SW_CFG0, 4606 4 << RT2860_DLY_PAPE_EN_SHIFT); 4607 } 4608 4609 /* wait while MAC is busy */ 4610 for (ntries = 0; ntries < 100; ntries++) { 4611 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4612 goto fail; 4613 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4614 break; 4615 DELAY(1000); 4616 } 4617 if (ntries == 100) { 4618 error = ETIMEDOUT; 4619 goto fail; 4620 } 4621 4622 /* clear Host to MCU mailbox */ 4623 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4624 run_write(sc, RT2860_H2M_MAILBOX, 0); 4625 usbd_delay_ms(sc->sc_udev, 10); 4626 4627 if ((error = run_bbp_init(sc)) != 0) { 4628 device_printf(sc->sc_dev, "could not initialize BBP\n"); 4629 goto fail; 4630 } 4631 4632 /* abort TSF synchronization */ 4633 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4634 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4635 RT2860_TBTT_TIMER_EN); 4636 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4637 4638 /* clear RX WCID search table */ 4639 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4640 /* clear Pair-wise key table */ 4641 run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); 4642 /* clear IV/EIV table */ 4643 run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); 4644 /* clear WCID attribute table */ 4645 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4646 /* clear shared key table */ 4647 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4648 /* clear shared key mode */ 4649 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4650 4651 /* clear RX WCID search table */ 4652 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4653 /* clear WCID attribute table */ 4654 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4655 4656 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4657 tmp = (tmp & ~0xff) | 0x1e; 4658 run_write(sc, RT2860_US_CYC_CNT, tmp); 4659 4660 if (sc->mac_rev != 0x0101) 4661 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4662 4663 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4664 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4665 4666 /* write vendor-specific BBP values (from EEPROM) */ 4667 if (sc->mac_ver < 0x3593) { 4668 for (i = 0; i < 10; i++) { 4669 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4670 continue; 4671 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4672 } 4673 } 4674 4675 /* select Main antenna for 1T1R devices */ 4676 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4677 run_set_rx_antenna(sc, 0); 4678 4679 /* send LEDs operating mode to microcontroller */ 4680 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4681 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4682 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4683 4684 if (sc->mac_ver >= 0x5390) 4685 run_rt5390_rf_init(sc); 4686 else if (sc->mac_ver == 0x3593) 4687 run_rt3593_rf_init(sc); 4688 else if (sc->mac_ver >= 0x3070) 4689 run_rt3070_rf_init(sc); 4690 4691 /* disable non-existing Rx chains */ 4692 run_bbp_read(sc, 3, &bbp3); 4693 bbp3 &= ~(1 << 3 | 1 << 4); 4694 if (sc->nrxchains == 2) 4695 bbp3 |= 1 << 3; 4696 else if (sc->nrxchains == 3) 4697 bbp3 |= 1 << 4; 4698 run_bbp_write(sc, 3, bbp3); 4699 4700 /* disable non-existing Tx chains */ 4701 run_bbp_read(sc, 1, &bbp1); 4702 if (sc->ntxchains == 1) 4703 bbp1 &= ~(1 << 3 | 1 << 4); 4704 run_bbp_write(sc, 1, bbp1); 4705 4706 if (sc->mac_ver >= 0x5390) 4707 run_rt5390_rf_setup(sc); 4708 else if (sc->mac_ver == 0x3593) 4709 run_rt3593_rf_setup(sc); 4710 else if (sc->mac_ver >= 0x3070) 4711 run_rt3070_rf_setup(sc); 4712 4713 /* select default channel */ 4714 run_set_chan(sc, ic->ic_curchan); 4715 4716 /* setup initial protection mode */ 4717 run_updateprot(sc); 4718 4719 /* turn radio LED on */ 4720 run_set_leds(sc, RT2860_LED_RADIO); 4721 4722 #ifdef RUN_HWCRYPTO 4723 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4724 /* install WEP keys */ 4725 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4726 (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], 4727 NULL); 4728 } 4729 #endif 4730 4731 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4732 struct run_rx_data *data = &sc->rxq.data[i]; 4733 4734 usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, 4735 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 4736 error = usbd_transfer(data->xfer); 4737 if (error != USBD_NORMAL_COMPLETION && 4738 error != USBD_IN_PROGRESS) 4739 goto fail; 4740 } 4741 4742 if ((error = run_txrx_enable(sc)) != 0) 4743 goto fail; 4744 4745 ifp->if_flags &= ~IFF_OACTIVE; 4746 ifp->if_flags |= IFF_RUNNING; 4747 4748 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4749 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4750 else 4751 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4752 4753 if (error != 0) 4754 fail: run_stop(ifp, 1); 4755 return error; 4756 } 4757 4758 static void 4759 run_stop(struct ifnet *ifp, int disable) 4760 { 4761 struct run_softc *sc = ifp->if_softc; 4762 struct ieee80211com *ic = &sc->sc_ic; 4763 uint32_t tmp; 4764 int ntries, qid; 4765 4766 if (ifp->if_flags & IFF_RUNNING) 4767 run_set_leds(sc, 0); /* turn all LEDs off */ 4768 4769 sc->sc_tx_timer = 0; 4770 ifp->if_timer = 0; 4771 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4772 4773 callout_stop(&sc->scan_to); 4774 callout_stop(&sc->calib_to); 4775 4776 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4777 /* wait for all queued asynchronous commands to complete */ 4778 while (sc->cmdq.queued > 0) 4779 tsleep(&sc->cmdq, 0, "cmdq", 0); 4780 4781 /* disable Tx/Rx */ 4782 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4783 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4784 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4785 4786 /* wait for pending Tx to complete */ 4787 for (ntries = 0; ntries < 100; ntries++) { 4788 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4789 break; 4790 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4791 break; 4792 } 4793 DELAY(1000); 4794 run_write(sc, RT2860_USB_DMA_CFG, 0); 4795 4796 /* reset adapter */ 4797 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4798 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4799 4800 /* reset Tx and Rx rings */ 4801 sc->qfullmsk = 0; 4802 for (qid = 0; qid < 4; qid++) 4803 run_free_tx_ring(sc, qid); 4804 run_free_rx_ring(sc); 4805 } 4806 4807 #ifndef IEEE80211_STA_ONLY 4808 static int 4809 run_setup_beacon(struct run_softc *sc) 4810 { 4811 struct ieee80211com *ic = &sc->sc_ic; 4812 struct rt2860_txwi txwi; 4813 struct mbuf *m; 4814 uint16_t txwisize; 4815 int ridx; 4816 4817 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 4818 return ENOBUFS; 4819 4820 memset(&txwi, 0, sizeof(txwi)); 4821 txwi.wcid = 0xff; 4822 txwi.len = htole16(m->m_pkthdr.len); 4823 /* send beacons at the lowest available rate */ 4824 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 4825 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4826 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4827 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4828 txwi.phy |= htole16(RT2860_PHY_OFDM); 4829 txwi.txop = RT2860_TX_TXOP_HT; 4830 txwi.flags = RT2860_TX_TS; 4831 4832 txwisize = (sc->mac_ver == 0x5592) ? 4833 sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); 4834 run_write_region_1(sc, RT2860_BCN_BASE(0), 4835 (uint8_t *)&txwi, txwisize); 4836 run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, 4837 mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); 4838 4839 m_freem(m); 4840 4841 return 0; 4842 } 4843 #endif 4844 4845 MODULE(MODULE_CLASS_DRIVER, if_run, NULL); 4846 4847 #ifdef _MODULE 4848 #include "ioconf.c" 4849 #endif 4850 4851 static int 4852 if_run_modcmd(modcmd_t cmd, void *arg) 4853 { 4854 int error = 0; 4855 4856 switch (cmd) { 4857 case MODULE_CMD_INIT: 4858 #ifdef _MODULE 4859 error = config_init_component(cfdriver_ioconf_run, 4860 cfattach_ioconf_run, cfdata_ioconf_run); 4861 #endif 4862 return error; 4863 case MODULE_CMD_FINI: 4864 #ifdef _MODULE 4865 error = config_fini_component(cfdriver_ioconf_run, 4866 cfattach_ioconf_run, cfdata_ioconf_run); 4867 #endif 4868 return error; 4869 default: 4870 return ENOTTY; 4871 } 4872 } 4873
Indexes created Thu Oct 02 10:09:58 GMT 2025