if_run.c revision 1.40
1 /* $NetBSD: if_run.c,v 1.40 2020/06/06 13:53:43 gson Exp $ */ 2 /* $OpenBSD: if_run.c,v 1.90 2012/03/24 15:11:04 jsg Exp $ */ 3 4 /*- 5 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_run.c,v 1.40 2020/06/06 13:53:43 gson Exp $"); 27 28 #ifdef _KERNEL_OPT 29 #include "opt_usb.h" 30 #endif 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/callout.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/device.h> 44 #include <sys/atomic.h> 45 46 #include <sys/bus.h> 47 #include <machine/endian.h> 48 #include <sys/intr.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_arp.h> 53 #include <net/if_dl.h> 54 #include <net/if_ether.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_amrr.h> 60 #include <net80211/ieee80211_radiotap.h> 61 62 #include <dev/firmload.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usbdi_util.h> 68 #include <dev/usb/usbdevs.h> 69 70 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 71 #include <dev/usb/if_runvar.h> 72 73 #ifdef RUN_DEBUG 74 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 75 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 76 int run_debug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n, x) 80 #endif 81 82 #define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 83 84 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 85 static const struct usb_devno run_devs[] = { 86 USB_ID(ABOCOM, RT2770), 87 USB_ID(ABOCOM, RT2870), 88 USB_ID(ABOCOM, RT3070), 89 USB_ID(ABOCOM, RT3071), 90 USB_ID(ABOCOM, RT3072), 91 USB_ID(ABOCOM2, RT2870_1), 92 USB_ID(ACCTON, RT2770), 93 USB_ID(ACCTON, RT2870_1), 94 USB_ID(ACCTON, RT2870_2), 95 USB_ID(ACCTON, RT2870_3), 96 USB_ID(ACCTON, RT2870_4), 97 USB_ID(ACCTON, RT2870_5), 98 USB_ID(ACCTON, RT3070), 99 USB_ID(ACCTON, RT3070_1), 100 USB_ID(ACCTON, RT3070_2), 101 USB_ID(ACCTON, RT3070_3), 102 USB_ID(ACCTON, RT3070_4), 103 USB_ID(ACCTON, RT3070_5), 104 USB_ID(ACCTON, RT3070_6), 105 USB_ID(AIRTIES, RT3070), 106 USB_ID(AIRTIES, RT3070_2), 107 USB_ID(ALLWIN, RT2070), 108 USB_ID(ALLWIN, RT2770), 109 USB_ID(ALLWIN, RT2870), 110 USB_ID(ALLWIN, RT3070), 111 USB_ID(ALLWIN, RT3071), 112 USB_ID(ALLWIN, RT3072), 113 USB_ID(ALLWIN, RT3572), 114 USB_ID(AMIGO, RT2870_1), 115 USB_ID(AMIGO, RT2870_2), 116 USB_ID(AMIT, CGWLUSB2GNR), 117 USB_ID(AMIT, RT2870_1), 118 USB_ID(AMIT2, RT2870), 119 USB_ID(ASUSTEK, RT2870_1), 120 USB_ID(ASUSTEK, RT2870_2), 121 USB_ID(ASUSTEK, RT2870_3), 122 USB_ID(ASUSTEK, RT2870_4), 123 USB_ID(ASUSTEK, RT2870_5), 124 USB_ID(ASUSTEK, RT3070), 125 USB_ID(ASUSTEK, RT3070_1), 126 USB_ID(ASUSTEK, USBN53), 127 USB_ID(ASUSTEK, USBN66), 128 USB_ID(ASUSTEK2, USBN11), 129 USB_ID(AZUREWAVE, RT2870_1), 130 USB_ID(AZUREWAVE, RT2870_2), 131 USB_ID(AZUREWAVE, RT3070), 132 USB_ID(AZUREWAVE, RT3070_2), 133 USB_ID(AZUREWAVE, RT3070_3), 134 USB_ID(AZUREWAVE, RT3070_4), 135 USB_ID(AZUREWAVE, RT3070_5), 136 USB_ID(BELKIN, F5D8053V3), 137 USB_ID(BELKIN, F5D8055), 138 USB_ID(BELKIN, F5D8055V2), 139 USB_ID(BELKIN, F6D4050V1), 140 USB_ID(BELKIN, F6D4050V2), 141 USB_ID(BELKIN, F7D1101V2), 142 USB_ID(BELKIN, RT2870_1), 143 USB_ID(BELKIN, RT2870_2), 144 USB_ID(BELKIN, RTL8192CU_2), 145 USB_ID(BEWAN, RT3070), 146 USB_ID(CISCOLINKSYS, AE1000), 147 USB_ID(CISCOLINKSYS, AM10), 148 USB_ID(CISCOLINKSYS2, RT3070), 149 USB_ID(CISCOLINKSYS3, RT3070), 150 USB_ID(CONCEPTRONIC, RT2870_1), 151 USB_ID(CONCEPTRONIC, RT2870_2), 152 USB_ID(CONCEPTRONIC, RT2870_3), 153 USB_ID(CONCEPTRONIC, RT2870_4), 154 USB_ID(CONCEPTRONIC, RT2870_5), 155 USB_ID(CONCEPTRONIC, RT2870_6), 156 USB_ID(CONCEPTRONIC, RT2870_7), 157 USB_ID(CONCEPTRONIC, RT2870_8), 158 USB_ID(CONCEPTRONIC, RT3070_1), 159 USB_ID(CONCEPTRONIC, RT3070_2), 160 USB_ID(CONCEPTRONIC, RT3070_3), 161 USB_ID(COREGA, CGWLUSB300GNM), 162 USB_ID(COREGA, RT2870_1), 163 USB_ID(COREGA, RT2870_2), 164 USB_ID(COREGA, RT2870_3), 165 USB_ID(COREGA, RT3070), 166 USB_ID(CYBERTAN, RT2870), 167 USB_ID(DLINK, RT2870), 168 USB_ID(DLINK, RT3072), 169 USB_ID(DLINK, DWA127), 170 USB_ID(DLINK, DWA140B3), 171 USB_ID(DLINK, DWA160B2), 172 USB_ID(DLINK, DWA162), 173 USB_ID(DLINK2, DWA130), 174 USB_ID(DLINK2, RT2870_1), 175 USB_ID(DLINK2, RT2870_2), 176 USB_ID(DLINK2, RT3070_1), 177 USB_ID(DLINK2, RT3070_2), 178 USB_ID(DLINK2, RT3070_3), 179 USB_ID(DLINK2, RT3070_4), 180 USB_ID(DLINK2, RT3070_5), 181 USB_ID(DLINK2, RT3072), 182 USB_ID(DLINK2, RT3072_1), 183 USB_ID(DVICO, RT3070), 184 USB_ID(EDIMAX, EW7717), 185 USB_ID(EDIMAX, EW7718), 186 USB_ID(EDIMAX, EW7722UTN), 187 USB_ID(EDIMAX, RT2870_1), 188 USB_ID(ENCORE, RT3070), 189 USB_ID(ENCORE, RT3070_2), 190 USB_ID(ENCORE, RT3070_3), 191 USB_ID(GIGABYTE, GNWB31N), 192 USB_ID(GIGABYTE, GNWB32L), 193 USB_ID(GIGABYTE, RT2870_1), 194 USB_ID(GIGASET, RT3070_1), 195 USB_ID(GIGASET, RT3070_2), 196 USB_ID(GUILLEMOT, HWNU300), 197 USB_ID(HAWKING, HWUN2), 198 USB_ID(HAWKING, RT2870_1), 199 USB_ID(HAWKING, RT2870_2), 200 USB_ID(HAWKING, RT2870_3), 201 USB_ID(HAWKING, RT2870_4), 202 USB_ID(HAWKING, RT2870_5), 203 USB_ID(HAWKING, RT3070), 204 USB_ID(IODATA, RT3072_1), 205 USB_ID(IODATA, RT3072_2), 206 USB_ID(IODATA, RT3072_3), 207 USB_ID(IODATA, RT3072_4), 208 USB_ID(LINKSYS4, RT3070), 209 USB_ID(LINKSYS4, WUSB100), 210 USB_ID(LINKSYS4, WUSB54GC_3), 211 USB_ID(LINKSYS4, WUSB600N), 212 USB_ID(LINKSYS4, WUSB600NV2), 213 USB_ID(LOGITEC, LANW300NU2), 214 USB_ID(LOGITEC, LANW300NU2S), 215 USB_ID(LOGITEC, LAN_W300ANU2), 216 USB_ID(LOGITEC, LAN_W450ANU2E), 217 USB_ID(LOGITEC, RT2870_1), 218 USB_ID(LOGITEC, RT2870_2), 219 USB_ID(LOGITEC, RT2870_3), 220 USB_ID(LOGITEC, RT3020), 221 USB_ID(MELCO, RT2870_1), 222 USB_ID(MELCO, RT2870_2), 223 USB_ID(MELCO, WLIUCAG300N), 224 USB_ID(MELCO, WLIUCG300N), 225 USB_ID(MELCO, WLIUCG301N), 226 USB_ID(MELCO, WLIUCGN), 227 USB_ID(MELCO, WLIUCGNHP), 228 USB_ID(MELCO, WLIUCGNM), 229 USB_ID(MELCO, WLIUCGNM2T), 230 USB_ID(MOTOROLA4, RT2770), 231 USB_ID(MOTOROLA4, RT3070), 232 USB_ID(MSI, RT3070), 233 USB_ID(MSI, RT3070_2), 234 USB_ID(MSI, RT3070_3), 235 USB_ID(MSI, RT3070_4), 236 USB_ID(MSI, RT3070_5), 237 USB_ID(MSI, RT3070_6), 238 USB_ID(MSI, RT3070_7), 239 USB_ID(MSI, RT3070_8), 240 USB_ID(MSI, RT3070_9), 241 USB_ID(MSI, RT3070_10), 242 USB_ID(MSI, RT3070_11), 243 USB_ID(MSI, RT3070_12), 244 USB_ID(MSI, RT3070_13), 245 USB_ID(MSI, RT3070_14), 246 USB_ID(MSI, RT3070_15), 247 USB_ID(OVISLINK, RT3071), 248 USB_ID(OVISLINK, RT3072), 249 USB_ID(PARA, RT3070), 250 USB_ID(PEGATRON, RT2870), 251 USB_ID(PEGATRON, RT3070), 252 USB_ID(PEGATRON, RT3070_2), 253 USB_ID(PEGATRON, RT3070_3), 254 USB_ID(PEGATRON, RT3072), 255 USB_ID(PHILIPS, RT2870), 256 USB_ID(PLANEX2, GWUS300MINIS), 257 USB_ID(PLANEX2, GWUSMICRO300), 258 USB_ID(PLANEX2, GWUSMICRON), 259 USB_ID(PLANEX2, GWUS300MINIX), 260 USB_ID(PLANEX2, RT3070), 261 USB_ID(QCOM, RT2870), 262 USB_ID(QUANTA, RT3070), 263 USB_ID(RALINK, RT2070), 264 USB_ID(RALINK, RT2770), 265 USB_ID(RALINK, RT2870), 266 USB_ID(RALINK, RT3070), 267 USB_ID(RALINK, RT3071), 268 USB_ID(RALINK, RT3072), 269 USB_ID(RALINK, RT3370), 270 USB_ID(RALINK, RT3572), 271 USB_ID(RALINK, RT3573), 272 USB_ID(RALINK, RT5370), 273 USB_ID(RALINK, RT5572), 274 USB_ID(RALINK, RT8070), 275 USB_ID(SAMSUNG, RT2870_1), 276 USB_ID(SENAO, RT2870_1), 277 USB_ID(SENAO, RT2870_2), 278 USB_ID(SENAO, RT2870_3), 279 USB_ID(SENAO, RT2870_4), 280 USB_ID(SENAO, RT3070), 281 USB_ID(SENAO, RT3071), 282 USB_ID(SENAO, RT3072), 283 USB_ID(SENAO, RT3072_2), 284 USB_ID(SENAO, RT3072_3), 285 USB_ID(SENAO, RT3072_4), 286 USB_ID(SENAO, RT3072_5), 287 USB_ID(SITECOMEU, RT2870_1), 288 USB_ID(SITECOMEU, RT2870_2), 289 USB_ID(SITECOMEU, RT2870_3), 290 USB_ID(SITECOMEU, RT3070_1), 291 USB_ID(SITECOMEU, RT3070_3), 292 USB_ID(SITECOMEU, RT3072_3), 293 USB_ID(SITECOMEU, RT3072_4), 294 USB_ID(SITECOMEU, RT3072_5), 295 USB_ID(SITECOMEU, RT3072_6), 296 USB_ID(SITECOMEU, WL302), 297 USB_ID(SITECOMEU, WL315), 298 USB_ID(SITECOMEU, WL321), 299 USB_ID(SITECOMEU, WL324), 300 USB_ID(SITECOMEU, WL329), 301 USB_ID(SITECOMEU, WL343), 302 USB_ID(SITECOMEU, WL344), 303 USB_ID(SITECOMEU, WL345), 304 USB_ID(SITECOMEU, WL349V4), 305 USB_ID(SITECOMEU, WL608), 306 USB_ID(SITECOMEU, WLA4000), 307 USB_ID(SITECOMEU, WLA5000), 308 USB_ID(SPARKLAN, RT2870_1), 309 USB_ID(SPARKLAN, RT2870_2), 310 USB_ID(SPARKLAN, RT3070), 311 USB_ID(SWEEX2, LW153), 312 USB_ID(SWEEX2, LW303), 313 USB_ID(SWEEX2, LW313), 314 USB_ID(TOSHIBA, RT3070), 315 USB_ID(UMEDIA, RT2870_1), 316 USB_ID(UMEDIA, TEW645UB), 317 USB_ID(ZCOM, RT2870_1), 318 USB_ID(ZCOM, RT2870_2), 319 USB_ID(ZINWELL, RT2870_1), 320 USB_ID(ZINWELL, RT2870_2), 321 USB_ID(ZINWELL, RT3070), 322 USB_ID(ZINWELL, RT3072), 323 USB_ID(ZINWELL, RT3072_2), 324 USB_ID(ZYXEL, NWD2105), 325 USB_ID(ZYXEL, NWD211AN), 326 USB_ID(ZYXEL, RT2870_1), 327 USB_ID(ZYXEL, RT2870_2), 328 USB_ID(ZYXEL, RT3070), 329 }; 330 331 static int run_match(device_t, cfdata_t, void *); 332 static void run_attach(device_t, device_t, void *); 333 static int run_detach(device_t, int); 334 static int run_activate(device_t, enum devact); 335 336 CFATTACH_DECL_NEW(run, sizeof(struct run_softc), 337 run_match, run_attach, run_detach, run_activate); 338 339 static int run_alloc_rx_ring(struct run_softc *); 340 static void run_free_rx_ring(struct run_softc *); 341 static int run_alloc_tx_ring(struct run_softc *, int); 342 static void run_free_tx_ring(struct run_softc *, int); 343 static int run_load_microcode(struct run_softc *); 344 static int run_reset(struct run_softc *); 345 static int run_read(struct run_softc *, uint16_t, uint32_t *); 346 static int run_read_region_1(struct run_softc *, uint16_t, 347 uint8_t *, int); 348 static int run_write_2(struct run_softc *, uint16_t, uint16_t); 349 static int run_write(struct run_softc *, uint16_t, uint32_t); 350 static int run_write_region_1(struct run_softc *, uint16_t, 351 const uint8_t *, int); 352 static int run_set_region_4(struct run_softc *, uint16_t, 353 uint32_t, int); 354 static int run_efuse_read(struct run_softc *, uint16_t, 355 uint16_t *, int); 356 static int run_efuse_read_2(struct run_softc *, uint16_t, 357 uint16_t *); 358 static int run_eeprom_read_2(struct run_softc *, uint16_t, 359 uint16_t *); 360 static int run_rt2870_rf_write(struct run_softc *, uint8_t, 361 uint32_t); 362 static int run_rt3070_rf_read(struct run_softc *, uint8_t, 363 uint8_t *); 364 static int run_rt3070_rf_write(struct run_softc *, uint8_t, 365 uint8_t); 366 static int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 367 static int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 368 static int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 369 static const char * run_get_rf(uint16_t); 370 static void run_rt3593_get_txpower(struct run_softc *); 371 static void run_get_txpower(struct run_softc *); 372 static int run_read_eeprom(struct run_softc *); 373 static struct ieee80211_node * 374 run_node_alloc(struct ieee80211_node_table *); 375 static int run_media_change(struct ifnet *); 376 static void run_next_scan(void *); 377 static void run_task(void *); 378 static void run_do_async(struct run_softc *, 379 void (*)(struct run_softc *, void *), void *, int); 380 static int run_newstate(struct ieee80211com *, 381 enum ieee80211_state, int); 382 static void run_newstate_cb(struct run_softc *, void *); 383 static int run_updateedca(struct ieee80211com *); 384 static void run_updateedca_cb(struct run_softc *, void *); 385 #ifdef RUN_HWCRYPTO 386 static int run_set_key(struct ieee80211com *, 387 const struct ieee80211_key *, const uint8_t *); 388 static void run_set_key_cb(struct run_softc *, void *); 389 static int run_delete_key(struct ieee80211com *, 390 const struct ieee80211_key *); 391 static void run_delete_key_cb(struct run_softc *, void *); 392 #endif 393 static void run_calibrate_to(void *); 394 static void run_calibrate_cb(struct run_softc *, void *); 395 static void run_newassoc(struct ieee80211_node *, int); 396 static void run_rx_frame(struct run_softc *, uint8_t *, int); 397 static void run_rxeof(struct usbd_xfer *, void *, 398 usbd_status); 399 static void run_txeof(struct usbd_xfer *, void *, 400 usbd_status); 401 static int run_tx(struct run_softc *, struct mbuf *, 402 struct ieee80211_node *); 403 static void run_start(struct ifnet *); 404 static void run_watchdog(struct ifnet *); 405 static int run_ioctl(struct ifnet *, u_long, void *); 406 static void run_select_chan_group(struct run_softc *, int); 407 static void run_iq_calib(struct run_softc *, u_int); 408 static void run_set_agc(struct run_softc *, uint8_t); 409 static void run_set_rx_antenna(struct run_softc *, int); 410 static void run_rt2870_set_chan(struct run_softc *, u_int); 411 static void run_rt3070_set_chan(struct run_softc *, u_int); 412 static void run_rt3572_set_chan(struct run_softc *, u_int); 413 static void run_rt3593_set_chan(struct run_softc *, u_int); 414 static void run_rt5390_set_chan(struct run_softc *, u_int); 415 static void run_rt5592_set_chan(struct run_softc *, u_int); 416 static int run_set_chan(struct run_softc *, 417 struct ieee80211_channel *); 418 static void run_updateprot(struct run_softc *); 419 static void run_enable_tsf_sync(struct run_softc *); 420 static void run_enable_mrr(struct run_softc *); 421 static void run_set_txpreamble(struct run_softc *); 422 static void run_set_basicrates(struct run_softc *); 423 static void run_set_leds(struct run_softc *, uint16_t); 424 static void run_set_bssid(struct run_softc *, const uint8_t *); 425 static void run_set_macaddr(struct run_softc *, const uint8_t *); 426 static void run_updateslot(struct ifnet *); 427 static void run_updateslot_cb(struct run_softc *, void *); 428 static int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 429 static void run_rt5390_bbp_init(struct run_softc *); 430 static int run_bbp_init(struct run_softc *); 431 static int run_rt3070_rf_init(struct run_softc *); 432 static int run_rt3593_rf_init(struct run_softc *); 433 static int run_rt5390_rf_init(struct run_softc *); 434 static int run_rt3070_filter_calib(struct run_softc *, uint8_t, 435 uint8_t, uint8_t *); 436 static void run_rt3070_rf_setup(struct run_softc *); 437 static void run_rt3593_rf_setup(struct run_softc *); 438 static void run_rt5390_rf_setup(struct run_softc *); 439 static int run_txrx_enable(struct run_softc *); 440 static int run_adjust_freq_offset(struct run_softc *); 441 static int run_init(struct ifnet *); 442 static void run_stop(struct ifnet *, int); 443 #ifndef IEEE80211_STA_ONLY 444 static int run_setup_beacon(struct run_softc *); 445 #endif 446 447 static const struct { 448 uint32_t reg; 449 uint32_t val; 450 } rt2870_def_mac[] = { 451 RT2870_DEF_MAC 452 }; 453 454 static const struct { 455 uint8_t reg; 456 uint8_t val; 457 } rt2860_def_bbp[] = { 458 RT2860_DEF_BBP 459 }, rt5390_def_bbp[] = { 460 RT5390_DEF_BBP 461 }, rt5592_def_bbp[] = { 462 RT5592_DEF_BBP 463 }; 464 465 /* 466 * Default values for BBP register R196 for RT5592. 467 */ 468 static const uint8_t rt5592_bbp_r196[] = { 469 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 470 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 471 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 472 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 473 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 474 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 475 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 476 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 477 0x2e, 0x36, 0x30, 0x6e 478 }; 479 480 static const struct rfprog { 481 uint8_t chan; 482 uint32_t r1, r2, r3, r4; 483 } rt2860_rf2850[] = { 484 RT2860_RF2850 485 }; 486 487 static const struct { 488 uint8_t n, r, k; 489 } rt3070_freqs[] = { 490 RT3070_RF3052 491 }; 492 493 static const struct rt5592_freqs { 494 uint16_t n; 495 uint8_t k, m, r; 496 } rt5592_freqs_20mhz[] = { 497 RT5592_RF5592_20MHZ 498 },rt5592_freqs_40mhz[] = { 499 RT5592_RF5592_40MHZ 500 }; 501 502 static const struct { 503 uint8_t reg; 504 uint8_t val; 505 } rt3070_def_rf[] = { 506 RT3070_DEF_RF 507 }, rt3572_def_rf[] = { 508 RT3572_DEF_RF 509 },rt3593_def_rf[] = { 510 RT3593_DEF_RF 511 },rt5390_def_rf[] = { 512 RT5390_DEF_RF 513 },rt5392_def_rf[] = { 514 RT5392_DEF_RF 515 },rt5592_def_rf[] = { 516 RT5592_DEF_RF 517 },rt5592_2ghz_def_rf[] = { 518 RT5592_2GHZ_DEF_RF 519 },rt5592_5ghz_def_rf[] = { 520 RT5592_5GHZ_DEF_RF 521 }; 522 523 static const struct { 524 u_int firstchan; 525 u_int lastchan; 526 uint8_t reg; 527 uint8_t val; 528 } rt5592_chan_5ghz[] = { 529 RT5592_CHAN_5GHZ 530 }; 531 532 static int 533 firmware_load(const char *dname, const char *iname, uint8_t **ucodep, 534 size_t *sizep) 535 { 536 firmware_handle_t fh; 537 int error; 538 539 if ((error = firmware_open(dname, iname, &fh)) != 0) 540 return error; 541 *sizep = firmware_get_size(fh); 542 if ((*ucodep = firmware_malloc(*sizep)) == NULL) { 543 firmware_close(fh); 544 return ENOMEM; 545 } 546 if ((error = firmware_read(fh, 0, *ucodep, *sizep)) != 0) 547 firmware_free(*ucodep, *sizep); 548 firmware_close(fh); 549 550 return error; 551 } 552 553 static int 554 run_match(device_t parent, cfdata_t match, void *aux) 555 { 556 struct usb_attach_arg *uaa = aux; 557 558 return (usb_lookup(run_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL) ? 559 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 560 } 561 562 static void 563 run_attach(device_t parent, device_t self, void *aux) 564 { 565 struct run_softc *sc = device_private(self); 566 struct usb_attach_arg *uaa = aux; 567 struct ieee80211com *ic = &sc->sc_ic; 568 struct ifnet *ifp = &sc->sc_if; 569 usb_interface_descriptor_t *id; 570 usb_endpoint_descriptor_t *ed; 571 char *devinfop; 572 int i, nrx, ntx, ntries, error; 573 uint32_t ver; 574 575 aprint_naive("\n"); 576 aprint_normal("\n"); 577 578 sc->sc_dev = self; 579 sc->sc_udev = uaa->uaa_device; 580 581 devinfop = usbd_devinfo_alloc(sc->sc_udev, 0); 582 aprint_normal_dev(sc->sc_dev, "%s\n", devinfop); 583 usbd_devinfo_free(devinfop); 584 585 error = usbd_set_config_no(sc->sc_udev, 1, 0); 586 if (error != 0) { 587 aprint_error_dev(sc->sc_dev, "failed to set configuration" 588 ", err=%s\n", usbd_errstr(error)); 589 return; 590 } 591 592 /* get the first interface handle */ 593 error = usbd_device2interface_handle(sc->sc_udev, 0, &sc->sc_iface); 594 if (error != 0) { 595 aprint_error_dev(sc->sc_dev, 596 "could not get interface handle\n"); 597 return; 598 } 599 600 /* 601 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 602 * and 6 for TX (4 EDCAs + HCCA + Prio). 603 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 604 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 605 */ 606 nrx = ntx = 0; 607 id = usbd_get_interface_descriptor(sc->sc_iface); 608 for (i = 0; i < id->bNumEndpoints; i++) { 609 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 610 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 611 continue; 612 613 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 614 sc->rxq.pipe_no = ed->bEndpointAddress; 615 nrx++; 616 } else if (ntx < RUN_MAXEPOUT) { 617 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 618 ntx++; 619 } 620 } 621 /* make sure we've got them all */ 622 if (nrx < 1 || ntx < RUN_MAXEPOUT) { 623 aprint_error_dev(sc->sc_dev, "missing endpoint\n"); 624 return; 625 } 626 627 usb_init_task(&sc->sc_task, run_task, sc, 0); 628 callout_init(&sc->scan_to, 0); 629 callout_setfunc(&sc->scan_to, run_next_scan, sc); 630 callout_init(&sc->calib_to, 0); 631 callout_setfunc(&sc->calib_to, run_calibrate_to, sc); 632 633 sc->amrr.amrr_min_success_threshold = 1; 634 sc->amrr.amrr_max_success_threshold = 10; 635 636 /* wait for the chip to settle */ 637 for (ntries = 0; ntries < 100; ntries++) { 638 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 639 return; 640 if (ver != 0 && ver != 0xffffffff) 641 break; 642 DELAY(10); 643 } 644 if (ntries == 100) { 645 aprint_error_dev(sc->sc_dev, 646 "timeout waiting for NIC to initialize\n"); 647 return; 648 } 649 sc->mac_ver = ver >> 16; 650 sc->mac_rev = ver & 0xffff; 651 652 /* 653 * Per the comment in run_write_region_1(), "the WRITE_REGION_1 654 * command is not stable on RT2860", but WRITE_REGION_1 calls 655 * of up to 64 bytes have been tested and found to work with 656 * mac_ver 0x5390, and they reduce the run time of "ifconfig 657 * run0 up" from 30 seconds to a couple of seconds on OHCI. 658 * Enable WRITE_REGION_1 for the tested version only. As other 659 * versions are tested and found to work, they can be added 660 * here. 661 */ 662 if (sc->mac_ver == 0x5390) 663 sc->sc_flags |= RUN_USE_BLOCK_WRITE; 664 665 /* retrieve RF rev. no and various other things from EEPROM */ 666 run_read_eeprom(sc); 667 668 aprint_verbose_dev(sc->sc_dev, 669 "MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), address %s\n", 670 sc->mac_ver, sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 671 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 672 673 ic->ic_ifp = ifp; 674 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 675 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 676 ic->ic_state = IEEE80211_S_INIT; 677 678 /* set device capabilities */ 679 ic->ic_caps = 680 IEEE80211_C_MONITOR | /* monitor mode supported */ 681 #ifndef IEEE80211_STA_ONLY 682 IEEE80211_C_IBSS | /* IBSS mode supported */ 683 IEEE80211_C_HOSTAP | /* HostAP mode supported */ 684 #endif 685 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 686 IEEE80211_C_SHSLOT | /* short slot time supported */ 687 #ifdef RUN_HWCRYPTO 688 IEEE80211_C_WEP | /* WEP */ 689 IEEE80211_C_TKIP | /* TKIP */ 690 IEEE80211_C_AES_CCM | /* AES CCMP */ 691 IEEE80211_C_TKIPMIC | /* TKIPMIC */ 692 #endif 693 IEEE80211_C_WME | /* WME */ 694 IEEE80211_C_WPA; /* WPA/RSN */ 695 696 if (sc->rf_rev == RT2860_RF_2750 || 697 sc->rf_rev == RT2860_RF_2850 || 698 sc->rf_rev == RT3070_RF_3052 || 699 sc->rf_rev == RT3070_RF_3053 || 700 sc->rf_rev == RT5592_RF_5592) { 701 /* set supported .11a rates */ 702 ic->ic_sup_rates[IEEE80211_MODE_11A] = 703 ieee80211_std_rateset_11a; 704 705 /* set supported .11a channels */ 706 for (i = 14; i < (int)__arraycount(rt2860_rf2850); i++) { 707 uint8_t chan = rt2860_rf2850[i].chan; 708 ic->ic_channels[chan].ic_freq = 709 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 710 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 711 } 712 } 713 714 /* set supported .11b and .11g rates */ 715 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 716 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 717 718 /* set supported .11b and .11g channels (1 through 14) */ 719 for (i = 1; i <= 14; i++) { 720 ic->ic_channels[i].ic_freq = 721 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 722 ic->ic_channels[i].ic_flags = 723 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 724 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 725 } 726 727 ifp->if_softc = sc; 728 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 729 ifp->if_init = run_init; 730 ifp->if_ioctl = run_ioctl; 731 ifp->if_start = run_start; 732 ifp->if_watchdog = run_watchdog; 733 IFQ_SET_READY(&ifp->if_snd); 734 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 735 736 if_attach(ifp); 737 ieee80211_ifattach(ic); 738 ic->ic_node_alloc = run_node_alloc; 739 ic->ic_newassoc = run_newassoc; 740 ic->ic_updateslot = run_updateslot; 741 ic->ic_wme.wme_update = run_updateedca; 742 #ifdef RUN_HWCRYPTO 743 ic->ic_crypto.cs_key_set = run_set_key; 744 ic->ic_crypto.cs_key_delete = run_delete_key; 745 #endif 746 /* override state transition machine */ 747 sc->sc_newstate = ic->ic_newstate; 748 ic->ic_newstate = run_newstate; 749 750 /* XXX media locking needs revisiting */ 751 mutex_init(&sc->sc_media_mtx, MUTEX_DEFAULT, IPL_SOFTUSB); 752 ieee80211_media_init_with_lock(ic, 753 run_media_change, ieee80211_media_status, &sc->sc_media_mtx); 754 755 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 756 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 757 &sc->sc_drvbpf); 758 759 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 760 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 761 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 762 763 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 764 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 765 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 766 767 ieee80211_announce(ic); 768 769 usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, sc->sc_udev, sc->sc_dev); 770 771 if (!pmf_device_register(self, NULL, NULL)) 772 aprint_error_dev(self, "couldn't establish power handler\n"); 773 } 774 775 static int 776 run_detach(device_t self, int flags) 777 { 778 struct run_softc *sc = device_private(self); 779 struct ifnet *ifp = &sc->sc_if; 780 struct ieee80211com *ic = &sc->sc_ic; 781 int s; 782 783 if (ifp->if_softc == NULL) 784 return 0; 785 786 pmf_device_deregister(self); 787 788 s = splusb(); 789 790 sc->sc_flags |= RUN_DETACHING; 791 792 if (ifp->if_flags & IFF_RUNNING) { 793 run_stop(ifp, 0); 794 callout_halt(&sc->scan_to, NULL); 795 callout_halt(&sc->calib_to, NULL); 796 usb_rem_task_wait(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER, 797 NULL); 798 } 799 800 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 801 bpf_detach(ifp); 802 ieee80211_ifdetach(ic); 803 if_detach(ifp); 804 805 splx(s); 806 807 usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev); 808 809 callout_stop(&sc->scan_to); 810 callout_stop(&sc->calib_to); 811 812 callout_destroy(&sc->scan_to); 813 callout_destroy(&sc->calib_to); 814 815 return 0; 816 } 817 818 static int 819 run_activate(device_t self, enum devact act) 820 { 821 struct run_softc *sc = device_private(self); 822 823 switch (act) { 824 case DVACT_DEACTIVATE: 825 if_deactivate(sc->sc_ic.ic_ifp); 826 return 0; 827 default: 828 return EOPNOTSUPP; 829 } 830 } 831 832 static int 833 run_alloc_rx_ring(struct run_softc *sc) 834 { 835 struct run_rx_ring *rxq = &sc->rxq; 836 int i, error; 837 838 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 839 if (error != 0) 840 goto fail; 841 842 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 843 struct run_rx_data *data = &rxq->data[i]; 844 845 data->sc = sc; /* backpointer for callbacks */ 846 847 error = usbd_create_xfer(sc->rxq.pipeh, RUN_MAX_RXSZ, 848 0, 0, &data->xfer); 849 if (error) 850 goto fail; 851 852 data->buf = usbd_get_buffer(data->xfer); 853 } 854 if (error != 0) 855 fail: run_free_rx_ring(sc); 856 return error; 857 } 858 859 static void 860 run_free_rx_ring(struct run_softc *sc) 861 { 862 struct run_rx_ring *rxq = &sc->rxq; 863 int i; 864 865 if (rxq->pipeh != NULL) { 866 usbd_abort_pipe(rxq->pipeh); 867 } 868 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 869 if (rxq->data[i].xfer != NULL) 870 usbd_destroy_xfer(rxq->data[i].xfer); 871 rxq->data[i].xfer = NULL; 872 } 873 if (rxq->pipeh != NULL) { 874 usbd_close_pipe(rxq->pipeh); 875 rxq->pipeh = NULL; 876 } 877 } 878 879 static int 880 run_alloc_tx_ring(struct run_softc *sc, int qid) 881 { 882 struct run_tx_ring *txq = &sc->txq[qid]; 883 int i, error; 884 uint16_t txwisize; 885 886 txwisize = sizeof(struct rt2860_txwi); 887 if (sc->mac_ver == 0x5592) 888 txwisize += sizeof(uint32_t); 889 890 txq->cur = txq->queued = 0; 891 892 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 893 if (error != 0) 894 goto fail; 895 896 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 897 struct run_tx_data *data = &txq->data[i]; 898 899 data->sc = sc; /* backpointer for callbacks */ 900 data->qid = qid; 901 902 error = usbd_create_xfer(txq->pipeh, RUN_MAX_TXSZ, 903 USBD_FORCE_SHORT_XFER, 0, &data->xfer); 904 if (error) 905 goto fail; 906 907 data->buf = usbd_get_buffer(data->xfer); 908 /* zeroize the TXD + TXWI part */ 909 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 910 } 911 if (error != 0) 912 fail: run_free_tx_ring(sc, qid); 913 return error; 914 } 915 916 static void 917 run_free_tx_ring(struct run_softc *sc, int qid) 918 { 919 struct run_tx_ring *txq = &sc->txq[qid]; 920 int i; 921 922 if (txq->pipeh != NULL) { 923 usbd_abort_pipe(txq->pipeh); 924 usbd_close_pipe(txq->pipeh); 925 txq->pipeh = NULL; 926 } 927 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 928 if (txq->data[i].xfer != NULL) 929 usbd_destroy_xfer(txq->data[i].xfer); 930 txq->data[i].xfer = NULL; 931 } 932 } 933 934 static int 935 run_load_microcode(struct run_softc *sc) 936 { 937 usb_device_request_t req; 938 const char *fwname; 939 u_char *ucode = NULL; /* XXX gcc 4.8.3: maybe-uninitialized */ 940 size_t size = 0; /* XXX gcc 4.8.3: maybe-uninitialized */ 941 uint32_t tmp; 942 int ntries, error; 943 944 /* RT3071/RT3072 use a different firmware */ 945 if (sc->mac_ver != 0x2860 && 946 sc->mac_ver != 0x2872 && 947 sc->mac_ver != 0x3070) 948 fwname = "run-rt3071"; 949 else 950 fwname = "run-rt2870"; 951 952 if ((error = firmware_load("run", fwname, &ucode, &size)) != 0) { 953 device_printf(sc->sc_dev, 954 "error %d, could not read firmware %s\n", error, fwname); 955 return error; 956 } 957 if (size != 4096) { 958 device_printf(sc->sc_dev, 959 "invalid firmware size (should be 4KB)\n"); 960 firmware_free(ucode, size); 961 return EINVAL; 962 } 963 964 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 965 /* write microcode image */ 966 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 967 firmware_free(ucode, size); 968 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 969 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 970 971 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 972 req.bRequest = RT2870_RESET; 973 USETW(req.wValue, 8); 974 USETW(req.wIndex, 0); 975 USETW(req.wLength, 0); 976 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 977 return error; 978 979 usbd_delay_ms(sc->sc_udev, 10); 980 run_write(sc, RT2860_H2M_BBPAGENT, 0); 981 run_write(sc, RT2860_H2M_MAILBOX, 0); 982 run_write(sc, RT2860_H2M_INTSRC, 0); 983 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 984 return error; 985 986 /* wait until microcontroller is ready */ 987 for (ntries = 0; ntries < 1000; ntries++) { 988 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 989 return error; 990 if (tmp & RT2860_MCU_READY) 991 break; 992 usbd_delay_ms(sc->sc_udev, 10); 993 } 994 if (ntries == 1000) { 995 device_printf(sc->sc_dev, 996 "timeout waiting for MCU to initialize\n"); 997 return ETIMEDOUT; 998 } 999 1000 sc->sc_flags |= RUN_FWLOADED; 1001 1002 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 1003 return 0; 1004 } 1005 1006 static int 1007 run_reset(struct run_softc *sc) 1008 { 1009 usb_device_request_t req; 1010 1011 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1012 req.bRequest = RT2870_RESET; 1013 USETW(req.wValue, 1); 1014 USETW(req.wIndex, 0); 1015 USETW(req.wLength, 0); 1016 return usbd_do_request(sc->sc_udev, &req, NULL); 1017 } 1018 1019 static int 1020 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 1021 { 1022 uint32_t tmp; 1023 int error; 1024 1025 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 1026 if (error == 0) 1027 *val = le32toh(tmp); 1028 else 1029 *val = 0xffffffff; 1030 return error; 1031 } 1032 1033 static int 1034 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 1035 { 1036 usb_device_request_t req; 1037 1038 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1039 req.bRequest = RT2870_READ_REGION_1; 1040 USETW(req.wValue, 0); 1041 USETW(req.wIndex, reg); 1042 USETW(req.wLength, len); 1043 return usbd_do_request(sc->sc_udev, &req, buf); 1044 } 1045 1046 static int 1047 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 1048 { 1049 usb_device_request_t req; 1050 1051 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1052 req.bRequest = RT2870_WRITE_2; 1053 USETW(req.wValue, val); 1054 USETW(req.wIndex, reg); 1055 USETW(req.wLength, 0); 1056 return usbd_do_request(sc->sc_udev, &req, NULL); 1057 } 1058 1059 static int 1060 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 1061 { 1062 uint32_t tmp = htole32(val); 1063 return run_write_region_1(sc, reg, (uint8_t *)&tmp, sizeof(tmp)); 1064 } 1065 1066 static int 1067 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 1068 int len) 1069 { 1070 int error = 0; 1071 if (sc->sc_flags & RUN_USE_BLOCK_WRITE) { 1072 usb_device_request_t req; 1073 /* 1074 * NOTE: It appears the WRITE_REGION_1 command cannot be 1075 * passed a huge amount of data, which will crash the 1076 * firmware. Limit amount of data passed to 64 bytes at a 1077 * time. 1078 */ 1079 while (len > 0) { 1080 int delta = MIN(len, 64); 1081 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1082 req.bRequest = RT2870_WRITE_REGION_1; 1083 USETW(req.wValue, 0); 1084 USETW(req.wIndex, reg); 1085 USETW(req.wLength, delta); 1086 error = usbd_do_request(sc->sc_udev, &req, 1087 __UNCONST(buf)); 1088 if (error != 0) 1089 break; 1090 reg += delta; 1091 buf += delta; 1092 len -= delta; 1093 } 1094 } else { 1095 /* 1096 * NB: the WRITE_REGION_1 command is not stable on RT2860. 1097 * We thus issue multiple WRITE_2 commands instead. 1098 */ 1099 int i; 1100 KASSERT((len & 1) == 0); 1101 for (i = 0; i < len && error == 0; i += 2) 1102 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 1103 } 1104 return error; 1105 } 1106 1107 static int 1108 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 1109 { 1110 int error = 0; 1111 1112 if (sc->sc_flags & RUN_USE_BLOCK_WRITE) { 1113 while (count > 0) { 1114 int i, delta; 1115 uint32_t tmp[16]; 1116 1117 delta = MIN(count, __arraycount(tmp)); 1118 for (i = 0; i < delta; i++) 1119 tmp[i] = htole32(val); 1120 error = run_write_region_1(sc, reg, (uint8_t *)tmp, 1121 delta * sizeof(uint32_t)); 1122 if (error != 0) 1123 break; 1124 reg += delta * sizeof(uint32_t); 1125 count -= delta; 1126 } 1127 } else { 1128 for (; count > 0 && error == 0; count--, reg += 4) 1129 error = run_write(sc, reg, val); 1130 } 1131 return error; 1132 } 1133 1134 static int 1135 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val, int count) 1136 { 1137 uint32_t tmp; 1138 uint16_t reg; 1139 int error, ntries; 1140 1141 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1142 return error; 1143 1144 if (count == 2) 1145 addr *= 2; 1146 /*- 1147 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1148 * DATA0: F E D C 1149 * DATA1: B A 9 8 1150 * DATA2: 7 6 5 4 1151 * DATA3: 3 2 1 0 1152 */ 1153 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1154 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1155 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1156 for (ntries = 0; ntries < 100; ntries++) { 1157 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1158 return error; 1159 if (!(tmp & RT3070_EFSROM_KICK)) 1160 break; 1161 usbd_delay_ms(sc->sc_udev, 2); 1162 } 1163 if (ntries == 100) 1164 return ETIMEDOUT; 1165 1166 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1167 *val = 0xffff; /* address not found */ 1168 return 0; 1169 } 1170 /* determine to which 32-bit register our 16-bit word belongs */ 1171 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1172 if ((error = run_read(sc, reg, &tmp)) != 0) 1173 return error; 1174 1175 tmp >>= (8 * (addr & 0x3)); 1176 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1177 return 0; 1178 } 1179 1180 /* Read 16-bit from eFUSE ROM for RT3xxxx. */ 1181 static int 1182 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1183 { 1184 return run_efuse_read(sc, addr, val, 2); 1185 } 1186 1187 static int 1188 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1189 { 1190 usb_device_request_t req; 1191 uint16_t tmp; 1192 int error; 1193 1194 addr *= 2; 1195 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1196 req.bRequest = RT2870_EEPROM_READ; 1197 USETW(req.wValue, 0); 1198 USETW(req.wIndex, addr); 1199 USETW(req.wLength, sizeof(tmp)); 1200 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1201 if (error == 0) 1202 *val = le16toh(tmp); 1203 else 1204 *val = 0xffff; 1205 return error; 1206 } 1207 1208 static __inline int 1209 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1210 { 1211 1212 /* either eFUSE ROM or EEPROM */ 1213 return sc->sc_srom_read(sc, addr, val); 1214 } 1215 1216 static int 1217 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1218 { 1219 uint32_t tmp; 1220 int error, ntries; 1221 1222 for (ntries = 0; ntries < 10; ntries++) { 1223 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1224 return error; 1225 if (!(tmp & RT2860_RF_REG_CTRL)) 1226 break; 1227 } 1228 if (ntries == 10) 1229 return ETIMEDOUT; 1230 1231 /* RF registers are 24-bit on the RT2860 */ 1232 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1233 (val & 0x3fffff) << 2 | (reg & 3); 1234 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1235 } 1236 1237 static int 1238 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1239 { 1240 uint32_t tmp; 1241 int error, ntries; 1242 1243 for (ntries = 0; ntries < 100; ntries++) { 1244 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1245 return error; 1246 if (!(tmp & RT3070_RF_KICK)) 1247 break; 1248 } 1249 if (ntries == 100) 1250 return ETIMEDOUT; 1251 1252 tmp = RT3070_RF_KICK | reg << 8; 1253 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1254 return error; 1255 1256 for (ntries = 0; ntries < 100; ntries++) { 1257 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1258 return error; 1259 if (!(tmp & RT3070_RF_KICK)) 1260 break; 1261 } 1262 if (ntries == 100) 1263 return ETIMEDOUT; 1264 1265 *val = tmp & 0xff; 1266 return 0; 1267 } 1268 1269 static int 1270 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1271 { 1272 uint32_t tmp; 1273 int error, ntries; 1274 1275 for (ntries = 0; ntries < 10; ntries++) { 1276 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1277 return error; 1278 if (!(tmp & RT3070_RF_KICK)) 1279 break; 1280 } 1281 if (ntries == 10) 1282 return ETIMEDOUT; 1283 1284 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1285 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1286 } 1287 1288 static int 1289 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1290 { 1291 uint32_t tmp; 1292 int ntries, error; 1293 1294 for (ntries = 0; ntries < 10; ntries++) { 1295 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1296 return error; 1297 if (!(tmp & RT2860_BBP_CSR_KICK)) 1298 break; 1299 } 1300 if (ntries == 10) 1301 return ETIMEDOUT; 1302 1303 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1304 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1305 return error; 1306 1307 for (ntries = 0; ntries < 10; ntries++) { 1308 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1309 return error; 1310 if (!(tmp & RT2860_BBP_CSR_KICK)) 1311 break; 1312 } 1313 if (ntries == 10) 1314 return ETIMEDOUT; 1315 1316 *val = tmp & 0xff; 1317 return 0; 1318 } 1319 1320 static int 1321 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1322 { 1323 uint32_t tmp; 1324 int ntries, error; 1325 1326 for (ntries = 0; ntries < 10; ntries++) { 1327 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1328 return error; 1329 if (!(tmp & RT2860_BBP_CSR_KICK)) 1330 break; 1331 } 1332 if (ntries == 10) 1333 return ETIMEDOUT; 1334 1335 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1336 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1337 } 1338 1339 /* 1340 * Send a command to the 8051 microcontroller unit. 1341 */ 1342 static int 1343 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1344 { 1345 uint32_t tmp; 1346 int error, ntries; 1347 1348 for (ntries = 0; ntries < 100; ntries++) { 1349 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1350 return error; 1351 if (!(tmp & RT2860_H2M_BUSY)) 1352 break; 1353 } 1354 if (ntries == 100) 1355 return ETIMEDOUT; 1356 1357 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1358 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1359 error = run_write(sc, RT2860_HOST_CMD, cmd); 1360 return error; 1361 } 1362 1363 /* 1364 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1365 * Used to adjust per-rate Tx power registers. 1366 */ 1367 static __inline uint32_t 1368 b4inc(uint32_t b32, int8_t delta) 1369 { 1370 int8_t i, b4; 1371 1372 for (i = 0; i < 8; i++) { 1373 b4 = b32 & 0xf; 1374 b4 += delta; 1375 if (b4 < 0) 1376 b4 = 0; 1377 else if (b4 > 0xf) 1378 b4 = 0xf; 1379 b32 = b32 >> 4 | b4 << 28; 1380 } 1381 return b32; 1382 } 1383 1384 static const char * 1385 run_get_rf(uint16_t rev) 1386 { 1387 switch (rev) { 1388 case RT2860_RF_2820: return "RT2820"; 1389 case RT2860_RF_2850: return "RT2850"; 1390 case RT2860_RF_2720: return "RT2720"; 1391 case RT2860_RF_2750: return "RT2750"; 1392 case RT3070_RF_3020: return "RT3020"; 1393 case RT3070_RF_2020: return "RT2020"; 1394 case RT3070_RF_3021: return "RT3021"; 1395 case RT3070_RF_3022: return "RT3022"; 1396 case RT3070_RF_3052: return "RT3052"; 1397 case RT3070_RF_3053: return "RT3053"; 1398 case RT5592_RF_5592: return "RT5592"; 1399 case RT5390_RF_5370: return "RT5370"; 1400 case RT5390_RF_5372: return "RT5372"; 1401 } 1402 return "unknown"; 1403 } 1404 1405 static void 1406 run_rt3593_get_txpower(struct run_softc *sc) 1407 { 1408 uint16_t addr, val; 1409 int i; 1410 1411 /* Read power settings for 2GHz channels. */ 1412 for (i = 0; i < 14; i += 2) { 1413 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1414 RT2860_EEPROM_PWR2GHZ_BASE1; 1415 run_srom_read(sc, addr + i / 2, &val); 1416 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1417 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1418 1419 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1420 RT2860_EEPROM_PWR2GHZ_BASE2; 1421 run_srom_read(sc, addr + i / 2, &val); 1422 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1423 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1424 1425 if (sc->ntxchains == 3) { 1426 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1427 &val); 1428 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1429 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1430 } 1431 } 1432 /* Fix broken Tx power entries. */ 1433 for (i = 0; i < 14; i++) { 1434 if (sc->txpow1[i] > 31) 1435 sc->txpow1[i] = 5; 1436 if (sc->txpow2[i] > 31) 1437 sc->txpow2[i] = 5; 1438 if (sc->ntxchains == 3) { 1439 if (sc->txpow3[i] > 31) 1440 sc->txpow3[i] = 5; 1441 } 1442 } 1443 /* Read power settings for 5GHz channels. */ 1444 for (i = 0; i < 40; i += 2) { 1445 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1446 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1447 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1448 1449 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1450 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1451 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1452 1453 if (sc->ntxchains == 3) { 1454 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1455 &val); 1456 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1457 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1458 } 1459 } 1460 } 1461 1462 static void 1463 run_get_txpower(struct run_softc *sc) 1464 { 1465 uint16_t val; 1466 int i; 1467 1468 /* Read power settings for 2GHz channels. */ 1469 for (i = 0; i < 14; i += 2) { 1470 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1471 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1472 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1473 1474 if (sc->mac_ver != 0x5390) { 1475 run_srom_read(sc, 1476 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1477 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1478 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1479 } 1480 } 1481 /* Fix broken Tx power entries. */ 1482 for (i = 0; i < 14; i++) { 1483 if (sc->mac_ver >= 0x5390) { 1484 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 39) 1485 sc->txpow1[i] = 5; 1486 } else { 1487 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1488 sc->txpow1[i] = 5; 1489 } 1490 if (sc->mac_ver > 0x5390) { 1491 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 39) 1492 sc->txpow2[i] = 5; 1493 } else if (sc->mac_ver < 0x5390) { 1494 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1495 sc->txpow2[i] = 5; 1496 } 1497 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1498 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1499 } 1500 /* Read power settings for 5GHz channels. */ 1501 for (i = 0; i < 40; i += 2) { 1502 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1503 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1504 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1505 1506 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1507 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1508 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1509 } 1510 /* Fix broken Tx power entries. */ 1511 for (i = 0; i < 40; i++ ) { 1512 if (sc->mac_ver != 0x5592) { 1513 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1514 sc->txpow1[14 + i] = 5; 1515 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1516 sc->txpow2[14 + i] = 5; 1517 } 1518 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1519 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1520 sc->txpow2[14 + i])); 1521 } 1522 } 1523 1524 static int 1525 run_read_eeprom(struct run_softc *sc) 1526 { 1527 struct ieee80211com *ic = &sc->sc_ic; 1528 int8_t delta_2ghz, delta_5ghz; 1529 uint32_t tmp; 1530 uint16_t val; 1531 int ridx, ant, i; 1532 1533 /* check whether the ROM is eFUSE ROM or EEPROM */ 1534 sc->sc_srom_read = run_eeprom_read_2; 1535 if (sc->mac_ver >= 0x3070) { 1536 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1537 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1538 if (tmp & RT3070_SEL_EFUSE) 1539 sc->sc_srom_read = run_efuse_read_2; 1540 } 1541 1542 /* read ROM version */ 1543 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1544 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1545 1546 /* read MAC address */ 1547 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1548 ic->ic_myaddr[0] = val & 0xff; 1549 ic->ic_myaddr[1] = val >> 8; 1550 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1551 ic->ic_myaddr[2] = val & 0xff; 1552 ic->ic_myaddr[3] = val >> 8; 1553 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1554 ic->ic_myaddr[4] = val & 0xff; 1555 ic->ic_myaddr[5] = val >> 8; 1556 1557 if (sc->mac_ver < 0x3593) { 1558 /* read vendor BBP settings */ 1559 for (i = 0; i < 10; i++) { 1560 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1561 sc->bbp[i].val = val & 0xff; 1562 sc->bbp[i].reg = val >> 8; 1563 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1564 sc->bbp[i].val)); 1565 } 1566 1567 if (sc->mac_ver >= 0x3071) { 1568 /* read vendor RF settings */ 1569 for (i = 0; i < 8; i++) { 1570 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1571 &val); 1572 sc->rf[i].val = val & 0xff; 1573 sc->rf[i].reg = val >> 8; 1574 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1575 sc->rf[i].val)); 1576 } 1577 } 1578 } 1579 1580 /* read RF frequency offset from EEPROM */ 1581 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1582 RT3593_EEPROM_FREQ, &val); 1583 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1584 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1585 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1586 RT3593_EEPROM_FREQ, &val); 1587 if ((val >> 8) != 0xff) { 1588 /* read LEDs operating mode */ 1589 sc->leds = val >> 8; 1590 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1591 RT3593_EEPROM_LED1, &sc->led[0]); 1592 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1593 RT3593_EEPROM_LED2, &sc->led[1]); 1594 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1595 RT3593_EEPROM_LED3, &sc->led[2]); 1596 } else { 1597 /* broken EEPROM, use default settings */ 1598 sc->leds = 0x01; 1599 sc->led[0] = 0x5555; 1600 sc->led[1] = 0x2221; 1601 sc->led[2] = 0x5627; /* differs from RT2860 */ 1602 } 1603 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1604 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1605 1606 /* read RF information */ 1607 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1608 run_srom_read(sc, 0x00, &val); 1609 else 1610 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1611 if (val == 0xffff) { 1612 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1613 if (sc->mac_ver == 0x3572) { 1614 /* default to RF3052 2T2R */ 1615 sc->rf_rev = RT3070_RF_3052; 1616 sc->ntxchains = 2; 1617 sc->nrxchains = 2; 1618 } else if (sc->mac_ver >= 0x3070) { 1619 /* default to RF3020 1T1R */ 1620 sc->rf_rev = RT3070_RF_3020; 1621 sc->ntxchains = 1; 1622 sc->nrxchains = 1; 1623 } else { 1624 /* default to RF2820 1T2R */ 1625 sc->rf_rev = RT2860_RF_2820; 1626 sc->ntxchains = 1; 1627 sc->nrxchains = 2; 1628 } 1629 } else { 1630 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1631 sc->rf_rev = val; 1632 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1633 } else 1634 sc->rf_rev = (val >> 8) & 0xf; 1635 sc->ntxchains = (val >> 4) & 0xf; 1636 sc->nrxchains = val & 0xf; 1637 } 1638 DPRINTF(("EEPROM RF rev=0x%04x chains=%dT%dR\n", 1639 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1640 1641 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1642 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1643 /* check if driver should patch the DAC issue */ 1644 if ((val >> 8) != 0xff) 1645 sc->patch_dac = (val >> 15) & 1; 1646 if ((val & 0xff) != 0xff) { 1647 sc->ext_5ghz_lna = (val >> 3) & 1; 1648 sc->ext_2ghz_lna = (val >> 2) & 1; 1649 /* check if RF supports automatic Tx access gain control */ 1650 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1651 /* check if we have a hardware radio switch */ 1652 sc->rfswitch = val & 1; 1653 } 1654 1655 /* Read Tx power settings. */ 1656 if (sc->mac_ver == 0x3593) 1657 run_rt3593_get_txpower(sc); 1658 else 1659 run_get_txpower(sc); 1660 1661 /* read Tx power compensation for each Tx rate */ 1662 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1663 delta_2ghz = delta_5ghz = 0; 1664 if ((val & 0xff) != 0xff && (val & 0x80)) { 1665 delta_2ghz = val & 0xf; 1666 if (!(val & 0x40)) /* negative number */ 1667 delta_2ghz = -delta_2ghz; 1668 } 1669 val >>= 8; 1670 if ((val & 0xff) != 0xff && (val & 0x80)) { 1671 delta_5ghz = val & 0xf; 1672 if (!(val & 0x40)) /* negative number */ 1673 delta_5ghz = -delta_5ghz; 1674 } 1675 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1676 delta_2ghz, delta_5ghz)); 1677 1678 for (ridx = 0; ridx < 5; ridx++) { 1679 uint32_t reg; 1680 1681 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1682 reg = val; 1683 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1684 reg |= (uint32_t)val << 16; 1685 1686 sc->txpow20mhz[ridx] = reg; 1687 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1688 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1689 1690 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1691 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1692 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1693 } 1694 1695 DPRINTF(("mac_ver %hx\n", sc->mac_ver)); 1696 /* read RSSI offsets and LNA gains from EEPROM */ 1697 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1698 RT3593_EEPROM_RSSI1_2GHZ, &val); 1699 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1700 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1701 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1702 RT3593_EEPROM_RSSI2_2GHZ, &val); 1703 if (sc->mac_ver >= 0x3070) { 1704 if (sc->mac_ver == 0x3593) { 1705 sc->txmixgain_2ghz = 0; 1706 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1707 } else { 1708 /* 1709 * On RT3070 chips (limited to 2 Rx chains), this ROM 1710 * field contains the Tx mixer gain for the 2GHz band. 1711 */ 1712 if ((val & 0xff) != 0xff) 1713 sc->txmixgain_2ghz = val & 0x7; 1714 } 1715 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1716 } else { 1717 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1718 } 1719 if (sc->mac_ver == 0x3593) 1720 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1721 sc->lna[2] = val >> 8; /* channel group 2 */ 1722 1723 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1724 RT3593_EEPROM_RSSI1_5GHZ, &val); 1725 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1726 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1727 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1728 RT3593_EEPROM_RSSI2_5GHZ, &val); 1729 if (sc->mac_ver == 0x3572) { 1730 /* 1731 * On RT3572 chips (limited to 2 Rx chains), this ROM 1732 * field contains the Tx mixer gain for the 5GHz band. 1733 */ 1734 if ((val & 0xff) != 0xff) 1735 sc->txmixgain_5ghz = val & 0x7; 1736 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1737 } else { 1738 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1739 } 1740 if (sc->mac_ver == 0x3593) { 1741 sc->txmixgain_5ghz = 0; 1742 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1743 } 1744 sc->lna[3] = val >> 8; /* channel group 3 */ 1745 1746 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1747 RT3593_EEPROM_LNA, &val); 1748 sc->lna[0] = val & 0xff; /* channel group 0 */ 1749 sc->lna[1] = val >> 8; /* channel group 1 */ 1750 1751 /* fix broken 5GHz LNA entries */ 1752 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1753 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1754 sc->lna[2] = sc->lna[1]; 1755 } 1756 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1757 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1758 sc->lna[3] = sc->lna[1]; 1759 } 1760 1761 /* fix broken RSSI offset entries */ 1762 for (ant = 0; ant < 3; ant++) { 1763 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1764 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1765 ant + 1, sc->rssi_2ghz[ant])); 1766 sc->rssi_2ghz[ant] = 0; 1767 } 1768 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1769 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1770 ant + 1, sc->rssi_5ghz[ant])); 1771 sc->rssi_5ghz[ant] = 0; 1772 } 1773 } 1774 return 0; 1775 } 1776 1777 static struct ieee80211_node * 1778 run_node_alloc(struct ieee80211_node_table *nt) 1779 { 1780 struct run_node *rn = 1781 malloc(sizeof(struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1782 return rn ? &rn->ni : NULL; 1783 } 1784 1785 static int 1786 run_media_change(struct ifnet *ifp) 1787 { 1788 struct run_softc *sc = ifp->if_softc; 1789 struct ieee80211com *ic = &sc->sc_ic; 1790 uint8_t rate, ridx; 1791 int error; 1792 1793 error = ieee80211_media_change(ifp); 1794 if (error != ENETRESET) 1795 return error; 1796 1797 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1798 rate = ic->ic_sup_rates[ic->ic_curmode]. 1799 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1800 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1801 if (rt2860_rates[ridx].rate == rate) 1802 break; 1803 sc->fixed_ridx = ridx; 1804 } 1805 1806 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1807 run_init(ifp); 1808 1809 return 0; 1810 } 1811 1812 static void 1813 run_next_scan(void *arg) 1814 { 1815 struct run_softc *sc = arg; 1816 1817 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1818 ieee80211_next_scan(&sc->sc_ic); 1819 } 1820 1821 static void 1822 run_task(void *arg) 1823 { 1824 struct run_softc *sc = arg; 1825 struct run_host_cmd_ring *ring = &sc->cmdq; 1826 struct run_host_cmd *cmd; 1827 int s; 1828 1829 /* process host commands */ 1830 s = splusb(); 1831 while (ring->next != ring->cur) { 1832 cmd = &ring->cmd[ring->next]; 1833 splx(s); 1834 membar_consumer(); 1835 /* callback */ 1836 cmd->cb(sc, cmd->data); 1837 s = splusb(); 1838 atomic_dec_uint(&ring->queued); 1839 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1840 } 1841 wakeup(ring); 1842 splx(s); 1843 } 1844 1845 static void 1846 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1847 void *arg, int len) 1848 { 1849 struct run_host_cmd_ring *ring = &sc->cmdq; 1850 struct run_host_cmd *cmd; 1851 int s; 1852 1853 if (sc->sc_flags & RUN_DETACHING) 1854 return; 1855 1856 s = splusb(); 1857 cmd = &ring->cmd[ring->cur]; 1858 cmd->cb = cb; 1859 KASSERT(len <= sizeof(cmd->data)); 1860 memcpy(cmd->data, arg, len); 1861 membar_producer(); 1862 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1863 1864 /* if there is no pending command already, schedule a task */ 1865 if (atomic_inc_uint_nv(&ring->queued) == 1) 1866 usb_add_task(sc->sc_udev, &sc->sc_task, USB_TASKQ_DRIVER); 1867 splx(s); 1868 } 1869 1870 static int 1871 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1872 { 1873 struct run_softc *sc = ic->ic_ifp->if_softc; 1874 struct run_cmd_newstate cmd; 1875 1876 callout_stop(&sc->scan_to); 1877 callout_stop(&sc->calib_to); 1878 1879 /* do it in a process context */ 1880 cmd.state = nstate; 1881 cmd.arg = arg; 1882 run_do_async(sc, run_newstate_cb, &cmd, sizeof(cmd)); 1883 return 0; 1884 } 1885 1886 static void 1887 run_newstate_cb(struct run_softc *sc, void *arg) 1888 { 1889 struct run_cmd_newstate *cmd = arg; 1890 struct ifnet *ifp = &sc->sc_if; 1891 struct ieee80211com *ic = &sc->sc_ic; 1892 enum ieee80211_state ostate; 1893 struct ieee80211_node *ni; 1894 uint32_t tmp, sta[3]; 1895 uint8_t wcid; 1896 int s; 1897 1898 s = splnet(); 1899 ostate = ic->ic_state; 1900 1901 if (ostate == IEEE80211_S_RUN) { 1902 /* turn link LED off */ 1903 run_set_leds(sc, RT2860_LED_RADIO); 1904 } 1905 1906 switch (cmd->state) { 1907 case IEEE80211_S_INIT: 1908 if (ostate == IEEE80211_S_RUN) { 1909 /* abort TSF synchronization */ 1910 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1911 run_write(sc, RT2860_BCN_TIME_CFG, 1912 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1913 RT2860_TBTT_TIMER_EN)); 1914 } 1915 break; 1916 1917 case IEEE80211_S_SCAN: 1918 run_set_chan(sc, ic->ic_curchan); 1919 callout_schedule(&sc->scan_to, hz / 5); 1920 break; 1921 1922 case IEEE80211_S_AUTH: 1923 case IEEE80211_S_ASSOC: 1924 run_set_chan(sc, ic->ic_curchan); 1925 break; 1926 1927 case IEEE80211_S_RUN: 1928 run_set_chan(sc, ic->ic_curchan); 1929 1930 ni = ic->ic_bss; 1931 1932 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1933 run_updateslot(ifp); 1934 run_enable_mrr(sc); 1935 run_set_txpreamble(sc); 1936 run_set_basicrates(sc); 1937 run_set_bssid(sc, ni->ni_bssid); 1938 } 1939 #ifndef IEEE80211_STA_ONLY 1940 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 1941 ic->ic_opmode == IEEE80211_M_IBSS) 1942 (void)run_setup_beacon(sc); 1943 #endif 1944 if (ic->ic_opmode == IEEE80211_M_STA) { 1945 /* add BSS entry to the WCID table */ 1946 wcid = RUN_AID2WCID(ni->ni_associd); 1947 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1948 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1949 1950 /* fake a join to init the tx rate */ 1951 run_newassoc(ni, 1); 1952 } 1953 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1954 run_enable_tsf_sync(sc); 1955 1956 /* clear statistic registers used by AMRR */ 1957 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1958 (uint8_t *)sta, sizeof(sta)); 1959 /* start calibration timer */ 1960 callout_schedule(&sc->calib_to, hz); 1961 } 1962 1963 /* turn link LED on */ 1964 run_set_leds(sc, RT2860_LED_RADIO | 1965 (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1966 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1967 break; 1968 } 1969 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1970 splx(s); 1971 } 1972 1973 static int 1974 run_updateedca(struct ieee80211com *ic) 1975 { 1976 1977 /* do it in a process context */ 1978 run_do_async(ic->ic_ifp->if_softc, run_updateedca_cb, NULL, 0); 1979 return 0; 1980 } 1981 1982 /* ARGSUSED */ 1983 static void 1984 run_updateedca_cb(struct run_softc *sc, void *arg) 1985 { 1986 struct ieee80211com *ic = &sc->sc_ic; 1987 int s, aci; 1988 1989 s = splnet(); 1990 /* update MAC TX configuration registers */ 1991 for (aci = 0; aci < WME_NUM_AC; aci++) { 1992 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1993 ic->ic_wme.wme_params[aci].wmep_logcwmax << 16 | 1994 ic->ic_wme.wme_params[aci].wmep_logcwmin << 12 | 1995 ic->ic_wme.wme_params[aci].wmep_aifsn << 8 | 1996 ic->ic_wme.wme_params[aci].wmep_txopLimit); 1997 } 1998 1999 /* update SCH/DMA registers too */ 2000 run_write(sc, RT2860_WMM_AIFSN_CFG, 2001 ic->ic_wme.wme_params[WME_AC_VO].wmep_aifsn << 12 | 2002 ic->ic_wme.wme_params[WME_AC_VI].wmep_aifsn << 8 | 2003 ic->ic_wme.wme_params[WME_AC_BK].wmep_aifsn << 4 | 2004 ic->ic_wme.wme_params[WME_AC_BE].wmep_aifsn); 2005 run_write(sc, RT2860_WMM_CWMIN_CFG, 2006 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmin << 12 | 2007 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmin << 8 | 2008 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmin << 4 | 2009 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmin); 2010 run_write(sc, RT2860_WMM_CWMAX_CFG, 2011 ic->ic_wme.wme_params[WME_AC_VO].wmep_logcwmax << 12 | 2012 ic->ic_wme.wme_params[WME_AC_VI].wmep_logcwmax << 8 | 2013 ic->ic_wme.wme_params[WME_AC_BK].wmep_logcwmax << 4 | 2014 ic->ic_wme.wme_params[WME_AC_BE].wmep_logcwmax); 2015 run_write(sc, RT2860_WMM_TXOP0_CFG, 2016 ic->ic_wme.wme_params[WME_AC_BK].wmep_txopLimit << 16 | 2017 ic->ic_wme.wme_params[WME_AC_BE].wmep_txopLimit); 2018 run_write(sc, RT2860_WMM_TXOP1_CFG, 2019 ic->ic_wme.wme_params[WME_AC_VO].wmep_txopLimit << 16 | 2020 ic->ic_wme.wme_params[WME_AC_VI].wmep_txopLimit); 2021 splx(s); 2022 } 2023 2024 #ifdef RUN_HWCRYPTO 2025 static int 2026 run_set_key(struct ieee80211com *ic, const struct ieee80211_key *k, 2027 const uint8_t *mac) 2028 { 2029 struct run_softc *sc = ic->ic_ifp->if_softc; 2030 struct ieee80211_node *ni = ic->ic_bss; 2031 struct run_cmd_key cmd; 2032 2033 /* do it in a process context */ 2034 cmd.key = *k; 2035 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2036 run_do_async(sc, run_set_key_cb, &cmd, sizeof(cmd)); 2037 return 1; 2038 } 2039 2040 static void 2041 run_set_key_cb(struct run_softc *sc, void *arg) 2042 { 2043 #ifndef IEEE80211_STA_ONLY 2044 struct ieee80211com *ic = &sc->sc_ic; 2045 #endif 2046 struct run_cmd_key *cmd = arg; 2047 struct ieee80211_key *k = &cmd->key; 2048 uint32_t attr; 2049 uint16_t base; 2050 uint8_t mode, wcid, iv[8]; 2051 2052 /* map net80211 cipher to RT2860 security mode */ 2053 switch (k->wk_cipher->ic_cipher) { 2054 case IEEE80211_CIPHER_WEP: 2055 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2056 if (k->wk_keylen == 5) 2057 mode = RT2860_MODE_WEP40; 2058 else 2059 mode = RT2860_MODE_WEP104; 2060 break; 2061 case IEEE80211_CIPHER_TKIP: 2062 mode = RT2860_MODE_TKIP; 2063 break; 2064 case IEEE80211_CIPHER_AES_CCM: 2065 mode = RT2860_MODE_AES_CCMP; 2066 break; 2067 default: 2068 return; 2069 } 2070 2071 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2072 wcid = 0; /* NB: update WCID0 for group keys */ 2073 base = RT2860_SKEY(0, k->wk_keyix); 2074 } else { 2075 wcid = RUN_AID2WCID(cmd->associd); 2076 base = RT2860_PKEY(wcid); 2077 } 2078 2079 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2080 run_write_region_1(sc, base, k->wk_key, 16); 2081 #ifndef IEEE80211_STA_ONLY 2082 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2083 run_write_region_1(sc, base + 16, &k->wk_key[16], 8); 2084 run_write_region_1(sc, base + 24, &k->wk_key[24], 8); 2085 } else 2086 #endif 2087 { 2088 run_write_region_1(sc, base + 16, &k->wk_key[24], 8); 2089 run_write_region_1(sc, base + 24, &k->wk_key[16], 8); 2090 } 2091 } else { 2092 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 2093 run_write_region_1(sc, base, k->wk_key, 2094 (k->wk_keylen + 1) & ~1); 2095 } 2096 2097 if (!(k->wk_flags & IEEE80211_KEY_GROUP) || 2098 (k->wk_flags & IEEE80211_KEY_XMIT)) { 2099 /* set initial packet number in IV+EIV */ 2100 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) { 2101 memset(iv, 0, sizeof(iv)); 2102 iv[3] = sc->sc_ic.ic_crypto.cs_def_txkey << 6; 2103 } else { 2104 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP) { 2105 iv[0] = k->wk_keytsc >> 8; 2106 iv[1] = (iv[0] | 0x20) & 0x7f; 2107 iv[2] = k->wk_keytsc; 2108 } else /* CCMP */ { 2109 iv[0] = k->wk_keytsc; 2110 iv[1] = k->wk_keytsc >> 8; 2111 iv[2] = 0; 2112 } 2113 iv[3] = k->wk_keyix << 6 | IEEE80211_WEP_EXTIV; 2114 iv[4] = k->wk_keytsc >> 16; 2115 iv[5] = k->wk_keytsc >> 24; 2116 iv[6] = k->wk_keytsc >> 32; 2117 iv[7] = k->wk_keytsc >> 40; 2118 } 2119 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 2120 } 2121 2122 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2123 /* install group key */ 2124 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2125 attr &= ~(0xf << (k->wk_keyix * 4)); 2126 attr |= mode << (k->wk_keyix * 4); 2127 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2128 } else { 2129 /* install pairwise key */ 2130 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2131 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2132 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2133 } 2134 } 2135 2136 static int 2137 run_delete_key(struct ieee80211com *ic, const struct ieee80211_key *k) 2138 { 2139 struct run_softc *sc = ic->ic_ifp->if_softc; 2140 struct ieee80211_node *ni = ic->ic_bss; 2141 struct run_cmd_key cmd; 2142 2143 /* do it in a process context */ 2144 cmd.key = *k; 2145 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2146 run_do_async(sc, run_delete_key_cb, &cmd, sizeof(cmd)); 2147 return 1; 2148 } 2149 2150 static void 2151 run_delete_key_cb(struct run_softc *sc, void *arg) 2152 { 2153 struct run_cmd_key *cmd = arg; 2154 struct ieee80211_key *k = &cmd->key; 2155 uint32_t attr; 2156 uint8_t wcid; 2157 2158 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_WEP) 2159 k->wk_flags |= IEEE80211_KEY_GROUP; /* XXX */ 2160 2161 if (k->wk_flags & IEEE80211_KEY_GROUP) { 2162 /* remove group key */ 2163 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2164 attr &= ~(0xf << (k->wk_keyix * 4)); 2165 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2166 2167 } else { 2168 /* remove pairwise key */ 2169 wcid = RUN_AID2WCID(cmd->associd); 2170 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2171 attr &= ~0xf; 2172 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2173 } 2174 } 2175 #endif 2176 2177 static void 2178 run_calibrate_to(void *arg) 2179 { 2180 2181 /* do it in a process context */ 2182 run_do_async(arg, run_calibrate_cb, NULL, 0); 2183 /* next timeout will be rescheduled in the calibration task */ 2184 } 2185 2186 /* ARGSUSED */ 2187 static void 2188 run_calibrate_cb(struct run_softc *sc, void *arg) 2189 { 2190 struct ifnet *ifp = &sc->sc_if; 2191 uint32_t sta[3]; 2192 int s, error; 2193 2194 /* read statistic counters (clear on read) and update AMRR state */ 2195 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2196 sizeof(sta)); 2197 if (error != 0) 2198 goto skip; 2199 2200 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2201 le32toh(sta[1]) >> 16, le32toh(sta[1]) & 0xffff, 2202 le32toh(sta[0]) & 0xffff)); 2203 2204 s = splnet(); 2205 /* count failed TX as errors */ 2206 if_statadd(ifp, if_oerrors, le32toh(sta[0]) & 0xffff); 2207 2208 sc->amn.amn_retrycnt = 2209 (le32toh(sta[0]) & 0xffff) + /* failed TX count */ 2210 (le32toh(sta[1]) >> 16); /* TX retransmission count */ 2211 2212 sc->amn.amn_txcnt = 2213 sc->amn.amn_retrycnt + 2214 (le32toh(sta[1]) & 0xffff); /* successful TX count */ 2215 2216 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2217 splx(s); 2218 2219 skip: callout_schedule(&sc->calib_to, hz); 2220 } 2221 2222 static void 2223 run_newassoc(struct ieee80211_node *ni, int isnew) 2224 { 2225 struct run_softc *sc = ni->ni_ic->ic_ifp->if_softc; 2226 struct run_node *rn = (void *)ni; 2227 struct ieee80211_rateset *rs = &ni->ni_rates; 2228 uint8_t rate; 2229 int ridx, i, j; 2230 2231 DPRINTF(("new assoc isnew=%d addr=%s\n", 2232 isnew, ether_sprintf(ni->ni_macaddr))); 2233 2234 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2235 /* start at lowest available bit-rate, AMRR will raise */ 2236 ni->ni_txrate = 0; 2237 2238 for (i = 0; i < rs->rs_nrates; i++) { 2239 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2240 /* convert 802.11 rate to hardware rate index */ 2241 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2242 if (rt2860_rates[ridx].rate == rate) 2243 break; 2244 rn->ridx[i] = ridx; 2245 /* determine rate of control response frames */ 2246 for (j = i; j >= 0; j--) { 2247 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2248 rt2860_rates[rn->ridx[i]].phy == 2249 rt2860_rates[rn->ridx[j]].phy) 2250 break; 2251 } 2252 if (j >= 0) { 2253 rn->ctl_ridx[i] = rn->ridx[j]; 2254 } else { 2255 /* no basic rate found, use mandatory one */ 2256 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2257 } 2258 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2259 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2260 } 2261 } 2262 2263 /* 2264 * Return the Rx chain with the highest RSSI for a given frame. 2265 */ 2266 static __inline uint8_t 2267 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2268 { 2269 uint8_t rxchain = 0; 2270 2271 if (sc->nrxchains > 1) { 2272 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2273 rxchain = 1; 2274 if (sc->nrxchains > 2) 2275 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2276 rxchain = 2; 2277 } 2278 return rxchain; 2279 } 2280 2281 static void 2282 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2283 { 2284 struct ieee80211com *ic = &sc->sc_ic; 2285 struct ifnet *ifp = &sc->sc_if; 2286 struct ieee80211_frame *wh; 2287 struct ieee80211_node *ni; 2288 struct rt2870_rxd *rxd; 2289 struct rt2860_rxwi *rxwi; 2290 struct mbuf *m; 2291 uint32_t flags; 2292 uint16_t len, rxwisize, phy; 2293 uint8_t ant, rssi; 2294 int s; 2295 #ifdef RUN_HWCRYPTO 2296 int decrypted = 0; 2297 #endif 2298 2299 rxwi = (struct rt2860_rxwi *)buf; 2300 rxwisize = sizeof(struct rt2860_rxwi); 2301 if (sc->mac_ver == 0x5592) 2302 rxwisize += sizeof(uint64_t); 2303 else if (sc->mac_ver == 0x3593) 2304 rxwisize += sizeof(uint32_t); 2305 len = le16toh(rxwi->len) & 0xfff; 2306 if (__predict_false(len > dmalen)) { 2307 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2308 return; 2309 } 2310 /* Rx descriptor is located at the end */ 2311 rxd = (struct rt2870_rxd *)(buf + dmalen); 2312 flags = le32toh(rxd->flags); 2313 2314 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2315 if_statinc(ifp, if_ierrors); 2316 return; 2317 } 2318 2319 wh = (struct ieee80211_frame *)(buf + rxwisize); 2320 2321 if (__predict_false((flags & RT2860_RX_MICERR))) { 2322 /* report MIC failures to net80211 for TKIP */ 2323 ieee80211_notify_michael_failure(ic, wh, 0/* XXX */); 2324 if_statinc(ifp, if_ierrors); 2325 return; 2326 } 2327 2328 if (flags & RT2860_RX_L2PAD) { 2329 u_int hdrlen = ieee80211_hdrspace(ic, wh); 2330 memmove((uint8_t *)wh + 2, wh, hdrlen); 2331 wh = (struct ieee80211_frame *)((uint8_t *)wh + 2); 2332 } 2333 2334 #ifdef RUN_HWCRYPTO 2335 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2336 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 2337 decrypted = 1; 2338 } 2339 #endif 2340 2341 /* could use m_devget but net80211 wants contig mgmt frames */ 2342 MGETHDR(m, M_DONTWAIT, MT_DATA); 2343 if (__predict_false(m == NULL)) { 2344 if_statinc(ifp, if_ierrors); 2345 return; 2346 } 2347 if (len > MHLEN) { 2348 MCLGET(m, M_DONTWAIT); 2349 if (__predict_false(!(m->m_flags & M_EXT))) { 2350 if_statinc(ifp, if_ierrors); 2351 m_freem(m); 2352 return; 2353 } 2354 } 2355 /* finalize mbuf */ 2356 m_set_rcvif(m, ifp); 2357 memcpy(mtod(m, void *), wh, len); 2358 m->m_pkthdr.len = m->m_len = len; 2359 2360 ant = run_maxrssi_chain(sc, rxwi); 2361 rssi = rxwi->rssi[ant]; 2362 2363 if (__predict_false(sc->sc_drvbpf != NULL)) { 2364 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2365 2366 tap->wr_flags = 0; 2367 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2368 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2369 tap->wr_antsignal = rssi; 2370 tap->wr_antenna = ant; 2371 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2372 tap->wr_rate = 2; /* in case it can't be found below */ 2373 phy = le16toh(rxwi->phy); 2374 switch (phy & RT2860_PHY_MODE) { 2375 case RT2860_PHY_CCK: 2376 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2377 case 0: tap->wr_rate = 2; break; 2378 case 1: tap->wr_rate = 4; break; 2379 case 2: tap->wr_rate = 11; break; 2380 case 3: tap->wr_rate = 22; break; 2381 } 2382 if (phy & RT2860_PHY_SHPRE) 2383 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2384 break; 2385 case RT2860_PHY_OFDM: 2386 switch (phy & RT2860_PHY_MCS) { 2387 case 0: tap->wr_rate = 12; break; 2388 case 1: tap->wr_rate = 18; break; 2389 case 2: tap->wr_rate = 24; break; 2390 case 3: tap->wr_rate = 36; break; 2391 case 4: tap->wr_rate = 48; break; 2392 case 5: tap->wr_rate = 72; break; 2393 case 6: tap->wr_rate = 96; break; 2394 case 7: tap->wr_rate = 108; break; 2395 } 2396 break; 2397 } 2398 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 2399 } 2400 2401 s = splnet(); 2402 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 2403 #ifdef RUN_HWCRYPTO 2404 if (decrypted) { 2405 uint32_t icflags = ic->ic_flags; 2406 2407 ic->ic_flags &= ~IEEE80211_F_DROPUNENC; /* XXX */ 2408 ieee80211_input(ic, m, ni, rssi, 0); 2409 ic->ic_flags = icflags; 2410 } else 2411 #endif 2412 ieee80211_input(ic, m, ni, rssi, 0); 2413 2414 /* node is no longer needed */ 2415 ieee80211_free_node(ni); 2416 2417 /* 2418 * In HostAP mode, ieee80211_input() will enqueue packets in if_snd 2419 * without calling if_start(). 2420 */ 2421 if (!IFQ_IS_EMPTY(&ifp->if_snd) && !(ifp->if_flags & IFF_OACTIVE)) 2422 run_start(ifp); 2423 2424 splx(s); 2425 } 2426 2427 static void 2428 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2429 { 2430 struct run_rx_data *data = priv; 2431 struct run_softc *sc = data->sc; 2432 uint8_t *buf; 2433 uint32_t dmalen; 2434 int xferlen; 2435 uint16_t rxwisize; 2436 2437 if (__predict_false(sc->sc_flags & RUN_DETACHING)) 2438 return; 2439 2440 rxwisize = sizeof(struct rt2860_rxwi); 2441 if (sc->mac_ver == 0x5592) 2442 rxwisize += sizeof(uint64_t); 2443 else if (sc->mac_ver == 0x3593) 2444 rxwisize += sizeof(uint32_t); 2445 2446 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2447 DPRINTF(("RX status=%s\n", usbd_errstr(status))); 2448 if (status == USBD_STALLED) 2449 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2450 if (status != USBD_CANCELLED) 2451 goto skip; 2452 return; 2453 } 2454 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2455 2456 if (__predict_false(xferlen < (int)(sizeof(uint32_t) + 2457 rxwisize + sizeof(struct rt2870_rxd)))) { 2458 DPRINTF(("xfer too short %d\n", xferlen)); 2459 goto skip; 2460 } 2461 2462 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2463 buf = data->buf; 2464 while (xferlen > 8) { 2465 dmalen = le32toh(*(uint32_t *)buf) & 0xffff; 2466 2467 if (__predict_false((dmalen >= (uint32_t)-8) || dmalen == 0 || 2468 (dmalen & 3) != 0)) { 2469 DPRINTF(("bad DMA length %u (%x)\n", dmalen, dmalen)); 2470 break; 2471 } 2472 if (__predict_false(dmalen + 8 > (uint32_t)xferlen)) { 2473 DPRINTF(("bad DMA length %u > %d\n", 2474 dmalen + 8, xferlen)); 2475 break; 2476 } 2477 run_rx_frame(sc, buf + sizeof(uint32_t), dmalen); 2478 buf += dmalen + 8; 2479 xferlen -= dmalen + 8; 2480 } 2481 2482 skip: /* setup a new transfer */ 2483 usbd_setup_xfer(xfer, data, data->buf, RUN_MAX_RXSZ, 2484 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 2485 status = usbd_transfer(xfer); 2486 if (status != USBD_NORMAL_COMPLETION && 2487 status != USBD_IN_PROGRESS) 2488 device_printf(sc->sc_dev, "requeuing rx failed: %s\n", 2489 usbd_errstr(status)); 2490 } 2491 2492 static void 2493 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2494 { 2495 struct run_tx_data *data = priv; 2496 struct run_softc *sc = data->sc; 2497 struct run_tx_ring *txq = &sc->txq[data->qid]; 2498 struct ifnet *ifp = &sc->sc_if; 2499 int s; 2500 2501 s = splnet(); 2502 txq->queued--; 2503 sc->qfullmsk &= ~(1 << data->qid); 2504 2505 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2506 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2507 return; 2508 2509 DPRINTF(("%s: usb error on tx: %s\n", 2510 device_xname(sc->sc_dev), usbd_errstr(status))); 2511 if (status == USBD_STALLED) 2512 usbd_clear_endpoint_stall_async(txq->pipeh); 2513 if_statinc(ifp, if_oerrors); 2514 splx(s); 2515 return; 2516 } 2517 2518 sc->sc_tx_timer = 0; 2519 if_statinc(ifp, if_opackets); 2520 ifp->if_flags &= ~IFF_OACTIVE; 2521 run_start(ifp); 2522 splx(s); 2523 } 2524 2525 static int 2526 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2527 { 2528 struct ieee80211com *ic = &sc->sc_ic; 2529 struct run_node *rn = (void *)ni; 2530 struct ieee80211_frame *wh; 2531 #ifndef RUN_HWCRYPTO 2532 struct ieee80211_key *k; 2533 #endif 2534 struct run_tx_ring *ring; 2535 struct run_tx_data *data; 2536 struct rt2870_txd *txd; 2537 struct rt2860_txwi *txwi; 2538 uint16_t qos, dur, mcs; 2539 uint16_t txwisize; 2540 uint8_t type, tid, qid; 2541 int hasqos, ridx, ctl_ridx, xferlen; 2542 uint8_t pad; 2543 usbd_status status; 2544 2545 wh = mtod(m, struct ieee80211_frame *); 2546 2547 #ifndef RUN_HWCRYPTO 2548 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 2549 k = ieee80211_crypto_encap(ic, ni, m); 2550 if (k == NULL) { 2551 m_freem(m); 2552 return ENOBUFS; 2553 } 2554 2555 /* packet header may have moved, reset our local pointer */ 2556 wh = mtod(m, struct ieee80211_frame *); 2557 } 2558 #endif 2559 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2560 2561 if ((hasqos = ieee80211_has_qos(wh))) { 2562 qos = ((struct ieee80211_qosframe *)wh)->i_qos[0]; 2563 tid = qos & IEEE80211_QOS_TID; 2564 qid = TID_TO_WME_AC(tid); 2565 } else { 2566 qos = 0; 2567 tid = 0; 2568 qid = WME_AC_BE; 2569 } 2570 ring = &sc->txq[qid]; 2571 data = &ring->data[ring->cur]; 2572 2573 /* pickup a rate index */ 2574 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2575 type != IEEE80211_FC0_TYPE_DATA) { 2576 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2577 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2578 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2579 } else if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 2580 ridx = sc->fixed_ridx; 2581 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2582 } else { 2583 ridx = rn->ridx[ni->ni_txrate]; 2584 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2585 } 2586 2587 /* get MCS code from rate index */ 2588 mcs = rt2860_rates[ridx].mcs; 2589 2590 txwisize = sizeof(struct rt2860_txwi); 2591 if (sc->mac_ver == 0x5592) 2592 txwisize += sizeof(uint32_t); 2593 xferlen = txwisize + m->m_pkthdr.len; 2594 2595 /* roundup to 32-bit alignment */ 2596 xferlen = (xferlen + 3) & ~3; 2597 2598 txd = (struct rt2870_txd *)data->buf; 2599 txd->flags = RT2860_TX_QSEL_EDCA; 2600 txd->len = htole16(xferlen); 2601 2602 /* 2603 * Ether both are true or both are false, the header 2604 * are nicely aligned to 32-bit. So, no L2 padding. 2605 */ 2606 if (IEEE80211_HAS_ADDR4(wh) == IEEE80211_QOS_HAS_SEQ(wh)) 2607 pad = 0; 2608 else 2609 pad = 2; 2610 2611 /* setup TX Wireless Information */ 2612 txwi = (struct rt2860_txwi *)(txd + 1); 2613 txwi->flags = 0; 2614 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2615 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2616 RUN_AID2WCID(ni->ni_associd) : 0xff; 2617 txwi->len = htole16(m->m_pkthdr.len - pad); 2618 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2619 txwi->phy = htole16(RT2860_PHY_CCK); 2620 if (ridx != RT2860_RIDX_CCK1 && 2621 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2622 mcs |= RT2860_PHY_SHPRE; 2623 } else 2624 mcs |= RT2860_PHY_OFDM; 2625 txwi->phy = htole16(mcs); 2626 2627 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2628 2629 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2630 (!hasqos || (qos & IEEE80211_QOS_ACKPOLICY) != 2631 IEEE80211_QOS_ACKPOLICY_NOACK)) { 2632 txwi->xflags |= RT2860_TX_ACK; 2633 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2634 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2635 else 2636 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2637 *(uint16_t *)wh->i_dur = htole16(dur); 2638 } 2639 2640 #ifndef IEEE80211_STA_ONLY 2641 /* ask MAC to insert timestamp into probe responses */ 2642 if ((wh->i_fc[0] & 2643 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 2644 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 2645 /* NOTE: beacons do not pass through tx_data() */ 2646 txwi->flags |= RT2860_TX_TS; 2647 #endif 2648 2649 if (__predict_false(sc->sc_drvbpf != NULL)) { 2650 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2651 2652 tap->wt_flags = 0; 2653 tap->wt_rate = rt2860_rates[ridx].rate; 2654 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2655 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2656 tap->wt_hwqueue = qid; 2657 if (mcs & RT2860_PHY_SHPRE) 2658 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2659 2660 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2661 } 2662 2663 m_copydata(m, 0, m->m_pkthdr.len, ((uint8_t *)txwi) + txwisize); 2664 m_freem(m); 2665 2666 xferlen += sizeof(*txd) + 4; 2667 2668 usbd_setup_xfer(data->xfer, data, data->buf, xferlen, 2669 USBD_FORCE_SHORT_XFER, RUN_TX_TIMEOUT, run_txeof); 2670 status = usbd_transfer(data->xfer); 2671 if (__predict_false(status != USBD_IN_PROGRESS && 2672 status != USBD_NORMAL_COMPLETION)) { 2673 device_printf(sc->sc_dev, "queuing tx failed: %s\n", 2674 usbd_errstr(status)); 2675 return EIO; 2676 } 2677 2678 ieee80211_free_node(ni); 2679 2680 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2681 if (++ring->queued >= RUN_TX_RING_COUNT) 2682 sc->qfullmsk |= 1 << qid; 2683 2684 return 0; 2685 } 2686 2687 static void 2688 run_start(struct ifnet *ifp) 2689 { 2690 struct run_softc *sc = ifp->if_softc; 2691 struct ieee80211com *ic = &sc->sc_ic; 2692 struct ether_header *eh; 2693 struct ieee80211_node *ni; 2694 struct mbuf *m; 2695 2696 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2697 return; 2698 2699 for (;;) { 2700 if (sc->qfullmsk != 0) { 2701 ifp->if_flags |= IFF_OACTIVE; 2702 break; 2703 } 2704 /* send pending management frames first */ 2705 IF_DEQUEUE(&ic->ic_mgtq, m); 2706 if (m != NULL) { 2707 ni = M_GETCTX(m, struct ieee80211_node *); 2708 M_CLEARCTX(m); 2709 goto sendit; 2710 } 2711 if (ic->ic_state != IEEE80211_S_RUN) 2712 break; 2713 2714 /* encapsulate and send data frames */ 2715 IFQ_DEQUEUE(&ifp->if_snd, m); 2716 if (m == NULL) 2717 break; 2718 if (m->m_len < (int)sizeof(*eh) && 2719 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2720 if_statinc(ifp, if_oerrors); 2721 continue; 2722 } 2723 2724 eh = mtod(m, struct ether_header *); 2725 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2726 if (ni == NULL) { 2727 m_freem(m); 2728 if_statinc(ifp, if_oerrors); 2729 continue; 2730 } 2731 2732 bpf_mtap(ifp, m, BPF_D_OUT); 2733 2734 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2735 ieee80211_free_node(ni); 2736 if_statinc(ifp, if_oerrors); 2737 continue; 2738 } 2739 sendit: 2740 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2741 2742 if (run_tx(sc, m, ni) != 0) { 2743 ieee80211_free_node(ni); 2744 if_statinc(ifp, if_oerrors); 2745 continue; 2746 } 2747 2748 sc->sc_tx_timer = 5; 2749 ifp->if_timer = 1; 2750 } 2751 } 2752 2753 static void 2754 run_watchdog(struct ifnet *ifp) 2755 { 2756 struct run_softc *sc = ifp->if_softc; 2757 struct ieee80211com *ic = &sc->sc_ic; 2758 2759 ifp->if_timer = 0; 2760 2761 if (sc->sc_tx_timer > 0) { 2762 if (--sc->sc_tx_timer == 0) { 2763 device_printf(sc->sc_dev, "device timeout\n"); 2764 /* run_init(ifp); XXX needs a process context! */ 2765 if_statinc(ifp, if_oerrors); 2766 return; 2767 } 2768 ifp->if_timer = 1; 2769 } 2770 2771 ieee80211_watchdog(ic); 2772 } 2773 2774 static int 2775 run_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2776 { 2777 struct run_softc *sc = ifp->if_softc; 2778 struct ieee80211com *ic = &sc->sc_ic; 2779 int s, error = 0; 2780 2781 s = splnet(); 2782 2783 switch (cmd) { 2784 case SIOCSIFFLAGS: 2785 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2786 break; 2787 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 2788 case IFF_UP|IFF_RUNNING: 2789 break; 2790 case IFF_UP: 2791 run_init(ifp); 2792 break; 2793 case IFF_RUNNING: 2794 run_stop(ifp, 1); 2795 break; 2796 case 0: 2797 break; 2798 } 2799 break; 2800 2801 case SIOCADDMULTI: 2802 case SIOCDELMULTI: 2803 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2804 /* setup multicast filter, etc */ 2805 error = 0; 2806 } 2807 break; 2808 2809 default: 2810 error = ieee80211_ioctl(ic, cmd, data); 2811 break; 2812 } 2813 2814 if (error == ENETRESET) { 2815 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2816 (IFF_UP | IFF_RUNNING)) { 2817 run_init(ifp); 2818 } 2819 error = 0; 2820 } 2821 2822 splx(s); 2823 2824 return error; 2825 } 2826 2827 static void 2828 run_select_chan_group(struct run_softc *sc, int group) 2829 { 2830 uint32_t tmp; 2831 uint8_t agc; 2832 2833 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2834 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2835 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2836 if (sc->mac_ver < 0x3572) 2837 run_bbp_write(sc, 86, 0x00); 2838 2839 if (sc->mac_ver == 0x3593) { 2840 run_bbp_write(sc, 77, 0x98); 2841 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2842 } 2843 2844 if (group == 0) { 2845 if (sc->ext_2ghz_lna) { 2846 if (sc->mac_ver >= 0x5390) 2847 run_bbp_write(sc, 75, 0x52); 2848 else { 2849 run_bbp_write(sc, 82, 0x62); 2850 run_bbp_write(sc, 75, 0x46); 2851 } 2852 } else { 2853 if (sc->mac_ver == 0x5592) { 2854 run_bbp_write(sc, 79, 0x1c); 2855 run_bbp_write(sc, 80, 0x0e); 2856 run_bbp_write(sc, 81, 0x3a); 2857 run_bbp_write(sc, 82, 0x62); 2858 2859 run_bbp_write(sc, 195, 0x80); 2860 run_bbp_write(sc, 196, 0xe0); 2861 run_bbp_write(sc, 195, 0x81); 2862 run_bbp_write(sc, 196, 0x1f); 2863 run_bbp_write(sc, 195, 0x82); 2864 run_bbp_write(sc, 196, 0x38); 2865 run_bbp_write(sc, 195, 0x83); 2866 run_bbp_write(sc, 196, 0x32); 2867 run_bbp_write(sc, 195, 0x85); 2868 run_bbp_write(sc, 196, 0x28); 2869 run_bbp_write(sc, 195, 0x86); 2870 run_bbp_write(sc, 196, 0x19); 2871 } else if (sc->mac_ver >= 0x5390) { 2872 run_bbp_write(sc, 75, 0x50); 2873 } else { 2874 run_bbp_write(sc, 82, 2875 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2876 run_bbp_write(sc, 75, 0x50); 2877 } 2878 } 2879 } else { 2880 if (sc->mac_ver == 0x5592) { 2881 run_bbp_write(sc, 79, 0x18); 2882 run_bbp_write(sc, 80, 0x08); 2883 run_bbp_write(sc, 81, 0x38); 2884 run_bbp_write(sc, 82, 0x92); 2885 2886 run_bbp_write(sc, 195, 0x80); 2887 run_bbp_write(sc, 196, 0xf0); 2888 run_bbp_write(sc, 195, 0x81); 2889 run_bbp_write(sc, 196, 0x1e); 2890 run_bbp_write(sc, 195, 0x82); 2891 run_bbp_write(sc, 196, 0x28); 2892 run_bbp_write(sc, 195, 0x83); 2893 run_bbp_write(sc, 196, 0x20); 2894 run_bbp_write(sc, 195, 0x85); 2895 run_bbp_write(sc, 196, 0x7f); 2896 run_bbp_write(sc, 195, 0x86); 2897 run_bbp_write(sc, 196, 0x7f); 2898 } else if (sc->mac_ver == 0x3572) 2899 run_bbp_write(sc, 82, 0x94); 2900 else 2901 run_bbp_write(sc, 82, 2902 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2903 if (sc->ext_5ghz_lna) 2904 run_bbp_write(sc, 75, 0x46); 2905 else 2906 run_bbp_write(sc, 75, 0x50); 2907 } 2908 2909 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2910 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2911 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2912 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2913 2914 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2915 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2916 if (sc->mac_ver == 0x3593) 2917 tmp |= RT3593_LNA_PE_G2_EN | RT3593_LNA_PE_A2_EN; 2918 if (sc->nrxchains > 1) 2919 tmp |= RT2860_LNA_PE1_EN; 2920 if (group == 0) { /* 2GHz */ 2921 tmp |= RT2860_PA_PE_G0_EN; 2922 if (sc->ntxchains > 1) 2923 tmp |= RT2860_PA_PE_G1_EN; 2924 } else { /* 5GHz */ 2925 tmp |= RT2860_PA_PE_A0_EN; 2926 if (sc->ntxchains > 1) 2927 tmp |= RT2860_PA_PE_A1_EN; 2928 if (sc->mac_ver == 0x3593) { 2929 if (sc->ntxchains > 2) 2930 tmp |= RT3593_PA_PE_G2_EN; 2931 } 2932 } 2933 if (sc->mac_ver == 0x3572) { 2934 run_rt3070_rf_write(sc, 8, 0x00); 2935 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2936 run_rt3070_rf_write(sc, 8, 0x80); 2937 } else 2938 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2939 2940 if (sc->mac_ver == 0x5592) { 2941 run_bbp_write(sc, 195, 0x8d); 2942 run_bbp_write(sc, 196, 0x1a); 2943 } 2944 2945 if (sc->mac_ver == 0x3593) { 2946 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2947 tmp &= ~0x01010000; 2948 if (group == 0) 2949 tmp |= 0x00010000; 2950 tmp = (tmp & ~0x00009090) | 0x00000090; 2951 run_write(sc, RT2860_GPIO_CTRL, tmp); 2952 } 2953 2954 /* set initial AGC value */ 2955 if (group == 0) { /* 2GHz band */ 2956 if (sc->mac_ver >= 0x3070) 2957 agc = 0x1c + sc->lna[0] * 2; 2958 else 2959 agc = 0x2e + sc->lna[0]; 2960 } else { /* 5GHz band */ 2961 if (sc->mac_ver == 0x3572) 2962 agc = 0x22 + (sc->lna[group] * 5) / 3; 2963 else 2964 agc = 0x32 + (sc->lna[group] * 5) / 3; 2965 } 2966 run_set_agc(sc, agc); 2967 } 2968 2969 static void 2970 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2971 { 2972 const struct rfprog *rfprog = rt2860_rf2850; 2973 uint32_t r2, r3, r4; 2974 int8_t txpow1, txpow2; 2975 int i; 2976 2977 /* find the settings for this channel (we know it exists) */ 2978 for (i = 0; rfprog[i].chan != chan; i++); 2979 2980 r2 = rfprog[i].r2; 2981 if (sc->ntxchains == 1) 2982 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2983 if (sc->nrxchains == 1) 2984 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2985 else if (sc->nrxchains == 2) 2986 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2987 2988 /* use Tx power values from EEPROM */ 2989 txpow1 = sc->txpow1[i]; 2990 txpow2 = sc->txpow2[i]; 2991 if (chan > 14) { 2992 if (txpow1 >= 0) 2993 txpow1 = txpow1 << 1 | 1; 2994 else 2995 txpow1 = (7 + txpow1) << 1; 2996 if (txpow2 >= 0) 2997 txpow2 = txpow2 << 1 | 1; 2998 else 2999 txpow2 = (7 + txpow2) << 1; 3000 } 3001 r3 = rfprog[i].r3 | txpow1 << 7; 3002 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 3003 3004 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 3005 run_rt2870_rf_write(sc, RT2860_RF2, r2); 3006 run_rt2870_rf_write(sc, RT2860_RF3, r3); 3007 run_rt2870_rf_write(sc, RT2860_RF4, r4); 3008 3009 usbd_delay_ms(sc->sc_udev, 10); 3010 3011 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 3012 run_rt2870_rf_write(sc, RT2860_RF2, r2); 3013 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 3014 run_rt2870_rf_write(sc, RT2860_RF4, r4); 3015 3016 usbd_delay_ms(sc->sc_udev, 10); 3017 3018 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 3019 run_rt2870_rf_write(sc, RT2860_RF2, r2); 3020 run_rt2870_rf_write(sc, RT2860_RF3, r3); 3021 run_rt2870_rf_write(sc, RT2860_RF4, r4); 3022 } 3023 3024 static void 3025 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 3026 { 3027 int8_t txpow1, txpow2; 3028 uint8_t rf; 3029 int i; 3030 3031 KASSERT(chan >= 1 && chan <= 14); /* RT3070 is 2GHz only */ 3032 3033 /* find the settings for this channel (we know it exists) */ 3034 for (i = 0; rt2860_rf2850[i].chan != chan; i++) 3035 continue; 3036 3037 /* use Tx power values from EEPROM */ 3038 txpow1 = sc->txpow1[i]; 3039 txpow2 = sc->txpow2[i]; 3040 3041 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3042 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3043 run_rt3070_rf_read(sc, 6, &rf); 3044 rf = (rf & ~0x03) | rt3070_freqs[i].r; 3045 run_rt3070_rf_write(sc, 6, rf); 3046 3047 /* set Tx0 power */ 3048 run_rt3070_rf_read(sc, 12, &rf); 3049 rf = (rf & ~0x1f) | txpow1; 3050 run_rt3070_rf_write(sc, 12, rf); 3051 3052 /* set Tx1 power */ 3053 run_rt3070_rf_read(sc, 13, &rf); 3054 rf = (rf & ~0x1f) | txpow2; 3055 run_rt3070_rf_write(sc, 13, rf); 3056 3057 run_rt3070_rf_read(sc, 1, &rf); 3058 rf &= ~0xfc; 3059 if (sc->ntxchains == 1) 3060 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3061 else if (sc->ntxchains == 2) 3062 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3063 if (sc->nrxchains == 1) 3064 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3065 else if (sc->nrxchains == 2) 3066 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3067 run_rt3070_rf_write(sc, 1, rf); 3068 3069 /* set RF offset */ 3070 run_rt3070_rf_read(sc, 23, &rf); 3071 rf = (rf & ~0x7f) | sc->freq; 3072 run_rt3070_rf_write(sc, 23, rf); 3073 3074 /* program RF filter */ 3075 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 3076 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3077 run_rt3070_rf_write(sc, 24, rf); 3078 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 3079 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3080 run_rt3070_rf_write(sc, 31, rf); 3081 3082 /* enable RF tuning */ 3083 run_rt3070_rf_read(sc, 7, &rf); 3084 run_rt3070_rf_write(sc, 7, rf | 0x01); 3085 } 3086 3087 static void 3088 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3089 { 3090 int8_t txpow1, txpow2; 3091 uint32_t tmp; 3092 uint8_t rf; 3093 int i; 3094 3095 /* find the settings for this channel (we know it exists) */ 3096 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3097 3098 /* use Tx power values from EEPROM */ 3099 txpow1 = sc->txpow1[i]; 3100 txpow2 = sc->txpow2[i]; 3101 3102 if (chan <= 14) { 3103 run_bbp_write(sc, 25, sc->bbp25); 3104 run_bbp_write(sc, 26, sc->bbp26); 3105 } else { 3106 /* enable IQ phase correction */ 3107 run_bbp_write(sc, 25, 0x09); 3108 run_bbp_write(sc, 26, 0xff); 3109 } 3110 3111 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3112 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3113 run_rt3070_rf_read(sc, 6, &rf); 3114 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3115 rf |= (chan <= 14) ? 0x08 : 0x04; 3116 run_rt3070_rf_write(sc, 6, rf); 3117 3118 /* set PLL mode */ 3119 run_rt3070_rf_read(sc, 5, &rf); 3120 rf &= ~(0x08 | 0x04); 3121 rf |= (chan <= 14) ? 0x04 : 0x08; 3122 run_rt3070_rf_write(sc, 5, rf); 3123 3124 /* set Tx power for chain 0 */ 3125 if (chan <= 14) 3126 rf = 0x60 | txpow1; 3127 else 3128 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3129 run_rt3070_rf_write(sc, 12, rf); 3130 3131 /* set Tx power for chain 1 */ 3132 if (chan <= 14) 3133 rf = 0x60 | txpow2; 3134 else 3135 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3136 run_rt3070_rf_write(sc, 13, rf); 3137 3138 /* set Tx/Rx streams */ 3139 run_rt3070_rf_read(sc, 1, &rf); 3140 rf &= ~0xfc; 3141 if (sc->ntxchains == 1) 3142 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3143 else if (sc->ntxchains == 2) 3144 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3145 if (sc->nrxchains == 1) 3146 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3147 else if (sc->nrxchains == 2) 3148 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3149 run_rt3070_rf_write(sc, 1, rf); 3150 3151 /* set RF offset */ 3152 run_rt3070_rf_read(sc, 23, &rf); 3153 rf = (rf & ~0x7f) | sc->freq; 3154 run_rt3070_rf_write(sc, 23, rf); 3155 3156 /* program RF filter */ 3157 rf = sc->rf24_20mhz; 3158 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3159 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3160 3161 /* enable RF tuning */ 3162 run_rt3070_rf_read(sc, 7, &rf); 3163 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3164 run_rt3070_rf_write(sc, 7, rf); 3165 3166 /* TSSI */ 3167 rf = (chan <= 14) ? 0xc3 : 0xc0; 3168 run_rt3070_rf_write(sc, 9, rf); 3169 3170 /* set loop filter 1 */ 3171 run_rt3070_rf_write(sc, 10, 0xf1); 3172 /* set loop filter 2 */ 3173 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3174 3175 /* set tx_mx2_ic */ 3176 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3177 /* set tx_mx1_ic */ 3178 if (chan <= 14) 3179 rf = 0x48 | sc->txmixgain_2ghz; 3180 else 3181 rf = 0x78 | sc->txmixgain_5ghz; 3182 run_rt3070_rf_write(sc, 16, rf); 3183 3184 /* set tx_lo1 */ 3185 run_rt3070_rf_write(sc, 17, 0x23); 3186 /* set tx_lo2 */ 3187 if (chan <= 14) 3188 rf = 0x93; 3189 else if (chan <= 64) 3190 rf = 0xb7; 3191 else if (chan <= 128) 3192 rf = 0x74; 3193 else 3194 rf = 0x72; 3195 run_rt3070_rf_write(sc, 19, rf); 3196 3197 /* set rx_lo1 */ 3198 if (chan <= 14) 3199 rf = 0xb3; 3200 else if (chan <= 64) 3201 rf = 0xf6; 3202 else if (chan <= 128) 3203 rf = 0xf4; 3204 else 3205 rf = 0xf3; 3206 run_rt3070_rf_write(sc, 20, rf); 3207 3208 /* set pfd_delay */ 3209 if (chan <= 14) 3210 rf = 0x15; 3211 else if (chan <= 64) 3212 rf = 0x3d; 3213 else 3214 rf = 0x01; 3215 run_rt3070_rf_write(sc, 25, rf); 3216 3217 /* set rx_lo2 */ 3218 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3219 /* set ldo_rf_vc */ 3220 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3221 /* set drv_cc */ 3222 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3223 3224 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3225 tmp &= ~0x8080; 3226 if (chan <= 14) 3227 tmp |= 0x80; 3228 run_write(sc, RT2860_GPIO_CTRL, tmp); 3229 3230 /* enable RF tuning */ 3231 run_rt3070_rf_read(sc, 7, &rf); 3232 run_rt3070_rf_write(sc, 7, rf | 0x01); 3233 3234 usbd_delay_ms(sc->sc_udev, 2); 3235 } 3236 3237 static void 3238 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3239 { 3240 int8_t txpow1, txpow2, txpow3; 3241 uint8_t h20mhz, rf; 3242 int i; 3243 3244 /* find the settings for this channel (we know it exists) */ 3245 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3246 3247 /* use Tx power values from EEPROM */ 3248 txpow1 = sc->txpow1[i]; 3249 txpow2 = sc->txpow2[i]; 3250 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3251 3252 if (chan <= 14) { 3253 run_bbp_write(sc, 25, sc->bbp25); 3254 run_bbp_write(sc, 26, sc->bbp26); 3255 } else { 3256 /* Enable IQ phase correction. */ 3257 run_bbp_write(sc, 25, 0x09); 3258 run_bbp_write(sc, 26, 0xff); 3259 } 3260 3261 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3262 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3263 run_rt3070_rf_read(sc, 11, &rf); 3264 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3265 run_rt3070_rf_write(sc, 11, rf); 3266 3267 /* Set pll_idoh. */ 3268 run_rt3070_rf_read(sc, 11, &rf); 3269 rf &= ~0x4c; 3270 rf |= (chan <= 14) ? 0x44 : 0x48; 3271 run_rt3070_rf_write(sc, 11, rf); 3272 3273 if (chan <= 14) 3274 rf = txpow1 & 0x1f; 3275 else 3276 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3277 run_rt3070_rf_write(sc, 53, rf); 3278 3279 if (chan <= 14) 3280 rf = txpow2 & 0x1f; 3281 else 3282 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3283 run_rt3070_rf_write(sc, 55, rf); 3284 3285 if (chan <= 14) 3286 rf = txpow3 & 0x1f; 3287 else 3288 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3289 run_rt3070_rf_write(sc, 54, rf); 3290 3291 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3292 if (sc->ntxchains == 3) 3293 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3294 else 3295 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3296 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3297 run_rt3070_rf_write(sc, 1, rf); 3298 3299 run_adjust_freq_offset(sc); 3300 3301 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3302 3303 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3304 run_rt3070_rf_read(sc, 30, &rf); 3305 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3306 run_rt3070_rf_write(sc, 30, rf); 3307 3308 run_rt3070_rf_read(sc, 36, &rf); 3309 if (chan <= 14) 3310 rf |= 0x80; 3311 else 3312 rf &= ~0x80; 3313 run_rt3070_rf_write(sc, 36, rf); 3314 3315 /* Set vcolo_bs. */ 3316 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3317 /* Set pfd_delay. */ 3318 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3319 3320 /* Set vco bias current control. */ 3321 run_rt3070_rf_read(sc, 6, &rf); 3322 rf &= ~0xc0; 3323 if (chan <= 14) 3324 rf |= 0x40; 3325 else if (chan <= 128) 3326 rf |= 0x80; 3327 else 3328 rf |= 0x40; 3329 run_rt3070_rf_write(sc, 6, rf); 3330 3331 run_rt3070_rf_read(sc, 30, &rf); 3332 rf = (rf & ~0x18) | 0x10; 3333 run_rt3070_rf_write(sc, 30, rf); 3334 3335 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3336 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3337 3338 run_rt3070_rf_read(sc, 51, &rf); 3339 rf = (rf & ~0x03) | 0x01; 3340 run_rt3070_rf_write(sc, 51, rf); 3341 /* Set tx_mx1_cc. */ 3342 run_rt3070_rf_read(sc, 51, &rf); 3343 rf &= ~0x1c; 3344 rf |= (chan <= 14) ? 0x14 : 0x10; 3345 run_rt3070_rf_write(sc, 51, rf); 3346 /* Set tx_mx1_ic. */ 3347 run_rt3070_rf_read(sc, 51, &rf); 3348 rf &= ~0xe0; 3349 rf |= (chan <= 14) ? 0x60 : 0x40; 3350 run_rt3070_rf_write(sc, 51, rf); 3351 /* Set tx_lo1_ic. */ 3352 run_rt3070_rf_read(sc, 49, &rf); 3353 rf &= ~0x1c; 3354 rf |= (chan <= 14) ? 0x0c : 0x08; 3355 run_rt3070_rf_write(sc, 49, rf); 3356 /* Set tx_lo1_en. */ 3357 run_rt3070_rf_read(sc, 50, &rf); 3358 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3359 /* Set drv_cc. */ 3360 run_rt3070_rf_read(sc, 57, &rf); 3361 rf &= ~0xfc; 3362 rf |= (chan <= 14) ? 0x6c : 0x3c; 3363 run_rt3070_rf_write(sc, 57, rf); 3364 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3365 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3366 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3367 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3368 /* Enable VCO calibration. */ 3369 run_rt3070_rf_read(sc, 3, &rf); 3370 rf &= ~RT5390_VCOCAL; 3371 rf |= (chan <= 14) ? RT5390_VCOCAL : 0xbe; 3372 run_rt3070_rf_write(sc, 3, rf); 3373 3374 if (chan <= 14) 3375 rf = 0x23; 3376 else if (chan <= 64) 3377 rf = 0x36; 3378 else if (chan <= 128) 3379 rf = 0x32; 3380 else 3381 rf = 0x30; 3382 run_rt3070_rf_write(sc, 39, rf); 3383 if (chan <= 14) 3384 rf = 0xbb; 3385 else if (chan <= 64) 3386 rf = 0xeb; 3387 else if (chan <= 128) 3388 rf = 0xb3; 3389 else 3390 rf = 0x9b; 3391 run_rt3070_rf_write(sc, 45, rf); 3392 3393 /* Set FEQ/AEQ control. */ 3394 run_bbp_write(sc, 105, 0x34); 3395 } 3396 3397 static void 3398 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3399 { 3400 int8_t txpow1, txpow2; 3401 uint8_t rf; 3402 int i; 3403 3404 /* find the settings for this channel (we know it exists) */ 3405 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3406 3407 /* use Tx power values from EEPROM */ 3408 txpow1 = sc->txpow1[i]; 3409 txpow2 = sc->txpow2[i]; 3410 3411 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3412 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3413 run_rt3070_rf_read(sc, 11, &rf); 3414 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3415 run_rt3070_rf_write(sc, 11, rf); 3416 3417 run_rt3070_rf_read(sc, 49, &rf); 3418 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3419 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3420 if ((rf & 0x3f) > 0x27) 3421 rf = (rf & ~0x3f) | 0x27; 3422 run_rt3070_rf_write(sc, 49, rf); 3423 3424 if (sc->mac_ver == 0x5392) { 3425 run_rt3070_rf_read(sc, 50, &rf); 3426 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3427 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3428 if ((rf & 0x3f) > 0x27) 3429 rf = (rf & ~0x3f) | 0x27; 3430 run_rt3070_rf_write(sc, 50, rf); 3431 } 3432 3433 run_rt3070_rf_read(sc, 1, &rf); 3434 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3435 if (sc->mac_ver == 0x5392) 3436 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3437 run_rt3070_rf_write(sc, 1, rf); 3438 3439 if (sc->mac_ver != 0x5392) { 3440 run_rt3070_rf_read(sc, 2, &rf); 3441 rf |= 0x80; 3442 run_rt3070_rf_write(sc, 2, rf); 3443 usbd_delay_ms(sc->sc_udev, 10); 3444 rf &= 0x7f; 3445 run_rt3070_rf_write(sc, 2, rf); 3446 } 3447 3448 run_adjust_freq_offset(sc); 3449 3450 if (sc->mac_ver == 0x5392) { 3451 /* Fix for RT5392C. */ 3452 if (sc->mac_rev >= 0x0223) { 3453 if (chan <= 4) 3454 rf = 0x0f; 3455 else if (chan >= 5 && chan <= 7) 3456 rf = 0x0e; 3457 else 3458 rf = 0x0d; 3459 run_rt3070_rf_write(sc, 23, rf); 3460 3461 if (chan <= 4) 3462 rf = 0x0c; 3463 else if (chan == 5) 3464 rf = 0x0b; 3465 else if (chan >= 6 && chan <= 7) 3466 rf = 0x0a; 3467 else if (chan >= 8 && chan <= 10) 3468 rf = 0x09; 3469 else 3470 rf = 0x08; 3471 run_rt3070_rf_write(sc, 59, rf); 3472 } else { 3473 if (chan <= 11) 3474 rf = 0x0f; 3475 else 3476 rf = 0x0b; 3477 run_rt3070_rf_write(sc, 59, rf); 3478 } 3479 } else { 3480 /* Fix for RT5390F. */ 3481 if (sc->mac_rev >= 0x0502) { 3482 if (chan <= 11) 3483 rf = 0x43; 3484 else 3485 rf = 0x23; 3486 run_rt3070_rf_write(sc, 55, rf); 3487 3488 if (chan <= 11) 3489 rf = 0x0f; 3490 else if (chan == 12) 3491 rf = 0x0d; 3492 else 3493 rf = 0x0b; 3494 run_rt3070_rf_write(sc, 59, rf); 3495 } else { 3496 run_rt3070_rf_write(sc, 55, 0x44); 3497 run_rt3070_rf_write(sc, 59, 0x8f); 3498 } 3499 } 3500 3501 /* Enable VCO calibration. */ 3502 run_rt3070_rf_read(sc, 3, &rf); 3503 rf |= RT5390_VCOCAL; 3504 run_rt3070_rf_write(sc, 3, rf); 3505 } 3506 3507 static void 3508 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3509 { 3510 const struct rt5592_freqs *freqs; 3511 uint32_t tmp; 3512 uint8_t reg, rf, txpow_bound; 3513 int8_t txpow1, txpow2; 3514 int i; 3515 3516 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3517 freqs = (tmp & RT5592_SEL_XTAL) ? 3518 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3519 3520 /* find the settings for this channel (we know it exists) */ 3521 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3522 3523 /* use Tx power values from EEPROM */ 3524 txpow1 = sc->txpow1[i]; 3525 txpow2 = sc->txpow2[i]; 3526 3527 run_read(sc, RT3070_LDO_CFG0, &tmp); 3528 tmp &= ~0x1c000000; 3529 if (chan > 14) 3530 tmp |= 0x14000000; 3531 run_write(sc, RT3070_LDO_CFG0, tmp); 3532 3533 /* N setting. */ 3534 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3535 run_rt3070_rf_read(sc, 9, &rf); 3536 rf &= ~(1 << 4); 3537 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3538 run_rt3070_rf_write(sc, 9, rf); 3539 3540 /* K setting. */ 3541 run_rt3070_rf_read(sc, 9, &rf); 3542 rf &= ~0x0f; 3543 rf |= (freqs->k & 0x0f); 3544 run_rt3070_rf_write(sc, 9, rf); 3545 3546 /* Mode setting. */ 3547 run_rt3070_rf_read(sc, 11, &rf); 3548 rf &= ~0x0c; 3549 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3550 run_rt3070_rf_write(sc, 11, rf); 3551 run_rt3070_rf_read(sc, 9, &rf); 3552 rf &= ~(1 << 7); 3553 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3554 run_rt3070_rf_write(sc, 9, rf); 3555 3556 /* R setting. */ 3557 run_rt3070_rf_read(sc, 11, &rf); 3558 rf &= ~0x03; 3559 rf |= (freqs->r - 0x1); 3560 run_rt3070_rf_write(sc, 11, rf); 3561 3562 if (chan <= 14) { 3563 /* Initialize RF registers for 2GHZ. */ 3564 for (i = 0; i < (int)__arraycount(rt5592_2ghz_def_rf); i++) { 3565 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3566 rt5592_2ghz_def_rf[i].val); 3567 } 3568 3569 rf = (chan <= 10) ? 0x07 : 0x06; 3570 run_rt3070_rf_write(sc, 23, rf); 3571 run_rt3070_rf_write(sc, 59, rf); 3572 3573 run_rt3070_rf_write(sc, 55, 0x43); 3574 3575 /* 3576 * RF R49/R50 Tx power ALC code. 3577 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3578 */ 3579 reg = 2; 3580 txpow_bound = 0x27; 3581 } else { 3582 /* Initialize RF registers for 5GHZ. */ 3583 for (i = 0; i < (int)__arraycount(rt5592_5ghz_def_rf); i++) { 3584 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3585 rt5592_5ghz_def_rf[i].val); 3586 } 3587 for (i = 0; i < (int)__arraycount(rt5592_chan_5ghz); i++) { 3588 if (chan >= rt5592_chan_5ghz[i].firstchan && 3589 chan <= rt5592_chan_5ghz[i].lastchan) { 3590 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3591 rt5592_chan_5ghz[i].val); 3592 } 3593 } 3594 3595 /* 3596 * RF R49/R50 Tx power ALC code. 3597 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3598 */ 3599 reg = 3; 3600 txpow_bound = 0x2b; 3601 } 3602 3603 /* RF R49 ch0 Tx power ALC code. */ 3604 run_rt3070_rf_read(sc, 49, &rf); 3605 rf &= ~0xc0; 3606 rf |= (reg << 6); 3607 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3608 if ((rf & 0x3f) > txpow_bound) 3609 rf = (rf & ~0x3f) | txpow_bound; 3610 run_rt3070_rf_write(sc, 49, rf); 3611 3612 /* RF R50 ch1 Tx power ALC code. */ 3613 run_rt3070_rf_read(sc, 50, &rf); 3614 rf &= ~(1 << 7 | 1 << 6); 3615 rf |= (reg << 6); 3616 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3617 if ((rf & 0x3f) > txpow_bound) 3618 rf = (rf & ~0x3f) | txpow_bound; 3619 run_rt3070_rf_write(sc, 50, rf); 3620 3621 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3622 run_rt3070_rf_read(sc, 1, &rf); 3623 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3624 if (sc->ntxchains > 1) 3625 rf |= RT3070_TX1_PD; 3626 if (sc->nrxchains > 1) 3627 rf |= RT3070_RX1_PD; 3628 run_rt3070_rf_write(sc, 1, rf); 3629 3630 run_rt3070_rf_write(sc, 6, 0xe4); 3631 3632 run_rt3070_rf_write(sc, 30, 0x10); 3633 run_rt3070_rf_write(sc, 31, 0x80); 3634 run_rt3070_rf_write(sc, 32, 0x80); 3635 3636 run_adjust_freq_offset(sc); 3637 3638 /* Enable VCO calibration. */ 3639 run_rt3070_rf_read(sc, 3, &rf); 3640 rf |= RT5390_VCOCAL; 3641 run_rt3070_rf_write(sc, 3, rf); 3642 } 3643 3644 static void 3645 run_iq_calib(struct run_softc *sc, u_int chan) 3646 { 3647 uint16_t val; 3648 3649 /* Tx0 IQ gain. */ 3650 run_bbp_write(sc, 158, 0x2c); 3651 if (chan <= 14) 3652 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val, 1); 3653 else if (chan <= 64) { 3654 run_efuse_read(sc, 3655 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, 3656 &val, 1); 3657 } else if (chan <= 138) { 3658 run_efuse_read(sc, 3659 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, 3660 &val, 1); 3661 } else if (chan <= 165) { 3662 run_efuse_read(sc, 3663 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 3664 &val, 1); 3665 } else 3666 val = 0; 3667 run_bbp_write(sc, 159, val); 3668 3669 /* Tx0 IQ phase. */ 3670 run_bbp_write(sc, 158, 0x2d); 3671 if (chan <= 14) { 3672 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, 3673 &val, 1); 3674 } else if (chan <= 64) { 3675 run_efuse_read(sc, 3676 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, 3677 &val, 1); 3678 } else if (chan <= 138) { 3679 run_efuse_read(sc, 3680 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, 3681 &val, 1); 3682 } else if (chan <= 165) { 3683 run_efuse_read(sc, 3684 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, 3685 &val, 1); 3686 } else 3687 val = 0; 3688 run_bbp_write(sc, 159, val); 3689 3690 /* Tx1 IQ gain. */ 3691 run_bbp_write(sc, 158, 0x4a); 3692 if (chan <= 14) { 3693 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, 3694 &val, 1); 3695 } else if (chan <= 64) { 3696 run_efuse_read(sc, 3697 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, 3698 &val, 1); 3699 } else if (chan <= 138) { 3700 run_efuse_read(sc, 3701 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, 3702 &val, 1); 3703 } else if (chan <= 165) { 3704 run_efuse_read(sc, 3705 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, 3706 &val, 1); 3707 } else 3708 val = 0; 3709 run_bbp_write(sc, 159, val); 3710 3711 /* Tx1 IQ phase. */ 3712 run_bbp_write(sc, 158, 0x4b); 3713 if (chan <= 14) { 3714 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, 3715 &val, 1); 3716 } else if (chan <= 64) { 3717 run_efuse_read(sc, 3718 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, 3719 &val, 1); 3720 } else if (chan <= 138) { 3721 run_efuse_read(sc, 3722 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, 3723 &val, 1); 3724 } else if (chan <= 165) { 3725 run_efuse_read(sc, 3726 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, 3727 &val, 1); 3728 } else 3729 val = 0; 3730 run_bbp_write(sc, 159, val); 3731 3732 /* RF IQ compensation control. */ 3733 run_bbp_write(sc, 158, 0x04); 3734 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, 3735 &val, 1); 3736 run_bbp_write(sc, 159, val); 3737 3738 /* RF IQ imbalance compensation control. */ 3739 run_bbp_write(sc, 158, 0x03); 3740 run_efuse_read(sc, 3741 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val, 1); 3742 run_bbp_write(sc, 159, val); 3743 } 3744 3745 static void 3746 run_set_agc(struct run_softc *sc, uint8_t agc) 3747 { 3748 uint8_t bbp; 3749 3750 if (sc->mac_ver == 0x3572) { 3751 run_bbp_read(sc, 27, &bbp); 3752 bbp &= ~(0x3 << 5); 3753 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3754 run_bbp_write(sc, 66, agc); 3755 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3756 run_bbp_write(sc, 66, agc); 3757 } else 3758 run_bbp_write(sc, 66, agc); 3759 } 3760 3761 static void 3762 run_set_rx_antenna(struct run_softc *sc, int aux) 3763 { 3764 uint32_t tmp; 3765 uint8_t bbp152; 3766 3767 if (aux) { 3768 if (sc->rf_rev == RT5390_RF_5370) { 3769 run_bbp_read(sc, 152, &bbp152); 3770 bbp152 &= ~0x80; 3771 run_bbp_write(sc, 152, bbp152); 3772 } else { 3773 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3774 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3775 tmp &= ~0x0808; 3776 tmp |= 0x08; 3777 run_write(sc, RT2860_GPIO_CTRL, tmp); 3778 } 3779 } else { 3780 if (sc->rf_rev == RT5390_RF_5370) { 3781 run_bbp_read(sc, 152, &bbp152); 3782 bbp152 |= 0x80; 3783 run_bbp_write(sc, 152, bbp152); 3784 } else { 3785 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, !aux); 3786 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3787 tmp &= ~0x0808; 3788 run_write(sc, RT2860_GPIO_CTRL, tmp); 3789 } 3790 } 3791 } 3792 3793 static int 3794 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3795 { 3796 struct ieee80211com *ic = &sc->sc_ic; 3797 u_int chan, group; 3798 3799 chan = ieee80211_chan2ieee(ic, c); 3800 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3801 return EINVAL; 3802 3803 if (sc->mac_ver == 0x5592) 3804 run_rt5592_set_chan(sc, chan); 3805 else if (sc->mac_ver >= 0x5390) 3806 run_rt5390_set_chan(sc, chan); 3807 else if (sc->mac_ver == 0x3593) 3808 run_rt3593_set_chan(sc, chan); 3809 else if (sc->mac_ver == 0x3572) 3810 run_rt3572_set_chan(sc, chan); 3811 else if (sc->mac_ver >= 0x3070) 3812 run_rt3070_set_chan(sc, chan); 3813 else 3814 run_rt2870_set_chan(sc, chan); 3815 3816 /* determine channel group */ 3817 if (chan <= 14) 3818 group = 0; 3819 else if (chan <= 64) 3820 group = 1; 3821 else if (chan <= 128) 3822 group = 2; 3823 else 3824 group = 3; 3825 3826 /* XXX necessary only when group has changed! */ 3827 run_select_chan_group(sc, group); 3828 3829 usbd_delay_ms(sc->sc_udev, 10); 3830 3831 /* Perform IQ calibration. */ 3832 if (sc->mac_ver >= 0x5392) 3833 run_iq_calib(sc, chan); 3834 3835 return 0; 3836 } 3837 3838 static void 3839 run_updateprot(struct run_softc *sc) 3840 { 3841 struct ieee80211com *ic = &sc->sc_ic; 3842 uint32_t tmp; 3843 3844 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3845 /* setup protection frame rate (MCS code) */ 3846 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ? 3847 rt2860_rates[RT2860_RIDX_OFDM6].mcs | RT2860_PHY_OFDM : 3848 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3849 3850 /* CCK frames don't require protection */ 3851 run_write(sc, RT2860_CCK_PROT_CFG, tmp); 3852 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3853 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3854 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3855 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3856 tmp |= RT2860_PROT_CTRL_CTS; 3857 } 3858 run_write(sc, RT2860_OFDM_PROT_CFG, tmp); 3859 } 3860 3861 static void 3862 run_enable_tsf_sync(struct run_softc *sc) 3863 { 3864 struct ieee80211com *ic = &sc->sc_ic; 3865 uint32_t tmp; 3866 3867 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3868 tmp &= ~0x1fffff; 3869 tmp |= ic->ic_bss->ni_intval * 16; 3870 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3871 if (ic->ic_opmode == IEEE80211_M_STA) { 3872 /* 3873 * Local TSF is always updated with remote TSF on beacon 3874 * reception. 3875 */ 3876 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3877 } 3878 #ifndef IEEE80211_STA_ONLY 3879 else if (ic->ic_opmode == IEEE80211_M_IBSS) { 3880 tmp |= RT2860_BCN_TX_EN; 3881 /* 3882 * Local TSF is updated with remote TSF on beacon reception 3883 * only if the remote TSF is greater than local TSF. 3884 */ 3885 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 3886 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3887 tmp |= RT2860_BCN_TX_EN; 3888 /* SYNC with nobody */ 3889 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 3890 } 3891 #endif 3892 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3893 } 3894 3895 static void 3896 run_enable_mrr(struct run_softc *sc) 3897 { 3898 #define CCK(mcs) (mcs) 3899 #define OFDM(mcs) (1 << 3 | (mcs)) 3900 run_write(sc, RT2860_LG_FBK_CFG0, 3901 OFDM(6) << 28 | /* 54->48 */ 3902 OFDM(5) << 24 | /* 48->36 */ 3903 OFDM(4) << 20 | /* 36->24 */ 3904 OFDM(3) << 16 | /* 24->18 */ 3905 OFDM(2) << 12 | /* 18->12 */ 3906 OFDM(1) << 8 | /* 12-> 9 */ 3907 OFDM(0) << 4 | /* 9-> 6 */ 3908 OFDM(0)); /* 6-> 6 */ 3909 3910 run_write(sc, RT2860_LG_FBK_CFG1, 3911 CCK(2) << 12 | /* 11->5.5 */ 3912 CCK(1) << 8 | /* 5.5-> 2 */ 3913 CCK(0) << 4 | /* 2-> 1 */ 3914 CCK(0)); /* 1-> 1 */ 3915 #undef OFDM 3916 #undef CCK 3917 } 3918 3919 static void 3920 run_set_txpreamble(struct run_softc *sc) 3921 { 3922 uint32_t tmp; 3923 3924 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3925 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3926 tmp |= RT2860_CCK_SHORT_EN; 3927 else 3928 tmp &= ~RT2860_CCK_SHORT_EN; 3929 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3930 } 3931 3932 static void 3933 run_set_basicrates(struct run_softc *sc) 3934 { 3935 struct ieee80211com *ic = &sc->sc_ic; 3936 3937 /* set basic rates mask */ 3938 if (ic->ic_curmode == IEEE80211_MODE_11B) 3939 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3940 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3941 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3942 else /* 11g */ 3943 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3944 } 3945 3946 static void 3947 run_set_leds(struct run_softc *sc, uint16_t which) 3948 { 3949 3950 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3951 which | (sc->leds & 0x7f)); 3952 } 3953 3954 static void 3955 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3956 { 3957 3958 run_write(sc, RT2860_MAC_BSSID_DW0, 3959 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3960 run_write(sc, RT2860_MAC_BSSID_DW1, 3961 bssid[4] | bssid[5] << 8); 3962 } 3963 3964 static void 3965 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3966 { 3967 3968 run_write(sc, RT2860_MAC_ADDR_DW0, 3969 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3970 run_write(sc, RT2860_MAC_ADDR_DW1, 3971 addr[4] | addr[5] << 8 | 0xff << 16); 3972 } 3973 3974 static void 3975 run_updateslot(struct ifnet *ifp) 3976 { 3977 3978 /* do it in a process context */ 3979 run_do_async(ifp->if_softc, run_updateslot_cb, NULL, 0); 3980 } 3981 3982 /* ARGSUSED */ 3983 static void 3984 run_updateslot_cb(struct run_softc *sc, void *arg) 3985 { 3986 uint32_t tmp; 3987 3988 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3989 tmp &= ~0xff; 3990 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3991 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3992 } 3993 3994 static int8_t 3995 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3996 { 3997 struct ieee80211com *ic = &sc->sc_ic; 3998 struct ieee80211_channel *c = ic->ic_curchan; 3999 int delta; 4000 4001 if (IEEE80211_IS_CHAN_5GHZ(c)) { 4002 u_int chan = ieee80211_chan2ieee(ic, c); 4003 delta = sc->rssi_5ghz[rxchain]; 4004 4005 /* determine channel group */ 4006 if (chan <= 64) 4007 delta -= sc->lna[1]; 4008 else if (chan <= 128) 4009 delta -= sc->lna[2]; 4010 else 4011 delta -= sc->lna[3]; 4012 } else 4013 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 4014 4015 return -12 - delta - rssi; 4016 } 4017 4018 static void 4019 run_rt5390_bbp_init(struct run_softc *sc) 4020 { 4021 u_int i; 4022 uint8_t bbp; 4023 4024 /* Apply maximum likelihood detection for 2 stream case. */ 4025 run_bbp_read(sc, 105, &bbp); 4026 if (sc->nrxchains > 1) 4027 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4028 4029 /* Avoid data lost and CRC error. */ 4030 run_bbp_read(sc, 4, &bbp); 4031 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4032 4033 if (sc->mac_ver == 0x5592) { 4034 for (i = 0; i < (int)__arraycount(rt5592_def_bbp); i++) { 4035 run_bbp_write(sc, rt5592_def_bbp[i].reg, 4036 rt5592_def_bbp[i].val); 4037 } 4038 for (i = 0; i < (int)__arraycount(rt5592_bbp_r196); i++) { 4039 run_bbp_write(sc, 195, i + 0x80); 4040 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 4041 } 4042 } else { 4043 for (i = 0; i < (int)__arraycount(rt5390_def_bbp); i++) { 4044 run_bbp_write(sc, rt5390_def_bbp[i].reg, 4045 rt5390_def_bbp[i].val); 4046 } 4047 } 4048 if (sc->mac_ver == 0x5392) { 4049 run_bbp_write(sc, 88, 0x90); 4050 run_bbp_write(sc, 95, 0x9a); 4051 run_bbp_write(sc, 98, 0x12); 4052 run_bbp_write(sc, 106, 0x12); 4053 run_bbp_write(sc, 134, 0xd0); 4054 run_bbp_write(sc, 135, 0xf6); 4055 run_bbp_write(sc, 148, 0x84); 4056 } 4057 4058 run_bbp_read(sc, 152, &bbp); 4059 run_bbp_write(sc, 152, bbp | 0x80); 4060 4061 /* Fix BBP254 for RT5592C. */ 4062 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 4063 run_bbp_read(sc, 254, &bbp); 4064 run_bbp_write(sc, 254, bbp | 0x80); 4065 } 4066 4067 /* Disable hardware antenna diversity. */ 4068 if (sc->mac_ver == 0x5390) 4069 run_bbp_write(sc, 154, 0); 4070 4071 /* Initialize Rx CCK/OFDM frequency offset report. */ 4072 run_bbp_write(sc, 142, 1); 4073 run_bbp_write(sc, 143, 57); 4074 } 4075 4076 static int 4077 run_bbp_init(struct run_softc *sc) 4078 { 4079 int i, error, ntries; 4080 uint8_t bbp0; 4081 4082 /* wait for BBP to wake up */ 4083 for (ntries = 0; ntries < 20; ntries++) { 4084 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 4085 return error; 4086 if (bbp0 != 0 && bbp0 != 0xff) 4087 break; 4088 } 4089 if (ntries == 20) 4090 return ETIMEDOUT; 4091 4092 /* initialize BBP registers to default values */ 4093 if (sc->mac_ver >= 0x5390) 4094 run_rt5390_bbp_init(sc); 4095 else { 4096 for (i = 0; i < (int)__arraycount(rt2860_def_bbp); i++) { 4097 run_bbp_write(sc, rt2860_def_bbp[i].reg, 4098 rt2860_def_bbp[i].val); 4099 } 4100 } 4101 4102 if (sc->mac_ver == 0x3593) { 4103 run_bbp_write(sc, 79, 0x13); 4104 run_bbp_write(sc, 80, 0x05); 4105 run_bbp_write(sc, 81, 0x33); 4106 run_bbp_write(sc, 86, 0x46); 4107 run_bbp_write(sc, 137, 0x0f); 4108 } 4109 4110 /* fix BBP84 for RT2860E */ 4111 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 4112 run_bbp_write(sc, 84, 0x19); 4113 4114 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 4115 sc->mac_ver != 0x5592)) { 4116 run_bbp_write(sc, 79, 0x13); 4117 run_bbp_write(sc, 80, 0x05); 4118 run_bbp_write(sc, 81, 0x33); 4119 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 4120 run_bbp_write(sc, 69, 0x16); 4121 run_bbp_write(sc, 73, 0x12); 4122 } 4123 return 0; 4124 } 4125 4126 static int 4127 run_rt3070_rf_init(struct run_softc *sc) 4128 { 4129 uint32_t tmp; 4130 uint8_t rf, target, bbp4; 4131 int i; 4132 4133 run_rt3070_rf_read(sc, 30, &rf); 4134 /* toggle RF R30 bit 7 */ 4135 run_rt3070_rf_write(sc, 30, rf | 0x80); 4136 usbd_delay_ms(sc->sc_udev, 10); 4137 run_rt3070_rf_write(sc, 30, rf & ~0x80); 4138 4139 /* initialize RF registers to default value */ 4140 if (sc->mac_ver == 0x3572) { 4141 for (i = 0; i < (int)__arraycount(rt3572_def_rf); i++) { 4142 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 4143 rt3572_def_rf[i].val); 4144 } 4145 } else { 4146 for (i = 0; i < (int)__arraycount(rt3070_def_rf); i++) { 4147 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 4148 rt3070_def_rf[i].val); 4149 } 4150 } 4151 if (sc->mac_ver == 0x3572) { 4152 run_rt3070_rf_read(sc, 6, &rf); 4153 run_rt3070_rf_write(sc, 6, rf | 0x40); 4154 run_rt3070_rf_write(sc, 31, 0x14); 4155 4156 run_read(sc, RT3070_LDO_CFG0, &tmp); 4157 tmp &= ~0x1f000000; 4158 if (sc->mac_rev < 0x0211 && sc->patch_dac) 4159 tmp |= 0x0d000000; /* 1.3V */ 4160 else 4161 tmp |= 0x01000000; /* 1.2V */ 4162 run_write(sc, RT3070_LDO_CFG0, tmp); 4163 } else if (sc->mac_ver == 0x3071) { 4164 run_rt3070_rf_read(sc, 6, &rf); 4165 run_rt3070_rf_write(sc, 6, rf | 0x40); 4166 run_rt3070_rf_write(sc, 31, 0x14); 4167 4168 run_read(sc, RT3070_LDO_CFG0, &tmp); 4169 tmp &= ~0x1f000000; 4170 if (sc->mac_rev < 0x0211) 4171 tmp |= 0x0d000000; /* 1.35V */ 4172 else 4173 tmp |= 0x01000000; /* 1.2V */ 4174 run_write(sc, RT3070_LDO_CFG0, tmp); 4175 4176 /* patch LNA_PE_G1 */ 4177 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4178 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 4179 } else if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 4180 /* 4181 * Change voltage from 1.2V to 1.35V for RT3070. 4182 * The DAC issue (RT3070_LD0_CFG0) has been fixed 4183 * in RT3070(F). 4184 */ 4185 run_read(sc, RT3070_LDO_CFG0, &tmp); 4186 tmp = (tmp & ~0x0f000000) | 0x0d000000; 4187 run_write(sc, RT3070_LDO_CFG0, tmp); 4188 } 4189 4190 /* select 20MHz bandwidth */ 4191 run_rt3070_rf_read(sc, 31, &rf); 4192 run_rt3070_rf_write(sc, 31, rf & ~0x20); 4193 4194 /* calibrate filter for 20MHz bandwidth */ 4195 sc->rf24_20mhz = 0x1f; /* default value */ 4196 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 4197 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 4198 4199 /* select 40MHz bandwidth */ 4200 run_bbp_read(sc, 4, &bbp4); 4201 run_bbp_write(sc, 4, (bbp4 & ~0x08) | 0x10); 4202 run_rt3070_rf_read(sc, 31, &rf); 4203 run_rt3070_rf_write(sc, 31, rf | 0x20); 4204 4205 /* calibrate filter for 40MHz bandwidth */ 4206 sc->rf24_40mhz = 0x2f; /* default value */ 4207 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 4208 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 4209 4210 /* go back to 20MHz bandwidth */ 4211 run_bbp_read(sc, 4, &bbp4); 4212 run_bbp_write(sc, 4, bbp4 & ~0x18); 4213 4214 if (sc->mac_ver == 0x3572) { 4215 /* save default BBP registers 25 and 26 values */ 4216 run_bbp_read(sc, 25, &sc->bbp25); 4217 run_bbp_read(sc, 26, &sc->bbp26); 4218 } else if (sc->mac_rev < 0x0211) 4219 run_rt3070_rf_write(sc, 27, 0x03); 4220 4221 run_read(sc, RT3070_OPT_14, &tmp); 4222 run_write(sc, RT3070_OPT_14, tmp | 1); 4223 4224 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4225 run_rt3070_rf_read(sc, 17, &rf); 4226 rf &= ~RT3070_TX_LO1; 4227 if ((sc->mac_ver == 0x3070 || 4228 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4229 !sc->ext_2ghz_lna) 4230 rf |= 0x20; /* fix for long range Rx issue */ 4231 if (sc->txmixgain_2ghz >= 1) 4232 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4233 run_rt3070_rf_write(sc, 17, rf); 4234 } 4235 if (sc->mac_ver == 0x3071) { 4236 run_rt3070_rf_read(sc, 1, &rf); 4237 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4238 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4239 run_rt3070_rf_write(sc, 1, rf); 4240 4241 run_rt3070_rf_read(sc, 15, &rf); 4242 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4243 4244 run_rt3070_rf_read(sc, 20, &rf); 4245 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4246 4247 run_rt3070_rf_read(sc, 21, &rf); 4248 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4249 } 4250 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4251 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4252 run_rt3070_rf_read(sc, 27, &rf); 4253 rf &= ~0x77; 4254 if (sc->mac_rev < 0x0211) 4255 rf |= 0x03; 4256 run_rt3070_rf_write(sc, 27, rf); 4257 } 4258 return 0; 4259 } 4260 4261 static int 4262 run_rt3593_rf_init(struct run_softc *sc) 4263 { 4264 uint32_t tmp; 4265 uint8_t rf; 4266 int i; 4267 4268 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4269 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4270 tmp &= ~(1 << 4 | 1 << 7); 4271 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4272 4273 /* Initialize RF registers to default value. */ 4274 for (i = 0; i < __arraycount(rt3593_def_rf); i++) { 4275 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4276 rt3593_def_rf[i].val); 4277 } 4278 4279 /* Toggle RF R2 to initiate calibration. */ 4280 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4281 4282 /* Initialize RF frequency offset. */ 4283 run_adjust_freq_offset(sc); 4284 4285 run_rt3070_rf_read(sc, 18, &rf); 4286 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4287 4288 /* 4289 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4290 * decrease voltage back to 1.2V. 4291 */ 4292 run_read(sc, RT3070_LDO_CFG0, &tmp); 4293 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4294 run_write(sc, RT3070_LDO_CFG0, tmp); 4295 usbd_delay_ms(sc->sc_udev, 1); 4296 tmp = (tmp & ~0x1f000000) | 0x01000000; 4297 run_write(sc, RT3070_LDO_CFG0, tmp); 4298 4299 sc->rf24_20mhz = 0x1f; 4300 sc->rf24_40mhz = 0x2f; 4301 4302 /* Save default BBP registers 25 and 26 values. */ 4303 run_bbp_read(sc, 25, &sc->bbp25); 4304 run_bbp_read(sc, 26, &sc->bbp26); 4305 4306 run_read(sc, RT3070_OPT_14, &tmp); 4307 run_write(sc, RT3070_OPT_14, tmp | 1); 4308 return 0; 4309 } 4310 4311 static int 4312 run_rt5390_rf_init(struct run_softc *sc) 4313 { 4314 uint32_t tmp; 4315 uint8_t rf; 4316 int i; 4317 4318 /* Toggle RF R2 to initiate calibration. */ 4319 if (sc->mac_ver == 0x5390) { 4320 run_rt3070_rf_read(sc, 2, &rf); 4321 run_rt3070_rf_write(sc, 2, rf | RT5390_RESCAL); 4322 usbd_delay_ms(sc->sc_udev, 10); 4323 run_rt3070_rf_write(sc, 2, rf & ~RT5390_RESCAL); 4324 } else { 4325 run_rt3070_rf_write(sc, 2, RT5390_RESCAL); 4326 usbd_delay_ms(sc->sc_udev, 10); 4327 } 4328 4329 /* Initialize RF registers to default value. */ 4330 if (sc->mac_ver == 0x5592) { 4331 for (i = 0; i < __arraycount(rt5592_def_rf); i++) { 4332 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4333 rt5592_def_rf[i].val); 4334 } 4335 /* Initialize RF frequency offset. */ 4336 run_adjust_freq_offset(sc); 4337 } else if (sc->mac_ver == 0x5392) { 4338 for (i = 0; i < __arraycount(rt5392_def_rf); i++) { 4339 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4340 rt5392_def_rf[i].val); 4341 } 4342 if (sc->mac_rev >= 0x0223) { 4343 run_rt3070_rf_write(sc, 23, 0x0f); 4344 run_rt3070_rf_write(sc, 24, 0x3e); 4345 run_rt3070_rf_write(sc, 51, 0x32); 4346 run_rt3070_rf_write(sc, 53, 0x22); 4347 run_rt3070_rf_write(sc, 56, 0xc1); 4348 run_rt3070_rf_write(sc, 59, 0x0f); 4349 } 4350 } else { 4351 for (i = 0; i < __arraycount(rt5390_def_rf); i++) { 4352 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4353 rt5390_def_rf[i].val); 4354 } 4355 if (sc->mac_rev >= 0x0502) { 4356 run_rt3070_rf_write(sc, 6, 0xe0); 4357 run_rt3070_rf_write(sc, 25, 0x80); 4358 run_rt3070_rf_write(sc, 46, 0x73); 4359 run_rt3070_rf_write(sc, 53, 0x00); 4360 run_rt3070_rf_write(sc, 56, 0x42); 4361 run_rt3070_rf_write(sc, 61, 0xd1); 4362 } 4363 } 4364 4365 sc->rf24_20mhz = 0x1f; /* default value */ 4366 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4367 4368 if (sc->mac_rev < 0x0211) 4369 run_rt3070_rf_write(sc, 27, 0x3); 4370 4371 run_read(sc, RT3070_OPT_14, &tmp); 4372 run_write(sc, RT3070_OPT_14, tmp | 1); 4373 return 0; 4374 } 4375 4376 static int 4377 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4378 uint8_t *val) 4379 { 4380 uint8_t rf22, rf24; 4381 uint8_t bbp55_pb, bbp55_sb, delta; 4382 int ntries; 4383 4384 /* program filter */ 4385 run_rt3070_rf_read(sc, 24, &rf24); 4386 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4387 run_rt3070_rf_write(sc, 24, rf24); 4388 4389 /* enable baseband loopback mode */ 4390 run_rt3070_rf_read(sc, 22, &rf22); 4391 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4392 4393 /* set power and frequency of passband test tone */ 4394 run_bbp_write(sc, 24, 0x00); 4395 for (ntries = 0; ntries < 100; ntries++) { 4396 /* transmit test tone */ 4397 run_bbp_write(sc, 25, 0x90); 4398 usbd_delay_ms(sc->sc_udev, 10); 4399 /* read received power */ 4400 run_bbp_read(sc, 55, &bbp55_pb); 4401 if (bbp55_pb != 0) 4402 break; 4403 } 4404 if (ntries == 100) 4405 return ETIMEDOUT; 4406 4407 /* set power and frequency of stopband test tone */ 4408 run_bbp_write(sc, 24, 0x06); 4409 for (ntries = 0; ntries < 100; ntries++) { 4410 /* transmit test tone */ 4411 run_bbp_write(sc, 25, 0x90); 4412 usbd_delay_ms(sc->sc_udev, 10); 4413 /* read received power */ 4414 run_bbp_read(sc, 55, &bbp55_sb); 4415 4416 delta = bbp55_pb - bbp55_sb; 4417 if (delta > target) 4418 break; 4419 4420 /* reprogram filter */ 4421 rf24++; 4422 run_rt3070_rf_write(sc, 24, rf24); 4423 } 4424 if (ntries < 100) { 4425 if (rf24 != init) 4426 rf24--; /* backtrack */ 4427 *val = rf24; 4428 run_rt3070_rf_write(sc, 24, rf24); 4429 } 4430 4431 /* restore initial state */ 4432 run_bbp_write(sc, 24, 0x00); 4433 4434 /* disable baseband loopback mode */ 4435 run_rt3070_rf_read(sc, 22, &rf22); 4436 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4437 4438 return 0; 4439 } 4440 4441 static void 4442 run_rt3070_rf_setup(struct run_softc *sc) 4443 { 4444 uint8_t bbp, rf; 4445 int i; 4446 4447 if (sc->mac_ver == 0x3572) { 4448 /* enable DC filter */ 4449 if (sc->mac_rev >= 0x0201) 4450 run_bbp_write(sc, 103, 0xc0); 4451 4452 run_bbp_read(sc, 138, &bbp); 4453 if (sc->ntxchains == 1) 4454 bbp |= 0x20; /* turn off DAC1 */ 4455 if (sc->nrxchains == 1) 4456 bbp &= ~0x02; /* turn off ADC1 */ 4457 run_bbp_write(sc, 138, bbp); 4458 4459 if (sc->mac_rev >= 0x0211) { 4460 /* improve power consumption */ 4461 run_bbp_read(sc, 31, &bbp); 4462 run_bbp_write(sc, 31, bbp & ~0x03); 4463 } 4464 4465 run_rt3070_rf_read(sc, 16, &rf); 4466 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4467 run_rt3070_rf_write(sc, 16, rf); 4468 } else if (sc->mac_ver == 0x3071) { 4469 /* enable DC filter */ 4470 if (sc->mac_rev >= 0x0201) 4471 run_bbp_write(sc, 103, 0xc0); 4472 4473 run_bbp_read(sc, 138, &bbp); 4474 if (sc->ntxchains == 1) 4475 bbp |= 0x20; /* turn off DAC1 */ 4476 if (sc->nrxchains == 1) 4477 bbp &= ~0x02; /* turn off ADC1 */ 4478 run_bbp_write(sc, 138, bbp); 4479 4480 if (sc->mac_rev >= 0x0211) { 4481 /* improve power consumption */ 4482 run_bbp_read(sc, 31, &bbp); 4483 run_bbp_write(sc, 31, bbp & ~0x03); 4484 } 4485 4486 run_write(sc, RT2860_TX_SW_CFG1, 0); 4487 if (sc->mac_rev < 0x0211) { 4488 run_write(sc, RT2860_TX_SW_CFG2, 4489 sc->patch_dac ? 0x2c : 0x0f); 4490 } else 4491 run_write(sc, RT2860_TX_SW_CFG2, 0); 4492 } else if (sc->mac_ver == 0x3070) { 4493 if (sc->mac_rev >= 0x0201) { 4494 /* enable DC filter */ 4495 run_bbp_write(sc, 103, 0xc0); 4496 4497 /* improve power consumption */ 4498 run_bbp_read(sc, 31, &bbp); 4499 run_bbp_write(sc, 31, bbp & ~0x03); 4500 } 4501 4502 if (sc->mac_rev < 0x0211) { 4503 run_write(sc, RT2860_TX_SW_CFG1, 0); 4504 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4505 } else 4506 run_write(sc, RT2860_TX_SW_CFG2, 0); 4507 } 4508 4509 /* initialize RF registers from ROM for >=RT3071*/ 4510 if (sc->mac_ver >= 0x3071) { 4511 for (i = 0; i < 10; i++) { 4512 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4513 continue; 4514 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4515 } 4516 } 4517 } 4518 4519 static void 4520 run_rt3593_rf_setup(struct run_softc *sc) 4521 { 4522 uint8_t bbp, rf; 4523 4524 if (sc->mac_rev >= 0x0211) { 4525 /* Enable DC filter. */ 4526 run_bbp_write(sc, 103, 0xc0); 4527 } 4528 run_write(sc, RT2860_TX_SW_CFG1, 0); 4529 if (sc->mac_rev < 0x0211) { 4530 run_write(sc, RT2860_TX_SW_CFG2, 4531 sc->patch_dac ? 0x2c : 0x0f); 4532 } else 4533 run_write(sc, RT2860_TX_SW_CFG2, 0); 4534 4535 run_rt3070_rf_read(sc, 50, &rf); 4536 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4537 4538 run_rt3070_rf_read(sc, 51, &rf); 4539 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4540 ((sc->txmixgain_2ghz & 0x07) << 2); 4541 run_rt3070_rf_write(sc, 51, rf); 4542 4543 run_rt3070_rf_read(sc, 38, &rf); 4544 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4545 4546 run_rt3070_rf_read(sc, 39, &rf); 4547 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4548 4549 run_rt3070_rf_read(sc, 1, &rf); 4550 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4551 4552 run_rt3070_rf_read(sc, 30, &rf); 4553 rf = (rf & ~0x18) | 0x10; 4554 run_rt3070_rf_write(sc, 30, rf); 4555 4556 /* Apply maximum likelihood detection for 2 stream case. */ 4557 run_bbp_read(sc, 105, &bbp); 4558 if (sc->nrxchains > 1) 4559 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4560 4561 /* Avoid data lost and CRC error. */ 4562 run_bbp_read(sc, 4, &bbp); 4563 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4564 4565 run_bbp_write(sc, 92, 0x02); 4566 run_bbp_write(sc, 82, 0x82); 4567 run_bbp_write(sc, 106, 0x05); 4568 run_bbp_write(sc, 104, 0x92); 4569 run_bbp_write(sc, 88, 0x90); 4570 run_bbp_write(sc, 148, 0xc8); 4571 run_bbp_write(sc, 47, 0x48); 4572 run_bbp_write(sc, 120, 0x50); 4573 4574 run_bbp_write(sc, 163, 0x9d); 4575 4576 /* SNR mapping. */ 4577 run_bbp_write(sc, 142, 0x06); 4578 run_bbp_write(sc, 143, 0xa0); 4579 run_bbp_write(sc, 142, 0x07); 4580 run_bbp_write(sc, 143, 0xa1); 4581 run_bbp_write(sc, 142, 0x08); 4582 run_bbp_write(sc, 143, 0xa2); 4583 4584 run_bbp_write(sc, 31, 0x08); 4585 run_bbp_write(sc, 68, 0x0b); 4586 run_bbp_write(sc, 105, 0x04); 4587 } 4588 4589 static void 4590 run_rt5390_rf_setup(struct run_softc *sc) 4591 { 4592 uint8_t bbp, rf; 4593 4594 if (sc->mac_rev >= 0x0211) { 4595 /* Enable DC filter. */ 4596 run_bbp_write(sc, 103, 0xc0); 4597 4598 if (sc->mac_ver != 0x5592) { 4599 /* Improve power consumption. */ 4600 run_bbp_read(sc, 31, &bbp); 4601 run_bbp_write(sc, 31, bbp & ~0x03); 4602 } 4603 } 4604 4605 run_bbp_read(sc, 138, &bbp); 4606 if (sc->ntxchains == 1) 4607 bbp |= 0x20; /* turn off DAC1 */ 4608 if (sc->nrxchains == 1) 4609 bbp &= ~0x02; /* turn off ADC1 */ 4610 run_bbp_write(sc, 138, bbp); 4611 4612 run_rt3070_rf_read(sc, 38, &rf); 4613 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4614 4615 run_rt3070_rf_read(sc, 39, &rf); 4616 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4617 4618 /* Avoid data lost and CRC error. */ 4619 run_bbp_read(sc, 4, &bbp); 4620 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4621 4622 run_rt3070_rf_read(sc, 30, &rf); 4623 rf = (rf & ~0x18) | 0x10; 4624 run_rt3070_rf_write(sc, 30, rf); 4625 4626 if (sc->mac_ver != 0x5592) { 4627 run_write(sc, RT2860_TX_SW_CFG1, 0); 4628 if (sc->mac_rev < 0x0211) { 4629 run_write(sc, RT2860_TX_SW_CFG2, 4630 sc->patch_dac ? 0x2c : 0x0f); 4631 } else 4632 run_write(sc, RT2860_TX_SW_CFG2, 0); 4633 } 4634 } 4635 4636 static int 4637 run_txrx_enable(struct run_softc *sc) 4638 { 4639 uint32_t tmp; 4640 int error, ntries; 4641 4642 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4643 for (ntries = 0; ntries < 200; ntries++) { 4644 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4645 return error; 4646 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4647 break; 4648 usbd_delay_ms(sc->sc_udev, 50); 4649 } 4650 if (ntries == 200) 4651 return ETIMEDOUT; 4652 4653 usbd_delay_ms(sc->sc_udev, 50); 4654 4655 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4656 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4657 4658 /* enable Rx bulk aggregation (set timeout and limit) */ 4659 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4660 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4661 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4662 4663 /* set Rx filter */ 4664 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4665 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4666 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4667 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4668 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4669 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4670 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4671 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4672 } 4673 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4674 4675 run_write(sc, RT2860_MAC_SYS_CTRL, 4676 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4677 4678 return 0; 4679 } 4680 4681 static int 4682 run_adjust_freq_offset(struct run_softc *sc) 4683 { 4684 uint8_t rf, tmp; 4685 4686 run_rt3070_rf_read(sc, 17, &rf); 4687 tmp = rf; 4688 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4689 rf = MIN(rf, 0x5f); 4690 4691 if (tmp != rf) 4692 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4693 4694 return 0; 4695 } 4696 4697 static int 4698 run_init(struct ifnet *ifp) 4699 { 4700 struct run_softc *sc = ifp->if_softc; 4701 struct ieee80211com *ic = &sc->sc_ic; 4702 uint32_t tmp; 4703 uint8_t bbp1, bbp3; 4704 int i, error, qid, ridx, ntries; 4705 usbd_status status; 4706 4707 for (ntries = 0; ntries < 100; ntries++) { 4708 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4709 goto fail; 4710 if (tmp != 0 && tmp != 0xffffffff) 4711 break; 4712 usbd_delay_ms(sc->sc_udev, 10); 4713 } 4714 if (ntries == 100) { 4715 error = ETIMEDOUT; 4716 goto fail; 4717 } 4718 4719 if ((sc->sc_flags & RUN_FWLOADED) == 0 && 4720 (error = run_load_microcode(sc)) != 0) { 4721 device_printf(sc->sc_dev, 4722 "could not load 8051 microcode\n"); 4723 goto fail; 4724 } 4725 4726 if (ifp->if_flags & IFF_RUNNING) 4727 run_stop(ifp, 0); 4728 4729 /* init host command ring */ 4730 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4731 4732 /* init Tx rings (4 EDCAs) */ 4733 for (qid = 0; qid < 4; qid++) { 4734 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4735 goto fail; 4736 } 4737 /* init Rx ring */ 4738 if ((error = run_alloc_rx_ring(sc)) != 0) 4739 goto fail; 4740 4741 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 4742 run_set_macaddr(sc, ic->ic_myaddr); 4743 4744 for (ntries = 0; ntries < 100; ntries++) { 4745 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4746 goto fail; 4747 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4748 break; 4749 usbd_delay_ms(sc->sc_udev, 10); 4750 } 4751 if (ntries == 100) { 4752 device_printf(sc->sc_dev, 4753 "timeout waiting for DMA engine\n"); 4754 error = ETIMEDOUT; 4755 goto fail; 4756 } 4757 tmp &= 0xff0; 4758 tmp |= RT2860_TX_WB_DDONE; 4759 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4760 4761 /* turn off PME_OEN to solve high-current issue */ 4762 run_read(sc, RT2860_SYS_CTRL, &tmp); 4763 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4764 4765 run_write(sc, RT2860_MAC_SYS_CTRL, 4766 RT2860_BBP_HRST | RT2860_MAC_SRST); 4767 run_write(sc, RT2860_USB_DMA_CFG, 0); 4768 4769 if ((error = run_reset(sc)) != 0) { 4770 device_printf(sc->sc_dev, "could not reset chipset\n"); 4771 goto fail; 4772 } 4773 4774 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4775 4776 /* init Tx power for all Tx rates (from EEPROM) */ 4777 for (ridx = 0; ridx < 5; ridx++) { 4778 if (sc->txpow20mhz[ridx] == 0xffffffff) 4779 continue; 4780 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4781 } 4782 4783 for (i = 0; i < (int)__arraycount(rt2870_def_mac); i++) 4784 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4785 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4786 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4787 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4788 4789 if (sc->mac_ver >= 0x5390) { 4790 run_write(sc, RT2860_TX_SW_CFG0, 4791 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4792 if (sc->mac_ver >= 0x5392) { 4793 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4794 if (sc->mac_ver == 0x5592) { 4795 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4796 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4797 } else { 4798 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4799 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4800 } 4801 } 4802 } else if (sc->mac_ver >= 0x3593) { 4803 run_write(sc, RT2860_TX_SW_CFG0, 4804 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4805 } else if (sc->mac_ver >= 0x3070) { 4806 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4807 run_write(sc, RT2860_TX_SW_CFG0, 4808 4 << RT2860_DLY_PAPE_EN_SHIFT); 4809 } 4810 4811 /* wait while MAC is busy */ 4812 for (ntries = 0; ntries < 100; ntries++) { 4813 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4814 goto fail; 4815 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4816 break; 4817 DELAY(1000); 4818 } 4819 if (ntries == 100) { 4820 error = ETIMEDOUT; 4821 goto fail; 4822 } 4823 4824 /* clear Host to MCU mailbox */ 4825 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4826 run_write(sc, RT2860_H2M_MAILBOX, 0); 4827 usbd_delay_ms(sc->sc_udev, 10); 4828 4829 if ((error = run_bbp_init(sc)) != 0) { 4830 device_printf(sc->sc_dev, "could not initialize BBP\n"); 4831 goto fail; 4832 } 4833 4834 /* abort TSF synchronization */ 4835 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4836 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4837 RT2860_TBTT_TIMER_EN); 4838 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4839 4840 /* clear RX WCID search table */ 4841 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4842 /* clear Pair-wise key table */ 4843 run_set_region_4(sc, RT2860_PKEY(0), 0, 2048); 4844 /* clear IV/EIV table */ 4845 run_set_region_4(sc, RT2860_IVEIV(0), 0, 512); 4846 /* clear WCID attribute table */ 4847 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4848 /* clear shared key table */ 4849 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4850 /* clear shared key mode */ 4851 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4852 4853 /* clear RX WCID search table */ 4854 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4855 /* clear WCID attribute table */ 4856 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4857 4858 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4859 tmp = (tmp & ~0xff) | 0x1e; 4860 run_write(sc, RT2860_US_CYC_CNT, tmp); 4861 4862 if (sc->mac_rev != 0x0101) 4863 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4864 4865 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4866 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4867 4868 /* write vendor-specific BBP values (from EEPROM) */ 4869 if (sc->mac_ver < 0x3593) { 4870 for (i = 0; i < 10; i++) { 4871 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4872 continue; 4873 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4874 } 4875 } 4876 4877 /* select Main antenna for 1T1R devices */ 4878 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4879 run_set_rx_antenna(sc, 0); 4880 4881 /* send LEDs operating mode to microcontroller */ 4882 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4883 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4884 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4885 4886 if (sc->mac_ver >= 0x5390) 4887 run_rt5390_rf_init(sc); 4888 else if (sc->mac_ver == 0x3593) 4889 run_rt3593_rf_init(sc); 4890 else if (sc->mac_ver >= 0x3070) 4891 run_rt3070_rf_init(sc); 4892 4893 /* disable non-existing Rx chains */ 4894 run_bbp_read(sc, 3, &bbp3); 4895 bbp3 &= ~(1 << 3 | 1 << 4); 4896 if (sc->nrxchains == 2) 4897 bbp3 |= 1 << 3; 4898 else if (sc->nrxchains == 3) 4899 bbp3 |= 1 << 4; 4900 run_bbp_write(sc, 3, bbp3); 4901 4902 /* disable non-existing Tx chains */ 4903 run_bbp_read(sc, 1, &bbp1); 4904 if (sc->ntxchains == 1) 4905 bbp1 &= ~(1 << 3 | 1 << 4); 4906 run_bbp_write(sc, 1, bbp1); 4907 4908 if (sc->mac_ver >= 0x5390) 4909 run_rt5390_rf_setup(sc); 4910 else if (sc->mac_ver == 0x3593) 4911 run_rt3593_rf_setup(sc); 4912 else if (sc->mac_ver >= 0x3070) 4913 run_rt3070_rf_setup(sc); 4914 4915 /* select default channel */ 4916 run_set_chan(sc, ic->ic_curchan); 4917 4918 /* setup initial protection mode */ 4919 run_updateprot(sc); 4920 4921 /* turn radio LED on */ 4922 run_set_leds(sc, RT2860_LED_RADIO); 4923 4924 #ifdef RUN_HWCRYPTO 4925 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4926 /* install WEP keys */ 4927 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4928 (void)run_set_key(ic, &ic->ic_crypto.cs_nw_keys[i], 4929 NULL); 4930 } 4931 #endif 4932 4933 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4934 struct run_rx_data *data = &sc->rxq.data[i]; 4935 4936 usbd_setup_xfer(data->xfer, data, data->buf, RUN_MAX_RXSZ, 4937 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, run_rxeof); 4938 status = usbd_transfer(data->xfer); 4939 if (status != USBD_NORMAL_COMPLETION && 4940 status != USBD_IN_PROGRESS) { 4941 device_printf(sc->sc_dev, "queuing rx failed: %s\n", 4942 usbd_errstr(status)); 4943 error = EIO; 4944 goto fail; 4945 } 4946 } 4947 4948 if ((error = run_txrx_enable(sc)) != 0) 4949 goto fail; 4950 4951 ifp->if_flags &= ~IFF_OACTIVE; 4952 ifp->if_flags |= IFF_RUNNING; 4953 4954 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4955 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4956 else 4957 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4958 4959 if (error != 0) 4960 fail: run_stop(ifp, 1); 4961 return error; 4962 } 4963 4964 static void 4965 run_stop(struct ifnet *ifp, int disable) 4966 { 4967 struct run_softc *sc = ifp->if_softc; 4968 struct ieee80211com *ic = &sc->sc_ic; 4969 uint32_t tmp; 4970 int ntries, qid; 4971 4972 if (ifp->if_flags & IFF_RUNNING) 4973 run_set_leds(sc, 0); /* turn all LEDs off */ 4974 4975 sc->sc_tx_timer = 0; 4976 ifp->if_timer = 0; 4977 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 4978 4979 callout_stop(&sc->scan_to); 4980 callout_stop(&sc->calib_to); 4981 4982 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4983 /* wait for all queued asynchronous commands to complete */ 4984 while (sc->cmdq.queued > 0) 4985 tsleep(&sc->cmdq, 0, "cmdq", 0); 4986 4987 /* disable Tx/Rx */ 4988 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4989 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4990 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4991 4992 /* wait for pending Tx to complete */ 4993 for (ntries = 0; ntries < 100; ntries++) { 4994 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4995 break; 4996 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4997 break; 4998 } 4999 DELAY(1000); 5000 run_write(sc, RT2860_USB_DMA_CFG, 0); 5001 5002 /* reset adapter */ 5003 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 5004 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 5005 5006 /* reset Tx and Rx rings */ 5007 sc->qfullmsk = 0; 5008 for (qid = 0; qid < 4; qid++) 5009 run_free_tx_ring(sc, qid); 5010 run_free_rx_ring(sc); 5011 } 5012 5013 #ifndef IEEE80211_STA_ONLY 5014 static int 5015 run_setup_beacon(struct run_softc *sc) 5016 { 5017 struct ieee80211com *ic = &sc->sc_ic; 5018 struct rt2860_txwi txwi; 5019 struct mbuf *m; 5020 uint16_t txwisize; 5021 int ridx; 5022 5023 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo)) == NULL) 5024 return ENOBUFS; 5025 5026 memset(&txwi, 0, sizeof(txwi)); 5027 txwi.wcid = 0xff; 5028 txwi.len = htole16(m->m_pkthdr.len); 5029 /* send beacons at the lowest available rate */ 5030 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 5031 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 5032 txwi.phy = htole16(rt2860_rates[ridx].mcs); 5033 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 5034 txwi.phy |= htole16(RT2860_PHY_OFDM); 5035 txwi.txop = RT2860_TX_TXOP_HT; 5036 txwi.flags = RT2860_TX_TS; 5037 5038 txwisize = (sc->mac_ver == 0x5592) ? 5039 sizeof(txwi) + sizeof(uint32_t) : sizeof(txwi); 5040 run_write_region_1(sc, RT2860_BCN_BASE(0), 5041 (uint8_t *)&txwi, txwisize); 5042 run_write_region_1(sc, RT2860_BCN_BASE(0) + txwisize, 5043 mtod(m, uint8_t *), (m->m_pkthdr.len + 1) & ~1); 5044 5045 m_freem(m); 5046 5047 return 0; 5048 } 5049 #endif 5050 5051 MODULE(MODULE_CLASS_DRIVER, if_run, NULL); 5052 5053 #ifdef _MODULE 5054 #include "ioconf.c" 5055 #endif 5056 5057 static int 5058 if_run_modcmd(modcmd_t cmd, void *arg) 5059 { 5060 int error = 0; 5061 5062 switch (cmd) { 5063 case MODULE_CMD_INIT: 5064 #ifdef _MODULE 5065 error = config_init_component(cfdriver_ioconf_run, 5066 cfattach_ioconf_run, cfdata_ioconf_run); 5067 #endif 5068 return error; 5069 case MODULE_CMD_FINI: 5070 #ifdef _MODULE 5071 error = config_fini_component(cfdriver_ioconf_run, 5072 cfattach_ioconf_run, cfdata_ioconf_run); 5073 #endif 5074 return error; 5075 default: 5076 return ENOTTY; 5077 } 5078 } 5079
Indexes created Thu Oct 02 10:09:58 GMT 2025