if_smscreg.h revision 1.2.6.2
1 1.2.6.2 tls /* $NetBSD: if_smscreg.h,v 1.2.6.2 2013/02/25 00:29:35 tls Exp $ */ 2 1.2.6.2 tls 3 1.2.6.2 tls /* $OpenBSD: if_smscreg.h,v 1.2 2012/09/27 12:38:11 jsg Exp $ */ 4 1.2.6.2 tls /*- 5 1.2.6.2 tls * Copyright (c) 2012 6 1.2.6.2 tls * Ben Gray <bgray (at) freebsd.org>. 7 1.2.6.2 tls * All rights reserved. 8 1.2.6.2 tls * 9 1.2.6.2 tls * Redistribution and use in source and binary forms, with or without 10 1.2.6.2 tls * modification, are permitted provided that the following conditions 11 1.2.6.2 tls * are met: 12 1.2.6.2 tls * 1. Redistributions of source code must retain the above copyright 13 1.2.6.2 tls * notice, this list of conditions and the following disclaimer. 14 1.2.6.2 tls * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.6.2 tls * notice, this list of conditions and the following disclaimer in the 16 1.2.6.2 tls * documentation and/or other materials provided with the distribution. 17 1.2.6.2 tls * 18 1.2.6.2 tls * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 1.2.6.2 tls * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 1.2.6.2 tls * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 1.2.6.2 tls * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 1.2.6.2 tls * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 1.2.6.2 tls * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 1.2.6.2 tls * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.2.6.2 tls * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 1.2.6.2 tls * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 1.2.6.2 tls * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 1.2.6.2 tls * SUCH DAMAGE. 29 1.2.6.2 tls * 30 1.2.6.2 tls * $FreeBSD: src/sys/dev/usb/net/if_smscreg.h,v 1.1 2012/08/15 04:03:55 gonzo Exp $ 31 1.2.6.2 tls */ 32 1.2.6.2 tls #ifndef _IF_SMSCREG_H_ 33 1.2.6.2 tls #define _IF_SMSCREG_H_ 34 1.2.6.2 tls 35 1.2.6.2 tls /* 36 1.2.6.2 tls * Definitions for the SMSC LAN9514 and LAN9514 USB to ethernet controllers. 37 1.2.6.2 tls * 38 1.2.6.2 tls * This information was gleaned from the SMSC driver in the linux kernel, where 39 1.2.6.2 tls * it is Copyrighted (C) 2007-2008 SMSC. 40 1.2.6.2 tls * 41 1.2.6.2 tls */ 42 1.2.6.2 tls 43 1.2.6.2 tls /** 44 1.2.6.2 tls * TRANSMIT FRAMES 45 1.2.6.2 tls * --------------- 46 1.2.6.2 tls * Tx frames are prefixed with an 8-byte header which describes the frame 47 1.2.6.2 tls * 48 1.2.6.2 tls * 4 bytes 4 bytes variable 49 1.2.6.2 tls * +------------+------------+--- . . . . . . . . . . . . ---+ 50 1.2.6.2 tls * | TX_CTRL_0 | TX_CTRL_1 | Ethernet frame data | 51 1.2.6.2 tls * +------------+------------+--- . . . . . . . . . . . . ---+ 52 1.2.6.2 tls * 53 1.2.6.2 tls * Where the headers have the following fields: 54 1.2.6.2 tls * 55 1.2.6.2 tls * TX_CTRL_0 <20:16> Data offset 56 1.2.6.2 tls * TX_CTRL_0 <13> First segment of frame indicator 57 1.2.6.2 tls * TX_CTRL_0 <12> Last segment of frame indicator 58 1.2.6.2 tls * TX_CTRL_0 <10:0> Buffer size (?) 59 1.2.6.2 tls * 60 1.2.6.2 tls * TX_CTRL_1 <14> Perform H/W checksuming on IP packets 61 1.2.6.2 tls * TX_CTRL_1 <13> Disable automatic ethernet CRC generation 62 1.2.6.2 tls * TX_CTRL_1 <12> Disable padding (?) 63 1.2.6.2 tls * TX_CTRL_1 <10:0> Packet byte length 64 1.2.6.2 tls * 65 1.2.6.2 tls */ 66 1.2.6.2 tls #define SMSC_TX_CTRL_0_OFFSET(x) (((x) & 0x1FUL) << 16) 67 1.2.6.2 tls #define SMSC_TX_CTRL_0_FIRST_SEG (0x1UL << 13) 68 1.2.6.2 tls #define SMSC_TX_CTRL_0_LAST_SEG (0x1UL << 12) 69 1.2.6.2 tls #define SMSC_TX_CTRL_0_BUF_SIZE(x) ((x) & 0x000007FFUL) 70 1.2.6.2 tls 71 1.2.6.2 tls #define SMSC_TX_CTRL_1_CSUM_ENABLE (0x1UL << 14) 72 1.2.6.2 tls #define SMSC_TX_CTRL_1_CRC_DISABLE (0x1UL << 13) 73 1.2.6.2 tls #define SMSC_TX_CTRL_1_PADDING_DISABLE (0x1UL << 12) 74 1.2.6.2 tls #define SMSC_TX_CTRL_1_PKT_LENGTH(x) ((x) & 0x000007FFUL) 75 1.2.6.2 tls 76 1.2.6.2 tls /** 77 1.2.6.2 tls * RECEIVE FRAMES 78 1.2.6.2 tls * -------------- 79 1.2.6.2 tls * Rx frames are prefixed with an 4-byte status header which describes any 80 1.2.6.2 tls * errors with the frame as well as things like the length 81 1.2.6.2 tls * 82 1.2.6.2 tls * 4 bytes variable 83 1.2.6.2 tls * +------------+--- . . . . . . . . . . . . ---+ 84 1.2.6.2 tls * | RX_STAT | Ethernet frame data | 85 1.2.6.2 tls * +------------+--- . . . . . . . . . . . . ---+ 86 1.2.6.2 tls * 87 1.2.6.2 tls * Where the status header has the following fields: 88 1.2.6.2 tls * 89 1.2.6.2 tls * RX_STAT <30> Filter Fail 90 1.2.6.2 tls * RX_STAT <29:16> Frame Length 91 1.2.6.2 tls * RX_STAT <15> Error Summary 92 1.2.6.2 tls * RX_STAT <13> Broadcast Frame 93 1.2.6.2 tls * RX_STAT <12> Length Error 94 1.2.6.2 tls * RX_STAT <11> Runt Frame 95 1.2.6.2 tls * RX_STAT <10> Multicast Frame 96 1.2.6.2 tls * RX_STAT <7> Frame too long 97 1.2.6.2 tls * RX_STAT <6> Collision Seen 98 1.2.6.2 tls * RX_STAT <5> Frame Type 99 1.2.6.2 tls * RX_STAT <4> Receive Watchdog 100 1.2.6.2 tls * RX_STAT <3> Mii Error 101 1.2.6.2 tls * RX_STAT <2> Dribbling 102 1.2.6.2 tls * RX_STAT <1> CRC Error 103 1.2.6.2 tls * 104 1.2.6.2 tls */ 105 1.2.6.2 tls #define SMSC_RX_STAT_FILTER_FAIL (0x1UL << 30) 106 1.2.6.2 tls #define SMSC_RX_STAT_FRM_LENGTH(x) (((x) >> 16) & 0x3FFFUL) 107 1.2.6.2 tls #define SMSC_RX_STAT_ERROR (0x1UL << 15) 108 1.2.6.2 tls #define SMSC_RX_STAT_BROADCAST (0x1UL << 13) 109 1.2.6.2 tls #define SMSC_RX_STAT_LENGTH_ERROR (0x1UL << 12) 110 1.2.6.2 tls #define SMSC_RX_STAT_RUNT (0x1UL << 11) 111 1.2.6.2 tls #define SMSC_RX_STAT_MULTICAST (0x1UL << 10) 112 1.2.6.2 tls #define SMSC_RX_STAT_FRM_TO_LONG (0x1UL << 7) 113 1.2.6.2 tls #define SMSC_RX_STAT_COLLISION (0x1UL << 6) 114 1.2.6.2 tls #define SMSC_RX_STAT_FRM_TYPE (0x1UL << 5) 115 1.2.6.2 tls #define SMSC_RX_STAT_WATCHDOG (0x1UL << 4) 116 1.2.6.2 tls #define SMSC_RX_STAT_MII_ERROR (0x1UL << 3) 117 1.2.6.2 tls #define SMSC_RX_STAT_DRIBBLING (0x1UL << 2) 118 1.2.6.2 tls #define SMSC_RX_STAT_CRC_ERROR (0x1UL << 1) 119 1.2.6.2 tls 120 1.2.6.2 tls /** 121 1.2.6.2 tls * REGISTERS 122 1.2.6.2 tls * 123 1.2.6.2 tls */ 124 1.2.6.2 tls #define SMSC_ID_REV 0x000 125 1.2.6.2 tls #define SMSC_INTR_STATUS 0x008 126 1.2.6.2 tls #define SMSC_RX_CFG 0x00C 127 1.2.6.2 tls #define SMSC_TX_CFG 0x010 128 1.2.6.2 tls #define SMSC_HW_CFG 0x014 129 1.2.6.2 tls #define SMSC_PM_CTRL 0x020 130 1.2.6.2 tls #define SMSC_LED_GPIO_CFG 0x024 131 1.2.6.2 tls #define SMSC_GPIO_CFG 0x028 132 1.2.6.2 tls #define SMSC_AFC_CFG 0x02C 133 1.2.6.2 tls #define SMSC_EEPROM_CMD 0x030 134 1.2.6.2 tls #define SMSC_EEPROM_DATA 0x034 135 1.2.6.2 tls #define SMSC_BURST_CAP 0x038 136 1.2.6.2 tls #define SMSC_GPIO_WAKE 0x064 137 1.2.6.2 tls #define SMSC_INTR_CFG 0x068 138 1.2.6.2 tls #define SMSC_BULK_IN_DLY 0x06C 139 1.2.6.2 tls #define SMSC_MAC_CSR 0x100 140 1.2.6.2 tls #define SMSC_MAC_ADDRH 0x104 141 1.2.6.2 tls #define SMSC_MAC_ADDRL 0x108 142 1.2.6.2 tls #define SMSC_HASHH 0x10C 143 1.2.6.2 tls #define SMSC_HASHL 0x110 144 1.2.6.2 tls #define SMSC_MII_ADDR 0x114 145 1.2.6.2 tls #define SMSC_MII_DATA 0x118 146 1.2.6.2 tls #define SMSC_FLOW 0x11C 147 1.2.6.2 tls #define SMSC_VLAN1 0x120 148 1.2.6.2 tls #define SMSC_VLAN2 0x124 149 1.2.6.2 tls #define SMSC_WUFF 0x128 150 1.2.6.2 tls #define SMSC_WUCSR 0x12C 151 1.2.6.2 tls #define SMSC_COE_CTRL 0x130 152 1.2.6.2 tls 153 1.2.6.2 tls /* ID / Revision register */ 154 1.2.6.2 tls #define SMSC_ID_REV_CHIP_ID_MASK 0xFFFF0000UL 155 1.2.6.2 tls #define SMSC_ID_REV_CHIP_REV_MASK 0x0000FFFFUL 156 1.2.6.2 tls 157 1.2.6.2 tls #define SMSC_RX_FIFO_FLUSH (0x1UL << 0) 158 1.2.6.2 tls 159 1.2.6.2 tls #define SMSC_TX_CFG_ON (0x1UL << 2) 160 1.2.6.2 tls #define SMSC_TX_CFG_STOP (0x1UL << 1) 161 1.2.6.2 tls #define SMSC_TX_CFG_FIFO_FLUSH (0x1UL << 0) 162 1.2.6.2 tls 163 1.2.6.2 tls #define SMSC_HW_CFG_BIR (0x1UL << 12) 164 1.2.6.2 tls #define SMSC_HW_CFG_LEDB (0x1UL << 11) 165 1.2.6.2 tls #define SMSC_HW_CFG_RXDOFF (0x3UL << 9) /* RX pkt alignment */ 166 1.2.6.2 tls #define SMSC_HW_CFG_DRP (0x1UL << 6) 167 1.2.6.2 tls #define SMSC_HW_CFG_MEF (0x1UL << 5) 168 1.2.6.2 tls #define SMSC_HW_CFG_LRST (0x1UL << 3) /* Lite reset */ 169 1.2.6.2 tls #define SMSC_HW_CFG_PSEL (0x1UL << 2) 170 1.2.6.2 tls #define SMSC_HW_CFG_BCE (0x1UL << 1) 171 1.2.6.2 tls #define SMSC_HW_CFG_SRST (0x1UL << 0) 172 1.2.6.2 tls 173 1.2.6.2 tls #define SMSC_PM_CTRL_PHY_RST (0x1UL << 4) /* PHY reset */ 174 1.2.6.2 tls 175 1.2.6.2 tls #define SMSC_LED_GPIO_CFG_SPD_LED (0x1UL << 24) 176 1.2.6.2 tls #define SMSC_LED_GPIO_CFG_LNK_LED (0x1UL << 20) 177 1.2.6.2 tls #define SMSC_LED_GPIO_CFG_FDX_LED (0x1UL << 16) 178 1.2.6.2 tls 179 1.2.6.2 tls /* Hi watermark = 15.5Kb (~10 mtu pkts) */ 180 1.2.6.2 tls /* low watermark = 3k (~2 mtu pkts) */ 181 1.2.6.2 tls /* backpressure duration = ~ 350us */ 182 1.2.6.2 tls /* Apply FC on any frame. */ 183 1.2.6.2 tls #define AFC_CFG_DEFAULT (0x00F830A1) 184 1.2.6.2 tls 185 1.2.6.2 tls #define SMSC_EEPROM_CMD_BUSY (0x1UL << 31) 186 1.2.6.2 tls #define SMSC_EEPROM_CMD_MASK (0x7UL << 28) 187 1.2.6.2 tls #define SMSC_EEPROM_CMD_READ (0x0UL << 28) 188 1.2.6.2 tls #define SMSC_EEPROM_CMD_WRITE (0x3UL << 28) 189 1.2.6.2 tls #define SMSC_EEPROM_CMD_ERASE (0x5UL << 28) 190 1.2.6.2 tls #define SMSC_EEPROM_CMD_RELOAD (0x7UL << 28) 191 1.2.6.2 tls #define SMSC_EEPROM_CMD_TIMEOUT (0x1UL << 10) 192 1.2.6.2 tls #define SMSC_EEPROM_CMD_ADDR_MASK 0x000001FFUL 193 1.2.6.2 tls 194 1.2.6.2 tls /* MAC Control and Status Register */ 195 1.2.6.2 tls #define SMSC_MAC_CSR_RCVOWN (0x1UL << 23) /* Half duplex */ 196 1.2.6.2 tls #define SMSC_MAC_CSR_LOOPBK (0x1UL << 21) /* Loopback */ 197 1.2.6.2 tls #define SMSC_MAC_CSR_FDPX (0x1UL << 20) /* Full duplex */ 198 1.2.6.2 tls #define SMSC_MAC_CSR_MCPAS (0x1UL << 19) /* Multicast mode */ 199 1.2.6.2 tls #define SMSC_MAC_CSR_PRMS (0x1UL << 18) /* Promiscuous mode */ 200 1.2.6.2 tls #define SMSC_MAC_CSR_INVFILT (0x1UL << 17) /* Inverse filtering */ 201 1.2.6.2 tls #define SMSC_MAC_CSR_PASSBAD (0x1UL << 16) /* Pass on bad frames */ 202 1.2.6.2 tls #define SMSC_MAC_CSR_HPFILT (0x1UL << 13) /* Hash filtering */ 203 1.2.6.2 tls #define SMSC_MAC_CSR_BCAST (0x1UL << 11) /* Broadcast */ 204 1.2.6.2 tls #define SMSC_MAC_CSR_TXEN (0x1UL << 3) /* TX enable */ 205 1.2.6.2 tls #define SMSC_MAC_CSR_RXEN (0x1UL << 2) /* RX enable */ 206 1.2.6.2 tls 207 1.2.6.2 tls /* Interrupt control register */ 208 1.2.6.2 tls #define SMSC_INTR_NTEP (0x1UL << 31) 209 1.2.6.2 tls #define SMSC_INTR_MACRTO (0x1UL << 19) 210 1.2.6.2 tls #define SMSC_INTR_TX_STOP (0x1UL << 17) 211 1.2.6.2 tls #define SMSC_INTR_RX_STOP (0x1UL << 16) 212 1.2.6.2 tls #define SMSC_INTR_PHY_INT (0x1UL << 15) 213 1.2.6.2 tls #define SMSC_INTR_TXE (0x1UL << 14) 214 1.2.6.2 tls #define SMSC_INTR_TDFU (0x1UL << 13) 215 1.2.6.2 tls #define SMSC_INTR_TDFO (0x1UL << 12) 216 1.2.6.2 tls #define SMSC_INTR_RXDF (0x1UL << 11) 217 1.2.6.2 tls #define SMSC_INTR_GPIOS 0x000007FFUL 218 1.2.6.2 tls 219 1.2.6.2 tls /* Phy MII interface register */ 220 1.2.6.2 tls #define SMSC_MII_WRITE (0x1UL << 1) 221 1.2.6.2 tls #define SMSC_MII_READ (0x0UL << 1) 222 1.2.6.2 tls #define SMSC_MII_BUSY (0x1UL << 0) 223 1.2.6.2 tls 224 1.2.6.2 tls /* H/W checksum register */ 225 1.2.6.2 tls #define SMSC_COE_CTRL_TX_EN (0x1UL << 16) /* Tx H/W csum enable */ 226 1.2.6.2 tls #define SMSC_COE_CTRL_RX_MODE (0x1UL << 1) 227 1.2.6.2 tls #define SMSC_COE_CTRL_RX_EN (0x1UL << 0) /* Rx H/W csum enable */ 228 1.2.6.2 tls 229 1.2.6.2 tls /* Registers on the phy, accessed via MII/MDIO */ 230 1.2.6.2 tls #define SMSC_PHY_INTR_STAT (29) 231 1.2.6.2 tls #define SMSC_PHY_INTR_MASK (30) 232 1.2.6.2 tls 233 1.2.6.2 tls #define SMSC_PHY_INTR_ENERGY_ON (0x1U << 7) 234 1.2.6.2 tls #define SMSC_PHY_INTR_ANEG_COMP (0x1U << 6) 235 1.2.6.2 tls #define SMSC_PHY_INTR_REMOTE_FAULT (0x1U << 5) 236 1.2.6.2 tls #define SMSC_PHY_INTR_LINK_DOWN (0x1U << 4) 237 1.2.6.2 tls 238 1.2.6.2 tls /* USB Vendor Requests */ 239 1.2.6.2 tls #define SMSC_UR_WRITE_REG 0xA0 240 1.2.6.2 tls #define SMSC_UR_READ_REG 0xA1 241 1.2.6.2 tls #define SMSC_UR_GET_STATS 0xA2 242 1.2.6.2 tls 243 1.2.6.2 tls #define SMSC_RX_LIST_CNT 1 244 1.2.6.2 tls #define SMSC_TX_LIST_CNT 1 245 1.2.6.2 tls 246 1.2.6.2 tls #define SMSC_CONFIG_INDEX 1 /* config number 1 */ 247 1.2.6.2 tls #define SMSC_IFACE_IDX 0 248 1.2.6.2 tls 249 1.2.6.2 tls #define SMSC_ENDPT_RX 0 250 1.2.6.2 tls #define SMSC_ENDPT_TX 1 251 1.2.6.2 tls #define SMSC_ENDPT_INTR 2 252 1.2.6.2 tls #define SMSC_ENDPT_MAX 3 253 1.2.6.2 tls 254 1.2.6.2 tls #define SMSC_MIN_BUFSZ 2048 255 1.2.6.2 tls #define SMSC_MAX_BUFSZ 18944 256 1.2.6.2 tls 257 1.2.6.2 tls #endif /* _IF_SMSCREG_H_ */ 258
Indexes created Sun Oct 19 02:09:48 GMT 2025