if_ure.c revision 1.15
1 /* $NetBSD: if_ure.c,v 1.15 2019/08/04 09:03:46 mrg Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.15 2019/08/04 09:03:46 mrg Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 44 #include <net/route.h> 45 46 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 47 #ifdef INET6 48 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 49 #endif 50 51 #include <dev/usb/usbnet.h> 52 53 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54 #include <dev/usb/if_urereg.h> 55 #include <dev/usb/if_urevar.h> 56 57 #define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60 #define URE_DEBUG 61 #ifdef URE_DEBUG 62 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64 int uredebug = 1; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 static const struct usb_devno ure_devs[] = { 71 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 72 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 73 }; 74 75 static int ure_match(device_t, cfdata_t, void *); 76 static void ure_attach(device_t, device_t, void *); 77 static int ure_init(struct ifnet *); 78 static void ure_reset(struct usbnet *); 79 static void ure_miibus_statchg(struct ifnet *); 80 static uint32_t ure_txcsum(struct mbuf *); 81 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 82 static unsigned ure_tx_prepare(struct usbnet *, struct mbuf *, 83 struct usbnet_chain *); 84 static void ure_rxeof_loop(struct usbnet *, struct usbd_xfer *, 85 struct usbnet_chain *, uint32_t); 86 static void ure_rtl8152_init(struct ure_softc *); 87 static void ure_rtl8153_init(struct ure_softc *); 88 static void ure_disable_teredo(struct ure_softc *); 89 static void ure_init_fifo(struct ure_softc *); 90 91 CFATTACH_DECL_NEW(ure, sizeof(struct ure_softc), ure_match, ure_attach, 92 usbnet_detach, usbnet_activate); 93 94 static int 95 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 96 void *buf, int len) 97 { 98 usb_device_request_t req; 99 usbd_status err; 100 101 if (un->un_dying) 102 return 0; 103 104 if (rw == URE_CTL_WRITE) 105 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 106 else 107 req.bmRequestType = UT_READ_VENDOR_DEVICE; 108 req.bRequest = UR_SET_ADDRESS; 109 USETW(req.wValue, val); 110 USETW(req.wIndex, index); 111 USETW(req.wLength, len); 112 113 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 114 rw, val, index, len)); 115 err = usbd_do_request(un->un_udev, &req, buf); 116 if (err) { 117 DPRINTF(("ure_ctl: error %d\n", err)); 118 return -1; 119 } 120 121 return 0; 122 } 123 124 static int 125 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 126 void *buf, int len) 127 { 128 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 129 } 130 131 static int 132 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 133 void *buf, int len) 134 { 135 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 136 } 137 138 static uint8_t 139 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 140 { 141 uint32_t val; 142 uint8_t temp[4]; 143 uint8_t shift; 144 145 shift = (reg & 3) << 3; 146 reg &= ~3; 147 148 ure_read_mem(un, reg, index, &temp, 4); 149 val = UGETDW(temp); 150 val >>= shift; 151 152 return val & 0xff; 153 } 154 155 static uint16_t 156 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 157 { 158 uint32_t val; 159 uint8_t temp[4]; 160 uint8_t shift; 161 162 shift = (reg & 2) << 3; 163 reg &= ~3; 164 165 ure_read_mem(un, reg, index, &temp, 4); 166 val = UGETDW(temp); 167 val >>= shift; 168 169 return val & 0xffff; 170 } 171 172 static uint32_t 173 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 174 { 175 uint8_t temp[4]; 176 177 ure_read_mem(un, reg, index, &temp, 4); 178 return UGETDW(temp); 179 } 180 181 static int 182 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 183 { 184 uint16_t byen; 185 uint8_t temp[4]; 186 uint8_t shift; 187 188 byen = URE_BYTE_EN_BYTE; 189 shift = reg & 3; 190 val &= 0xff; 191 192 if (reg & 3) { 193 byen <<= shift; 194 val <<= (shift << 3); 195 reg &= ~3; 196 } 197 198 USETDW(temp, val); 199 return ure_write_mem(un, reg, index | byen, &temp, 4); 200 } 201 202 static int 203 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 204 { 205 uint16_t byen; 206 uint8_t temp[4]; 207 uint8_t shift; 208 209 byen = URE_BYTE_EN_WORD; 210 shift = reg & 2; 211 val &= 0xffff; 212 213 if (reg & 2) { 214 byen <<= shift; 215 val <<= (shift << 3); 216 reg &= ~3; 217 } 218 219 USETDW(temp, val); 220 return ure_write_mem(un, reg, index | byen, &temp, 4); 221 } 222 223 static int 224 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 225 { 226 uint8_t temp[4]; 227 228 USETDW(temp, val); 229 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 230 } 231 232 static uint16_t 233 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 234 { 235 uint16_t reg; 236 237 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 238 reg = (addr & 0x0fff) | 0xb000; 239 240 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 241 } 242 243 static void 244 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 245 { 246 uint16_t reg; 247 248 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 249 reg = (addr & 0x0fff) | 0xb000; 250 251 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 252 } 253 254 static usbd_status 255 ure_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 256 { 257 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 258 if (reg == RTK_GMEDIASTAT) { 259 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 260 return USBD_NORMAL_COMPLETION; 261 } 262 263 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 264 265 return USBD_NORMAL_COMPLETION; 266 } 267 268 static usbd_status 269 ure_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 270 { 271 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 272 273 return USBD_NORMAL_COMPLETION; 274 } 275 276 static void 277 ure_miibus_statchg(struct ifnet *ifp) 278 { 279 struct usbnet * const un = ifp->if_softc; 280 struct ure_softc * const sc = usbnet_softc(un); 281 struct mii_data * const mii = usbnet_mii(un); 282 283 if (un->un_dying) 284 return; 285 286 un->un_link = false; 287 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 288 (IFM_ACTIVE | IFM_AVALID)) { 289 switch (IFM_SUBTYPE(mii->mii_media_active)) { 290 case IFM_10_T: 291 case IFM_100_TX: 292 un->un_link = true; 293 break; 294 case IFM_1000_T: 295 if ((sc->ure_flags & URE_FLAG_8152) != 0) 296 break; 297 un->un_link = true; 298 break; 299 default: 300 break; 301 } 302 } 303 } 304 305 static void 306 ure_setiff_locked(struct usbnet *un) 307 { 308 struct ethercom *ec = usbnet_ec(un); 309 struct ifnet *ifp = usbnet_ifp(un); 310 struct ether_multi *enm; 311 struct ether_multistep step; 312 uint32_t hashes[2] = { 0, 0 }; 313 uint32_t hash; 314 uint32_t rxmode; 315 316 usbnet_isowned(un); 317 318 if (un->un_dying) 319 return; 320 321 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 322 rxmode &= ~URE_RCR_ACPT_ALL; 323 324 /* 325 * Always accept frames destined to our station address. 326 * Always accept broadcast frames. 327 */ 328 rxmode |= URE_RCR_APM | URE_RCR_AB; 329 330 if (ifp->if_flags & IFF_PROMISC) { 331 rxmode |= URE_RCR_AAP; 332 allmulti: 333 ETHER_LOCK(ec); 334 ec->ec_flags |= ETHER_F_ALLMULTI; 335 ETHER_UNLOCK(ec); 336 rxmode |= URE_RCR_AM; 337 hashes[0] = hashes[1] = 0xffffffff; 338 } else { 339 rxmode |= URE_RCR_AM; 340 341 ETHER_LOCK(ec); 342 ec->ec_flags &= ~ETHER_F_ALLMULTI; 343 344 ETHER_FIRST_MULTI(step, ec, enm); 345 while (enm != NULL) { 346 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 347 ETHER_ADDR_LEN)) { 348 ETHER_UNLOCK(ec); 349 goto allmulti; 350 } 351 352 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 353 >> 26; 354 if (hash < 32) 355 hashes[0] |= (1 << hash); 356 else 357 hashes[1] |= (1 << (hash - 32)); 358 359 ETHER_NEXT_MULTI(step, enm); 360 } 361 ETHER_UNLOCK(ec); 362 363 hash = bswap32(hashes[0]); 364 hashes[0] = bswap32(hashes[1]); 365 hashes[1] = hash; 366 } 367 368 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 369 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 370 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 371 } 372 373 static void 374 ure_setiff(struct usbnet *un) 375 { 376 377 usbnet_lock(un); 378 ure_setiff_locked(un); 379 usbnet_unlock(un); 380 } 381 382 static void 383 ure_reset(struct usbnet *un) 384 { 385 int i; 386 387 usbnet_isowned(un); 388 389 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 390 391 for (i = 0; i < URE_TIMEOUT; i++) { 392 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 393 URE_CR_RST)) 394 break; 395 usbd_delay_ms(un->un_udev, 10); 396 } 397 if (i == URE_TIMEOUT) 398 URE_PRINTF(un, "reset never completed\n"); 399 } 400 401 static int 402 ure_init_locked(struct ifnet *ifp) 403 { 404 struct usbnet * const un = ifp->if_softc; 405 uint8_t eaddr[8]; 406 407 usbnet_isowned(un); 408 409 if (un->un_dying) 410 return EIO; 411 412 /* Cancel pending I/O. */ 413 if (ifp->if_flags & IFF_RUNNING) 414 usbnet_stop(un, ifp, 1); 415 416 /* Set MAC address. */ 417 memset(eaddr, 0, sizeof(eaddr)); 418 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 419 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 420 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 421 eaddr, 8); 422 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 423 424 /* Reset the packet filter. */ 425 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 426 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 427 ~URE_FMC_FCR_MCU_EN); 428 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 429 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 430 URE_FMC_FCR_MCU_EN); 431 432 /* Enable transmit and receive. */ 433 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 434 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 435 URE_CR_TE); 436 437 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 438 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 439 ~URE_RXDY_GATED_EN); 440 441 /* Load the multicast filter. */ 442 ure_setiff_locked(un); 443 444 return usbnet_init_rx_tx(un, 0, 0); 445 } 446 447 static int 448 ure_init(struct ifnet *ifp) 449 { 450 struct usbnet * const un = ifp->if_softc; 451 452 usbnet_lock(un); 453 int ret = ure_init_locked(ifp); 454 usbnet_unlock(un); 455 456 return ret; 457 } 458 459 static void 460 ure_stop_cb(struct ifnet *ifp, int disable __unused) 461 { 462 struct usbnet * const un = ifp->if_softc; 463 464 ure_reset(un); 465 } 466 467 static void 468 ure_rtl8152_init(struct ure_softc *sc) 469 { 470 struct usbnet * const un = &sc->ure_un; 471 uint32_t pwrctrl; 472 473 /* Disable ALDPS. */ 474 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 475 URE_DIS_SDSAVE); 476 usbd_delay_ms(un->un_udev, 20); 477 478 if (sc->ure_chip & URE_CHIP_VER_4C00) { 479 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 480 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 481 ~URE_LED_MODE_MASK); 482 } 483 484 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 485 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 486 ~URE_POWER_CUT); 487 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 488 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 489 ~URE_RESUME_INDICATE); 490 491 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 492 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 493 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 494 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 495 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 496 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 497 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 498 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 499 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 500 URE_SPDWN_LINKCHG_MSK); 501 502 /* Enable Rx aggregation. */ 503 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 504 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 505 ~URE_RX_AGG_DISABLE); 506 507 /* Disable ALDPS. */ 508 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 509 URE_DIS_SDSAVE); 510 usbd_delay_ms(un->un_udev, 20); 511 512 ure_init_fifo(sc); 513 514 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 515 URE_TX_AGG_MAX_THRESHOLD); 516 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 517 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 518 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 519 } 520 521 static void 522 ure_rtl8153_init(struct ure_softc *sc) 523 { 524 struct usbnet * const un = &sc->ure_un; 525 uint16_t val; 526 uint8_t u1u2[8]; 527 int i; 528 529 /* Disable ALDPS. */ 530 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 531 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 532 usbd_delay_ms(un->un_udev, 20); 533 534 memset(u1u2, 0x00, sizeof(u1u2)); 535 ure_write_mem(un, URE_USB_TOLERANCE, 536 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 537 538 for (i = 0; i < URE_TIMEOUT; i++) { 539 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 540 URE_AUTOLOAD_DONE) 541 break; 542 usbd_delay_ms(un->un_udev, 10); 543 } 544 if (i == URE_TIMEOUT) 545 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 546 547 for (i = 0; i < URE_TIMEOUT; i++) { 548 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 549 URE_PHY_STAT_MASK; 550 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 551 break; 552 usbd_delay_ms(un->un_udev, 10); 553 } 554 if (i == URE_TIMEOUT) 555 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 556 557 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 558 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 559 ~URE_U2P3_ENABLE); 560 561 if (sc->ure_chip & URE_CHIP_VER_5C10) { 562 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 563 val &= ~URE_PWD_DN_SCALE_MASK; 564 val |= URE_PWD_DN_SCALE(96); 565 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 566 567 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 568 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 569 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 570 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 571 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 572 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 573 ~URE_ECM_ALDPS); 574 } 575 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 576 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 577 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 578 0) 579 val &= ~URE_DYNAMIC_BURST; 580 else 581 val |= URE_DYNAMIC_BURST; 582 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 583 } 584 585 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 586 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 587 URE_EP4_FULL_FC); 588 589 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 590 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 591 ~URE_TIMER11_EN); 592 593 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 594 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 595 ~URE_LED_MODE_MASK); 596 597 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 598 un->un_udev->ud_speed != USB_SPEED_SUPER) 599 val = URE_LPM_TIMER_500MS; 600 else 601 val = URE_LPM_TIMER_500US; 602 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 603 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 604 605 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 606 val &= ~URE_SEN_VAL_MASK; 607 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 608 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 609 610 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 611 612 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 613 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 614 ~(URE_PWR_EN | URE_PHASE2_EN)); 615 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 616 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 617 ~URE_PCUT_STATUS); 618 619 memset(u1u2, 0xff, sizeof(u1u2)); 620 ure_write_mem(un, URE_USB_TOLERANCE, 621 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 622 623 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 624 URE_ALDPS_SPDWN_RATIO); 625 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 626 URE_EEE_SPDWN_RATIO); 627 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 628 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 629 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 630 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 631 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 632 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 633 URE_EEE_SPDWN_EN); 634 635 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 636 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 637 val |= URE_U2P3_ENABLE; 638 else 639 val &= ~URE_U2P3_ENABLE; 640 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 641 642 memset(u1u2, 0x00, sizeof(u1u2)); 643 ure_write_mem(un, URE_USB_TOLERANCE, 644 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 645 646 /* Disable ALDPS. */ 647 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 648 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 649 usbd_delay_ms(un->un_udev, 20); 650 651 ure_init_fifo(sc); 652 653 /* Enable Rx aggregation. */ 654 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 655 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 656 ~URE_RX_AGG_DISABLE); 657 658 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 659 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 660 val |= URE_U2P3_ENABLE; 661 else 662 val &= ~URE_U2P3_ENABLE; 663 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 664 665 memset(u1u2, 0xff, sizeof(u1u2)); 666 ure_write_mem(un, URE_USB_TOLERANCE, 667 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 668 } 669 670 static void 671 ure_disable_teredo(struct ure_softc *sc) 672 { 673 struct usbnet * const un = &sc->ure_un; 674 675 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 676 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 677 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 678 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 679 URE_WDT6_SET_MODE); 680 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 681 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 682 } 683 684 static void 685 ure_init_fifo(struct ure_softc *sc) 686 { 687 struct usbnet * const un = &sc->ure_un; 688 uint32_t rx_fifo1, rx_fifo2; 689 int i; 690 691 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 692 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 693 URE_RXDY_GATED_EN); 694 695 ure_disable_teredo(sc); 696 697 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, 698 ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 699 ~URE_RCR_ACPT_ALL); 700 701 if (!(sc->ure_flags & URE_FLAG_8152)) { 702 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 703 URE_CHIP_VER_5C20)) 704 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 705 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 706 if (sc->ure_chip & URE_CHIP_VER_5C00) 707 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 708 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 709 ~URE_CTAP_SHORT_EN); 710 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 711 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 712 URE_EEE_CLKDIV_EN); 713 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 714 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 715 URE_EN_10M_BGOFF); 716 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 717 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 718 URE_EN_10M_PLLOFF); 719 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 720 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 721 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 722 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 723 URE_PFM_PWM_SWITCH); 724 725 /* Enable LPF corner auto tune. */ 726 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 727 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 728 729 /* Adjust 10M amplitude. */ 730 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 731 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 732 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 733 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 734 } 735 736 ure_reset(un); 737 738 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 739 740 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 741 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 742 ~URE_NOW_IS_OOB); 743 744 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 745 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 746 ~URE_MCU_BORW_EN); 747 for (i = 0; i < URE_TIMEOUT; i++) { 748 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 749 URE_LINK_LIST_READY) 750 break; 751 usbd_delay_ms(un->un_udev, 10); 752 } 753 if (i == URE_TIMEOUT) 754 URE_PRINTF(un, "timeout waiting for OOB control\n"); 755 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 756 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 757 URE_RE_INIT_LL); 758 for (i = 0; i < URE_TIMEOUT; i++) { 759 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 760 URE_LINK_LIST_READY) 761 break; 762 usbd_delay_ms(un->un_udev, 10); 763 } 764 if (i == URE_TIMEOUT) 765 URE_PRINTF(un, "timeout waiting for OOB control\n"); 766 767 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 768 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 769 ~URE_CPCR_RX_VLAN); 770 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 771 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 772 URE_TCR0_AUTO_FIFO); 773 774 /* Configure Rx FIFO threshold and coalescing. */ 775 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 776 URE_RXFIFO_THR1_NORMAL); 777 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 778 rx_fifo1 = URE_RXFIFO_THR2_FULL; 779 rx_fifo2 = URE_RXFIFO_THR3_FULL; 780 } else { 781 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 782 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 783 } 784 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 785 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 786 787 /* Configure Tx FIFO threshold. */ 788 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 789 URE_TXFIFO_THR_NORMAL); 790 } 791 792 static int 793 ure_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data) 794 { 795 struct usbnet * const un = ifp->if_softc; 796 797 switch (cmd) { 798 case SIOCADDMULTI: 799 case SIOCDELMULTI: 800 ure_setiff(un); 801 break; 802 default: 803 break; 804 } 805 806 return 0; 807 } 808 809 static int 810 ure_match(device_t parent, cfdata_t match, void *aux) 811 { 812 struct usb_attach_arg *uaa = aux; 813 814 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 815 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 816 } 817 818 static void 819 ure_attach(device_t parent, device_t self, void *aux) 820 { 821 struct ure_softc *sc = device_private(self); 822 struct usbnet * const un = &sc->ure_un; 823 struct usb_attach_arg *uaa = aux; 824 struct usbd_device *dev = uaa->uaa_device; 825 usb_interface_descriptor_t *id; 826 usb_endpoint_descriptor_t *ed; 827 int error, i; 828 uint16_t ver; 829 uint8_t eaddr[8]; /* 2byte padded */ 830 char *devinfop; 831 832 /* Switch to usbnet for device_private() */ 833 self->dv_private = un; 834 835 aprint_naive("\n"); 836 aprint_normal("\n"); 837 devinfop = usbd_devinfo_alloc(dev, 0); 838 aprint_normal_dev(self, "%s\n", devinfop); 839 usbd_devinfo_free(devinfop); 840 841 un->un_dev = self; 842 un->un_udev = dev; 843 un->un_sc = sc; 844 un->un_stop_cb = ure_stop_cb; 845 un->un_ioctl_cb = ure_ioctl_cb; 846 un->un_read_reg_cb = ure_mii_read_reg; 847 un->un_write_reg_cb = ure_mii_write_reg; 848 un->un_statchg_cb = ure_miibus_statchg; 849 un->un_tx_prepare_cb = ure_tx_prepare; 850 un->un_rx_loop_cb = ure_rxeof_loop; 851 un->un_init_cb = ure_init; 852 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 853 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 854 855 #define URE_CONFIG_NO 1 /* XXX */ 856 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 857 if (error) { 858 aprint_error_dev(self, "failed to set configuration: %s\n", 859 usbd_errstr(error)); 860 return; /* XXX */ 861 } 862 863 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 864 sc->ure_flags |= URE_FLAG_8152; 865 866 #define URE_IFACE_IDX 0 /* XXX */ 867 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 868 if (error) { 869 aprint_error_dev(self, "failed to get interface handle: %s\n", 870 usbd_errstr(error)); 871 return; /* XXX */ 872 } 873 874 un->un_cdata.uncd_rx_bufsz = un->un_cdata.uncd_tx_bufsz = 16 * 1024; 875 876 id = usbd_get_interface_descriptor(un->un_iface); 877 for (i = 0; i < id->bNumEndpoints; i++) { 878 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 879 if (ed == NULL) { 880 aprint_error_dev(self, "couldn't get ep %d\n", i); 881 return; /* XXX */ 882 } 883 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 884 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 885 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 886 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 887 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 888 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 889 } 890 } 891 892 /* Set these up now for ure_ctl(). */ 893 usbnet_attach(un, "uredet", URE_RX_LIST_CNT, URE_TX_LIST_CNT); 894 895 un->un_phyno = 0; 896 897 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 898 switch (ver) { 899 case 0x4c00: 900 sc->ure_chip |= URE_CHIP_VER_4C00; 901 break; 902 case 0x4c10: 903 sc->ure_chip |= URE_CHIP_VER_4C10; 904 break; 905 case 0x5c00: 906 sc->ure_chip |= URE_CHIP_VER_5C00; 907 break; 908 case 0x5c10: 909 sc->ure_chip |= URE_CHIP_VER_5C10; 910 break; 911 case 0x5c20: 912 sc->ure_chip |= URE_CHIP_VER_5C20; 913 break; 914 case 0x5c30: 915 sc->ure_chip |= URE_CHIP_VER_5C30; 916 break; 917 default: 918 /* fake addr? or just fail? */ 919 break; 920 } 921 aprint_normal_dev(self, "RTL%d %sver %04x\n", 922 (sc->ure_flags & URE_FLAG_8152) ? 8152 : 8153, 923 (sc->ure_chip != 0) ? "" : "unknown ", 924 ver); 925 926 usbnet_lock(un); 927 if (sc->ure_flags & URE_FLAG_8152) 928 ure_rtl8152_init(sc); 929 else 930 ure_rtl8153_init(sc); 931 932 if (sc->ure_chip & URE_CHIP_VER_4C00) 933 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 934 sizeof(eaddr)); 935 else 936 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 937 sizeof(eaddr)); 938 usbnet_unlock(un); 939 memcpy(un->un_eaddr, eaddr, sizeof un->un_eaddr); 940 941 aprint_normal_dev(self, "Ethernet address %s\n", 942 ether_sprintf(un->un_eaddr)); 943 944 struct ifnet *ifp = usbnet_ifp(un); 945 946 /* 947 * We don't support TSOv4 and v6 for now, that are required to 948 * be handled in software for some cases. 949 */ 950 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 951 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 952 #ifdef INET6 953 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 954 #endif 955 if (sc->ure_chip & ~URE_CHIP_VER_4C00) { 956 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 957 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 958 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 959 } 960 struct ethercom *ec = usbnet_ec(un); 961 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 962 #ifdef notyet 963 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 964 #endif 965 966 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 967 0, 0); 968 } 969 970 static void 971 ure_rxeof_loop(struct usbnet *un, struct usbd_xfer *xfer, 972 struct usbnet_chain *c, uint32_t total_len) 973 { 974 struct ifnet *ifp = usbnet_ifp(un); 975 uint8_t *buf = c->unc_buf; 976 uint16_t pkt_len = 0; 977 uint16_t pkt_count = 0; 978 struct ure_rxpkt rxhdr; 979 980 usbnet_isowned_rx(un); 981 982 do { 983 if (total_len < sizeof(rxhdr)) { 984 DPRINTF(("too few bytes left for a packet header\n")); 985 ifp->if_ierrors++; 986 return; 987 } 988 989 buf += roundup(pkt_len, 8); 990 991 memcpy(&rxhdr, buf, sizeof(rxhdr)); 992 total_len -= sizeof(rxhdr); 993 994 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 995 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 996 if (pkt_len > total_len) { 997 DPRINTF(("not enough bytes left for next packet\n")); 998 ifp->if_ierrors++; 999 return; 1000 } 1001 1002 total_len -= roundup(pkt_len, 8); 1003 buf += sizeof(rxhdr); 1004 1005 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1006 ure_rxcsum(ifp, &rxhdr)); 1007 1008 pkt_count++; 1009 1010 } while (total_len > 0); 1011 1012 if (pkt_count) 1013 rnd_add_uint32(&un->un_rndsrc, pkt_count); 1014 } 1015 1016 static int 1017 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1018 { 1019 int enabled = ifp->if_csum_flags_rx, flags = 0; 1020 uint32_t csum, misc; 1021 1022 if (enabled == 0) 1023 return 0; 1024 1025 csum = le32toh(rp->ure_csum); 1026 misc = le32toh(rp->ure_misc); 1027 1028 if (csum & URE_RXPKT_IPV4_CS) { 1029 flags |= M_CSUM_IPv4; 1030 if (csum & URE_RXPKT_TCP_CS) 1031 flags |= M_CSUM_TCPv4; 1032 if (csum & URE_RXPKT_UDP_CS) 1033 flags |= M_CSUM_UDPv4; 1034 } else if (csum & URE_RXPKT_IPV6_CS) { 1035 flags = 0; 1036 if (csum & URE_RXPKT_TCP_CS) 1037 flags |= M_CSUM_TCPv6; 1038 if (csum & URE_RXPKT_UDP_CS) 1039 flags |= M_CSUM_UDPv6; 1040 } 1041 1042 flags &= enabled; 1043 if (__predict_false((flags & M_CSUM_IPv4) && 1044 (misc & URE_RXPKT_IP_F))) 1045 flags |= M_CSUM_IPv4_BAD; 1046 if (__predict_false( 1047 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1048 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1049 )) 1050 flags |= M_CSUM_TCP_UDP_BAD; 1051 1052 return flags; 1053 } 1054 1055 static unsigned 1056 ure_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1057 { 1058 struct ure_txpkt txhdr; 1059 uint32_t frm_len = 0; 1060 uint8_t *buf = c->unc_buf; 1061 1062 usbnet_isowned_tx(un); 1063 1064 /* header */ 1065 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1066 URE_TXPKT_TX_LS); 1067 txhdr.ure_csum = htole32(ure_txcsum(m)); 1068 memcpy(buf, &txhdr, sizeof(txhdr)); 1069 buf += sizeof(txhdr); 1070 frm_len = sizeof(txhdr); 1071 1072 /* packet */ 1073 m_copydata(m, 0, m->m_pkthdr.len, buf); 1074 frm_len += m->m_pkthdr.len; 1075 1076 if (__predict_false(c->unc_xfer == NULL)) 1077 return EIO; /* XXX plugged out or down */ 1078 1079 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1080 1081 return frm_len; 1082 } 1083 1084 /* 1085 * We need to calculate L4 checksum in software, if the offset of 1086 * L4 header is larger than 0x7ff = 2047. 1087 */ 1088 static uint32_t 1089 ure_txcsum(struct mbuf *m) 1090 { 1091 struct ether_header *eh; 1092 int flags = m->m_pkthdr.csum_flags; 1093 uint32_t data = m->m_pkthdr.csum_data; 1094 uint32_t reg = 0; 1095 int l3off, l4off; 1096 uint16_t type; 1097 1098 if (flags == 0) 1099 return 0; 1100 1101 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1102 eh = mtod(m, struct ether_header *); 1103 type = eh->ether_type; 1104 } else 1105 m_copydata(m, offsetof(struct ether_header, ether_type), 1106 sizeof(type), &type); 1107 switch (type = htons(type)) { 1108 case ETHERTYPE_IP: 1109 case ETHERTYPE_IPV6: 1110 l3off = ETHER_HDR_LEN; 1111 break; 1112 case ETHERTYPE_VLAN: 1113 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1114 break; 1115 default: 1116 return 0; 1117 } 1118 1119 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1120 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1121 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1122 in_undefer_cksum(m, l3off, flags); 1123 return 0; 1124 } 1125 reg |= URE_TXPKT_IPV4_CS; 1126 if (flags & M_CSUM_TCPv4) 1127 reg |= URE_TXPKT_TCP_CS; 1128 else 1129 reg |= URE_TXPKT_UDP_CS; 1130 reg |= l4off << URE_L4_OFFSET_SHIFT; 1131 } 1132 #ifdef INET6 1133 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1134 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1135 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1136 in6_undefer_cksum(m, l3off, flags); 1137 return 0; 1138 } 1139 reg |= URE_TXPKT_IPV6_CS; 1140 if (flags & M_CSUM_TCPv6) 1141 reg |= URE_TXPKT_TCP_CS; 1142 else 1143 reg |= URE_TXPKT_UDP_CS; 1144 reg |= l4off << URE_L4_OFFSET_SHIFT; 1145 } 1146 #endif 1147 else if (flags & M_CSUM_IPv4) 1148 reg |= URE_TXPKT_IPV4_CS; 1149 1150 return reg; 1151 } 1152
Indexes created Mon Sep 29 21:09:56 GMT 2025