if_ure.c revision 1.18
1 /* $NetBSD: if_ure.c,v 1.18 2019/08/06 01:42:22 mrg Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.18 2019/08/06 01:42:22 mrg Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 44 #include <net/route.h> 45 46 #include <dev/usb/usbnet.h> 47 48 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 49 #ifdef INET6 50 #include <netinet/in.h> 51 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 52 #endif 53 54 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 55 #include <dev/usb/if_urereg.h> 56 #include <dev/usb/if_urevar.h> 57 58 #define URE_PRINTF(un, fmt, args...) \ 59 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 60 61 #define URE_DEBUG 62 #ifdef URE_DEBUG 63 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 65 int uredebug = 1; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 static const struct usb_devno ure_devs[] = { 72 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 73 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 74 }; 75 76 static int ure_match(device_t, cfdata_t, void *); 77 static void ure_attach(device_t, device_t, void *); 78 static int ure_init(struct ifnet *); 79 static void ure_reset(struct usbnet *); 80 static void ure_miibus_statchg(struct ifnet *); 81 static uint32_t ure_txcsum(struct mbuf *); 82 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 83 static unsigned ure_tx_prepare(struct usbnet *, struct mbuf *, 84 struct usbnet_chain *); 85 static void ure_rxeof_loop(struct usbnet *, struct usbd_xfer *, 86 struct usbnet_chain *, uint32_t); 87 static void ure_rtl8152_init(struct ure_softc *); 88 static void ure_rtl8153_init(struct ure_softc *); 89 static void ure_disable_teredo(struct ure_softc *); 90 static void ure_init_fifo(struct ure_softc *); 91 92 CFATTACH_DECL_NEW(ure, sizeof(struct ure_softc), ure_match, ure_attach, 93 usbnet_detach, usbnet_activate); 94 95 static int 96 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 97 void *buf, int len) 98 { 99 usb_device_request_t req; 100 usbd_status err; 101 102 if (un->un_dying) 103 return 0; 104 105 if (rw == URE_CTL_WRITE) 106 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 107 else 108 req.bmRequestType = UT_READ_VENDOR_DEVICE; 109 req.bRequest = UR_SET_ADDRESS; 110 USETW(req.wValue, val); 111 USETW(req.wIndex, index); 112 USETW(req.wLength, len); 113 114 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 115 rw, val, index, len)); 116 err = usbd_do_request(un->un_udev, &req, buf); 117 if (err) { 118 DPRINTF(("ure_ctl: error %d\n", err)); 119 return -1; 120 } 121 122 return 0; 123 } 124 125 static int 126 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 127 void *buf, int len) 128 { 129 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 130 } 131 132 static int 133 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 134 void *buf, int len) 135 { 136 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 137 } 138 139 static uint8_t 140 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 141 { 142 uint32_t val; 143 uint8_t temp[4]; 144 uint8_t shift; 145 146 shift = (reg & 3) << 3; 147 reg &= ~3; 148 149 ure_read_mem(un, reg, index, &temp, 4); 150 val = UGETDW(temp); 151 val >>= shift; 152 153 return val & 0xff; 154 } 155 156 static uint16_t 157 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 158 { 159 uint32_t val; 160 uint8_t temp[4]; 161 uint8_t shift; 162 163 shift = (reg & 2) << 3; 164 reg &= ~3; 165 166 ure_read_mem(un, reg, index, &temp, 4); 167 val = UGETDW(temp); 168 val >>= shift; 169 170 return val & 0xffff; 171 } 172 173 static uint32_t 174 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 175 { 176 uint8_t temp[4]; 177 178 ure_read_mem(un, reg, index, &temp, 4); 179 return UGETDW(temp); 180 } 181 182 static int 183 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 184 { 185 uint16_t byen; 186 uint8_t temp[4]; 187 uint8_t shift; 188 189 byen = URE_BYTE_EN_BYTE; 190 shift = reg & 3; 191 val &= 0xff; 192 193 if (reg & 3) { 194 byen <<= shift; 195 val <<= (shift << 3); 196 reg &= ~3; 197 } 198 199 USETDW(temp, val); 200 return ure_write_mem(un, reg, index | byen, &temp, 4); 201 } 202 203 static int 204 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 205 { 206 uint16_t byen; 207 uint8_t temp[4]; 208 uint8_t shift; 209 210 byen = URE_BYTE_EN_WORD; 211 shift = reg & 2; 212 val &= 0xffff; 213 214 if (reg & 2) { 215 byen <<= shift; 216 val <<= (shift << 3); 217 reg &= ~3; 218 } 219 220 USETDW(temp, val); 221 return ure_write_mem(un, reg, index | byen, &temp, 4); 222 } 223 224 static int 225 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 226 { 227 uint8_t temp[4]; 228 229 USETDW(temp, val); 230 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 231 } 232 233 static uint16_t 234 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 235 { 236 uint16_t reg; 237 238 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 239 reg = (addr & 0x0fff) | 0xb000; 240 241 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 242 } 243 244 static void 245 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 246 { 247 uint16_t reg; 248 249 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 250 reg = (addr & 0x0fff) | 0xb000; 251 252 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 253 } 254 255 static usbd_status 256 ure_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 257 { 258 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 259 if (reg == RTK_GMEDIASTAT) { 260 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 261 return USBD_NORMAL_COMPLETION; 262 } 263 264 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 265 266 return USBD_NORMAL_COMPLETION; 267 } 268 269 static usbd_status 270 ure_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 271 { 272 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 273 274 return USBD_NORMAL_COMPLETION; 275 } 276 277 static void 278 ure_miibus_statchg(struct ifnet *ifp) 279 { 280 struct usbnet * const un = ifp->if_softc; 281 struct ure_softc * const sc = usbnet_softc(un); 282 struct mii_data * const mii = usbnet_mii(un); 283 284 if (un->un_dying) 285 return; 286 287 un->un_link = false; 288 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 289 (IFM_ACTIVE | IFM_AVALID)) { 290 switch (IFM_SUBTYPE(mii->mii_media_active)) { 291 case IFM_10_T: 292 case IFM_100_TX: 293 un->un_link = true; 294 break; 295 case IFM_1000_T: 296 if ((sc->ure_flags & URE_FLAG_8152) != 0) 297 break; 298 un->un_link = true; 299 break; 300 default: 301 break; 302 } 303 } 304 } 305 306 static void 307 ure_setiff_locked(struct usbnet *un) 308 { 309 struct ethercom *ec = usbnet_ec(un); 310 struct ifnet *ifp = usbnet_ifp(un); 311 struct ether_multi *enm; 312 struct ether_multistep step; 313 uint32_t hashes[2] = { 0, 0 }; 314 uint32_t hash; 315 uint32_t rxmode; 316 317 usbnet_isowned(un); 318 319 if (un->un_dying) 320 return; 321 322 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 323 rxmode &= ~URE_RCR_ACPT_ALL; 324 325 /* 326 * Always accept frames destined to our station address. 327 * Always accept broadcast frames. 328 */ 329 rxmode |= URE_RCR_APM | URE_RCR_AB; 330 331 if (ifp->if_flags & IFF_PROMISC) { 332 rxmode |= URE_RCR_AAP; 333 allmulti: 334 ETHER_LOCK(ec); 335 ec->ec_flags |= ETHER_F_ALLMULTI; 336 ETHER_UNLOCK(ec); 337 rxmode |= URE_RCR_AM; 338 hashes[0] = hashes[1] = 0xffffffff; 339 } else { 340 rxmode |= URE_RCR_AM; 341 342 ETHER_LOCK(ec); 343 ec->ec_flags &= ~ETHER_F_ALLMULTI; 344 345 ETHER_FIRST_MULTI(step, ec, enm); 346 while (enm != NULL) { 347 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 348 ETHER_ADDR_LEN)) { 349 ETHER_UNLOCK(ec); 350 goto allmulti; 351 } 352 353 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 354 >> 26; 355 if (hash < 32) 356 hashes[0] |= (1 << hash); 357 else 358 hashes[1] |= (1 << (hash - 32)); 359 360 ETHER_NEXT_MULTI(step, enm); 361 } 362 ETHER_UNLOCK(ec); 363 364 hash = bswap32(hashes[0]); 365 hashes[0] = bswap32(hashes[1]); 366 hashes[1] = hash; 367 } 368 369 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 370 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 371 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 372 } 373 374 static void 375 ure_setiff(struct usbnet *un) 376 { 377 378 usbnet_lock(un); 379 ure_setiff_locked(un); 380 usbnet_unlock(un); 381 } 382 383 static void 384 ure_reset(struct usbnet *un) 385 { 386 int i; 387 388 usbnet_isowned(un); 389 390 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 391 392 for (i = 0; i < URE_TIMEOUT; i++) { 393 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 394 URE_CR_RST)) 395 break; 396 usbd_delay_ms(un->un_udev, 10); 397 } 398 if (i == URE_TIMEOUT) 399 URE_PRINTF(un, "reset never completed\n"); 400 } 401 402 static int 403 ure_init_locked(struct ifnet *ifp) 404 { 405 struct usbnet * const un = ifp->if_softc; 406 uint8_t eaddr[8]; 407 408 usbnet_isowned(un); 409 410 if (un->un_dying) 411 return EIO; 412 413 /* Cancel pending I/O. */ 414 if (ifp->if_flags & IFF_RUNNING) 415 usbnet_stop(un, ifp, 1); 416 417 /* Set MAC address. */ 418 memset(eaddr, 0, sizeof(eaddr)); 419 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 420 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 421 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 422 eaddr, 8); 423 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 424 425 /* Reset the packet filter. */ 426 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 427 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 428 ~URE_FMC_FCR_MCU_EN); 429 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 430 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 431 URE_FMC_FCR_MCU_EN); 432 433 /* Enable transmit and receive. */ 434 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 435 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 436 URE_CR_TE); 437 438 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 439 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 440 ~URE_RXDY_GATED_EN); 441 442 /* Load the multicast filter. */ 443 ure_setiff_locked(un); 444 445 return usbnet_init_rx_tx(un, 0, 0); 446 } 447 448 static int 449 ure_init(struct ifnet *ifp) 450 { 451 struct usbnet * const un = ifp->if_softc; 452 453 usbnet_lock(un); 454 int ret = ure_init_locked(ifp); 455 usbnet_unlock(un); 456 457 return ret; 458 } 459 460 static void 461 ure_stop_cb(struct ifnet *ifp, int disable __unused) 462 { 463 struct usbnet * const un = ifp->if_softc; 464 465 ure_reset(un); 466 } 467 468 static void 469 ure_rtl8152_init(struct ure_softc *sc) 470 { 471 struct usbnet * const un = &sc->ure_un; 472 uint32_t pwrctrl; 473 474 /* Disable ALDPS. */ 475 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 476 URE_DIS_SDSAVE); 477 usbd_delay_ms(un->un_udev, 20); 478 479 if (sc->ure_chip & URE_CHIP_VER_4C00) { 480 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 481 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 482 ~URE_LED_MODE_MASK); 483 } 484 485 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 486 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 487 ~URE_POWER_CUT); 488 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 489 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 490 ~URE_RESUME_INDICATE); 491 492 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 493 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 494 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 495 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 496 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 497 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 498 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 499 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 500 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 501 URE_SPDWN_LINKCHG_MSK); 502 503 /* Enable Rx aggregation. */ 504 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 505 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 506 ~URE_RX_AGG_DISABLE); 507 508 /* Disable ALDPS. */ 509 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 510 URE_DIS_SDSAVE); 511 usbd_delay_ms(un->un_udev, 20); 512 513 ure_init_fifo(sc); 514 515 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 516 URE_TX_AGG_MAX_THRESHOLD); 517 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 518 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 519 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 520 } 521 522 static void 523 ure_rtl8153_init(struct ure_softc *sc) 524 { 525 struct usbnet * const un = &sc->ure_un; 526 uint16_t val; 527 uint8_t u1u2[8]; 528 int i; 529 530 /* Disable ALDPS. */ 531 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 532 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 533 usbd_delay_ms(un->un_udev, 20); 534 535 memset(u1u2, 0x00, sizeof(u1u2)); 536 ure_write_mem(un, URE_USB_TOLERANCE, 537 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 538 539 for (i = 0; i < URE_TIMEOUT; i++) { 540 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 541 URE_AUTOLOAD_DONE) 542 break; 543 usbd_delay_ms(un->un_udev, 10); 544 } 545 if (i == URE_TIMEOUT) 546 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 547 548 for (i = 0; i < URE_TIMEOUT; i++) { 549 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 550 URE_PHY_STAT_MASK; 551 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 552 break; 553 usbd_delay_ms(un->un_udev, 10); 554 } 555 if (i == URE_TIMEOUT) 556 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 557 558 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 559 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 560 ~URE_U2P3_ENABLE); 561 562 if (sc->ure_chip & URE_CHIP_VER_5C10) { 563 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 564 val &= ~URE_PWD_DN_SCALE_MASK; 565 val |= URE_PWD_DN_SCALE(96); 566 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 567 568 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 569 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 570 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 571 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 572 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 573 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 574 ~URE_ECM_ALDPS); 575 } 576 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 577 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 578 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 579 0) 580 val &= ~URE_DYNAMIC_BURST; 581 else 582 val |= URE_DYNAMIC_BURST; 583 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 584 } 585 586 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 587 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 588 URE_EP4_FULL_FC); 589 590 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 591 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 592 ~URE_TIMER11_EN); 593 594 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 595 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 596 ~URE_LED_MODE_MASK); 597 598 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 599 un->un_udev->ud_speed != USB_SPEED_SUPER) 600 val = URE_LPM_TIMER_500MS; 601 else 602 val = URE_LPM_TIMER_500US; 603 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 604 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 605 606 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 607 val &= ~URE_SEN_VAL_MASK; 608 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 609 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 610 611 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 612 613 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 614 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 615 ~(URE_PWR_EN | URE_PHASE2_EN)); 616 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 617 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 618 ~URE_PCUT_STATUS); 619 620 memset(u1u2, 0xff, sizeof(u1u2)); 621 ure_write_mem(un, URE_USB_TOLERANCE, 622 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 623 624 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 625 URE_ALDPS_SPDWN_RATIO); 626 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 627 URE_EEE_SPDWN_RATIO); 628 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 629 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 630 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 631 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 632 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 633 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 634 URE_EEE_SPDWN_EN); 635 636 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 637 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 638 val |= URE_U2P3_ENABLE; 639 else 640 val &= ~URE_U2P3_ENABLE; 641 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 642 643 memset(u1u2, 0x00, sizeof(u1u2)); 644 ure_write_mem(un, URE_USB_TOLERANCE, 645 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 646 647 /* Disable ALDPS. */ 648 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 649 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 650 usbd_delay_ms(un->un_udev, 20); 651 652 ure_init_fifo(sc); 653 654 /* Enable Rx aggregation. */ 655 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 656 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 657 ~URE_RX_AGG_DISABLE); 658 659 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 660 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 661 val |= URE_U2P3_ENABLE; 662 else 663 val &= ~URE_U2P3_ENABLE; 664 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 665 666 memset(u1u2, 0xff, sizeof(u1u2)); 667 ure_write_mem(un, URE_USB_TOLERANCE, 668 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 669 } 670 671 static void 672 ure_disable_teredo(struct ure_softc *sc) 673 { 674 struct usbnet * const un = &sc->ure_un; 675 676 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 677 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 678 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 679 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 680 URE_WDT6_SET_MODE); 681 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 682 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 683 } 684 685 static void 686 ure_init_fifo(struct ure_softc *sc) 687 { 688 struct usbnet * const un = &sc->ure_un; 689 uint32_t rx_fifo1, rx_fifo2; 690 int i; 691 692 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 693 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 694 URE_RXDY_GATED_EN); 695 696 ure_disable_teredo(sc); 697 698 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, 699 ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 700 ~URE_RCR_ACPT_ALL); 701 702 if (!(sc->ure_flags & URE_FLAG_8152)) { 703 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 704 URE_CHIP_VER_5C20)) 705 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 706 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 707 if (sc->ure_chip & URE_CHIP_VER_5C00) 708 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 709 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 710 ~URE_CTAP_SHORT_EN); 711 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 712 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 713 URE_EEE_CLKDIV_EN); 714 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 715 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 716 URE_EN_10M_BGOFF); 717 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 718 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 719 URE_EN_10M_PLLOFF); 720 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 721 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 722 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 723 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 724 URE_PFM_PWM_SWITCH); 725 726 /* Enable LPF corner auto tune. */ 727 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 728 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 729 730 /* Adjust 10M amplitude. */ 731 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 732 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 733 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 734 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 735 } 736 737 ure_reset(un); 738 739 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 740 741 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 742 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 743 ~URE_NOW_IS_OOB); 744 745 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 746 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 747 ~URE_MCU_BORW_EN); 748 for (i = 0; i < URE_TIMEOUT; i++) { 749 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 750 URE_LINK_LIST_READY) 751 break; 752 usbd_delay_ms(un->un_udev, 10); 753 } 754 if (i == URE_TIMEOUT) 755 URE_PRINTF(un, "timeout waiting for OOB control\n"); 756 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 757 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 758 URE_RE_INIT_LL); 759 for (i = 0; i < URE_TIMEOUT; i++) { 760 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 761 URE_LINK_LIST_READY) 762 break; 763 usbd_delay_ms(un->un_udev, 10); 764 } 765 if (i == URE_TIMEOUT) 766 URE_PRINTF(un, "timeout waiting for OOB control\n"); 767 768 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 769 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 770 ~URE_CPCR_RX_VLAN); 771 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 772 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 773 URE_TCR0_AUTO_FIFO); 774 775 /* Configure Rx FIFO threshold and coalescing. */ 776 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 777 URE_RXFIFO_THR1_NORMAL); 778 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 779 rx_fifo1 = URE_RXFIFO_THR2_FULL; 780 rx_fifo2 = URE_RXFIFO_THR3_FULL; 781 } else { 782 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 783 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 784 } 785 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 786 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 787 788 /* Configure Tx FIFO threshold. */ 789 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 790 URE_TXFIFO_THR_NORMAL); 791 } 792 793 static int 794 ure_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data) 795 { 796 struct usbnet * const un = ifp->if_softc; 797 798 switch (cmd) { 799 case SIOCADDMULTI: 800 case SIOCDELMULTI: 801 ure_setiff(un); 802 break; 803 default: 804 break; 805 } 806 807 return 0; 808 } 809 810 static int 811 ure_match(device_t parent, cfdata_t match, void *aux) 812 { 813 struct usb_attach_arg *uaa = aux; 814 815 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 816 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 817 } 818 819 static void 820 ure_attach(device_t parent, device_t self, void *aux) 821 { 822 struct ure_softc *sc = device_private(self); 823 struct usbnet * const un = &sc->ure_un; 824 struct usb_attach_arg *uaa = aux; 825 struct usbd_device *dev = uaa->uaa_device; 826 usb_interface_descriptor_t *id; 827 usb_endpoint_descriptor_t *ed; 828 int error, i; 829 uint16_t ver; 830 uint8_t eaddr[8]; /* 2byte padded */ 831 char *devinfop; 832 833 /* Switch to usbnet for device_private() */ 834 self->dv_private = un; 835 836 aprint_naive("\n"); 837 aprint_normal("\n"); 838 devinfop = usbd_devinfo_alloc(dev, 0); 839 aprint_normal_dev(self, "%s\n", devinfop); 840 usbd_devinfo_free(devinfop); 841 842 un->un_dev = self; 843 un->un_udev = dev; 844 un->un_sc = sc; 845 un->un_stop_cb = ure_stop_cb; 846 un->un_ioctl_cb = ure_ioctl_cb; 847 un->un_read_reg_cb = ure_mii_read_reg; 848 un->un_write_reg_cb = ure_mii_write_reg; 849 un->un_statchg_cb = ure_miibus_statchg; 850 un->un_tx_prepare_cb = ure_tx_prepare; 851 un->un_rx_loop_cb = ure_rxeof_loop; 852 un->un_init_cb = ure_init; 853 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 854 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 855 856 #define URE_CONFIG_NO 1 /* XXX */ 857 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 858 if (error) { 859 aprint_error_dev(self, "failed to set configuration: %s\n", 860 usbd_errstr(error)); 861 return; /* XXX */ 862 } 863 864 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 865 sc->ure_flags |= URE_FLAG_8152; 866 867 #define URE_IFACE_IDX 0 /* XXX */ 868 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 869 if (error) { 870 aprint_error_dev(self, "failed to get interface handle: %s\n", 871 usbd_errstr(error)); 872 return; /* XXX */ 873 } 874 875 un->un_cdata.uncd_rx_bufsz = un->un_cdata.uncd_tx_bufsz = 16 * 1024; 876 877 id = usbd_get_interface_descriptor(un->un_iface); 878 for (i = 0; i < id->bNumEndpoints; i++) { 879 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 880 if (ed == NULL) { 881 aprint_error_dev(self, "couldn't get ep %d\n", i); 882 return; /* XXX */ 883 } 884 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 885 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 886 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 887 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 888 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 889 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 890 } 891 } 892 893 /* Set these up now for ure_ctl(). */ 894 usbnet_attach(un, "uredet", URE_RX_LIST_CNT, URE_TX_LIST_CNT); 895 896 un->un_phyno = 0; 897 898 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 899 switch (ver) { 900 case 0x4c00: 901 sc->ure_chip |= URE_CHIP_VER_4C00; 902 break; 903 case 0x4c10: 904 sc->ure_chip |= URE_CHIP_VER_4C10; 905 break; 906 case 0x5c00: 907 sc->ure_chip |= URE_CHIP_VER_5C00; 908 break; 909 case 0x5c10: 910 sc->ure_chip |= URE_CHIP_VER_5C10; 911 break; 912 case 0x5c20: 913 sc->ure_chip |= URE_CHIP_VER_5C20; 914 break; 915 case 0x5c30: 916 sc->ure_chip |= URE_CHIP_VER_5C30; 917 break; 918 default: 919 /* fake addr? or just fail? */ 920 break; 921 } 922 aprint_normal_dev(self, "RTL%d %sver %04x\n", 923 (sc->ure_flags & URE_FLAG_8152) ? 8152 : 8153, 924 (sc->ure_chip != 0) ? "" : "unknown ", 925 ver); 926 927 usbnet_lock(un); 928 if (sc->ure_flags & URE_FLAG_8152) 929 ure_rtl8152_init(sc); 930 else 931 ure_rtl8153_init(sc); 932 933 if (sc->ure_chip & URE_CHIP_VER_4C00) 934 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 935 sizeof(eaddr)); 936 else 937 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 938 sizeof(eaddr)); 939 usbnet_unlock(un); 940 memcpy(un->un_eaddr, eaddr, sizeof un->un_eaddr); 941 942 struct ifnet *ifp = usbnet_ifp(un); 943 944 /* 945 * We don't support TSOv4 and v6 for now, that are required to 946 * be handled in software for some cases. 947 */ 948 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 949 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 950 #ifdef INET6 951 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 952 #endif 953 if (sc->ure_chip & ~URE_CHIP_VER_4C00) { 954 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 955 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 956 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 957 } 958 struct ethercom *ec = usbnet_ec(un); 959 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 960 #ifdef notyet 961 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 962 #endif 963 964 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 965 0, 0); 966 } 967 968 static void 969 ure_rxeof_loop(struct usbnet *un, struct usbd_xfer *xfer, 970 struct usbnet_chain *c, uint32_t total_len) 971 { 972 struct ifnet *ifp = usbnet_ifp(un); 973 uint8_t *buf = c->unc_buf; 974 uint16_t pkt_len = 0; 975 uint16_t pkt_count = 0; 976 struct ure_rxpkt rxhdr; 977 978 usbnet_isowned_rx(un); 979 980 do { 981 if (total_len < sizeof(rxhdr)) { 982 DPRINTF(("too few bytes left for a packet header\n")); 983 ifp->if_ierrors++; 984 return; 985 } 986 987 buf += roundup(pkt_len, 8); 988 989 memcpy(&rxhdr, buf, sizeof(rxhdr)); 990 total_len -= sizeof(rxhdr); 991 992 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 993 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 994 if (pkt_len > total_len) { 995 DPRINTF(("not enough bytes left for next packet\n")); 996 ifp->if_ierrors++; 997 return; 998 } 999 1000 total_len -= roundup(pkt_len, 8); 1001 buf += sizeof(rxhdr); 1002 1003 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1004 ure_rxcsum(ifp, &rxhdr), 0, 0); 1005 1006 pkt_count++; 1007 1008 } while (total_len > 0); 1009 1010 if (pkt_count) 1011 rnd_add_uint32(&un->un_rndsrc, pkt_count); 1012 } 1013 1014 static int 1015 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1016 { 1017 int enabled = ifp->if_csum_flags_rx, flags = 0; 1018 uint32_t csum, misc; 1019 1020 if (enabled == 0) 1021 return 0; 1022 1023 csum = le32toh(rp->ure_csum); 1024 misc = le32toh(rp->ure_misc); 1025 1026 if (csum & URE_RXPKT_IPV4_CS) { 1027 flags |= M_CSUM_IPv4; 1028 if (csum & URE_RXPKT_TCP_CS) 1029 flags |= M_CSUM_TCPv4; 1030 if (csum & URE_RXPKT_UDP_CS) 1031 flags |= M_CSUM_UDPv4; 1032 } else if (csum & URE_RXPKT_IPV6_CS) { 1033 flags = 0; 1034 if (csum & URE_RXPKT_TCP_CS) 1035 flags |= M_CSUM_TCPv6; 1036 if (csum & URE_RXPKT_UDP_CS) 1037 flags |= M_CSUM_UDPv6; 1038 } 1039 1040 flags &= enabled; 1041 if (__predict_false((flags & M_CSUM_IPv4) && 1042 (misc & URE_RXPKT_IP_F))) 1043 flags |= M_CSUM_IPv4_BAD; 1044 if (__predict_false( 1045 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1046 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1047 )) 1048 flags |= M_CSUM_TCP_UDP_BAD; 1049 1050 return flags; 1051 } 1052 1053 static unsigned 1054 ure_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1055 { 1056 struct ure_txpkt txhdr; 1057 uint32_t frm_len = 0; 1058 uint8_t *buf = c->unc_buf; 1059 1060 usbnet_isowned_tx(un); 1061 1062 /* header */ 1063 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1064 URE_TXPKT_TX_LS); 1065 txhdr.ure_csum = htole32(ure_txcsum(m)); 1066 memcpy(buf, &txhdr, sizeof(txhdr)); 1067 buf += sizeof(txhdr); 1068 frm_len = sizeof(txhdr); 1069 1070 /* packet */ 1071 m_copydata(m, 0, m->m_pkthdr.len, buf); 1072 frm_len += m->m_pkthdr.len; 1073 1074 if (__predict_false(c->unc_xfer == NULL)) 1075 return EIO; /* XXX plugged out or down */ 1076 1077 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1078 1079 return frm_len; 1080 } 1081 1082 /* 1083 * We need to calculate L4 checksum in software, if the offset of 1084 * L4 header is larger than 0x7ff = 2047. 1085 */ 1086 static uint32_t 1087 ure_txcsum(struct mbuf *m) 1088 { 1089 struct ether_header *eh; 1090 int flags = m->m_pkthdr.csum_flags; 1091 uint32_t data = m->m_pkthdr.csum_data; 1092 uint32_t reg = 0; 1093 int l3off, l4off; 1094 uint16_t type; 1095 1096 if (flags == 0) 1097 return 0; 1098 1099 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1100 eh = mtod(m, struct ether_header *); 1101 type = eh->ether_type; 1102 } else 1103 m_copydata(m, offsetof(struct ether_header, ether_type), 1104 sizeof(type), &type); 1105 switch (type = htons(type)) { 1106 case ETHERTYPE_IP: 1107 case ETHERTYPE_IPV6: 1108 l3off = ETHER_HDR_LEN; 1109 break; 1110 case ETHERTYPE_VLAN: 1111 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1112 break; 1113 default: 1114 return 0; 1115 } 1116 1117 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1118 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1119 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1120 in_undefer_cksum(m, l3off, flags); 1121 return 0; 1122 } 1123 reg |= URE_TXPKT_IPV4_CS; 1124 if (flags & M_CSUM_TCPv4) 1125 reg |= URE_TXPKT_TCP_CS; 1126 else 1127 reg |= URE_TXPKT_UDP_CS; 1128 reg |= l4off << URE_L4_OFFSET_SHIFT; 1129 } 1130 #ifdef INET6 1131 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1132 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1133 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1134 in6_undefer_cksum(m, l3off, flags); 1135 return 0; 1136 } 1137 reg |= URE_TXPKT_IPV6_CS; 1138 if (flags & M_CSUM_TCPv6) 1139 reg |= URE_TXPKT_TCP_CS; 1140 else 1141 reg |= URE_TXPKT_UDP_CS; 1142 reg |= l4off << URE_L4_OFFSET_SHIFT; 1143 } 1144 #endif 1145 else if (flags & M_CSUM_IPv4) 1146 reg |= URE_TXPKT_IPV4_CS; 1147 1148 return reg; 1149 } 1150
Indexes created Thu Oct 02 01:09:59 GMT 2025