if_ure.c revision 1.19
1 /* $NetBSD: if_ure.c,v 1.19 2019/08/09 01:17:33 mrg Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.19 2019/08/09 01:17:33 mrg Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 44 #include <net/route.h> 45 46 #include <dev/usb/usbnet.h> 47 48 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 49 #ifdef INET6 50 #include <netinet/in.h> 51 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 52 #endif 53 54 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 55 #include <dev/usb/if_urereg.h> 56 #include <dev/usb/if_urevar.h> 57 58 #define URE_PRINTF(un, fmt, args...) \ 59 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 60 61 #define URE_DEBUG 62 #ifdef URE_DEBUG 63 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 65 int uredebug = 1; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 static const struct usb_devno ure_devs[] = { 72 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 73 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 74 }; 75 76 #define URE_BUFSZ (16 * 1024) 77 78 static void ure_reset(struct usbnet *); 79 static uint32_t ure_txcsum(struct mbuf *); 80 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 81 static void ure_rtl8152_init(struct ure_softc *); 82 static void ure_rtl8153_init(struct ure_softc *); 83 static void ure_disable_teredo(struct ure_softc *); 84 static void ure_init_fifo(struct ure_softc *); 85 86 static void ure_stop_cb(struct ifnet *, int); 87 static int ure_ioctl_cb(struct ifnet *, u_long, void *); 88 static usbd_status ure_mii_read_reg(struct usbnet *, int, int, uint16_t *); 89 static usbd_status ure_mii_write_reg(struct usbnet *, int, int, uint16_t); 90 static void ure_miibus_statchg(struct ifnet *); 91 static unsigned ure_tx_prepare(struct usbnet *, struct mbuf *, 92 struct usbnet_chain *); 93 static void ure_rxeof_loop(struct usbnet *, struct usbd_xfer *, 94 struct usbnet_chain *, uint32_t); 95 static int ure_init(struct ifnet *); 96 97 static int ure_match(device_t, cfdata_t, void *); 98 static void ure_attach(device_t, device_t, void *); 99 100 CFATTACH_DECL_NEW(ure, sizeof(struct ure_softc), ure_match, ure_attach, 101 usbnet_detach, usbnet_activate); 102 103 static struct usbnet_ops ure_ops = { 104 .uno_stop = ure_stop_cb, 105 .uno_ioctl = ure_ioctl_cb, 106 .uno_read_reg = ure_mii_read_reg, 107 .uno_write_reg = ure_mii_write_reg, 108 .uno_statchg = ure_miibus_statchg, 109 .uno_tx_prepare = ure_tx_prepare, 110 .uno_rx_loop = ure_rxeof_loop, 111 .uno_init = ure_init, 112 }; 113 114 static int 115 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 116 void *buf, int len) 117 { 118 usb_device_request_t req; 119 usbd_status err; 120 121 if (usbnet_isdying(un)) 122 return 0; 123 124 if (rw == URE_CTL_WRITE) 125 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 126 else 127 req.bmRequestType = UT_READ_VENDOR_DEVICE; 128 req.bRequest = UR_SET_ADDRESS; 129 USETW(req.wValue, val); 130 USETW(req.wIndex, index); 131 USETW(req.wLength, len); 132 133 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 134 rw, val, index, len)); 135 err = usbd_do_request(un->un_udev, &req, buf); 136 if (err) { 137 DPRINTF(("ure_ctl: error %d\n", err)); 138 return -1; 139 } 140 141 return 0; 142 } 143 144 static int 145 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 146 void *buf, int len) 147 { 148 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 149 } 150 151 static int 152 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 153 void *buf, int len) 154 { 155 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 156 } 157 158 static uint8_t 159 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 160 { 161 uint32_t val; 162 uint8_t temp[4]; 163 uint8_t shift; 164 165 shift = (reg & 3) << 3; 166 reg &= ~3; 167 168 ure_read_mem(un, reg, index, &temp, 4); 169 val = UGETDW(temp); 170 val >>= shift; 171 172 return val & 0xff; 173 } 174 175 static uint16_t 176 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 177 { 178 uint32_t val; 179 uint8_t temp[4]; 180 uint8_t shift; 181 182 shift = (reg & 2) << 3; 183 reg &= ~3; 184 185 ure_read_mem(un, reg, index, &temp, 4); 186 val = UGETDW(temp); 187 val >>= shift; 188 189 return val & 0xffff; 190 } 191 192 static uint32_t 193 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 194 { 195 uint8_t temp[4]; 196 197 ure_read_mem(un, reg, index, &temp, 4); 198 return UGETDW(temp); 199 } 200 201 static int 202 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 203 { 204 uint16_t byen; 205 uint8_t temp[4]; 206 uint8_t shift; 207 208 byen = URE_BYTE_EN_BYTE; 209 shift = reg & 3; 210 val &= 0xff; 211 212 if (reg & 3) { 213 byen <<= shift; 214 val <<= (shift << 3); 215 reg &= ~3; 216 } 217 218 USETDW(temp, val); 219 return ure_write_mem(un, reg, index | byen, &temp, 4); 220 } 221 222 static int 223 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 224 { 225 uint16_t byen; 226 uint8_t temp[4]; 227 uint8_t shift; 228 229 byen = URE_BYTE_EN_WORD; 230 shift = reg & 2; 231 val &= 0xffff; 232 233 if (reg & 2) { 234 byen <<= shift; 235 val <<= (shift << 3); 236 reg &= ~3; 237 } 238 239 USETDW(temp, val); 240 return ure_write_mem(un, reg, index | byen, &temp, 4); 241 } 242 243 static int 244 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 245 { 246 uint8_t temp[4]; 247 248 USETDW(temp, val); 249 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 250 } 251 252 static uint16_t 253 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 254 { 255 uint16_t reg; 256 257 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 258 reg = (addr & 0x0fff) | 0xb000; 259 260 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 261 } 262 263 static void 264 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 265 { 266 uint16_t reg; 267 268 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 269 reg = (addr & 0x0fff) | 0xb000; 270 271 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 272 } 273 274 static usbd_status 275 ure_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 276 { 277 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 278 if (reg == RTK_GMEDIASTAT) { 279 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 280 return USBD_NORMAL_COMPLETION; 281 } 282 283 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 284 285 return USBD_NORMAL_COMPLETION; 286 } 287 288 static usbd_status 289 ure_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 290 { 291 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 292 293 return USBD_NORMAL_COMPLETION; 294 } 295 296 static void 297 ure_miibus_statchg(struct ifnet *ifp) 298 { 299 struct usbnet * const un = ifp->if_softc; 300 struct ure_softc * const sc = usbnet_softc(un); 301 struct mii_data * const mii = usbnet_mii(un); 302 303 if (usbnet_isdying(un)) 304 return; 305 306 un->un_link = false; 307 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 308 (IFM_ACTIVE | IFM_AVALID)) { 309 switch (IFM_SUBTYPE(mii->mii_media_active)) { 310 case IFM_10_T: 311 case IFM_100_TX: 312 un->un_link = true; 313 break; 314 case IFM_1000_T: 315 if ((sc->ure_flags & URE_FLAG_8152) != 0) 316 break; 317 un->un_link = true; 318 break; 319 default: 320 break; 321 } 322 } 323 } 324 325 static void 326 ure_setiff_locked(struct usbnet *un) 327 { 328 struct ethercom *ec = usbnet_ec(un); 329 struct ifnet *ifp = usbnet_ifp(un); 330 struct ether_multi *enm; 331 struct ether_multistep step; 332 uint32_t hashes[2] = { 0, 0 }; 333 uint32_t hash; 334 uint32_t rxmode; 335 336 usbnet_isowned(un); 337 338 if (usbnet_isdying(un)) 339 return; 340 341 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 342 rxmode &= ~URE_RCR_ACPT_ALL; 343 344 /* 345 * Always accept frames destined to our station address. 346 * Always accept broadcast frames. 347 */ 348 rxmode |= URE_RCR_APM | URE_RCR_AB; 349 350 if (ifp->if_flags & IFF_PROMISC) { 351 rxmode |= URE_RCR_AAP; 352 allmulti: 353 ETHER_LOCK(ec); 354 ec->ec_flags |= ETHER_F_ALLMULTI; 355 ETHER_UNLOCK(ec); 356 rxmode |= URE_RCR_AM; 357 hashes[0] = hashes[1] = 0xffffffff; 358 } else { 359 rxmode |= URE_RCR_AM; 360 361 ETHER_LOCK(ec); 362 ec->ec_flags &= ~ETHER_F_ALLMULTI; 363 364 ETHER_FIRST_MULTI(step, ec, enm); 365 while (enm != NULL) { 366 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 367 ETHER_ADDR_LEN)) { 368 ETHER_UNLOCK(ec); 369 goto allmulti; 370 } 371 372 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 373 >> 26; 374 if (hash < 32) 375 hashes[0] |= (1 << hash); 376 else 377 hashes[1] |= (1 << (hash - 32)); 378 379 ETHER_NEXT_MULTI(step, enm); 380 } 381 ETHER_UNLOCK(ec); 382 383 hash = bswap32(hashes[0]); 384 hashes[0] = bswap32(hashes[1]); 385 hashes[1] = hash; 386 } 387 388 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 389 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 390 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 391 } 392 393 static void 394 ure_setiff(struct usbnet *un) 395 { 396 397 usbnet_lock(un); 398 ure_setiff_locked(un); 399 usbnet_unlock(un); 400 } 401 402 static void 403 ure_reset(struct usbnet *un) 404 { 405 int i; 406 407 usbnet_isowned(un); 408 409 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 410 411 for (i = 0; i < URE_TIMEOUT; i++) { 412 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 413 URE_CR_RST)) 414 break; 415 usbd_delay_ms(un->un_udev, 10); 416 } 417 if (i == URE_TIMEOUT) 418 URE_PRINTF(un, "reset never completed\n"); 419 } 420 421 static int 422 ure_init_locked(struct ifnet *ifp) 423 { 424 struct usbnet * const un = ifp->if_softc; 425 uint8_t eaddr[8]; 426 427 usbnet_isowned(un); 428 429 if (usbnet_isdying(un)) 430 return EIO; 431 432 /* Cancel pending I/O. */ 433 if (ifp->if_flags & IFF_RUNNING) 434 usbnet_stop(un, ifp, 1); 435 436 /* Set MAC address. */ 437 memset(eaddr, 0, sizeof(eaddr)); 438 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 439 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 440 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 441 eaddr, 8); 442 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 443 444 /* Reset the packet filter. */ 445 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 446 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 447 ~URE_FMC_FCR_MCU_EN); 448 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 449 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 450 URE_FMC_FCR_MCU_EN); 451 452 /* Enable transmit and receive. */ 453 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 454 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 455 URE_CR_TE); 456 457 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 458 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 459 ~URE_RXDY_GATED_EN); 460 461 /* Load the multicast filter. */ 462 ure_setiff_locked(un); 463 464 return usbnet_init_rx_tx(un); 465 } 466 467 static int 468 ure_init(struct ifnet *ifp) 469 { 470 struct usbnet * const un = ifp->if_softc; 471 472 usbnet_lock(un); 473 int ret = ure_init_locked(ifp); 474 usbnet_unlock(un); 475 476 return ret; 477 } 478 479 static void 480 ure_stop_cb(struct ifnet *ifp, int disable __unused) 481 { 482 struct usbnet * const un = ifp->if_softc; 483 484 ure_reset(un); 485 } 486 487 static void 488 ure_rtl8152_init(struct ure_softc *sc) 489 { 490 struct usbnet * const un = &sc->ure_un; 491 uint32_t pwrctrl; 492 493 /* Disable ALDPS. */ 494 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 495 URE_DIS_SDSAVE); 496 usbd_delay_ms(un->un_udev, 20); 497 498 if (sc->ure_chip & URE_CHIP_VER_4C00) { 499 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 500 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 501 ~URE_LED_MODE_MASK); 502 } 503 504 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 505 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 506 ~URE_POWER_CUT); 507 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 508 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 509 ~URE_RESUME_INDICATE); 510 511 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 512 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 513 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 514 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 515 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 516 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 517 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 518 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 519 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 520 URE_SPDWN_LINKCHG_MSK); 521 522 /* Enable Rx aggregation. */ 523 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 524 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 525 ~URE_RX_AGG_DISABLE); 526 527 /* Disable ALDPS. */ 528 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 529 URE_DIS_SDSAVE); 530 usbd_delay_ms(un->un_udev, 20); 531 532 ure_init_fifo(sc); 533 534 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 535 URE_TX_AGG_MAX_THRESHOLD); 536 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 537 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 538 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 539 } 540 541 static void 542 ure_rtl8153_init(struct ure_softc *sc) 543 { 544 struct usbnet * const un = &sc->ure_un; 545 uint16_t val; 546 uint8_t u1u2[8]; 547 int i; 548 549 /* Disable ALDPS. */ 550 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 551 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 552 usbd_delay_ms(un->un_udev, 20); 553 554 memset(u1u2, 0x00, sizeof(u1u2)); 555 ure_write_mem(un, URE_USB_TOLERANCE, 556 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 557 558 for (i = 0; i < URE_TIMEOUT; i++) { 559 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 560 URE_AUTOLOAD_DONE) 561 break; 562 usbd_delay_ms(un->un_udev, 10); 563 } 564 if (i == URE_TIMEOUT) 565 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 566 567 for (i = 0; i < URE_TIMEOUT; i++) { 568 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 569 URE_PHY_STAT_MASK; 570 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 571 break; 572 usbd_delay_ms(un->un_udev, 10); 573 } 574 if (i == URE_TIMEOUT) 575 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 576 577 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 578 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 579 ~URE_U2P3_ENABLE); 580 581 if (sc->ure_chip & URE_CHIP_VER_5C10) { 582 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 583 val &= ~URE_PWD_DN_SCALE_MASK; 584 val |= URE_PWD_DN_SCALE(96); 585 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 586 587 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 588 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 589 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 590 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 591 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 592 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 593 ~URE_ECM_ALDPS); 594 } 595 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 596 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 597 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 598 0) 599 val &= ~URE_DYNAMIC_BURST; 600 else 601 val |= URE_DYNAMIC_BURST; 602 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 603 } 604 605 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 606 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 607 URE_EP4_FULL_FC); 608 609 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 610 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 611 ~URE_TIMER11_EN); 612 613 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 614 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 615 ~URE_LED_MODE_MASK); 616 617 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 618 un->un_udev->ud_speed != USB_SPEED_SUPER) 619 val = URE_LPM_TIMER_500MS; 620 else 621 val = URE_LPM_TIMER_500US; 622 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 623 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 624 625 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 626 val &= ~URE_SEN_VAL_MASK; 627 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 628 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 629 630 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 631 632 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 633 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 634 ~(URE_PWR_EN | URE_PHASE2_EN)); 635 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 636 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 637 ~URE_PCUT_STATUS); 638 639 memset(u1u2, 0xff, sizeof(u1u2)); 640 ure_write_mem(un, URE_USB_TOLERANCE, 641 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 642 643 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 644 URE_ALDPS_SPDWN_RATIO); 645 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 646 URE_EEE_SPDWN_RATIO); 647 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 648 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 649 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 650 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 651 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 652 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 653 URE_EEE_SPDWN_EN); 654 655 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 656 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 657 val |= URE_U2P3_ENABLE; 658 else 659 val &= ~URE_U2P3_ENABLE; 660 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 661 662 memset(u1u2, 0x00, sizeof(u1u2)); 663 ure_write_mem(un, URE_USB_TOLERANCE, 664 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 665 666 /* Disable ALDPS. */ 667 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 668 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 669 usbd_delay_ms(un->un_udev, 20); 670 671 ure_init_fifo(sc); 672 673 /* Enable Rx aggregation. */ 674 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 675 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 676 ~URE_RX_AGG_DISABLE); 677 678 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 679 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 680 val |= URE_U2P3_ENABLE; 681 else 682 val &= ~URE_U2P3_ENABLE; 683 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 684 685 memset(u1u2, 0xff, sizeof(u1u2)); 686 ure_write_mem(un, URE_USB_TOLERANCE, 687 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 688 } 689 690 static void 691 ure_disable_teredo(struct ure_softc *sc) 692 { 693 struct usbnet * const un = &sc->ure_un; 694 695 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 696 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 697 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 698 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 699 URE_WDT6_SET_MODE); 700 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 701 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 702 } 703 704 static void 705 ure_init_fifo(struct ure_softc *sc) 706 { 707 struct usbnet * const un = &sc->ure_un; 708 uint32_t rx_fifo1, rx_fifo2; 709 int i; 710 711 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 712 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 713 URE_RXDY_GATED_EN); 714 715 ure_disable_teredo(sc); 716 717 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, 718 ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 719 ~URE_RCR_ACPT_ALL); 720 721 if (!(sc->ure_flags & URE_FLAG_8152)) { 722 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 723 URE_CHIP_VER_5C20)) 724 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 725 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 726 if (sc->ure_chip & URE_CHIP_VER_5C00) 727 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 728 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 729 ~URE_CTAP_SHORT_EN); 730 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 731 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 732 URE_EEE_CLKDIV_EN); 733 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 734 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 735 URE_EN_10M_BGOFF); 736 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 737 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 738 URE_EN_10M_PLLOFF); 739 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 740 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 741 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 742 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 743 URE_PFM_PWM_SWITCH); 744 745 /* Enable LPF corner auto tune. */ 746 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 747 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 748 749 /* Adjust 10M amplitude. */ 750 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 751 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 752 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 753 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 754 } 755 756 ure_reset(un); 757 758 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 759 760 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 761 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 762 ~URE_NOW_IS_OOB); 763 764 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 765 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 766 ~URE_MCU_BORW_EN); 767 for (i = 0; i < URE_TIMEOUT; i++) { 768 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 769 URE_LINK_LIST_READY) 770 break; 771 usbd_delay_ms(un->un_udev, 10); 772 } 773 if (i == URE_TIMEOUT) 774 URE_PRINTF(un, "timeout waiting for OOB control\n"); 775 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 776 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 777 URE_RE_INIT_LL); 778 for (i = 0; i < URE_TIMEOUT; i++) { 779 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 780 URE_LINK_LIST_READY) 781 break; 782 usbd_delay_ms(un->un_udev, 10); 783 } 784 if (i == URE_TIMEOUT) 785 URE_PRINTF(un, "timeout waiting for OOB control\n"); 786 787 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 788 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 789 ~URE_CPCR_RX_VLAN); 790 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 791 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 792 URE_TCR0_AUTO_FIFO); 793 794 /* Configure Rx FIFO threshold and coalescing. */ 795 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 796 URE_RXFIFO_THR1_NORMAL); 797 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 798 rx_fifo1 = URE_RXFIFO_THR2_FULL; 799 rx_fifo2 = URE_RXFIFO_THR3_FULL; 800 } else { 801 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 802 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 803 } 804 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 805 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 806 807 /* Configure Tx FIFO threshold. */ 808 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 809 URE_TXFIFO_THR_NORMAL); 810 } 811 812 static int 813 ure_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data) 814 { 815 struct usbnet * const un = ifp->if_softc; 816 817 switch (cmd) { 818 case SIOCADDMULTI: 819 case SIOCDELMULTI: 820 ure_setiff(un); 821 break; 822 default: 823 break; 824 } 825 826 return 0; 827 } 828 829 static int 830 ure_match(device_t parent, cfdata_t match, void *aux) 831 { 832 struct usb_attach_arg *uaa = aux; 833 834 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 835 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 836 } 837 838 static void 839 ure_attach(device_t parent, device_t self, void *aux) 840 { 841 struct ure_softc *sc = device_private(self); 842 struct usbnet * const un = &sc->ure_un; 843 struct usb_attach_arg *uaa = aux; 844 struct usbd_device *dev = uaa->uaa_device; 845 usb_interface_descriptor_t *id; 846 usb_endpoint_descriptor_t *ed; 847 int error, i; 848 uint16_t ver; 849 uint8_t eaddr[8]; /* 2byte padded */ 850 char *devinfop; 851 852 /* Switch to usbnet for device_private() */ 853 self->dv_private = un; 854 855 aprint_naive("\n"); 856 aprint_normal("\n"); 857 devinfop = usbd_devinfo_alloc(dev, 0); 858 aprint_normal_dev(self, "%s\n", devinfop); 859 usbd_devinfo_free(devinfop); 860 861 un->un_dev = self; 862 un->un_udev = dev; 863 un->un_sc = sc; 864 un->un_ops = &ure_ops; 865 866 #define URE_CONFIG_NO 1 /* XXX */ 867 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 868 if (error) { 869 aprint_error_dev(self, "failed to set configuration: %s\n", 870 usbd_errstr(error)); 871 return; /* XXX */ 872 } 873 874 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 875 sc->ure_flags |= URE_FLAG_8152; 876 877 #define URE_IFACE_IDX 0 /* XXX */ 878 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 879 if (error) { 880 aprint_error_dev(self, "failed to get interface handle: %s\n", 881 usbd_errstr(error)); 882 return; /* XXX */ 883 } 884 885 id = usbd_get_interface_descriptor(un->un_iface); 886 for (i = 0; i < id->bNumEndpoints; i++) { 887 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 888 if (ed == NULL) { 889 aprint_error_dev(self, "couldn't get ep %d\n", i); 890 return; /* XXX */ 891 } 892 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 893 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 894 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 895 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 896 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 897 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 898 } 899 } 900 901 /* Set these up now for ure_ctl(). */ 902 usbnet_attach(un, "uredet", URE_RX_LIST_CNT, URE_TX_LIST_CNT, 903 USBD_SHORT_XFER_OK, USBD_FORCE_SHORT_XFER, 904 URE_BUFSZ, URE_BUFSZ); 905 906 un->un_phyno = 0; 907 908 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 909 switch (ver) { 910 case 0x4c00: 911 sc->ure_chip |= URE_CHIP_VER_4C00; 912 break; 913 case 0x4c10: 914 sc->ure_chip |= URE_CHIP_VER_4C10; 915 break; 916 case 0x5c00: 917 sc->ure_chip |= URE_CHIP_VER_5C00; 918 break; 919 case 0x5c10: 920 sc->ure_chip |= URE_CHIP_VER_5C10; 921 break; 922 case 0x5c20: 923 sc->ure_chip |= URE_CHIP_VER_5C20; 924 break; 925 case 0x5c30: 926 sc->ure_chip |= URE_CHIP_VER_5C30; 927 break; 928 default: 929 /* fake addr? or just fail? */ 930 break; 931 } 932 aprint_normal_dev(self, "RTL%d %sver %04x\n", 933 (sc->ure_flags & URE_FLAG_8152) ? 8152 : 8153, 934 (sc->ure_chip != 0) ? "" : "unknown ", 935 ver); 936 937 usbnet_lock(un); 938 if (sc->ure_flags & URE_FLAG_8152) 939 ure_rtl8152_init(sc); 940 else 941 ure_rtl8153_init(sc); 942 943 if (sc->ure_chip & URE_CHIP_VER_4C00) 944 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 945 sizeof(eaddr)); 946 else 947 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 948 sizeof(eaddr)); 949 usbnet_unlock(un); 950 memcpy(un->un_eaddr, eaddr, sizeof un->un_eaddr); 951 952 struct ifnet *ifp = usbnet_ifp(un); 953 954 /* 955 * We don't support TSOv4 and v6 for now, that are required to 956 * be handled in software for some cases. 957 */ 958 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 959 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 960 #ifdef INET6 961 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 962 #endif 963 if (sc->ure_chip & ~URE_CHIP_VER_4C00) { 964 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 965 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 966 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 967 } 968 struct ethercom *ec = usbnet_ec(un); 969 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 970 #ifdef notyet 971 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 972 #endif 973 974 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 975 0, 0); 976 } 977 978 static void 979 ure_rxeof_loop(struct usbnet *un, struct usbd_xfer *xfer, 980 struct usbnet_chain *c, uint32_t total_len) 981 { 982 struct ifnet *ifp = usbnet_ifp(un); 983 uint8_t *buf = c->unc_buf; 984 uint16_t pkt_len = 0; 985 uint16_t pkt_count = 0; 986 struct ure_rxpkt rxhdr; 987 988 usbnet_isowned_rx(un); 989 990 do { 991 if (total_len < sizeof(rxhdr)) { 992 DPRINTF(("too few bytes left for a packet header\n")); 993 ifp->if_ierrors++; 994 return; 995 } 996 997 buf += roundup(pkt_len, 8); 998 999 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1000 total_len -= sizeof(rxhdr); 1001 1002 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1003 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 1004 if (pkt_len > total_len) { 1005 DPRINTF(("not enough bytes left for next packet\n")); 1006 ifp->if_ierrors++; 1007 return; 1008 } 1009 1010 total_len -= roundup(pkt_len, 8); 1011 buf += sizeof(rxhdr); 1012 1013 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1014 ure_rxcsum(ifp, &rxhdr), 0, 0); 1015 1016 pkt_count++; 1017 1018 } while (total_len > 0); 1019 1020 if (pkt_count) 1021 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 1022 } 1023 1024 static int 1025 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1026 { 1027 int enabled = ifp->if_csum_flags_rx, flags = 0; 1028 uint32_t csum, misc; 1029 1030 if (enabled == 0) 1031 return 0; 1032 1033 csum = le32toh(rp->ure_csum); 1034 misc = le32toh(rp->ure_misc); 1035 1036 if (csum & URE_RXPKT_IPV4_CS) { 1037 flags |= M_CSUM_IPv4; 1038 if (csum & URE_RXPKT_TCP_CS) 1039 flags |= M_CSUM_TCPv4; 1040 if (csum & URE_RXPKT_UDP_CS) 1041 flags |= M_CSUM_UDPv4; 1042 } else if (csum & URE_RXPKT_IPV6_CS) { 1043 flags = 0; 1044 if (csum & URE_RXPKT_TCP_CS) 1045 flags |= M_CSUM_TCPv6; 1046 if (csum & URE_RXPKT_UDP_CS) 1047 flags |= M_CSUM_UDPv6; 1048 } 1049 1050 flags &= enabled; 1051 if (__predict_false((flags & M_CSUM_IPv4) && 1052 (misc & URE_RXPKT_IP_F))) 1053 flags |= M_CSUM_IPv4_BAD; 1054 if (__predict_false( 1055 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1056 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1057 )) 1058 flags |= M_CSUM_TCP_UDP_BAD; 1059 1060 return flags; 1061 } 1062 1063 static unsigned 1064 ure_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1065 { 1066 struct ure_txpkt txhdr; 1067 uint32_t frm_len = 0; 1068 uint8_t *buf = c->unc_buf; 1069 1070 usbnet_isowned_tx(un); 1071 1072 /* header */ 1073 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1074 URE_TXPKT_TX_LS); 1075 txhdr.ure_csum = htole32(ure_txcsum(m)); 1076 memcpy(buf, &txhdr, sizeof(txhdr)); 1077 buf += sizeof(txhdr); 1078 frm_len = sizeof(txhdr); 1079 1080 /* packet */ 1081 m_copydata(m, 0, m->m_pkthdr.len, buf); 1082 frm_len += m->m_pkthdr.len; 1083 1084 if (__predict_false(c->unc_xfer == NULL)) 1085 return EIO; /* XXX plugged out or down */ 1086 1087 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1088 1089 return frm_len; 1090 } 1091 1092 /* 1093 * We need to calculate L4 checksum in software, if the offset of 1094 * L4 header is larger than 0x7ff = 2047. 1095 */ 1096 static uint32_t 1097 ure_txcsum(struct mbuf *m) 1098 { 1099 struct ether_header *eh; 1100 int flags = m->m_pkthdr.csum_flags; 1101 uint32_t data = m->m_pkthdr.csum_data; 1102 uint32_t reg = 0; 1103 int l3off, l4off; 1104 uint16_t type; 1105 1106 if (flags == 0) 1107 return 0; 1108 1109 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1110 eh = mtod(m, struct ether_header *); 1111 type = eh->ether_type; 1112 } else 1113 m_copydata(m, offsetof(struct ether_header, ether_type), 1114 sizeof(type), &type); 1115 switch (type = htons(type)) { 1116 case ETHERTYPE_IP: 1117 case ETHERTYPE_IPV6: 1118 l3off = ETHER_HDR_LEN; 1119 break; 1120 case ETHERTYPE_VLAN: 1121 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1122 break; 1123 default: 1124 return 0; 1125 } 1126 1127 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1128 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1129 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1130 in_undefer_cksum(m, l3off, flags); 1131 return 0; 1132 } 1133 reg |= URE_TXPKT_IPV4_CS; 1134 if (flags & M_CSUM_TCPv4) 1135 reg |= URE_TXPKT_TCP_CS; 1136 else 1137 reg |= URE_TXPKT_UDP_CS; 1138 reg |= l4off << URE_L4_OFFSET_SHIFT; 1139 } 1140 #ifdef INET6 1141 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1142 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1143 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1144 in6_undefer_cksum(m, l3off, flags); 1145 return 0; 1146 } 1147 reg |= URE_TXPKT_IPV6_CS; 1148 if (flags & M_CSUM_TCPv6) 1149 reg |= URE_TXPKT_TCP_CS; 1150 else 1151 reg |= URE_TXPKT_UDP_CS; 1152 reg |= l4off << URE_L4_OFFSET_SHIFT; 1153 } 1154 #endif 1155 else if (flags & M_CSUM_IPv4) 1156 reg |= URE_TXPKT_IPV4_CS; 1157 1158 return reg; 1159 } 1160
Indexes created Mon Sep 29 21:09:56 GMT 2025