if_ure.c revision 1.25
1 /* $NetBSD: if_ure.c,v 1.25 2019/08/11 23:55:43 mrg Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.25 2019/08/11 23:55:43 mrg Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 44 #include <net/route.h> 45 46 #include <dev/usb/usbnet.h> 47 48 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 49 #ifdef INET6 50 #include <netinet/in.h> 51 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 52 #endif 53 54 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 55 #include <dev/usb/if_urereg.h> 56 #include <dev/usb/if_urevar.h> 57 58 #define URE_PRINTF(un, fmt, args...) \ 59 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 60 61 #define URE_DEBUG 62 #ifdef URE_DEBUG 63 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 65 int uredebug = 1; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 static const struct usb_devno ure_devs[] = { 72 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 73 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 74 }; 75 76 #define URE_BUFSZ (16 * 1024) 77 78 static void ure_reset(struct usbnet *); 79 static uint32_t ure_txcsum(struct mbuf *); 80 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 81 static void ure_rtl8152_init(struct usbnet *); 82 static void ure_rtl8153_init(struct usbnet *); 83 static void ure_disable_teredo(struct usbnet *); 84 static void ure_init_fifo(struct usbnet *); 85 86 static void ure_stop_cb(struct ifnet *, int); 87 static int ure_ioctl_cb(struct ifnet *, u_long, void *); 88 static usbd_status ure_mii_read_reg(struct usbnet *, int, int, uint16_t *); 89 static usbd_status ure_mii_write_reg(struct usbnet *, int, int, uint16_t); 90 static void ure_miibus_statchg(struct ifnet *); 91 static unsigned ure_tx_prepare(struct usbnet *, struct mbuf *, 92 struct usbnet_chain *); 93 static void ure_rxeof_loop(struct usbnet *, struct usbd_xfer *, 94 struct usbnet_chain *, uint32_t); 95 static int ure_init(struct ifnet *); 96 97 static int ure_match(device_t, cfdata_t, void *); 98 static void ure_attach(device_t, device_t, void *); 99 100 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 101 usbnet_detach, usbnet_activate); 102 103 static struct usbnet_ops ure_ops = { 104 .uno_stop = ure_stop_cb, 105 .uno_ioctl = ure_ioctl_cb, 106 .uno_read_reg = ure_mii_read_reg, 107 .uno_write_reg = ure_mii_write_reg, 108 .uno_statchg = ure_miibus_statchg, 109 .uno_tx_prepare = ure_tx_prepare, 110 .uno_rx_loop = ure_rxeof_loop, 111 .uno_init = ure_init, 112 }; 113 114 static int 115 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 116 void *buf, int len) 117 { 118 usb_device_request_t req; 119 usbd_status err; 120 121 if (usbnet_isdying(un)) 122 return 0; 123 124 if (rw == URE_CTL_WRITE) 125 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 126 else 127 req.bmRequestType = UT_READ_VENDOR_DEVICE; 128 req.bRequest = UR_SET_ADDRESS; 129 USETW(req.wValue, val); 130 USETW(req.wIndex, index); 131 USETW(req.wLength, len); 132 133 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 134 rw, val, index, len)); 135 err = usbd_do_request(un->un_udev, &req, buf); 136 if (err) { 137 DPRINTF(("ure_ctl: error %d\n", err)); 138 return -1; 139 } 140 141 return 0; 142 } 143 144 static int 145 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 146 void *buf, int len) 147 { 148 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 149 } 150 151 static int 152 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 153 void *buf, int len) 154 { 155 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 156 } 157 158 static uint8_t 159 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 160 { 161 uint32_t val; 162 uint8_t temp[4]; 163 uint8_t shift; 164 165 shift = (reg & 3) << 3; 166 reg &= ~3; 167 168 ure_read_mem(un, reg, index, &temp, 4); 169 val = UGETDW(temp); 170 val >>= shift; 171 172 return val & 0xff; 173 } 174 175 static uint16_t 176 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 177 { 178 uint32_t val; 179 uint8_t temp[4]; 180 uint8_t shift; 181 182 shift = (reg & 2) << 3; 183 reg &= ~3; 184 185 ure_read_mem(un, reg, index, &temp, 4); 186 val = UGETDW(temp); 187 val >>= shift; 188 189 return val & 0xffff; 190 } 191 192 static uint32_t 193 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 194 { 195 uint8_t temp[4]; 196 197 ure_read_mem(un, reg, index, &temp, 4); 198 return UGETDW(temp); 199 } 200 201 static int 202 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 203 { 204 uint16_t byen; 205 uint8_t temp[4]; 206 uint8_t shift; 207 208 byen = URE_BYTE_EN_BYTE; 209 shift = reg & 3; 210 val &= 0xff; 211 212 if (reg & 3) { 213 byen <<= shift; 214 val <<= (shift << 3); 215 reg &= ~3; 216 } 217 218 USETDW(temp, val); 219 return ure_write_mem(un, reg, index | byen, &temp, 4); 220 } 221 222 static int 223 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 224 { 225 uint16_t byen; 226 uint8_t temp[4]; 227 uint8_t shift; 228 229 byen = URE_BYTE_EN_WORD; 230 shift = reg & 2; 231 val &= 0xffff; 232 233 if (reg & 2) { 234 byen <<= shift; 235 val <<= (shift << 3); 236 reg &= ~3; 237 } 238 239 USETDW(temp, val); 240 return ure_write_mem(un, reg, index | byen, &temp, 4); 241 } 242 243 static int 244 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 245 { 246 uint8_t temp[4]; 247 248 USETDW(temp, val); 249 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 250 } 251 252 static uint16_t 253 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 254 { 255 uint16_t reg; 256 257 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 258 reg = (addr & 0x0fff) | 0xb000; 259 260 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 261 } 262 263 static void 264 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 265 { 266 uint16_t reg; 267 268 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 269 reg = (addr & 0x0fff) | 0xb000; 270 271 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 272 } 273 274 static usbd_status 275 ure_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 276 { 277 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 278 if (reg == RTK_GMEDIASTAT) { 279 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 280 return USBD_NORMAL_COMPLETION; 281 } 282 283 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 284 285 return USBD_NORMAL_COMPLETION; 286 } 287 288 static usbd_status 289 ure_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 290 { 291 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 292 293 return USBD_NORMAL_COMPLETION; 294 } 295 296 static void 297 ure_miibus_statchg(struct ifnet *ifp) 298 { 299 struct usbnet * const un = ifp->if_softc; 300 struct mii_data * const mii = usbnet_mii(un); 301 302 if (usbnet_isdying(un)) 303 return; 304 305 usbnet_set_link(un, false); 306 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 307 (IFM_ACTIVE | IFM_AVALID)) { 308 switch (IFM_SUBTYPE(mii->mii_media_active)) { 309 case IFM_10_T: 310 case IFM_100_TX: 311 usbnet_set_link(un, true); 312 break; 313 case IFM_1000_T: 314 if ((un->un_flags & URE_FLAG_8152) != 0) 315 break; 316 usbnet_set_link(un, true); 317 break; 318 default: 319 break; 320 } 321 } 322 } 323 324 static void 325 ure_setiff_locked(struct usbnet *un) 326 { 327 struct ethercom *ec = usbnet_ec(un); 328 struct ifnet *ifp = usbnet_ifp(un); 329 struct ether_multi *enm; 330 struct ether_multistep step; 331 uint32_t hashes[2] = { 0, 0 }; 332 uint32_t hash; 333 uint32_t rxmode; 334 335 usbnet_isowned(un); 336 337 if (usbnet_isdying(un)) 338 return; 339 340 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 341 rxmode &= ~URE_RCR_ACPT_ALL; 342 343 /* 344 * Always accept frames destined to our station address. 345 * Always accept broadcast frames. 346 */ 347 rxmode |= URE_RCR_APM | URE_RCR_AB; 348 349 if (ifp->if_flags & IFF_PROMISC) { 350 rxmode |= URE_RCR_AAP; 351 allmulti: 352 ETHER_LOCK(ec); 353 ec->ec_flags |= ETHER_F_ALLMULTI; 354 ETHER_UNLOCK(ec); 355 rxmode |= URE_RCR_AM; 356 hashes[0] = hashes[1] = 0xffffffff; 357 } else { 358 rxmode |= URE_RCR_AM; 359 360 ETHER_LOCK(ec); 361 ec->ec_flags &= ~ETHER_F_ALLMULTI; 362 363 ETHER_FIRST_MULTI(step, ec, enm); 364 while (enm != NULL) { 365 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 366 ETHER_ADDR_LEN)) { 367 ETHER_UNLOCK(ec); 368 goto allmulti; 369 } 370 371 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 372 >> 26; 373 if (hash < 32) 374 hashes[0] |= (1 << hash); 375 else 376 hashes[1] |= (1 << (hash - 32)); 377 378 ETHER_NEXT_MULTI(step, enm); 379 } 380 ETHER_UNLOCK(ec); 381 382 hash = bswap32(hashes[0]); 383 hashes[0] = bswap32(hashes[1]); 384 hashes[1] = hash; 385 } 386 387 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 388 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 389 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 390 } 391 392 static void 393 ure_setiff(struct usbnet *un) 394 { 395 396 usbnet_lock(un); 397 ure_setiff_locked(un); 398 usbnet_unlock(un); 399 } 400 401 static void 402 ure_reset(struct usbnet *un) 403 { 404 int i; 405 406 usbnet_isowned(un); 407 408 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 409 410 for (i = 0; i < URE_TIMEOUT; i++) { 411 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 412 URE_CR_RST)) 413 break; 414 usbd_delay_ms(un->un_udev, 10); 415 } 416 if (i == URE_TIMEOUT) 417 URE_PRINTF(un, "reset never completed\n"); 418 } 419 420 static int 421 ure_init_locked(struct ifnet *ifp) 422 { 423 struct usbnet * const un = ifp->if_softc; 424 uint8_t eaddr[8]; 425 426 usbnet_isowned(un); 427 428 if (usbnet_isdying(un)) 429 return EIO; 430 431 /* Cancel pending I/O. */ 432 if (ifp->if_flags & IFF_RUNNING) 433 usbnet_stop(un, ifp, 1); 434 435 /* Set MAC address. */ 436 memset(eaddr, 0, sizeof(eaddr)); 437 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 438 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 439 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 440 eaddr, 8); 441 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 442 443 /* Reset the packet filter. */ 444 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 445 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 446 ~URE_FMC_FCR_MCU_EN); 447 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 448 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 449 URE_FMC_FCR_MCU_EN); 450 451 /* Enable transmit and receive. */ 452 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 453 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 454 URE_CR_TE); 455 456 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 457 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 458 ~URE_RXDY_GATED_EN); 459 460 /* Load the multicast filter. */ 461 ure_setiff_locked(un); 462 463 return usbnet_init_rx_tx(un); 464 } 465 466 static int 467 ure_init(struct ifnet *ifp) 468 { 469 struct usbnet * const un = ifp->if_softc; 470 471 usbnet_lock(un); 472 int ret = ure_init_locked(ifp); 473 usbnet_unlock(un); 474 475 return ret; 476 } 477 478 static void 479 ure_stop_cb(struct ifnet *ifp, int disable __unused) 480 { 481 struct usbnet * const un = ifp->if_softc; 482 483 ure_reset(un); 484 } 485 486 static void 487 ure_rtl8152_init(struct usbnet *un) 488 { 489 uint32_t pwrctrl; 490 491 /* Disable ALDPS. */ 492 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 493 URE_DIS_SDSAVE); 494 usbd_delay_ms(un->un_udev, 20); 495 496 if (un->un_flags & URE_FLAG_VER_4C00) { 497 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 498 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 499 ~URE_LED_MODE_MASK); 500 } 501 502 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 503 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 504 ~URE_POWER_CUT); 505 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 506 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 507 ~URE_RESUME_INDICATE); 508 509 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 510 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 511 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 512 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 513 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 514 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 515 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 516 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 517 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 518 URE_SPDWN_LINKCHG_MSK); 519 520 /* Enable Rx aggregation. */ 521 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 522 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 523 ~URE_RX_AGG_DISABLE); 524 525 /* Disable ALDPS. */ 526 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 527 URE_DIS_SDSAVE); 528 usbd_delay_ms(un->un_udev, 20); 529 530 ure_init_fifo(un); 531 532 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 533 URE_TX_AGG_MAX_THRESHOLD); 534 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 535 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 536 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 537 } 538 539 static void 540 ure_rtl8153_init(struct usbnet *un) 541 { 542 uint16_t val; 543 uint8_t u1u2[8]; 544 int i; 545 546 /* Disable ALDPS. */ 547 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 548 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 549 usbd_delay_ms(un->un_udev, 20); 550 551 memset(u1u2, 0x00, sizeof(u1u2)); 552 ure_write_mem(un, URE_USB_TOLERANCE, 553 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 554 555 for (i = 0; i < URE_TIMEOUT; i++) { 556 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 557 URE_AUTOLOAD_DONE) 558 break; 559 usbd_delay_ms(un->un_udev, 10); 560 } 561 if (i == URE_TIMEOUT) 562 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 563 564 for (i = 0; i < URE_TIMEOUT; i++) { 565 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 566 URE_PHY_STAT_MASK; 567 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 568 break; 569 usbd_delay_ms(un->un_udev, 10); 570 } 571 if (i == URE_TIMEOUT) 572 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 573 574 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 575 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 576 ~URE_U2P3_ENABLE); 577 578 if (un->un_flags & URE_FLAG_VER_5C10) { 579 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 580 val &= ~URE_PWD_DN_SCALE_MASK; 581 val |= URE_PWD_DN_SCALE(96); 582 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 583 584 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 585 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 586 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 587 } else if (un->un_flags & URE_FLAG_VER_5C20) { 588 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 589 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 590 ~URE_ECM_ALDPS); 591 } 592 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 593 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 594 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 595 0) 596 val &= ~URE_DYNAMIC_BURST; 597 else 598 val |= URE_DYNAMIC_BURST; 599 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 600 } 601 602 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 603 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 604 URE_EP4_FULL_FC); 605 606 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 607 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 608 ~URE_TIMER11_EN); 609 610 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 611 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 612 ~URE_LED_MODE_MASK); 613 614 if ((un->un_flags & URE_FLAG_VER_5C10) && 615 un->un_udev->ud_speed != USB_SPEED_SUPER) 616 val = URE_LPM_TIMER_500MS; 617 else 618 val = URE_LPM_TIMER_500US; 619 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 620 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 621 622 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 623 val &= ~URE_SEN_VAL_MASK; 624 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 625 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 626 627 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 628 629 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 630 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 631 ~(URE_PWR_EN | URE_PHASE2_EN)); 632 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 633 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 634 ~URE_PCUT_STATUS); 635 636 memset(u1u2, 0xff, sizeof(u1u2)); 637 ure_write_mem(un, URE_USB_TOLERANCE, 638 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 639 640 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 641 URE_ALDPS_SPDWN_RATIO); 642 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 643 URE_EEE_SPDWN_RATIO); 644 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 645 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 646 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 647 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 648 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 649 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 650 URE_EEE_SPDWN_EN); 651 652 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 653 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 654 val |= URE_U2P3_ENABLE; 655 else 656 val &= ~URE_U2P3_ENABLE; 657 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 658 659 memset(u1u2, 0x00, sizeof(u1u2)); 660 ure_write_mem(un, URE_USB_TOLERANCE, 661 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 662 663 /* Disable ALDPS. */ 664 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 665 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 666 usbd_delay_ms(un->un_udev, 20); 667 668 ure_init_fifo(un); 669 670 /* Enable Rx aggregation. */ 671 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 672 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 673 ~URE_RX_AGG_DISABLE); 674 675 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 676 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 677 val |= URE_U2P3_ENABLE; 678 else 679 val &= ~URE_U2P3_ENABLE; 680 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 681 682 memset(u1u2, 0xff, sizeof(u1u2)); 683 ure_write_mem(un, URE_USB_TOLERANCE, 684 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 685 } 686 687 static void 688 ure_disable_teredo(struct usbnet *un) 689 { 690 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 691 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 692 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 693 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 694 URE_WDT6_SET_MODE); 695 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 696 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 697 } 698 699 static void 700 ure_init_fifo(struct usbnet *un) 701 { 702 uint32_t rx_fifo1, rx_fifo2; 703 int i; 704 705 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 706 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 707 URE_RXDY_GATED_EN); 708 709 ure_disable_teredo(un); 710 711 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, 712 ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 713 ~URE_RCR_ACPT_ALL); 714 715 if (!(un->un_flags & URE_FLAG_8152)) { 716 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 717 URE_FLAG_VER_5C20)) 718 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 719 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 720 if (un->un_flags & URE_FLAG_VER_5C00) 721 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 722 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 723 ~URE_CTAP_SHORT_EN); 724 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 725 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 726 URE_EEE_CLKDIV_EN); 727 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 728 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 729 URE_EN_10M_BGOFF); 730 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 731 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 732 URE_EN_10M_PLLOFF); 733 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 734 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 735 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 736 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 737 URE_PFM_PWM_SWITCH); 738 739 /* Enable LPF corner auto tune. */ 740 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 741 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 742 743 /* Adjust 10M amplitude. */ 744 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 745 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 746 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 747 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 748 } 749 750 ure_reset(un); 751 752 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 753 754 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 755 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 756 ~URE_NOW_IS_OOB); 757 758 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 759 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 760 ~URE_MCU_BORW_EN); 761 for (i = 0; i < URE_TIMEOUT; i++) { 762 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 763 URE_LINK_LIST_READY) 764 break; 765 usbd_delay_ms(un->un_udev, 10); 766 } 767 if (i == URE_TIMEOUT) 768 URE_PRINTF(un, "timeout waiting for OOB control\n"); 769 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 770 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 771 URE_RE_INIT_LL); 772 for (i = 0; i < URE_TIMEOUT; i++) { 773 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 774 URE_LINK_LIST_READY) 775 break; 776 usbd_delay_ms(un->un_udev, 10); 777 } 778 if (i == URE_TIMEOUT) 779 URE_PRINTF(un, "timeout waiting for OOB control\n"); 780 781 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 782 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 783 ~URE_CPCR_RX_VLAN); 784 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 785 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 786 URE_TCR0_AUTO_FIFO); 787 788 /* Configure Rx FIFO threshold and coalescing. */ 789 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 790 URE_RXFIFO_THR1_NORMAL); 791 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 792 rx_fifo1 = URE_RXFIFO_THR2_FULL; 793 rx_fifo2 = URE_RXFIFO_THR3_FULL; 794 } else { 795 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 796 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 797 } 798 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 799 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 800 801 /* Configure Tx FIFO threshold. */ 802 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 803 URE_TXFIFO_THR_NORMAL); 804 } 805 806 static int 807 ure_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data) 808 { 809 struct usbnet * const un = ifp->if_softc; 810 811 switch (cmd) { 812 case SIOCADDMULTI: 813 case SIOCDELMULTI: 814 ure_setiff(un); 815 break; 816 default: 817 break; 818 } 819 820 return 0; 821 } 822 823 static int 824 ure_match(device_t parent, cfdata_t match, void *aux) 825 { 826 struct usb_attach_arg *uaa = aux; 827 828 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 829 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 830 } 831 832 static void 833 ure_attach(device_t parent, device_t self, void *aux) 834 { 835 struct usbnet * const un = device_private(self); 836 struct usb_attach_arg *uaa = aux; 837 struct usbd_device *dev = uaa->uaa_device; 838 usb_interface_descriptor_t *id; 839 usb_endpoint_descriptor_t *ed; 840 int error, i; 841 uint16_t ver; 842 uint8_t eaddr[8]; /* 2byte padded */ 843 char *devinfop; 844 845 aprint_naive("\n"); 846 aprint_normal("\n"); 847 devinfop = usbd_devinfo_alloc(dev, 0); 848 aprint_normal_dev(self, "%s\n", devinfop); 849 usbd_devinfo_free(devinfop); 850 851 un->un_dev = self; 852 un->un_udev = dev; 853 un->un_sc = un; 854 un->un_ops = &ure_ops; 855 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 856 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 857 un->un_rx_list_cnt = URE_RX_LIST_CNT; 858 un->un_tx_list_cnt = URE_TX_LIST_CNT; 859 un->un_rx_bufsz = URE_BUFSZ; 860 un->un_tx_bufsz = URE_BUFSZ; 861 862 #define URE_CONFIG_NO 1 /* XXX */ 863 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 864 if (error) { 865 aprint_error_dev(self, "failed to set configuration: %s\n", 866 usbd_errstr(error)); 867 return; /* XXX */ 868 } 869 870 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 871 un->un_flags |= URE_FLAG_8152; 872 873 #define URE_IFACE_IDX 0 /* XXX */ 874 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 875 if (error) { 876 aprint_error_dev(self, "failed to get interface handle: %s\n", 877 usbd_errstr(error)); 878 return; /* XXX */ 879 } 880 881 id = usbd_get_interface_descriptor(un->un_iface); 882 for (i = 0; i < id->bNumEndpoints; i++) { 883 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 884 if (ed == NULL) { 885 aprint_error_dev(self, "couldn't get ep %d\n", i); 886 return; /* XXX */ 887 } 888 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 889 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 890 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 891 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 892 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 893 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 894 } 895 } 896 897 /* Set these up now for ure_ctl(). */ 898 usbnet_attach(un, "uredet"); 899 900 un->un_phyno = 0; 901 902 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 903 switch (ver) { 904 case 0x4c00: 905 un->un_flags |= URE_FLAG_VER_4C00; 906 break; 907 case 0x4c10: 908 un->un_flags |= URE_FLAG_VER_4C10; 909 break; 910 case 0x5c00: 911 un->un_flags |= URE_FLAG_VER_5C00; 912 break; 913 case 0x5c10: 914 un->un_flags |= URE_FLAG_VER_5C10; 915 break; 916 case 0x5c20: 917 un->un_flags |= URE_FLAG_VER_5C20; 918 break; 919 case 0x5c30: 920 un->un_flags |= URE_FLAG_VER_5C30; 921 break; 922 default: 923 /* fake addr? or just fail? */ 924 break; 925 } 926 aprint_normal_dev(self, "RTL%d %sver %04x\n", 927 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 928 (un->un_flags != 0) ? "" : "unknown ", 929 ver); 930 931 usbnet_lock(un); 932 if (un->un_flags & URE_FLAG_8152) 933 ure_rtl8152_init(un); 934 else 935 ure_rtl8153_init(un); 936 937 if (un->un_flags & URE_FLAG_VER_4C00) 938 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 939 sizeof(eaddr)); 940 else 941 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 942 sizeof(eaddr)); 943 usbnet_unlock(un); 944 memcpy(un->un_eaddr, eaddr, sizeof un->un_eaddr); 945 946 struct ifnet *ifp = usbnet_ifp(un); 947 948 /* 949 * We don't support TSOv4 and v6 for now, that are required to 950 * be handled in software for some cases. 951 */ 952 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 953 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 954 #ifdef INET6 955 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 956 #endif 957 if (un->un_flags & ~URE_FLAG_VER_4C00) { 958 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 959 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 960 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 961 } 962 struct ethercom *ec = usbnet_ec(un); 963 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 964 #ifdef notyet 965 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 966 #endif 967 968 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 969 0, 0); 970 } 971 972 static void 973 ure_rxeof_loop(struct usbnet *un, struct usbd_xfer *xfer, 974 struct usbnet_chain *c, uint32_t total_len) 975 { 976 struct ifnet *ifp = usbnet_ifp(un); 977 uint8_t *buf = c->unc_buf; 978 uint16_t pkt_len = 0; 979 uint16_t pkt_count = 0; 980 struct ure_rxpkt rxhdr; 981 982 usbnet_isowned_rx(un); 983 984 do { 985 if (total_len < sizeof(rxhdr)) { 986 DPRINTF(("too few bytes left for a packet header\n")); 987 ifp->if_ierrors++; 988 return; 989 } 990 991 buf += roundup(pkt_len, 8); 992 993 memcpy(&rxhdr, buf, sizeof(rxhdr)); 994 total_len -= sizeof(rxhdr); 995 996 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 997 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 998 if (pkt_len > total_len) { 999 DPRINTF(("not enough bytes left for next packet\n")); 1000 ifp->if_ierrors++; 1001 return; 1002 } 1003 1004 total_len -= roundup(pkt_len, 8); 1005 buf += sizeof(rxhdr); 1006 1007 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1008 ure_rxcsum(ifp, &rxhdr), 0, 0); 1009 1010 pkt_count++; 1011 1012 } while (total_len > 0); 1013 1014 if (pkt_count) 1015 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 1016 } 1017 1018 static int 1019 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1020 { 1021 int enabled = ifp->if_csum_flags_rx, flags = 0; 1022 uint32_t csum, misc; 1023 1024 if (enabled == 0) 1025 return 0; 1026 1027 csum = le32toh(rp->ure_csum); 1028 misc = le32toh(rp->ure_misc); 1029 1030 if (csum & URE_RXPKT_IPV4_CS) { 1031 flags |= M_CSUM_IPv4; 1032 if (csum & URE_RXPKT_TCP_CS) 1033 flags |= M_CSUM_TCPv4; 1034 if (csum & URE_RXPKT_UDP_CS) 1035 flags |= M_CSUM_UDPv4; 1036 } else if (csum & URE_RXPKT_IPV6_CS) { 1037 flags = 0; 1038 if (csum & URE_RXPKT_TCP_CS) 1039 flags |= M_CSUM_TCPv6; 1040 if (csum & URE_RXPKT_UDP_CS) 1041 flags |= M_CSUM_UDPv6; 1042 } 1043 1044 flags &= enabled; 1045 if (__predict_false((flags & M_CSUM_IPv4) && 1046 (misc & URE_RXPKT_IP_F))) 1047 flags |= M_CSUM_IPv4_BAD; 1048 if (__predict_false( 1049 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1050 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1051 )) 1052 flags |= M_CSUM_TCP_UDP_BAD; 1053 1054 return flags; 1055 } 1056 1057 static unsigned 1058 ure_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1059 { 1060 struct ure_txpkt txhdr; 1061 uint32_t frm_len = 0; 1062 uint8_t *buf = c->unc_buf; 1063 1064 usbnet_isowned_tx(un); 1065 1066 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1067 return 0; 1068 1069 /* header */ 1070 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1071 URE_TXPKT_TX_LS); 1072 txhdr.ure_csum = htole32(ure_txcsum(m)); 1073 memcpy(buf, &txhdr, sizeof(txhdr)); 1074 buf += sizeof(txhdr); 1075 frm_len = sizeof(txhdr); 1076 1077 /* packet */ 1078 m_copydata(m, 0, m->m_pkthdr.len, buf); 1079 frm_len += m->m_pkthdr.len; 1080 1081 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1082 1083 return frm_len; 1084 } 1085 1086 /* 1087 * We need to calculate L4 checksum in software, if the offset of 1088 * L4 header is larger than 0x7ff = 2047. 1089 */ 1090 static uint32_t 1091 ure_txcsum(struct mbuf *m) 1092 { 1093 struct ether_header *eh; 1094 int flags = m->m_pkthdr.csum_flags; 1095 uint32_t data = m->m_pkthdr.csum_data; 1096 uint32_t reg = 0; 1097 int l3off, l4off; 1098 uint16_t type; 1099 1100 if (flags == 0) 1101 return 0; 1102 1103 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1104 eh = mtod(m, struct ether_header *); 1105 type = eh->ether_type; 1106 } else 1107 m_copydata(m, offsetof(struct ether_header, ether_type), 1108 sizeof(type), &type); 1109 switch (type = htons(type)) { 1110 case ETHERTYPE_IP: 1111 case ETHERTYPE_IPV6: 1112 l3off = ETHER_HDR_LEN; 1113 break; 1114 case ETHERTYPE_VLAN: 1115 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1116 break; 1117 default: 1118 return 0; 1119 } 1120 1121 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1122 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1123 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1124 in_undefer_cksum(m, l3off, flags); 1125 return 0; 1126 } 1127 reg |= URE_TXPKT_IPV4_CS; 1128 if (flags & M_CSUM_TCPv4) 1129 reg |= URE_TXPKT_TCP_CS; 1130 else 1131 reg |= URE_TXPKT_UDP_CS; 1132 reg |= l4off << URE_L4_OFFSET_SHIFT; 1133 } 1134 #ifdef INET6 1135 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1136 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1137 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1138 in6_undefer_cksum(m, l3off, flags); 1139 return 0; 1140 } 1141 reg |= URE_TXPKT_IPV6_CS; 1142 if (flags & M_CSUM_TCPv6) 1143 reg |= URE_TXPKT_TCP_CS; 1144 else 1145 reg |= URE_TXPKT_UDP_CS; 1146 reg |= l4off << URE_L4_OFFSET_SHIFT; 1147 } 1148 #endif 1149 else if (flags & M_CSUM_IPv4) 1150 reg |= URE_TXPKT_IPV4_CS; 1151 1152 return reg; 1153 } 1154 1155 /* XXX module is built but no MODULE() or modcmd */ 1156
Indexes created Thu Oct 02 01:09:59 GMT 2025