if_ure.c revision 1.28
1 /* $NetBSD: if_ure.c,v 1.28 2019/08/16 08:29:20 mrg Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.28 2019/08/16 08:29:20 mrg Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 42 #include <net/route.h> 43 44 #include <dev/usb/usbnet.h> 45 46 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 47 #ifdef INET6 48 #include <netinet/in.h> 49 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 50 #endif 51 52 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 53 #include <dev/usb/if_urereg.h> 54 #include <dev/usb/if_urevar.h> 55 56 #define URE_PRINTF(un, fmt, args...) \ 57 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 58 59 #define URE_DEBUG 60 #ifdef URE_DEBUG 61 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 62 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 63 int uredebug = 0; 64 #else 65 #define DPRINTF(x) 66 #define DPRINTFN(n, x) 67 #endif 68 69 static const struct usb_devno ure_devs[] = { 70 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 71 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 72 }; 73 74 #define URE_BUFSZ (16 * 1024) 75 76 static void ure_reset(struct usbnet *); 77 static uint32_t ure_txcsum(struct mbuf *); 78 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 79 static void ure_rtl8152_init(struct usbnet *); 80 static void ure_rtl8153_init(struct usbnet *); 81 static void ure_disable_teredo(struct usbnet *); 82 static void ure_init_fifo(struct usbnet *); 83 84 static void ure_stop_cb(struct ifnet *, int); 85 static int ure_ioctl_cb(struct ifnet *, u_long, void *); 86 static usbd_status ure_mii_read_reg(struct usbnet *, int, int, uint16_t *); 87 static usbd_status ure_mii_write_reg(struct usbnet *, int, int, uint16_t); 88 static void ure_miibus_statchg(struct ifnet *); 89 static unsigned ure_tx_prepare(struct usbnet *, struct mbuf *, 90 struct usbnet_chain *); 91 static void ure_rx_loop(struct usbnet *, struct usbnet_chain *, uint32_t); 92 static int ure_init(struct ifnet *); 93 94 static int ure_match(device_t, cfdata_t, void *); 95 static void ure_attach(device_t, device_t, void *); 96 97 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 98 usbnet_detach, usbnet_activate); 99 100 static struct usbnet_ops ure_ops = { 101 .uno_stop = ure_stop_cb, 102 .uno_ioctl = ure_ioctl_cb, 103 .uno_read_reg = ure_mii_read_reg, 104 .uno_write_reg = ure_mii_write_reg, 105 .uno_statchg = ure_miibus_statchg, 106 .uno_tx_prepare = ure_tx_prepare, 107 .uno_rx_loop = ure_rx_loop, 108 .uno_init = ure_init, 109 }; 110 111 static int 112 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 113 void *buf, int len) 114 { 115 usb_device_request_t req; 116 usbd_status err; 117 118 if (usbnet_isdying(un)) 119 return 0; 120 121 if (rw == URE_CTL_WRITE) 122 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 123 else 124 req.bmRequestType = UT_READ_VENDOR_DEVICE; 125 req.bRequest = UR_SET_ADDRESS; 126 USETW(req.wValue, val); 127 USETW(req.wIndex, index); 128 USETW(req.wLength, len); 129 130 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 131 rw, val, index, len)); 132 err = usbd_do_request(un->un_udev, &req, buf); 133 if (err) { 134 DPRINTF(("ure_ctl: error %d\n", err)); 135 return -1; 136 } 137 138 return 0; 139 } 140 141 static int 142 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 143 void *buf, int len) 144 { 145 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 146 } 147 148 static int 149 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 150 void *buf, int len) 151 { 152 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 153 } 154 155 static uint8_t 156 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 157 { 158 uint32_t val; 159 uint8_t temp[4]; 160 uint8_t shift; 161 162 shift = (reg & 3) << 3; 163 reg &= ~3; 164 165 ure_read_mem(un, reg, index, &temp, 4); 166 val = UGETDW(temp); 167 val >>= shift; 168 169 return val & 0xff; 170 } 171 172 static uint16_t 173 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 174 { 175 uint32_t val; 176 uint8_t temp[4]; 177 uint8_t shift; 178 179 shift = (reg & 2) << 3; 180 reg &= ~3; 181 182 ure_read_mem(un, reg, index, &temp, 4); 183 val = UGETDW(temp); 184 val >>= shift; 185 186 return val & 0xffff; 187 } 188 189 static uint32_t 190 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 191 { 192 uint8_t temp[4]; 193 194 ure_read_mem(un, reg, index, &temp, 4); 195 return UGETDW(temp); 196 } 197 198 static int 199 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 200 { 201 uint16_t byen; 202 uint8_t temp[4]; 203 uint8_t shift; 204 205 byen = URE_BYTE_EN_BYTE; 206 shift = reg & 3; 207 val &= 0xff; 208 209 if (reg & 3) { 210 byen <<= shift; 211 val <<= (shift << 3); 212 reg &= ~3; 213 } 214 215 USETDW(temp, val); 216 return ure_write_mem(un, reg, index | byen, &temp, 4); 217 } 218 219 static int 220 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 221 { 222 uint16_t byen; 223 uint8_t temp[4]; 224 uint8_t shift; 225 226 byen = URE_BYTE_EN_WORD; 227 shift = reg & 2; 228 val &= 0xffff; 229 230 if (reg & 2) { 231 byen <<= shift; 232 val <<= (shift << 3); 233 reg &= ~3; 234 } 235 236 USETDW(temp, val); 237 return ure_write_mem(un, reg, index | byen, &temp, 4); 238 } 239 240 static int 241 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 242 { 243 uint8_t temp[4]; 244 245 USETDW(temp, val); 246 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 247 } 248 249 static uint16_t 250 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 251 { 252 uint16_t reg; 253 254 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 255 reg = (addr & 0x0fff) | 0xb000; 256 257 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 258 } 259 260 static void 261 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 262 { 263 uint16_t reg; 264 265 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 266 reg = (addr & 0x0fff) | 0xb000; 267 268 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 269 } 270 271 static usbd_status 272 ure_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 273 { 274 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 275 if (reg == RTK_GMEDIASTAT) { 276 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 277 return USBD_NORMAL_COMPLETION; 278 } 279 280 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 281 282 return USBD_NORMAL_COMPLETION; 283 } 284 285 static usbd_status 286 ure_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 287 { 288 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 289 290 return USBD_NORMAL_COMPLETION; 291 } 292 293 static void 294 ure_miibus_statchg(struct ifnet *ifp) 295 { 296 struct usbnet * const un = ifp->if_softc; 297 struct mii_data * const mii = usbnet_mii(un); 298 299 if (usbnet_isdying(un)) 300 return; 301 302 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 303 (IFM_ACTIVE | IFM_AVALID)) { 304 switch (IFM_SUBTYPE(mii->mii_media_active)) { 305 case IFM_10_T: 306 case IFM_100_TX: 307 usbnet_set_link(un, true); 308 break; 309 case IFM_1000_T: 310 if ((un->un_flags & URE_FLAG_8152) != 0) 311 break; 312 usbnet_set_link(un, true); 313 break; 314 default: 315 break; 316 } 317 } 318 } 319 320 static void 321 ure_setiff_locked(struct usbnet *un) 322 { 323 struct ethercom *ec = usbnet_ec(un); 324 struct ifnet *ifp = usbnet_ifp(un); 325 struct ether_multi *enm; 326 struct ether_multistep step; 327 uint32_t hashes[2] = { 0, 0 }; 328 uint32_t hash; 329 uint32_t rxmode; 330 331 usbnet_isowned(un); 332 333 if (usbnet_isdying(un)) 334 return; 335 336 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 337 rxmode &= ~URE_RCR_ACPT_ALL; 338 339 /* 340 * Always accept frames destined to our station address. 341 * Always accept broadcast frames. 342 */ 343 rxmode |= URE_RCR_APM | URE_RCR_AB; 344 345 if (ifp->if_flags & IFF_PROMISC) { 346 rxmode |= URE_RCR_AAP; 347 allmulti: 348 ETHER_LOCK(ec); 349 ec->ec_flags |= ETHER_F_ALLMULTI; 350 ETHER_UNLOCK(ec); 351 rxmode |= URE_RCR_AM; 352 hashes[0] = hashes[1] = 0xffffffff; 353 } else { 354 rxmode |= URE_RCR_AM; 355 356 ETHER_LOCK(ec); 357 ec->ec_flags &= ~ETHER_F_ALLMULTI; 358 359 ETHER_FIRST_MULTI(step, ec, enm); 360 while (enm != NULL) { 361 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 362 ETHER_ADDR_LEN)) { 363 ETHER_UNLOCK(ec); 364 goto allmulti; 365 } 366 367 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 368 >> 26; 369 if (hash < 32) 370 hashes[0] |= (1 << hash); 371 else 372 hashes[1] |= (1 << (hash - 32)); 373 374 ETHER_NEXT_MULTI(step, enm); 375 } 376 ETHER_UNLOCK(ec); 377 378 hash = bswap32(hashes[0]); 379 hashes[0] = bswap32(hashes[1]); 380 hashes[1] = hash; 381 } 382 383 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 384 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 385 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 386 } 387 388 static void 389 ure_setiff(struct usbnet *un) 390 { 391 392 usbnet_lock(un); 393 ure_setiff_locked(un); 394 usbnet_unlock(un); 395 } 396 397 static void 398 ure_reset(struct usbnet *un) 399 { 400 int i; 401 402 usbnet_isowned(un); 403 404 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 405 406 for (i = 0; i < URE_TIMEOUT; i++) { 407 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 408 URE_CR_RST)) 409 break; 410 usbd_delay_ms(un->un_udev, 10); 411 } 412 if (i == URE_TIMEOUT) 413 URE_PRINTF(un, "reset never completed\n"); 414 } 415 416 static int 417 ure_init_locked(struct ifnet *ifp) 418 { 419 struct usbnet * const un = ifp->if_softc; 420 uint8_t eaddr[8]; 421 422 usbnet_isowned(un); 423 424 if (usbnet_isdying(un)) 425 return EIO; 426 427 /* Cancel pending I/O. */ 428 if (ifp->if_flags & IFF_RUNNING) 429 usbnet_stop(un, ifp, 1); 430 431 /* Set MAC address. */ 432 memset(eaddr, 0, sizeof(eaddr)); 433 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 434 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 435 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 436 eaddr, 8); 437 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 438 439 /* Reset the packet filter. */ 440 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 441 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 442 ~URE_FMC_FCR_MCU_EN); 443 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 444 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 445 URE_FMC_FCR_MCU_EN); 446 447 /* Enable transmit and receive. */ 448 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 449 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 450 URE_CR_TE); 451 452 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 453 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 454 ~URE_RXDY_GATED_EN); 455 456 /* Load the multicast filter. */ 457 ure_setiff_locked(un); 458 459 return usbnet_init_rx_tx(un); 460 } 461 462 static int 463 ure_init(struct ifnet *ifp) 464 { 465 struct usbnet * const un = ifp->if_softc; 466 467 usbnet_lock(un); 468 int ret = ure_init_locked(ifp); 469 usbnet_unlock(un); 470 471 return ret; 472 } 473 474 static void 475 ure_stop_cb(struct ifnet *ifp, int disable __unused) 476 { 477 struct usbnet * const un = ifp->if_softc; 478 479 ure_reset(un); 480 } 481 482 static void 483 ure_rtl8152_init(struct usbnet *un) 484 { 485 uint32_t pwrctrl; 486 487 /* Disable ALDPS. */ 488 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 489 URE_DIS_SDSAVE); 490 usbd_delay_ms(un->un_udev, 20); 491 492 if (un->un_flags & URE_FLAG_VER_4C00) { 493 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 494 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 495 ~URE_LED_MODE_MASK); 496 } 497 498 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 499 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 500 ~URE_POWER_CUT); 501 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 502 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 503 ~URE_RESUME_INDICATE); 504 505 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 506 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 507 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 508 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 509 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 510 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 511 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 512 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 513 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 514 URE_SPDWN_LINKCHG_MSK); 515 516 /* Enable Rx aggregation. */ 517 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 518 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 519 ~URE_RX_AGG_DISABLE); 520 521 /* Disable ALDPS. */ 522 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 523 URE_DIS_SDSAVE); 524 usbd_delay_ms(un->un_udev, 20); 525 526 ure_init_fifo(un); 527 528 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 529 URE_TX_AGG_MAX_THRESHOLD); 530 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 531 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 532 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 533 } 534 535 static void 536 ure_rtl8153_init(struct usbnet *un) 537 { 538 uint16_t val; 539 uint8_t u1u2[8]; 540 int i; 541 542 /* Disable ALDPS. */ 543 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 544 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 545 usbd_delay_ms(un->un_udev, 20); 546 547 memset(u1u2, 0x00, sizeof(u1u2)); 548 ure_write_mem(un, URE_USB_TOLERANCE, 549 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 550 551 for (i = 0; i < URE_TIMEOUT; i++) { 552 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 553 URE_AUTOLOAD_DONE) 554 break; 555 usbd_delay_ms(un->un_udev, 10); 556 } 557 if (i == URE_TIMEOUT) 558 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 559 560 for (i = 0; i < URE_TIMEOUT; i++) { 561 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 562 URE_PHY_STAT_MASK; 563 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 564 break; 565 usbd_delay_ms(un->un_udev, 10); 566 } 567 if (i == URE_TIMEOUT) 568 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 569 570 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 571 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 572 ~URE_U2P3_ENABLE); 573 574 if (un->un_flags & URE_FLAG_VER_5C10) { 575 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 576 val &= ~URE_PWD_DN_SCALE_MASK; 577 val |= URE_PWD_DN_SCALE(96); 578 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 579 580 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 581 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 582 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 583 } else if (un->un_flags & URE_FLAG_VER_5C20) { 584 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 585 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 586 ~URE_ECM_ALDPS); 587 } 588 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 589 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 590 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 591 0) 592 val &= ~URE_DYNAMIC_BURST; 593 else 594 val |= URE_DYNAMIC_BURST; 595 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 596 } 597 598 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 599 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 600 URE_EP4_FULL_FC); 601 602 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 603 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 604 ~URE_TIMER11_EN); 605 606 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 607 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 608 ~URE_LED_MODE_MASK); 609 610 if ((un->un_flags & URE_FLAG_VER_5C10) && 611 un->un_udev->ud_speed != USB_SPEED_SUPER) 612 val = URE_LPM_TIMER_500MS; 613 else 614 val = URE_LPM_TIMER_500US; 615 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 616 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 617 618 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 619 val &= ~URE_SEN_VAL_MASK; 620 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 621 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 622 623 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 624 625 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 626 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 627 ~(URE_PWR_EN | URE_PHASE2_EN)); 628 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 629 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 630 ~URE_PCUT_STATUS); 631 632 memset(u1u2, 0xff, sizeof(u1u2)); 633 ure_write_mem(un, URE_USB_TOLERANCE, 634 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 635 636 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 637 URE_ALDPS_SPDWN_RATIO); 638 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 639 URE_EEE_SPDWN_RATIO); 640 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 641 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 642 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 643 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 644 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 645 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 646 URE_EEE_SPDWN_EN); 647 648 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 649 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 650 val |= URE_U2P3_ENABLE; 651 else 652 val &= ~URE_U2P3_ENABLE; 653 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 654 655 memset(u1u2, 0x00, sizeof(u1u2)); 656 ure_write_mem(un, URE_USB_TOLERANCE, 657 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 658 659 /* Disable ALDPS. */ 660 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 661 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 662 usbd_delay_ms(un->un_udev, 20); 663 664 ure_init_fifo(un); 665 666 /* Enable Rx aggregation. */ 667 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 668 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 669 ~URE_RX_AGG_DISABLE); 670 671 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 672 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 673 val |= URE_U2P3_ENABLE; 674 else 675 val &= ~URE_U2P3_ENABLE; 676 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 677 678 memset(u1u2, 0xff, sizeof(u1u2)); 679 ure_write_mem(un, URE_USB_TOLERANCE, 680 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 681 } 682 683 static void 684 ure_disable_teredo(struct usbnet *un) 685 { 686 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 687 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 688 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 689 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 690 URE_WDT6_SET_MODE); 691 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 692 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 693 } 694 695 static void 696 ure_init_fifo(struct usbnet *un) 697 { 698 uint32_t rx_fifo1, rx_fifo2; 699 int i; 700 701 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 702 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 703 URE_RXDY_GATED_EN); 704 705 ure_disable_teredo(un); 706 707 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, 708 ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 709 ~URE_RCR_ACPT_ALL); 710 711 if (!(un->un_flags & URE_FLAG_8152)) { 712 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 713 URE_FLAG_VER_5C20)) 714 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 715 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 716 if (un->un_flags & URE_FLAG_VER_5C00) 717 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 718 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 719 ~URE_CTAP_SHORT_EN); 720 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 721 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 722 URE_EEE_CLKDIV_EN); 723 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 724 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 725 URE_EN_10M_BGOFF); 726 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 727 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 728 URE_EN_10M_PLLOFF); 729 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 730 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 731 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 732 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 733 URE_PFM_PWM_SWITCH); 734 735 /* Enable LPF corner auto tune. */ 736 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 737 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 738 739 /* Adjust 10M amplitude. */ 740 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 741 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 742 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 743 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 744 } 745 746 ure_reset(un); 747 748 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 749 750 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 751 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 752 ~URE_NOW_IS_OOB); 753 754 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 755 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 756 ~URE_MCU_BORW_EN); 757 for (i = 0; i < URE_TIMEOUT; i++) { 758 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 759 URE_LINK_LIST_READY) 760 break; 761 usbd_delay_ms(un->un_udev, 10); 762 } 763 if (i == URE_TIMEOUT) 764 URE_PRINTF(un, "timeout waiting for OOB control\n"); 765 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 766 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 767 URE_RE_INIT_LL); 768 for (i = 0; i < URE_TIMEOUT; i++) { 769 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 770 URE_LINK_LIST_READY) 771 break; 772 usbd_delay_ms(un->un_udev, 10); 773 } 774 if (i == URE_TIMEOUT) 775 URE_PRINTF(un, "timeout waiting for OOB control\n"); 776 777 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 778 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 779 ~URE_CPCR_RX_VLAN); 780 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 781 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 782 URE_TCR0_AUTO_FIFO); 783 784 /* Configure Rx FIFO threshold and coalescing. */ 785 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 786 URE_RXFIFO_THR1_NORMAL); 787 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 788 rx_fifo1 = URE_RXFIFO_THR2_FULL; 789 rx_fifo2 = URE_RXFIFO_THR3_FULL; 790 } else { 791 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 792 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 793 } 794 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 795 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 796 797 /* Configure Tx FIFO threshold. */ 798 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 799 URE_TXFIFO_THR_NORMAL); 800 } 801 802 static int 803 ure_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data) 804 { 805 struct usbnet * const un = ifp->if_softc; 806 807 switch (cmd) { 808 case SIOCADDMULTI: 809 case SIOCDELMULTI: 810 ure_setiff(un); 811 break; 812 default: 813 break; 814 } 815 816 return 0; 817 } 818 819 static int 820 ure_match(device_t parent, cfdata_t match, void *aux) 821 { 822 struct usb_attach_arg *uaa = aux; 823 824 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 825 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 826 } 827 828 static void 829 ure_attach(device_t parent, device_t self, void *aux) 830 { 831 struct usbnet * const un = device_private(self); 832 struct usb_attach_arg *uaa = aux; 833 struct usbd_device *dev = uaa->uaa_device; 834 usb_interface_descriptor_t *id; 835 usb_endpoint_descriptor_t *ed; 836 int error, i; 837 uint16_t ver; 838 uint8_t eaddr[8]; /* 2byte padded */ 839 char *devinfop; 840 841 aprint_naive("\n"); 842 aprint_normal("\n"); 843 devinfop = usbd_devinfo_alloc(dev, 0); 844 aprint_normal_dev(self, "%s\n", devinfop); 845 usbd_devinfo_free(devinfop); 846 847 un->un_dev = self; 848 un->un_udev = dev; 849 un->un_sc = un; 850 un->un_ops = &ure_ops; 851 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 852 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 853 un->un_rx_list_cnt = URE_RX_LIST_CNT; 854 un->un_tx_list_cnt = URE_TX_LIST_CNT; 855 un->un_rx_bufsz = URE_BUFSZ; 856 un->un_tx_bufsz = URE_BUFSZ; 857 858 #define URE_CONFIG_NO 1 /* XXX */ 859 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 860 if (error) { 861 aprint_error_dev(self, "failed to set configuration: %s\n", 862 usbd_errstr(error)); 863 return; /* XXX */ 864 } 865 866 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 867 un->un_flags |= URE_FLAG_8152; 868 869 #define URE_IFACE_IDX 0 /* XXX */ 870 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 871 if (error) { 872 aprint_error_dev(self, "failed to get interface handle: %s\n", 873 usbd_errstr(error)); 874 return; /* XXX */ 875 } 876 877 id = usbd_get_interface_descriptor(un->un_iface); 878 for (i = 0; i < id->bNumEndpoints; i++) { 879 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 880 if (ed == NULL) { 881 aprint_error_dev(self, "couldn't get ep %d\n", i); 882 return; /* XXX */ 883 } 884 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 885 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 886 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 887 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 888 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 889 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 890 } 891 } 892 893 /* Set these up now for ure_ctl(). */ 894 usbnet_attach(un, "uredet"); 895 896 un->un_phyno = 0; 897 898 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 899 switch (ver) { 900 case 0x4c00: 901 un->un_flags |= URE_FLAG_VER_4C00; 902 break; 903 case 0x4c10: 904 un->un_flags |= URE_FLAG_VER_4C10; 905 break; 906 case 0x5c00: 907 un->un_flags |= URE_FLAG_VER_5C00; 908 break; 909 case 0x5c10: 910 un->un_flags |= URE_FLAG_VER_5C10; 911 break; 912 case 0x5c20: 913 un->un_flags |= URE_FLAG_VER_5C20; 914 break; 915 case 0x5c30: 916 un->un_flags |= URE_FLAG_VER_5C30; 917 break; 918 default: 919 /* fake addr? or just fail? */ 920 break; 921 } 922 aprint_normal_dev(self, "RTL%d %sver %04x\n", 923 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 924 (un->un_flags != 0) ? "" : "unknown ", 925 ver); 926 927 usbnet_lock(un); 928 if (un->un_flags & URE_FLAG_8152) 929 ure_rtl8152_init(un); 930 else 931 ure_rtl8153_init(un); 932 933 if (un->un_flags & URE_FLAG_VER_4C00) 934 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 935 sizeof(eaddr)); 936 else 937 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 938 sizeof(eaddr)); 939 usbnet_unlock(un); 940 memcpy(un->un_eaddr, eaddr, sizeof un->un_eaddr); 941 942 struct ifnet *ifp = usbnet_ifp(un); 943 944 /* 945 * We don't support TSOv4 and v6 for now, that are required to 946 * be handled in software for some cases. 947 */ 948 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 949 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 950 #ifdef INET6 951 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 952 #endif 953 if (un->un_flags & ~URE_FLAG_VER_4C00) { 954 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 955 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 956 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 957 } 958 struct ethercom *ec = usbnet_ec(un); 959 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 960 #ifdef notyet 961 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 962 #endif 963 964 usbnet_attach_ifp(un, true, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 965 0, 0); 966 } 967 968 static void 969 ure_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 970 { 971 struct ifnet *ifp = usbnet_ifp(un); 972 uint8_t *buf = c->unc_buf; 973 uint16_t pkt_len = 0; 974 uint16_t pkt_count = 0; 975 struct ure_rxpkt rxhdr; 976 977 usbnet_isowned_rx(un); 978 979 do { 980 if (total_len < sizeof(rxhdr)) { 981 DPRINTF(("too few bytes left for a packet header\n")); 982 ifp->if_ierrors++; 983 return; 984 } 985 986 buf += roundup(pkt_len, 8); 987 988 memcpy(&rxhdr, buf, sizeof(rxhdr)); 989 total_len -= sizeof(rxhdr); 990 991 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 992 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 993 if (pkt_len > total_len) { 994 DPRINTF(("not enough bytes left for next packet\n")); 995 ifp->if_ierrors++; 996 return; 997 } 998 999 total_len -= roundup(pkt_len, 8); 1000 buf += sizeof(rxhdr); 1001 1002 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1003 ure_rxcsum(ifp, &rxhdr), 0, 0); 1004 1005 pkt_count++; 1006 1007 } while (total_len > 0); 1008 1009 if (pkt_count) 1010 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 1011 } 1012 1013 static int 1014 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1015 { 1016 int enabled = ifp->if_csum_flags_rx, flags = 0; 1017 uint32_t csum, misc; 1018 1019 if (enabled == 0) 1020 return 0; 1021 1022 csum = le32toh(rp->ure_csum); 1023 misc = le32toh(rp->ure_misc); 1024 1025 if (csum & URE_RXPKT_IPV4_CS) { 1026 flags |= M_CSUM_IPv4; 1027 if (csum & URE_RXPKT_TCP_CS) 1028 flags |= M_CSUM_TCPv4; 1029 if (csum & URE_RXPKT_UDP_CS) 1030 flags |= M_CSUM_UDPv4; 1031 } else if (csum & URE_RXPKT_IPV6_CS) { 1032 flags = 0; 1033 if (csum & URE_RXPKT_TCP_CS) 1034 flags |= M_CSUM_TCPv6; 1035 if (csum & URE_RXPKT_UDP_CS) 1036 flags |= M_CSUM_UDPv6; 1037 } 1038 1039 flags &= enabled; 1040 if (__predict_false((flags & M_CSUM_IPv4) && 1041 (misc & URE_RXPKT_IP_F))) 1042 flags |= M_CSUM_IPv4_BAD; 1043 if (__predict_false( 1044 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1045 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1046 )) 1047 flags |= M_CSUM_TCP_UDP_BAD; 1048 1049 return flags; 1050 } 1051 1052 static unsigned 1053 ure_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1054 { 1055 struct ure_txpkt txhdr; 1056 uint32_t frm_len = 0; 1057 uint8_t *buf = c->unc_buf; 1058 1059 usbnet_isowned_tx(un); 1060 1061 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1062 return 0; 1063 1064 /* header */ 1065 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1066 URE_TXPKT_TX_LS); 1067 txhdr.ure_csum = htole32(ure_txcsum(m)); 1068 memcpy(buf, &txhdr, sizeof(txhdr)); 1069 buf += sizeof(txhdr); 1070 frm_len = sizeof(txhdr); 1071 1072 /* packet */ 1073 m_copydata(m, 0, m->m_pkthdr.len, buf); 1074 frm_len += m->m_pkthdr.len; 1075 1076 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1077 1078 return frm_len; 1079 } 1080 1081 /* 1082 * We need to calculate L4 checksum in software, if the offset of 1083 * L4 header is larger than 0x7ff = 2047. 1084 */ 1085 static uint32_t 1086 ure_txcsum(struct mbuf *m) 1087 { 1088 struct ether_header *eh; 1089 int flags = m->m_pkthdr.csum_flags; 1090 uint32_t data = m->m_pkthdr.csum_data; 1091 uint32_t reg = 0; 1092 int l3off, l4off; 1093 uint16_t type; 1094 1095 if (flags == 0) 1096 return 0; 1097 1098 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1099 eh = mtod(m, struct ether_header *); 1100 type = eh->ether_type; 1101 } else 1102 m_copydata(m, offsetof(struct ether_header, ether_type), 1103 sizeof(type), &type); 1104 switch (type = htons(type)) { 1105 case ETHERTYPE_IP: 1106 case ETHERTYPE_IPV6: 1107 l3off = ETHER_HDR_LEN; 1108 break; 1109 case ETHERTYPE_VLAN: 1110 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1111 break; 1112 default: 1113 return 0; 1114 } 1115 1116 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1117 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1118 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1119 in_undefer_cksum(m, l3off, flags); 1120 return 0; 1121 } 1122 reg |= URE_TXPKT_IPV4_CS; 1123 if (flags & M_CSUM_TCPv4) 1124 reg |= URE_TXPKT_TCP_CS; 1125 else 1126 reg |= URE_TXPKT_UDP_CS; 1127 reg |= l4off << URE_L4_OFFSET_SHIFT; 1128 } 1129 #ifdef INET6 1130 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1131 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1132 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1133 in6_undefer_cksum(m, l3off, flags); 1134 return 0; 1135 } 1136 reg |= URE_TXPKT_IPV6_CS; 1137 if (flags & M_CSUM_TCPv6) 1138 reg |= URE_TXPKT_TCP_CS; 1139 else 1140 reg |= URE_TXPKT_UDP_CS; 1141 reg |= l4off << URE_L4_OFFSET_SHIFT; 1142 } 1143 #endif 1144 else if (flags & M_CSUM_IPv4) 1145 reg |= URE_TXPKT_IPV4_CS; 1146 1147 return reg; 1148 } 1149 1150 #ifdef _MODULE 1151 #include "ioconf.c" 1152 #endif 1153 1154 USBNET_MODULE(ure) 1155
Indexes created Mon Sep 29 21:09:56 GMT 2025