if_ure.c revision 1.30
1 /* $NetBSD: if_ure.c,v 1.30 2019/08/20 06:37:06 mrg Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.30 2019/08/20 06:37:06 mrg Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 42 #include <net/route.h> 43 44 #include <dev/usb/usbnet.h> 45 46 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 47 #ifdef INET6 48 #include <netinet/in.h> 49 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 50 #endif 51 52 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 53 #include <dev/usb/if_urereg.h> 54 #include <dev/usb/if_urevar.h> 55 56 #define URE_PRINTF(un, fmt, args...) \ 57 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 58 59 #define URE_DEBUG 60 #ifdef URE_DEBUG 61 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 62 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 63 int uredebug = 0; 64 #else 65 #define DPRINTF(x) 66 #define DPRINTFN(n, x) 67 #endif 68 69 static const struct usb_devno ure_devs[] = { 70 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 71 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 72 }; 73 74 #define URE_BUFSZ (16 * 1024) 75 76 static void ure_reset(struct usbnet *); 77 static uint32_t ure_txcsum(struct mbuf *); 78 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 79 static void ure_rtl8152_init(struct usbnet *); 80 static void ure_rtl8153_init(struct usbnet *); 81 static void ure_disable_teredo(struct usbnet *); 82 static void ure_init_fifo(struct usbnet *); 83 84 static void ure_stop_cb(struct ifnet *, int); 85 static int ure_ioctl_cb(struct ifnet *, u_long, void *); 86 static int ure_mii_read_reg(struct usbnet *, int, int, uint16_t *); 87 static int ure_mii_write_reg(struct usbnet *, int, int, uint16_t); 88 static void ure_miibus_statchg(struct ifnet *); 89 static unsigned ure_tx_prepare(struct usbnet *, struct mbuf *, 90 struct usbnet_chain *); 91 static void ure_rx_loop(struct usbnet *, struct usbnet_chain *, uint32_t); 92 static int ure_init(struct ifnet *); 93 94 static int ure_match(device_t, cfdata_t, void *); 95 static void ure_attach(device_t, device_t, void *); 96 97 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 98 usbnet_detach, usbnet_activate); 99 100 static struct usbnet_ops ure_ops = { 101 .uno_stop = ure_stop_cb, 102 .uno_ioctl = ure_ioctl_cb, 103 .uno_read_reg = ure_mii_read_reg, 104 .uno_write_reg = ure_mii_write_reg, 105 .uno_statchg = ure_miibus_statchg, 106 .uno_tx_prepare = ure_tx_prepare, 107 .uno_rx_loop = ure_rx_loop, 108 .uno_init = ure_init, 109 }; 110 111 static int 112 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 113 void *buf, int len) 114 { 115 usb_device_request_t req; 116 usbd_status err; 117 118 if (usbnet_isdying(un)) 119 return 0; 120 121 if (rw == URE_CTL_WRITE) 122 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 123 else 124 req.bmRequestType = UT_READ_VENDOR_DEVICE; 125 req.bRequest = UR_SET_ADDRESS; 126 USETW(req.wValue, val); 127 USETW(req.wIndex, index); 128 USETW(req.wLength, len); 129 130 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 131 rw, val, index, len)); 132 err = usbd_do_request(un->un_udev, &req, buf); 133 if (err) { 134 DPRINTF(("ure_ctl: error %d\n", err)); 135 return -1; 136 } 137 138 return 0; 139 } 140 141 static int 142 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 143 void *buf, int len) 144 { 145 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 146 } 147 148 static int 149 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 150 void *buf, int len) 151 { 152 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 153 } 154 155 static uint8_t 156 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 157 { 158 uint32_t val; 159 uint8_t temp[4]; 160 uint8_t shift; 161 162 shift = (reg & 3) << 3; 163 reg &= ~3; 164 165 ure_read_mem(un, reg, index, &temp, 4); 166 val = UGETDW(temp); 167 val >>= shift; 168 169 return val & 0xff; 170 } 171 172 static uint16_t 173 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 174 { 175 uint32_t val; 176 uint8_t temp[4]; 177 uint8_t shift; 178 179 shift = (reg & 2) << 3; 180 reg &= ~3; 181 182 ure_read_mem(un, reg, index, &temp, 4); 183 val = UGETDW(temp); 184 val >>= shift; 185 186 return val & 0xffff; 187 } 188 189 static uint32_t 190 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 191 { 192 uint8_t temp[4]; 193 194 ure_read_mem(un, reg, index, &temp, 4); 195 return UGETDW(temp); 196 } 197 198 static int 199 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 200 { 201 uint16_t byen; 202 uint8_t temp[4]; 203 uint8_t shift; 204 205 byen = URE_BYTE_EN_BYTE; 206 shift = reg & 3; 207 val &= 0xff; 208 209 if (reg & 3) { 210 byen <<= shift; 211 val <<= (shift << 3); 212 reg &= ~3; 213 } 214 215 USETDW(temp, val); 216 return ure_write_mem(un, reg, index | byen, &temp, 4); 217 } 218 219 static int 220 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 221 { 222 uint16_t byen; 223 uint8_t temp[4]; 224 uint8_t shift; 225 226 byen = URE_BYTE_EN_WORD; 227 shift = reg & 2; 228 val &= 0xffff; 229 230 if (reg & 2) { 231 byen <<= shift; 232 val <<= (shift << 3); 233 reg &= ~3; 234 } 235 236 USETDW(temp, val); 237 return ure_write_mem(un, reg, index | byen, &temp, 4); 238 } 239 240 static int 241 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 242 { 243 uint8_t temp[4]; 244 245 USETDW(temp, val); 246 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 247 } 248 249 static uint16_t 250 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 251 { 252 uint16_t reg; 253 254 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 255 reg = (addr & 0x0fff) | 0xb000; 256 257 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 258 } 259 260 static void 261 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 262 { 263 uint16_t reg; 264 265 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 266 reg = (addr & 0x0fff) | 0xb000; 267 268 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 269 } 270 271 static int 272 ure_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 273 { 274 usbnet_isowned_mii(un); 275 276 if (un->un_phyno != phy) 277 return EINVAL; 278 279 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 280 if (reg == RTK_GMEDIASTAT) { 281 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 282 return USBD_NORMAL_COMPLETION; 283 } 284 285 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 286 287 return 0; 288 } 289 290 static int 291 ure_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 292 { 293 usbnet_isowned_mii(un); 294 295 if (un->un_phyno != phy) 296 return EINVAL; 297 298 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 299 300 return 0; 301 } 302 303 static void 304 ure_miibus_statchg(struct ifnet *ifp) 305 { 306 struct usbnet * const un = ifp->if_softc; 307 struct mii_data * const mii = usbnet_mii(un); 308 309 if (usbnet_isdying(un)) 310 return; 311 312 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 313 (IFM_ACTIVE | IFM_AVALID)) { 314 switch (IFM_SUBTYPE(mii->mii_media_active)) { 315 case IFM_10_T: 316 case IFM_100_TX: 317 usbnet_set_link(un, true); 318 break; 319 case IFM_1000_T: 320 if ((un->un_flags & URE_FLAG_8152) != 0) 321 break; 322 usbnet_set_link(un, true); 323 break; 324 default: 325 break; 326 } 327 } 328 } 329 330 static void 331 ure_setiff_locked(struct usbnet *un) 332 { 333 struct ethercom *ec = usbnet_ec(un); 334 struct ifnet *ifp = usbnet_ifp(un); 335 struct ether_multi *enm; 336 struct ether_multistep step; 337 uint32_t hashes[2] = { 0, 0 }; 338 uint32_t hash; 339 uint32_t rxmode; 340 341 usbnet_isowned(un); 342 343 if (usbnet_isdying(un)) 344 return; 345 346 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 347 rxmode &= ~URE_RCR_ACPT_ALL; 348 349 /* 350 * Always accept frames destined to our station address. 351 * Always accept broadcast frames. 352 */ 353 rxmode |= URE_RCR_APM | URE_RCR_AB; 354 355 if (ifp->if_flags & IFF_PROMISC) { 356 rxmode |= URE_RCR_AAP; 357 allmulti: 358 ETHER_LOCK(ec); 359 ec->ec_flags |= ETHER_F_ALLMULTI; 360 ETHER_UNLOCK(ec); 361 rxmode |= URE_RCR_AM; 362 hashes[0] = hashes[1] = 0xffffffff; 363 } else { 364 rxmode |= URE_RCR_AM; 365 366 ETHER_LOCK(ec); 367 ec->ec_flags &= ~ETHER_F_ALLMULTI; 368 369 ETHER_FIRST_MULTI(step, ec, enm); 370 while (enm != NULL) { 371 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 372 ETHER_ADDR_LEN)) { 373 ETHER_UNLOCK(ec); 374 goto allmulti; 375 } 376 377 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 378 >> 26; 379 if (hash < 32) 380 hashes[0] |= (1 << hash); 381 else 382 hashes[1] |= (1 << (hash - 32)); 383 384 ETHER_NEXT_MULTI(step, enm); 385 } 386 ETHER_UNLOCK(ec); 387 388 hash = bswap32(hashes[0]); 389 hashes[0] = bswap32(hashes[1]); 390 hashes[1] = hash; 391 } 392 393 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 394 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 395 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 396 } 397 398 static void 399 ure_setiff(struct usbnet *un) 400 { 401 402 usbnet_lock(un); 403 ure_setiff_locked(un); 404 usbnet_unlock(un); 405 } 406 407 static void 408 ure_reset(struct usbnet *un) 409 { 410 int i; 411 412 usbnet_isowned(un); 413 414 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 415 416 for (i = 0; i < URE_TIMEOUT; i++) { 417 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 418 URE_CR_RST)) 419 break; 420 usbd_delay_ms(un->un_udev, 10); 421 } 422 if (i == URE_TIMEOUT) 423 URE_PRINTF(un, "reset never completed\n"); 424 } 425 426 static int 427 ure_init_locked(struct ifnet *ifp) 428 { 429 struct usbnet * const un = ifp->if_softc; 430 uint8_t eaddr[8]; 431 432 usbnet_isowned(un); 433 434 if (usbnet_isdying(un)) 435 return EIO; 436 437 /* Cancel pending I/O. */ 438 if (ifp->if_flags & IFF_RUNNING) 439 usbnet_stop(un, ifp, 1); 440 441 /* Set MAC address. */ 442 memset(eaddr, 0, sizeof(eaddr)); 443 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 444 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 445 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 446 eaddr, 8); 447 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 448 449 /* Reset the packet filter. */ 450 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 451 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 452 ~URE_FMC_FCR_MCU_EN); 453 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 454 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 455 URE_FMC_FCR_MCU_EN); 456 457 /* Enable transmit and receive. */ 458 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 459 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 460 URE_CR_TE); 461 462 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 463 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 464 ~URE_RXDY_GATED_EN); 465 466 /* Load the multicast filter. */ 467 ure_setiff_locked(un); 468 469 return usbnet_init_rx_tx(un); 470 } 471 472 static int 473 ure_init(struct ifnet *ifp) 474 { 475 struct usbnet * const un = ifp->if_softc; 476 477 usbnet_lock(un); 478 int ret = ure_init_locked(ifp); 479 usbnet_unlock(un); 480 481 return ret; 482 } 483 484 static void 485 ure_stop_cb(struct ifnet *ifp, int disable __unused) 486 { 487 struct usbnet * const un = ifp->if_softc; 488 489 ure_reset(un); 490 } 491 492 static void 493 ure_rtl8152_init(struct usbnet *un) 494 { 495 uint32_t pwrctrl; 496 497 /* Disable ALDPS. */ 498 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 499 URE_DIS_SDSAVE); 500 usbd_delay_ms(un->un_udev, 20); 501 502 if (un->un_flags & URE_FLAG_VER_4C00) { 503 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 504 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 505 ~URE_LED_MODE_MASK); 506 } 507 508 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 509 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 510 ~URE_POWER_CUT); 511 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 512 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 513 ~URE_RESUME_INDICATE); 514 515 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 516 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 517 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 518 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 519 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 520 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 521 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 522 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 523 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 524 URE_SPDWN_LINKCHG_MSK); 525 526 /* Enable Rx aggregation. */ 527 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 528 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 529 ~URE_RX_AGG_DISABLE); 530 531 /* Disable ALDPS. */ 532 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 533 URE_DIS_SDSAVE); 534 usbd_delay_ms(un->un_udev, 20); 535 536 ure_init_fifo(un); 537 538 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 539 URE_TX_AGG_MAX_THRESHOLD); 540 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 541 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 542 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 543 } 544 545 static void 546 ure_rtl8153_init(struct usbnet *un) 547 { 548 uint16_t val; 549 uint8_t u1u2[8]; 550 int i; 551 552 /* Disable ALDPS. */ 553 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 554 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 555 usbd_delay_ms(un->un_udev, 20); 556 557 memset(u1u2, 0x00, sizeof(u1u2)); 558 ure_write_mem(un, URE_USB_TOLERANCE, 559 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 560 561 for (i = 0; i < URE_TIMEOUT; i++) { 562 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 563 URE_AUTOLOAD_DONE) 564 break; 565 usbd_delay_ms(un->un_udev, 10); 566 } 567 if (i == URE_TIMEOUT) 568 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 569 570 for (i = 0; i < URE_TIMEOUT; i++) { 571 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 572 URE_PHY_STAT_MASK; 573 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 574 break; 575 usbd_delay_ms(un->un_udev, 10); 576 } 577 if (i == URE_TIMEOUT) 578 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 579 580 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 581 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 582 ~URE_U2P3_ENABLE); 583 584 if (un->un_flags & URE_FLAG_VER_5C10) { 585 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 586 val &= ~URE_PWD_DN_SCALE_MASK; 587 val |= URE_PWD_DN_SCALE(96); 588 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 589 590 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 591 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 592 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 593 } else if (un->un_flags & URE_FLAG_VER_5C20) { 594 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 595 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 596 ~URE_ECM_ALDPS); 597 } 598 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 599 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 600 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 601 0) 602 val &= ~URE_DYNAMIC_BURST; 603 else 604 val |= URE_DYNAMIC_BURST; 605 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 606 } 607 608 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 609 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 610 URE_EP4_FULL_FC); 611 612 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 613 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 614 ~URE_TIMER11_EN); 615 616 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 617 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 618 ~URE_LED_MODE_MASK); 619 620 if ((un->un_flags & URE_FLAG_VER_5C10) && 621 un->un_udev->ud_speed != USB_SPEED_SUPER) 622 val = URE_LPM_TIMER_500MS; 623 else 624 val = URE_LPM_TIMER_500US; 625 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 626 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 627 628 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 629 val &= ~URE_SEN_VAL_MASK; 630 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 631 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 632 633 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 634 635 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 636 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 637 ~(URE_PWR_EN | URE_PHASE2_EN)); 638 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 639 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 640 ~URE_PCUT_STATUS); 641 642 memset(u1u2, 0xff, sizeof(u1u2)); 643 ure_write_mem(un, URE_USB_TOLERANCE, 644 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 645 646 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 647 URE_ALDPS_SPDWN_RATIO); 648 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 649 URE_EEE_SPDWN_RATIO); 650 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 651 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 652 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 653 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 654 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 655 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 656 URE_EEE_SPDWN_EN); 657 658 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 659 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 660 val |= URE_U2P3_ENABLE; 661 else 662 val &= ~URE_U2P3_ENABLE; 663 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 664 665 memset(u1u2, 0x00, sizeof(u1u2)); 666 ure_write_mem(un, URE_USB_TOLERANCE, 667 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 668 669 /* Disable ALDPS. */ 670 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 671 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 672 usbd_delay_ms(un->un_udev, 20); 673 674 ure_init_fifo(un); 675 676 /* Enable Rx aggregation. */ 677 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 678 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 679 ~URE_RX_AGG_DISABLE); 680 681 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 682 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 683 val |= URE_U2P3_ENABLE; 684 else 685 val &= ~URE_U2P3_ENABLE; 686 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 687 688 memset(u1u2, 0xff, sizeof(u1u2)); 689 ure_write_mem(un, URE_USB_TOLERANCE, 690 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 691 } 692 693 static void 694 ure_disable_teredo(struct usbnet *un) 695 { 696 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 697 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 698 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 699 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 700 URE_WDT6_SET_MODE); 701 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 702 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 703 } 704 705 static void 706 ure_init_fifo(struct usbnet *un) 707 { 708 uint32_t rx_fifo1, rx_fifo2; 709 int i; 710 711 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 712 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 713 URE_RXDY_GATED_EN); 714 715 ure_disable_teredo(un); 716 717 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, 718 ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 719 ~URE_RCR_ACPT_ALL); 720 721 if (!(un->un_flags & URE_FLAG_8152)) { 722 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 723 URE_FLAG_VER_5C20)) 724 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 725 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 726 if (un->un_flags & URE_FLAG_VER_5C00) 727 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 728 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 729 ~URE_CTAP_SHORT_EN); 730 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 731 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 732 URE_EEE_CLKDIV_EN); 733 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 734 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 735 URE_EN_10M_BGOFF); 736 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 737 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 738 URE_EN_10M_PLLOFF); 739 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 740 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 741 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 742 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 743 URE_PFM_PWM_SWITCH); 744 745 /* Enable LPF corner auto tune. */ 746 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 747 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 748 749 /* Adjust 10M amplitude. */ 750 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 751 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 752 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 753 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 754 } 755 756 ure_reset(un); 757 758 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 759 760 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 761 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 762 ~URE_NOW_IS_OOB); 763 764 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 765 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 766 ~URE_MCU_BORW_EN); 767 for (i = 0; i < URE_TIMEOUT; i++) { 768 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 769 URE_LINK_LIST_READY) 770 break; 771 usbd_delay_ms(un->un_udev, 10); 772 } 773 if (i == URE_TIMEOUT) 774 URE_PRINTF(un, "timeout waiting for OOB control\n"); 775 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 776 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 777 URE_RE_INIT_LL); 778 for (i = 0; i < URE_TIMEOUT; i++) { 779 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 780 URE_LINK_LIST_READY) 781 break; 782 usbd_delay_ms(un->un_udev, 10); 783 } 784 if (i == URE_TIMEOUT) 785 URE_PRINTF(un, "timeout waiting for OOB control\n"); 786 787 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 788 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 789 ~URE_CPCR_RX_VLAN); 790 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 791 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 792 URE_TCR0_AUTO_FIFO); 793 794 /* Configure Rx FIFO threshold and coalescing. */ 795 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 796 URE_RXFIFO_THR1_NORMAL); 797 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 798 rx_fifo1 = URE_RXFIFO_THR2_FULL; 799 rx_fifo2 = URE_RXFIFO_THR3_FULL; 800 } else { 801 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 802 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 803 } 804 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 805 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 806 807 /* Configure Tx FIFO threshold. */ 808 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 809 URE_TXFIFO_THR_NORMAL); 810 } 811 812 static int 813 ure_ioctl_cb(struct ifnet *ifp, u_long cmd, void *data) 814 { 815 struct usbnet * const un = ifp->if_softc; 816 817 switch (cmd) { 818 case SIOCADDMULTI: 819 case SIOCDELMULTI: 820 ure_setiff(un); 821 break; 822 default: 823 break; 824 } 825 826 return 0; 827 } 828 829 static int 830 ure_match(device_t parent, cfdata_t match, void *aux) 831 { 832 struct usb_attach_arg *uaa = aux; 833 834 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 835 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 836 } 837 838 static void 839 ure_attach(device_t parent, device_t self, void *aux) 840 { 841 UBSNET_MII_DECL_DEFAULT(unm); 842 struct usbnet * const un = device_private(self); 843 struct usb_attach_arg *uaa = aux; 844 struct usbd_device *dev = uaa->uaa_device; 845 usb_interface_descriptor_t *id; 846 usb_endpoint_descriptor_t *ed; 847 int error, i; 848 uint16_t ver; 849 uint8_t eaddr[8]; /* 2byte padded */ 850 char *devinfop; 851 852 aprint_naive("\n"); 853 aprint_normal("\n"); 854 devinfop = usbd_devinfo_alloc(dev, 0); 855 aprint_normal_dev(self, "%s\n", devinfop); 856 usbd_devinfo_free(devinfop); 857 858 un->un_dev = self; 859 un->un_udev = dev; 860 un->un_sc = un; 861 un->un_ops = &ure_ops; 862 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 863 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 864 un->un_rx_list_cnt = URE_RX_LIST_CNT; 865 un->un_tx_list_cnt = URE_TX_LIST_CNT; 866 un->un_rx_bufsz = URE_BUFSZ; 867 un->un_tx_bufsz = URE_BUFSZ; 868 869 #define URE_CONFIG_NO 1 /* XXX */ 870 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 871 if (error) { 872 aprint_error_dev(self, "failed to set configuration: %s\n", 873 usbd_errstr(error)); 874 return; /* XXX */ 875 } 876 877 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 878 un->un_flags |= URE_FLAG_8152; 879 880 #define URE_IFACE_IDX 0 /* XXX */ 881 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 882 if (error) { 883 aprint_error_dev(self, "failed to get interface handle: %s\n", 884 usbd_errstr(error)); 885 return; /* XXX */ 886 } 887 888 id = usbd_get_interface_descriptor(un->un_iface); 889 for (i = 0; i < id->bNumEndpoints; i++) { 890 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 891 if (ed == NULL) { 892 aprint_error_dev(self, "couldn't get ep %d\n", i); 893 return; /* XXX */ 894 } 895 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 896 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 897 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 898 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 899 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 900 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 901 } 902 } 903 904 /* Set these up now for ure_ctl(). */ 905 usbnet_attach(un, "uredet"); 906 907 un->un_phyno = 0; 908 909 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 910 switch (ver) { 911 case 0x4c00: 912 un->un_flags |= URE_FLAG_VER_4C00; 913 break; 914 case 0x4c10: 915 un->un_flags |= URE_FLAG_VER_4C10; 916 break; 917 case 0x5c00: 918 un->un_flags |= URE_FLAG_VER_5C00; 919 break; 920 case 0x5c10: 921 un->un_flags |= URE_FLAG_VER_5C10; 922 break; 923 case 0x5c20: 924 un->un_flags |= URE_FLAG_VER_5C20; 925 break; 926 case 0x5c30: 927 un->un_flags |= URE_FLAG_VER_5C30; 928 break; 929 default: 930 /* fake addr? or just fail? */ 931 break; 932 } 933 aprint_normal_dev(self, "RTL%d %sver %04x\n", 934 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 935 (un->un_flags != 0) ? "" : "unknown ", 936 ver); 937 938 usbnet_lock(un); 939 if (un->un_flags & URE_FLAG_8152) 940 ure_rtl8152_init(un); 941 else 942 ure_rtl8153_init(un); 943 944 if (un->un_flags & URE_FLAG_VER_4C00) 945 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 946 sizeof(eaddr)); 947 else 948 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 949 sizeof(eaddr)); 950 usbnet_unlock(un); 951 memcpy(un->un_eaddr, eaddr, sizeof un->un_eaddr); 952 953 struct ifnet *ifp = usbnet_ifp(un); 954 955 /* 956 * We don't support TSOv4 and v6 for now, that are required to 957 * be handled in software for some cases. 958 */ 959 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 960 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 961 #ifdef INET6 962 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 963 #endif 964 if (un->un_flags & ~URE_FLAG_VER_4C00) { 965 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 966 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 967 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 968 } 969 struct ethercom *ec = usbnet_ec(un); 970 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 971 #ifdef notyet 972 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 973 #endif 974 975 unm.un_mii_phyloc = un->un_phyno; 976 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 977 0, &unm); 978 } 979 980 static void 981 ure_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 982 { 983 struct ifnet *ifp = usbnet_ifp(un); 984 uint8_t *buf = c->unc_buf; 985 uint16_t pkt_len = 0; 986 uint16_t pkt_count = 0; 987 struct ure_rxpkt rxhdr; 988 989 usbnet_isowned_rx(un); 990 991 do { 992 if (total_len < sizeof(rxhdr)) { 993 DPRINTF(("too few bytes left for a packet header\n")); 994 ifp->if_ierrors++; 995 return; 996 } 997 998 buf += roundup(pkt_len, 8); 999 1000 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1001 total_len -= sizeof(rxhdr); 1002 1003 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1004 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 1005 if (pkt_len > total_len) { 1006 DPRINTF(("not enough bytes left for next packet\n")); 1007 ifp->if_ierrors++; 1008 return; 1009 } 1010 1011 total_len -= roundup(pkt_len, 8); 1012 buf += sizeof(rxhdr); 1013 1014 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1015 ure_rxcsum(ifp, &rxhdr), 0, 0); 1016 1017 pkt_count++; 1018 1019 } while (total_len > 0); 1020 1021 if (pkt_count) 1022 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 1023 } 1024 1025 static int 1026 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1027 { 1028 int enabled = ifp->if_csum_flags_rx, flags = 0; 1029 uint32_t csum, misc; 1030 1031 if (enabled == 0) 1032 return 0; 1033 1034 csum = le32toh(rp->ure_csum); 1035 misc = le32toh(rp->ure_misc); 1036 1037 if (csum & URE_RXPKT_IPV4_CS) { 1038 flags |= M_CSUM_IPv4; 1039 if (csum & URE_RXPKT_TCP_CS) 1040 flags |= M_CSUM_TCPv4; 1041 if (csum & URE_RXPKT_UDP_CS) 1042 flags |= M_CSUM_UDPv4; 1043 } else if (csum & URE_RXPKT_IPV6_CS) { 1044 flags = 0; 1045 if (csum & URE_RXPKT_TCP_CS) 1046 flags |= M_CSUM_TCPv6; 1047 if (csum & URE_RXPKT_UDP_CS) 1048 flags |= M_CSUM_UDPv6; 1049 } 1050 1051 flags &= enabled; 1052 if (__predict_false((flags & M_CSUM_IPv4) && 1053 (misc & URE_RXPKT_IP_F))) 1054 flags |= M_CSUM_IPv4_BAD; 1055 if (__predict_false( 1056 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1057 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1058 )) 1059 flags |= M_CSUM_TCP_UDP_BAD; 1060 1061 return flags; 1062 } 1063 1064 static unsigned 1065 ure_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1066 { 1067 struct ure_txpkt txhdr; 1068 uint32_t frm_len = 0; 1069 uint8_t *buf = c->unc_buf; 1070 1071 usbnet_isowned_tx(un); 1072 1073 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1074 return 0; 1075 1076 /* header */ 1077 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1078 URE_TXPKT_TX_LS); 1079 txhdr.ure_csum = htole32(ure_txcsum(m)); 1080 memcpy(buf, &txhdr, sizeof(txhdr)); 1081 buf += sizeof(txhdr); 1082 frm_len = sizeof(txhdr); 1083 1084 /* packet */ 1085 m_copydata(m, 0, m->m_pkthdr.len, buf); 1086 frm_len += m->m_pkthdr.len; 1087 1088 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1089 1090 return frm_len; 1091 } 1092 1093 /* 1094 * We need to calculate L4 checksum in software, if the offset of 1095 * L4 header is larger than 0x7ff = 2047. 1096 */ 1097 static uint32_t 1098 ure_txcsum(struct mbuf *m) 1099 { 1100 struct ether_header *eh; 1101 int flags = m->m_pkthdr.csum_flags; 1102 uint32_t data = m->m_pkthdr.csum_data; 1103 uint32_t reg = 0; 1104 int l3off, l4off; 1105 uint16_t type; 1106 1107 if (flags == 0) 1108 return 0; 1109 1110 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1111 eh = mtod(m, struct ether_header *); 1112 type = eh->ether_type; 1113 } else 1114 m_copydata(m, offsetof(struct ether_header, ether_type), 1115 sizeof(type), &type); 1116 switch (type = htons(type)) { 1117 case ETHERTYPE_IP: 1118 case ETHERTYPE_IPV6: 1119 l3off = ETHER_HDR_LEN; 1120 break; 1121 case ETHERTYPE_VLAN: 1122 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1123 break; 1124 default: 1125 return 0; 1126 } 1127 1128 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1129 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1130 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1131 in_undefer_cksum(m, l3off, flags); 1132 return 0; 1133 } 1134 reg |= URE_TXPKT_IPV4_CS; 1135 if (flags & M_CSUM_TCPv4) 1136 reg |= URE_TXPKT_TCP_CS; 1137 else 1138 reg |= URE_TXPKT_UDP_CS; 1139 reg |= l4off << URE_L4_OFFSET_SHIFT; 1140 } 1141 #ifdef INET6 1142 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1143 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1144 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1145 in6_undefer_cksum(m, l3off, flags); 1146 return 0; 1147 } 1148 reg |= URE_TXPKT_IPV6_CS; 1149 if (flags & M_CSUM_TCPv6) 1150 reg |= URE_TXPKT_TCP_CS; 1151 else 1152 reg |= URE_TXPKT_UDP_CS; 1153 reg |= l4off << URE_L4_OFFSET_SHIFT; 1154 } 1155 #endif 1156 else if (flags & M_CSUM_IPv4) 1157 reg |= URE_TXPKT_IPV4_CS; 1158 1159 return reg; 1160 } 1161 1162 #ifdef _MODULE 1163 #include "ioconf.c" 1164 #endif 1165 1166 USBNET_MODULE(ure) 1167
Indexes created Mon Sep 29 21:09:56 GMT 2025