if_ure.c revision 1.39
1 /* $NetBSD: if_ure.c,v 1.39 2020/03/21 06:54:43 skrll Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.39 2020/03/21 06:54:43 skrll Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/cprng.h> 42 43 #include <net/route.h> 44 45 #include <dev/usb/usbnet.h> 46 47 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 48 #ifdef INET6 49 #include <netinet/in.h> 50 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 51 #endif 52 53 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54 #include <dev/usb/if_urereg.h> 55 #include <dev/usb/if_urevar.h> 56 57 #define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60 #define URE_DEBUG 61 #ifdef URE_DEBUG 62 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64 int uredebug = 0; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 #define ETHER_IS_ZERO(addr) \ 71 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 72 73 static const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 76 }; 77 78 #define URE_BUFSZ (16 * 1024) 79 80 static void ure_reset(struct usbnet *); 81 static uint32_t ure_txcsum(struct mbuf *); 82 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 83 static void ure_rtl8152_init(struct usbnet *); 84 static void ure_rtl8153_init(struct usbnet *); 85 static void ure_disable_teredo(struct usbnet *); 86 static void ure_init_fifo(struct usbnet *); 87 88 static void ure_uno_stop(struct ifnet *, int); 89 static int ure_uno_ioctl(struct ifnet *, u_long, void *); 90 static int ure_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 91 static int ure_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 92 static void ure_uno_miibus_statchg(struct ifnet *); 93 static unsigned ure_uno_tx_prepare(struct usbnet *, struct mbuf *, 94 struct usbnet_chain *); 95 static void ure_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 96 uint32_t); 97 static int ure_uno_init(struct ifnet *); 98 99 static int ure_match(device_t, cfdata_t, void *); 100 static void ure_attach(device_t, device_t, void *); 101 102 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 103 usbnet_detach, usbnet_activate); 104 105 static const struct usbnet_ops ure_ops = { 106 .uno_stop = ure_uno_stop, 107 .uno_ioctl = ure_uno_ioctl, 108 .uno_read_reg = ure_uno_mii_read_reg, 109 .uno_write_reg = ure_uno_mii_write_reg, 110 .uno_statchg = ure_uno_miibus_statchg, 111 .uno_tx_prepare = ure_uno_tx_prepare, 112 .uno_rx_loop = ure_uno_rx_loop, 113 .uno_init = ure_uno_init, 114 }; 115 116 static int 117 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 118 void *buf, int len) 119 { 120 usb_device_request_t req; 121 usbd_status err; 122 123 if (usbnet_isdying(un)) 124 return 0; 125 126 if (rw == URE_CTL_WRITE) 127 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 128 else 129 req.bmRequestType = UT_READ_VENDOR_DEVICE; 130 req.bRequest = UR_SET_ADDRESS; 131 USETW(req.wValue, val); 132 USETW(req.wIndex, index); 133 USETW(req.wLength, len); 134 135 DPRINTFN(5, ("ure_ctl: rw %d, val %04hu, index %04hu, len %d\n", 136 rw, val, index, len)); 137 err = usbd_do_request(un->un_udev, &req, buf); 138 if (err) { 139 DPRINTF(("ure_ctl: error %d\n", err)); 140 return -1; 141 } 142 143 return 0; 144 } 145 146 static int 147 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 148 void *buf, int len) 149 { 150 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 151 } 152 153 static int 154 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 155 void *buf, int len) 156 { 157 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 158 } 159 160 static uint8_t 161 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 162 { 163 uint32_t val; 164 uint8_t temp[4]; 165 uint8_t shift; 166 167 shift = (reg & 3) << 3; 168 reg &= ~3; 169 170 ure_read_mem(un, reg, index, &temp, 4); 171 val = UGETDW(temp); 172 val >>= shift; 173 174 return val & 0xff; 175 } 176 177 static uint16_t 178 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 179 { 180 uint32_t val; 181 uint8_t temp[4]; 182 uint8_t shift; 183 184 shift = (reg & 2) << 3; 185 reg &= ~3; 186 187 ure_read_mem(un, reg, index, &temp, 4); 188 val = UGETDW(temp); 189 val >>= shift; 190 191 return val & 0xffff; 192 } 193 194 static uint32_t 195 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 196 { 197 uint8_t temp[4]; 198 199 ure_read_mem(un, reg, index, &temp, 4); 200 return UGETDW(temp); 201 } 202 203 static int 204 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 205 { 206 uint16_t byen; 207 uint8_t temp[4]; 208 uint8_t shift; 209 210 byen = URE_BYTE_EN_BYTE; 211 shift = reg & 3; 212 val &= 0xff; 213 214 if (reg & 3) { 215 byen <<= shift; 216 val <<= (shift << 3); 217 reg &= ~3; 218 } 219 220 USETDW(temp, val); 221 return ure_write_mem(un, reg, index | byen, &temp, 4); 222 } 223 224 static int 225 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 226 { 227 uint16_t byen; 228 uint8_t temp[4]; 229 uint8_t shift; 230 231 byen = URE_BYTE_EN_WORD; 232 shift = reg & 2; 233 val &= 0xffff; 234 235 if (reg & 2) { 236 byen <<= shift; 237 val <<= (shift << 3); 238 reg &= ~3; 239 } 240 241 USETDW(temp, val); 242 return ure_write_mem(un, reg, index | byen, &temp, 4); 243 } 244 245 static int 246 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 247 { 248 uint8_t temp[4]; 249 250 USETDW(temp, val); 251 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 252 } 253 254 static uint16_t 255 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 256 { 257 uint16_t reg; 258 259 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 260 reg = (addr & 0x0fff) | 0xb000; 261 262 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 263 } 264 265 static void 266 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 267 { 268 uint16_t reg; 269 270 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 271 reg = (addr & 0x0fff) | 0xb000; 272 273 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 274 } 275 276 static int 277 ure_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 278 { 279 280 if (un->un_phyno != phy) 281 return EINVAL; 282 283 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 284 if (reg == RTK_GMEDIASTAT) { 285 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 286 return USBD_NORMAL_COMPLETION; 287 } 288 289 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 290 291 return 0; 292 } 293 294 static int 295 ure_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 296 { 297 298 if (un->un_phyno != phy) 299 return EINVAL; 300 301 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 302 303 return 0; 304 } 305 306 static void 307 ure_uno_miibus_statchg(struct ifnet *ifp) 308 { 309 struct usbnet * const un = ifp->if_softc; 310 struct mii_data * const mii = usbnet_mii(un); 311 312 if (usbnet_isdying(un)) 313 return; 314 315 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 316 (IFM_ACTIVE | IFM_AVALID)) { 317 switch (IFM_SUBTYPE(mii->mii_media_active)) { 318 case IFM_10_T: 319 case IFM_100_TX: 320 usbnet_set_link(un, true); 321 break; 322 case IFM_1000_T: 323 if ((un->un_flags & URE_FLAG_8152) != 0) 324 break; 325 usbnet_set_link(un, true); 326 break; 327 default: 328 break; 329 } 330 } 331 } 332 333 static void 334 ure_setiff_locked(struct usbnet *un) 335 { 336 struct ethercom *ec = usbnet_ec(un); 337 struct ifnet *ifp = usbnet_ifp(un); 338 struct ether_multi *enm; 339 struct ether_multistep step; 340 uint32_t hashes[2] = { 0, 0 }; 341 uint32_t hash; 342 uint32_t rxmode; 343 344 usbnet_isowned_core(un); 345 346 if (usbnet_isdying(un)) 347 return; 348 349 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 350 rxmode &= ~URE_RCR_ACPT_ALL; 351 352 /* 353 * Always accept frames destined to our station address. 354 * Always accept broadcast frames. 355 */ 356 rxmode |= URE_RCR_APM | URE_RCR_AB; 357 358 if (ifp->if_flags & IFF_PROMISC) { 359 rxmode |= URE_RCR_AAP; 360 allmulti: 361 ETHER_LOCK(ec); 362 ec->ec_flags |= ETHER_F_ALLMULTI; 363 ETHER_UNLOCK(ec); 364 rxmode |= URE_RCR_AM; 365 hashes[0] = hashes[1] = 0xffffffff; 366 } else { 367 rxmode |= URE_RCR_AM; 368 369 ETHER_LOCK(ec); 370 ec->ec_flags &= ~ETHER_F_ALLMULTI; 371 372 ETHER_FIRST_MULTI(step, ec, enm); 373 while (enm != NULL) { 374 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 375 ETHER_ADDR_LEN)) { 376 ETHER_UNLOCK(ec); 377 goto allmulti; 378 } 379 380 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 381 >> 26; 382 if (hash < 32) 383 hashes[0] |= (1 << hash); 384 else 385 hashes[1] |= (1 << (hash - 32)); 386 387 ETHER_NEXT_MULTI(step, enm); 388 } 389 ETHER_UNLOCK(ec); 390 391 hash = bswap32(hashes[0]); 392 hashes[0] = bswap32(hashes[1]); 393 hashes[1] = hash; 394 } 395 396 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 397 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 398 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 399 } 400 401 static void 402 ure_reset(struct usbnet *un) 403 { 404 int i; 405 406 usbnet_isowned_core(un); 407 408 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 409 410 for (i = 0; i < URE_TIMEOUT; i++) { 411 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 412 URE_CR_RST)) 413 break; 414 usbd_delay_ms(un->un_udev, 10); 415 } 416 if (i == URE_TIMEOUT) 417 URE_PRINTF(un, "reset never completed\n"); 418 } 419 420 static int 421 ure_init_locked(struct ifnet *ifp) 422 { 423 struct usbnet * const un = ifp->if_softc; 424 uint8_t eaddr[8]; 425 426 usbnet_isowned_core(un); 427 428 if (usbnet_isdying(un)) 429 return EIO; 430 431 /* Cancel pending I/O. */ 432 if (ifp->if_flags & IFF_RUNNING) 433 usbnet_stop(un, ifp, 1); 434 435 /* Set MAC address. */ 436 memset(eaddr, 0, sizeof(eaddr)); 437 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 438 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 439 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 440 eaddr, 8); 441 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 442 443 /* Reset the packet filter. */ 444 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 445 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 446 ~URE_FMC_FCR_MCU_EN); 447 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 448 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 449 URE_FMC_FCR_MCU_EN); 450 451 /* Enable transmit and receive. */ 452 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 453 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 454 URE_CR_TE); 455 456 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 457 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 458 ~URE_RXDY_GATED_EN); 459 460 /* Load the multicast filter. */ 461 ure_setiff_locked(un); 462 463 return usbnet_init_rx_tx(un); 464 } 465 466 static int 467 ure_uno_init(struct ifnet *ifp) 468 { 469 struct usbnet * const un = ifp->if_softc; 470 471 usbnet_lock_core(un); 472 usbnet_busy(un); 473 int ret = ure_init_locked(ifp); 474 usbnet_unbusy(un); 475 usbnet_unlock_core(un); 476 477 return ret; 478 } 479 480 static void 481 ure_uno_stop(struct ifnet *ifp, int disable __unused) 482 { 483 struct usbnet * const un = ifp->if_softc; 484 485 ure_reset(un); 486 } 487 488 static void 489 ure_rtl8152_init(struct usbnet *un) 490 { 491 uint32_t pwrctrl; 492 493 /* Disable ALDPS. */ 494 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 495 URE_DIS_SDSAVE); 496 usbd_delay_ms(un->un_udev, 20); 497 498 if (un->un_flags & URE_FLAG_VER_4C00) { 499 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 500 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 501 ~URE_LED_MODE_MASK); 502 } 503 504 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 505 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 506 ~URE_POWER_CUT); 507 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 508 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 509 ~URE_RESUME_INDICATE); 510 511 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 512 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 513 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 514 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 515 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 516 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 517 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 518 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 519 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 520 URE_SPDWN_LINKCHG_MSK); 521 522 /* Enable Rx aggregation. */ 523 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 524 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 525 ~URE_RX_AGG_DISABLE); 526 527 /* Disable ALDPS. */ 528 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 529 URE_DIS_SDSAVE); 530 usbd_delay_ms(un->un_udev, 20); 531 532 ure_init_fifo(un); 533 534 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 535 URE_TX_AGG_MAX_THRESHOLD); 536 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 537 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 538 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 539 } 540 541 static void 542 ure_rtl8153_init(struct usbnet *un) 543 { 544 uint16_t val; 545 uint8_t u1u2[8]; 546 int i; 547 548 /* Disable ALDPS. */ 549 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 550 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 551 usbd_delay_ms(un->un_udev, 20); 552 553 memset(u1u2, 0x00, sizeof(u1u2)); 554 ure_write_mem(un, URE_USB_TOLERANCE, 555 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 556 557 for (i = 0; i < URE_TIMEOUT; i++) { 558 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 559 URE_AUTOLOAD_DONE) 560 break; 561 usbd_delay_ms(un->un_udev, 10); 562 } 563 if (i == URE_TIMEOUT) 564 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 565 566 for (i = 0; i < URE_TIMEOUT; i++) { 567 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 568 URE_PHY_STAT_MASK; 569 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 570 break; 571 usbd_delay_ms(un->un_udev, 10); 572 } 573 if (i == URE_TIMEOUT) 574 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 575 576 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 577 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 578 ~URE_U2P3_ENABLE); 579 580 if (un->un_flags & URE_FLAG_VER_5C10) { 581 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 582 val &= ~URE_PWD_DN_SCALE_MASK; 583 val |= URE_PWD_DN_SCALE(96); 584 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 585 586 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 587 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 588 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 589 } else if (un->un_flags & URE_FLAG_VER_5C20) { 590 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 591 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 592 ~URE_ECM_ALDPS); 593 } 594 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 595 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 596 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 597 0) 598 val &= ~URE_DYNAMIC_BURST; 599 else 600 val |= URE_DYNAMIC_BURST; 601 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 602 } 603 604 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 605 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 606 URE_EP4_FULL_FC); 607 608 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 609 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 610 ~URE_TIMER11_EN); 611 612 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 613 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 614 ~URE_LED_MODE_MASK); 615 616 if ((un->un_flags & URE_FLAG_VER_5C10) && 617 un->un_udev->ud_speed != USB_SPEED_SUPER) 618 val = URE_LPM_TIMER_500MS; 619 else 620 val = URE_LPM_TIMER_500US; 621 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 622 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 623 624 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 625 val &= ~URE_SEN_VAL_MASK; 626 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 627 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 628 629 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 630 631 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 632 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 633 ~(URE_PWR_EN | URE_PHASE2_EN)); 634 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 635 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 636 ~URE_PCUT_STATUS); 637 638 memset(u1u2, 0xff, sizeof(u1u2)); 639 ure_write_mem(un, URE_USB_TOLERANCE, 640 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 641 642 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 643 URE_ALDPS_SPDWN_RATIO); 644 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 645 URE_EEE_SPDWN_RATIO); 646 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 647 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 648 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 649 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 650 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 651 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 652 URE_EEE_SPDWN_EN); 653 654 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 655 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 656 val |= URE_U2P3_ENABLE; 657 else 658 val &= ~URE_U2P3_ENABLE; 659 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 660 661 memset(u1u2, 0x00, sizeof(u1u2)); 662 ure_write_mem(un, URE_USB_TOLERANCE, 663 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 664 665 /* Disable ALDPS. */ 666 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 667 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 668 usbd_delay_ms(un->un_udev, 20); 669 670 ure_init_fifo(un); 671 672 /* Enable Rx aggregation. */ 673 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 674 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 675 ~URE_RX_AGG_DISABLE); 676 677 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 678 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 679 val |= URE_U2P3_ENABLE; 680 else 681 val &= ~URE_U2P3_ENABLE; 682 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 683 684 memset(u1u2, 0xff, sizeof(u1u2)); 685 ure_write_mem(un, URE_USB_TOLERANCE, 686 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 687 } 688 689 static void 690 ure_disable_teredo(struct usbnet *un) 691 { 692 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 693 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 694 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 695 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 696 URE_WDT6_SET_MODE); 697 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 698 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 699 } 700 701 static void 702 ure_init_fifo(struct usbnet *un) 703 { 704 uint32_t rx_fifo1, rx_fifo2; 705 int i; 706 707 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 708 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 709 URE_RXDY_GATED_EN); 710 711 ure_disable_teredo(un); 712 713 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, 714 ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 715 ~URE_RCR_ACPT_ALL); 716 717 if (!(un->un_flags & URE_FLAG_8152)) { 718 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 719 URE_FLAG_VER_5C20)) 720 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 721 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 722 if (un->un_flags & URE_FLAG_VER_5C00) 723 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 724 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 725 ~URE_CTAP_SHORT_EN); 726 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 727 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 728 URE_EEE_CLKDIV_EN); 729 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 730 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 731 URE_EN_10M_BGOFF); 732 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 733 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 734 URE_EN_10M_PLLOFF); 735 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 736 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 737 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 738 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 739 URE_PFM_PWM_SWITCH); 740 741 /* Enable LPF corner auto tune. */ 742 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 743 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 744 745 /* Adjust 10M amplitude. */ 746 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 747 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 748 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 749 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 750 } 751 752 ure_reset(un); 753 754 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 755 756 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 757 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 758 ~URE_NOW_IS_OOB); 759 760 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 761 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 762 ~URE_MCU_BORW_EN); 763 for (i = 0; i < URE_TIMEOUT; i++) { 764 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 765 URE_LINK_LIST_READY) 766 break; 767 usbd_delay_ms(un->un_udev, 10); 768 } 769 if (i == URE_TIMEOUT) 770 URE_PRINTF(un, "timeout waiting for OOB control\n"); 771 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 772 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 773 URE_RE_INIT_LL); 774 for (i = 0; i < URE_TIMEOUT; i++) { 775 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 776 URE_LINK_LIST_READY) 777 break; 778 usbd_delay_ms(un->un_udev, 10); 779 } 780 if (i == URE_TIMEOUT) 781 URE_PRINTF(un, "timeout waiting for OOB control\n"); 782 783 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 784 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 785 ~URE_CPCR_RX_VLAN); 786 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 787 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 788 URE_TCR0_AUTO_FIFO); 789 790 /* Configure Rx FIFO threshold and coalescing. */ 791 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 792 URE_RXFIFO_THR1_NORMAL); 793 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 794 rx_fifo1 = URE_RXFIFO_THR2_FULL; 795 rx_fifo2 = URE_RXFIFO_THR3_FULL; 796 } else { 797 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 798 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 799 } 800 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 801 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 802 803 /* Configure Tx FIFO threshold. */ 804 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 805 URE_TXFIFO_THR_NORMAL); 806 } 807 808 static int 809 ure_uno_ioctl(struct ifnet *ifp, u_long cmd, void *data) 810 { 811 struct usbnet * const un = ifp->if_softc; 812 813 usbnet_lock_core(un); 814 usbnet_busy(un); 815 816 switch (cmd) { 817 case SIOCADDMULTI: 818 case SIOCDELMULTI: 819 ure_setiff_locked(un); 820 break; 821 default: 822 break; 823 } 824 825 usbnet_unbusy(un); 826 usbnet_unlock_core(un); 827 828 return 0; 829 } 830 831 static int 832 ure_match(device_t parent, cfdata_t match, void *aux) 833 { 834 struct usb_attach_arg *uaa = aux; 835 836 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 837 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 838 } 839 840 static void 841 ure_attach(device_t parent, device_t self, void *aux) 842 { 843 USBNET_MII_DECL_DEFAULT(unm); 844 struct usbnet * const un = device_private(self); 845 struct usb_attach_arg *uaa = aux; 846 struct usbd_device *dev = uaa->uaa_device; 847 usb_interface_descriptor_t *id; 848 usb_endpoint_descriptor_t *ed; 849 int error, i; 850 uint16_t ver; 851 uint8_t eaddr[8]; /* 2byte padded */ 852 char *devinfop; 853 uint32_t maclo, machi; 854 855 aprint_naive("\n"); 856 aprint_normal("\n"); 857 devinfop = usbd_devinfo_alloc(dev, 0); 858 aprint_normal_dev(self, "%s\n", devinfop); 859 usbd_devinfo_free(devinfop); 860 861 un->un_dev = self; 862 un->un_udev = dev; 863 un->un_sc = un; 864 un->un_ops = &ure_ops; 865 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 866 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 867 un->un_rx_list_cnt = URE_RX_LIST_CNT; 868 un->un_tx_list_cnt = URE_TX_LIST_CNT; 869 un->un_rx_bufsz = URE_BUFSZ; 870 un->un_tx_bufsz = URE_BUFSZ; 871 872 #define URE_CONFIG_NO 1 /* XXX */ 873 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 874 if (error) { 875 aprint_error_dev(self, "failed to set configuration: %s\n", 876 usbd_errstr(error)); 877 return; /* XXX */ 878 } 879 880 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 881 un->un_flags |= URE_FLAG_8152; 882 883 #define URE_IFACE_IDX 0 /* XXX */ 884 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 885 if (error) { 886 aprint_error_dev(self, "failed to get interface handle: %s\n", 887 usbd_errstr(error)); 888 return; /* XXX */ 889 } 890 891 id = usbd_get_interface_descriptor(un->un_iface); 892 for (i = 0; i < id->bNumEndpoints; i++) { 893 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 894 if (ed == NULL) { 895 aprint_error_dev(self, "couldn't get ep %d\n", i); 896 return; /* XXX */ 897 } 898 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 899 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 900 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 901 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 902 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 903 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 904 } 905 } 906 907 /* Set these up now for ure_ctl(). */ 908 usbnet_attach(un, "uredet"); 909 910 un->un_phyno = 0; 911 912 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 913 switch (ver) { 914 case 0x4c00: 915 un->un_flags |= URE_FLAG_VER_4C00; 916 break; 917 case 0x4c10: 918 un->un_flags |= URE_FLAG_VER_4C10; 919 break; 920 case 0x5c00: 921 un->un_flags |= URE_FLAG_VER_5C00; 922 break; 923 case 0x5c10: 924 un->un_flags |= URE_FLAG_VER_5C10; 925 break; 926 case 0x5c20: 927 un->un_flags |= URE_FLAG_VER_5C20; 928 break; 929 case 0x5c30: 930 un->un_flags |= URE_FLAG_VER_5C30; 931 break; 932 default: 933 /* fake addr? or just fail? */ 934 break; 935 } 936 aprint_normal_dev(self, "RTL%d %sver %04x\n", 937 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 938 (un->un_flags != 0) ? "" : "unknown ", 939 ver); 940 941 usbnet_lock_core(un); 942 if (un->un_flags & URE_FLAG_8152) 943 ure_rtl8152_init(un); 944 else 945 ure_rtl8153_init(un); 946 947 if ((un->un_flags & URE_FLAG_VER_4C00) || 948 (un->un_flags & URE_FLAG_VER_4C10)) 949 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 950 sizeof(eaddr)); 951 else 952 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 953 sizeof(eaddr)); 954 usbnet_unlock_core(un); 955 if (ETHER_IS_ZERO(eaddr)) { 956 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 957 machi = cprng_strong32() & 0xffff; 958 eaddr[0] = maclo & 0xff; 959 eaddr[1] = (maclo >> 8) & 0xff; 960 eaddr[2] = (maclo >> 16) & 0xff; 961 eaddr[3] = (maclo >> 24) & 0xff; 962 eaddr[4] = machi & 0xff; 963 eaddr[5] = (machi >> 8) & 0xff; 964 } 965 memcpy(un->un_eaddr, eaddr, sizeof(un->un_eaddr)); 966 967 struct ifnet *ifp = usbnet_ifp(un); 968 969 /* 970 * We don't support TSOv4 and v6 for now, that are required to 971 * be handled in software for some cases. 972 */ 973 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 974 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 975 #ifdef INET6 976 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 977 #endif 978 if (un->un_flags & ~URE_FLAG_VER_4C00) { 979 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 980 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 981 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 982 } 983 struct ethercom *ec = usbnet_ec(un); 984 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 985 #ifdef notyet 986 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 987 #endif 988 989 unm.un_mii_phyloc = un->un_phyno; 990 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 991 0, &unm); 992 } 993 994 static void 995 ure_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 996 { 997 struct ifnet *ifp = usbnet_ifp(un); 998 uint8_t *buf = c->unc_buf; 999 uint16_t pkt_len = 0; 1000 uint16_t pkt_count = 0; 1001 struct ure_rxpkt rxhdr; 1002 1003 do { 1004 if (total_len < sizeof(rxhdr)) { 1005 DPRINTF(("too few bytes left for a packet header\n")); 1006 if_statinc(ifp, if_ierrors); 1007 return; 1008 } 1009 1010 buf += roundup(pkt_len, 8); 1011 1012 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1013 total_len -= sizeof(rxhdr); 1014 1015 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1016 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 1017 if (pkt_len > total_len) { 1018 DPRINTF(("not enough bytes left for next packet\n")); 1019 if_statinc(ifp, if_ierrors); 1020 return; 1021 } 1022 1023 total_len -= roundup(pkt_len, 8); 1024 buf += sizeof(rxhdr); 1025 1026 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1027 ure_rxcsum(ifp, &rxhdr), 0, 0); 1028 1029 pkt_count++; 1030 1031 } while (total_len > 0); 1032 1033 if (pkt_count) 1034 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 1035 } 1036 1037 static int 1038 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1039 { 1040 int enabled = ifp->if_csum_flags_rx, flags = 0; 1041 uint32_t csum, misc; 1042 1043 if (enabled == 0) 1044 return 0; 1045 1046 csum = le32toh(rp->ure_csum); 1047 misc = le32toh(rp->ure_misc); 1048 1049 if (csum & URE_RXPKT_IPV4_CS) { 1050 flags |= M_CSUM_IPv4; 1051 if (csum & URE_RXPKT_TCP_CS) 1052 flags |= M_CSUM_TCPv4; 1053 if (csum & URE_RXPKT_UDP_CS) 1054 flags |= M_CSUM_UDPv4; 1055 } else if (csum & URE_RXPKT_IPV6_CS) { 1056 flags = 0; 1057 if (csum & URE_RXPKT_TCP_CS) 1058 flags |= M_CSUM_TCPv6; 1059 if (csum & URE_RXPKT_UDP_CS) 1060 flags |= M_CSUM_UDPv6; 1061 } 1062 1063 flags &= enabled; 1064 if (__predict_false((flags & M_CSUM_IPv4) && 1065 (misc & URE_RXPKT_IP_F))) 1066 flags |= M_CSUM_IPv4_BAD; 1067 if (__predict_false( 1068 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1069 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1070 )) 1071 flags |= M_CSUM_TCP_UDP_BAD; 1072 1073 return flags; 1074 } 1075 1076 static unsigned 1077 ure_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1078 { 1079 struct ure_txpkt txhdr; 1080 uint32_t frm_len = 0; 1081 uint8_t *buf = c->unc_buf; 1082 1083 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1084 return 0; 1085 1086 /* header */ 1087 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1088 URE_TXPKT_TX_LS); 1089 txhdr.ure_csum = htole32(ure_txcsum(m)); 1090 memcpy(buf, &txhdr, sizeof(txhdr)); 1091 buf += sizeof(txhdr); 1092 frm_len = sizeof(txhdr); 1093 1094 /* packet */ 1095 m_copydata(m, 0, m->m_pkthdr.len, buf); 1096 frm_len += m->m_pkthdr.len; 1097 1098 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1099 1100 return frm_len; 1101 } 1102 1103 /* 1104 * We need to calculate L4 checksum in software, if the offset of 1105 * L4 header is larger than 0x7ff = 2047. 1106 */ 1107 static uint32_t 1108 ure_txcsum(struct mbuf *m) 1109 { 1110 struct ether_header *eh; 1111 int flags = m->m_pkthdr.csum_flags; 1112 uint32_t data = m->m_pkthdr.csum_data; 1113 uint32_t reg = 0; 1114 int l3off, l4off; 1115 uint16_t type; 1116 1117 if (flags == 0) 1118 return 0; 1119 1120 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1121 eh = mtod(m, struct ether_header *); 1122 type = eh->ether_type; 1123 } else 1124 m_copydata(m, offsetof(struct ether_header, ether_type), 1125 sizeof(type), &type); 1126 switch (type = htons(type)) { 1127 case ETHERTYPE_IP: 1128 case ETHERTYPE_IPV6: 1129 l3off = ETHER_HDR_LEN; 1130 break; 1131 case ETHERTYPE_VLAN: 1132 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1133 break; 1134 default: 1135 return 0; 1136 } 1137 1138 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1139 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1140 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1141 in_undefer_cksum(m, l3off, flags); 1142 return 0; 1143 } 1144 reg |= URE_TXPKT_IPV4_CS; 1145 if (flags & M_CSUM_TCPv4) 1146 reg |= URE_TXPKT_TCP_CS; 1147 else 1148 reg |= URE_TXPKT_UDP_CS; 1149 reg |= l4off << URE_L4_OFFSET_SHIFT; 1150 } 1151 #ifdef INET6 1152 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1153 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1154 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1155 in6_undefer_cksum(m, l3off, flags); 1156 return 0; 1157 } 1158 reg |= URE_TXPKT_IPV6_CS; 1159 if (flags & M_CSUM_TCPv6) 1160 reg |= URE_TXPKT_TCP_CS; 1161 else 1162 reg |= URE_TXPKT_UDP_CS; 1163 reg |= l4off << URE_L4_OFFSET_SHIFT; 1164 } 1165 #endif 1166 else if (flags & M_CSUM_IPv4) 1167 reg |= URE_TXPKT_IPV4_CS; 1168 1169 return reg; 1170 } 1171 1172 #ifdef _MODULE 1173 #include "ioconf.c" 1174 #endif 1175 1176 USBNET_MODULE(ure) 1177
Indexes created Mon Sep 29 21:09:56 GMT 2025