if_ure.c revision 1.40
1 /* $NetBSD: if_ure.c,v 1.40 2020/03/27 18:04:45 nisimura Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.40 2020/03/27 18:04:45 nisimura Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/cprng.h> 42 43 #include <net/route.h> 44 45 #include <dev/usb/usbnet.h> 46 47 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 48 #ifdef INET6 49 #include <netinet/in.h> 50 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 51 #endif 52 53 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54 #include <dev/usb/if_urereg.h> 55 #include <dev/usb/if_urevar.h> 56 57 #define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60 #define URE_DEBUG 61 #ifdef URE_DEBUG 62 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64 int uredebug = 0; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 #define ETHER_IS_ZERO(addr) \ 71 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 72 73 static const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 76 }; 77 78 #define URE_BUFSZ (16 * 1024) 79 80 static void ure_reset(struct usbnet *); 81 static uint32_t ure_txcsum(struct mbuf *); 82 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 83 static void ure_rtl8152_init(struct usbnet *); 84 static void ure_rtl8153_init(struct usbnet *); 85 static void ure_disable_teredo(struct usbnet *); 86 static void ure_init_fifo(struct usbnet *); 87 88 static void ure_uno_stop(struct ifnet *, int); 89 static int ure_uno_ioctl(struct ifnet *, u_long, void *); 90 static int ure_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 91 static int ure_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 92 static void ure_uno_miibus_statchg(struct ifnet *); 93 static unsigned ure_uno_tx_prepare(struct usbnet *, struct mbuf *, 94 struct usbnet_chain *); 95 static void ure_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 96 uint32_t); 97 static int ure_uno_init(struct ifnet *); 98 99 static int ure_match(device_t, cfdata_t, void *); 100 static void ure_attach(device_t, device_t, void *); 101 102 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 103 usbnet_detach, usbnet_activate); 104 105 static const struct usbnet_ops ure_ops = { 106 .uno_stop = ure_uno_stop, 107 .uno_ioctl = ure_uno_ioctl, 108 .uno_read_reg = ure_uno_mii_read_reg, 109 .uno_write_reg = ure_uno_mii_write_reg, 110 .uno_statchg = ure_uno_miibus_statchg, 111 .uno_tx_prepare = ure_uno_tx_prepare, 112 .uno_rx_loop = ure_uno_rx_loop, 113 .uno_init = ure_uno_init, 114 }; 115 116 static int 117 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 118 void *buf, int len) 119 { 120 usb_device_request_t req; 121 usbd_status err; 122 123 if (usbnet_isdying(un)) 124 return 0; 125 126 if (rw == URE_CTL_WRITE) 127 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 128 else 129 req.bmRequestType = UT_READ_VENDOR_DEVICE; 130 req.bRequest = UR_SET_ADDRESS; 131 USETW(req.wValue, val); 132 USETW(req.wIndex, index); 133 USETW(req.wLength, len); 134 135 DPRINTFN(5, ("ure_ctl: rw %d, val %04hu, index %04hu, len %d\n", 136 rw, val, index, len)); 137 err = usbd_do_request(un->un_udev, &req, buf); 138 if (err) { 139 DPRINTF(("ure_ctl: error %d\n", err)); 140 return -1; 141 } 142 143 return 0; 144 } 145 146 static int 147 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 148 void *buf, int len) 149 { 150 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 151 } 152 153 static int 154 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 155 void *buf, int len) 156 { 157 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 158 } 159 160 static uint8_t 161 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 162 { 163 uint32_t val; 164 uint8_t temp[4]; 165 uint8_t shift; 166 167 shift = (reg & 3) << 3; 168 reg &= ~3; 169 170 ure_read_mem(un, reg, index, &temp, 4); 171 val = UGETDW(temp); 172 val >>= shift; 173 174 return val & 0xff; 175 } 176 177 static uint16_t 178 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 179 { 180 uint32_t val; 181 uint8_t temp[4]; 182 uint8_t shift; 183 184 shift = (reg & 2) << 3; 185 reg &= ~3; 186 187 ure_read_mem(un, reg, index, &temp, 4); 188 val = UGETDW(temp); 189 val >>= shift; 190 191 return val & 0xffff; 192 } 193 194 static uint32_t 195 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 196 { 197 uint8_t temp[4]; 198 199 ure_read_mem(un, reg, index, &temp, 4); 200 return UGETDW(temp); 201 } 202 203 static int 204 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 205 { 206 uint16_t byen; 207 uint8_t temp[4]; 208 uint8_t shift; 209 210 byen = URE_BYTE_EN_BYTE; 211 shift = reg & 3; 212 val &= 0xff; 213 214 if (reg & 3) { 215 byen <<= shift; 216 val <<= (shift << 3); 217 reg &= ~3; 218 } 219 220 USETDW(temp, val); 221 return ure_write_mem(un, reg, index | byen, &temp, 4); 222 } 223 224 static int 225 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 226 { 227 uint16_t byen; 228 uint8_t temp[4]; 229 uint8_t shift; 230 231 byen = URE_BYTE_EN_WORD; 232 shift = reg & 2; 233 val &= 0xffff; 234 235 if (reg & 2) { 236 byen <<= shift; 237 val <<= (shift << 3); 238 reg &= ~3; 239 } 240 241 USETDW(temp, val); 242 return ure_write_mem(un, reg, index | byen, &temp, 4); 243 } 244 245 static int 246 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 247 { 248 uint8_t temp[4]; 249 250 USETDW(temp, val); 251 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 252 } 253 254 static uint16_t 255 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 256 { 257 uint16_t reg; 258 259 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 260 reg = (addr & 0x0fff) | 0xb000; 261 262 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 263 } 264 265 static void 266 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 267 { 268 uint16_t reg; 269 270 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 271 reg = (addr & 0x0fff) | 0xb000; 272 273 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 274 } 275 276 static int 277 ure_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 278 { 279 280 if (un->un_phyno != phy) 281 return EINVAL; 282 283 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 284 if (reg == RTK_GMEDIASTAT) { 285 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 286 return USBD_NORMAL_COMPLETION; 287 } 288 289 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 290 291 return 0; 292 } 293 294 static int 295 ure_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 296 { 297 298 if (un->un_phyno != phy) 299 return EINVAL; 300 301 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 302 303 return 0; 304 } 305 306 static void 307 ure_uno_miibus_statchg(struct ifnet *ifp) 308 { 309 struct usbnet * const un = ifp->if_softc; 310 struct mii_data * const mii = usbnet_mii(un); 311 312 if (usbnet_isdying(un)) 313 return; 314 315 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 316 (IFM_ACTIVE | IFM_AVALID)) { 317 switch (IFM_SUBTYPE(mii->mii_media_active)) { 318 case IFM_10_T: 319 case IFM_100_TX: 320 usbnet_set_link(un, true); 321 break; 322 case IFM_1000_T: 323 if ((un->un_flags & URE_FLAG_8152) != 0) 324 break; 325 usbnet_set_link(un, true); 326 break; 327 default: 328 break; 329 } 330 } 331 } 332 333 static void 334 ure_rcvfilt_locked(struct usbnet *un) 335 { 336 struct ethercom *ec = usbnet_ec(un); 337 struct ifnet *ifp = usbnet_ifp(un); 338 struct ether_multi *enm; 339 struct ether_multistep step; 340 uint32_t mchash[2] = { 0, 0 }; 341 uint32_t h = 0, rxmode; 342 343 usbnet_isowned_core(un); 344 345 if (usbnet_isdying(un)) 346 return; 347 348 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 349 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 350 /* continue to accept my own DA and bcast frames */ 351 352 ETHER_LOCK(ec); 353 if (ifp->if_flags & IFF_PROMISC) { 354 ec->ec_flags |= ETHER_F_ALLMULTI; 355 ETHER_UNLOCK(ec); 356 /* run promisc. mode */ 357 rxmode |= URE_RCR_AM; /* ??? */ 358 rxmode |= URE_RCR_AAP; 359 goto update; 360 } 361 ec->ec_flags &= ~ETHER_F_ALLMULTI; 362 ETHER_FIRST_MULTI(step, ec, enm); 363 while (enm != NULL) { 364 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 365 ec->ec_flags |= ETHER_F_ALLMULTI; 366 ETHER_UNLOCK(ec); 367 /* accept all mcast frames */ 368 rxmode |= URE_RCR_AM; 369 mchash[0] = mchash[1] = ~0U; /* necessary ?? */ 370 goto update; 371 } 372 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 373 mchash[h >> 31] |= 1 << ((h >> 26) & 0x1f); 374 ETHER_NEXT_MULTI(step, enm); 375 } 376 ETHER_UNLOCK(ec); 377 if (h != 0) { 378 rxmode |= URE_RCR_AM; /* activate mcast hash filter */ 379 h = bswap32(mchash[0]); 380 mchash[0] = bswap32(mchash[1]); 381 mchash[1] = h; 382 } 383 update: 384 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, mchash[0]); 385 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, mchash[1]); 386 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 387 } 388 389 static void 390 ure_reset(struct usbnet *un) 391 { 392 int i; 393 394 usbnet_isowned_core(un); 395 396 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 397 398 for (i = 0; i < URE_TIMEOUT; i++) { 399 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 400 URE_CR_RST)) 401 break; 402 usbd_delay_ms(un->un_udev, 10); 403 } 404 if (i == URE_TIMEOUT) 405 URE_PRINTF(un, "reset never completed\n"); 406 } 407 408 static int 409 ure_init_locked(struct ifnet *ifp) 410 { 411 struct usbnet * const un = ifp->if_softc; 412 uint8_t eaddr[8]; 413 414 usbnet_isowned_core(un); 415 416 if (usbnet_isdying(un)) 417 return EIO; 418 419 /* Cancel pending I/O. */ 420 if (ifp->if_flags & IFF_RUNNING) 421 usbnet_stop(un, ifp, 1); 422 423 /* Set MAC address. */ 424 memset(eaddr, 0, sizeof(eaddr)); 425 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 426 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 427 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 428 eaddr, 8); 429 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 430 431 /* Reset the packet filter. */ 432 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 433 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 434 ~URE_FMC_FCR_MCU_EN); 435 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 436 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 437 URE_FMC_FCR_MCU_EN); 438 439 /* Enable transmit and receive. */ 440 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 441 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 442 URE_CR_TE); 443 444 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 445 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 446 ~URE_RXDY_GATED_EN); 447 448 /* Accept multicast frame or run promisc. mode. */ 449 ure_rcvfilt_locked(un); 450 451 return usbnet_init_rx_tx(un); 452 } 453 454 static int 455 ure_uno_init(struct ifnet *ifp) 456 { 457 struct usbnet * const un = ifp->if_softc; 458 459 usbnet_lock_core(un); 460 usbnet_busy(un); 461 int ret = ure_init_locked(ifp); 462 usbnet_unbusy(un); 463 usbnet_unlock_core(un); 464 465 return ret; 466 } 467 468 static void 469 ure_uno_stop(struct ifnet *ifp, int disable __unused) 470 { 471 struct usbnet * const un = ifp->if_softc; 472 473 ure_reset(un); 474 } 475 476 static void 477 ure_rtl8152_init(struct usbnet *un) 478 { 479 uint32_t pwrctrl; 480 481 /* Disable ALDPS. */ 482 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 483 URE_DIS_SDSAVE); 484 usbd_delay_ms(un->un_udev, 20); 485 486 if (un->un_flags & URE_FLAG_VER_4C00) { 487 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 488 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 489 ~URE_LED_MODE_MASK); 490 } 491 492 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 493 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 494 ~URE_POWER_CUT); 495 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 496 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 497 ~URE_RESUME_INDICATE); 498 499 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 500 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 501 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 502 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 503 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 504 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 505 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 506 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 507 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 508 URE_SPDWN_LINKCHG_MSK); 509 510 /* Enable Rx aggregation. */ 511 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 512 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 513 ~URE_RX_AGG_DISABLE); 514 515 /* Disable ALDPS. */ 516 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 517 URE_DIS_SDSAVE); 518 usbd_delay_ms(un->un_udev, 20); 519 520 ure_init_fifo(un); 521 522 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 523 URE_TX_AGG_MAX_THRESHOLD); 524 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 525 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 526 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 527 } 528 529 static void 530 ure_rtl8153_init(struct usbnet *un) 531 { 532 uint16_t val; 533 uint8_t u1u2[8]; 534 int i; 535 536 /* Disable ALDPS. */ 537 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 538 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 539 usbd_delay_ms(un->un_udev, 20); 540 541 memset(u1u2, 0x00, sizeof(u1u2)); 542 ure_write_mem(un, URE_USB_TOLERANCE, 543 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 544 545 for (i = 0; i < URE_TIMEOUT; i++) { 546 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 547 URE_AUTOLOAD_DONE) 548 break; 549 usbd_delay_ms(un->un_udev, 10); 550 } 551 if (i == URE_TIMEOUT) 552 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 553 554 for (i = 0; i < URE_TIMEOUT; i++) { 555 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 556 URE_PHY_STAT_MASK; 557 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 558 break; 559 usbd_delay_ms(un->un_udev, 10); 560 } 561 if (i == URE_TIMEOUT) 562 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 563 564 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 565 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 566 ~URE_U2P3_ENABLE); 567 568 if (un->un_flags & URE_FLAG_VER_5C10) { 569 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 570 val &= ~URE_PWD_DN_SCALE_MASK; 571 val |= URE_PWD_DN_SCALE(96); 572 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 573 574 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 575 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 576 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 577 } else if (un->un_flags & URE_FLAG_VER_5C20) { 578 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 579 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 580 ~URE_ECM_ALDPS); 581 } 582 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 583 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 584 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 585 0) 586 val &= ~URE_DYNAMIC_BURST; 587 else 588 val |= URE_DYNAMIC_BURST; 589 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 590 } 591 592 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 593 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 594 URE_EP4_FULL_FC); 595 596 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 597 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 598 ~URE_TIMER11_EN); 599 600 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 601 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 602 ~URE_LED_MODE_MASK); 603 604 if ((un->un_flags & URE_FLAG_VER_5C10) && 605 un->un_udev->ud_speed != USB_SPEED_SUPER) 606 val = URE_LPM_TIMER_500MS; 607 else 608 val = URE_LPM_TIMER_500US; 609 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 610 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 611 612 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 613 val &= ~URE_SEN_VAL_MASK; 614 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 615 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 616 617 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 618 619 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 620 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 621 ~(URE_PWR_EN | URE_PHASE2_EN)); 622 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 623 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 624 ~URE_PCUT_STATUS); 625 626 memset(u1u2, 0xff, sizeof(u1u2)); 627 ure_write_mem(un, URE_USB_TOLERANCE, 628 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 629 630 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 631 URE_ALDPS_SPDWN_RATIO); 632 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 633 URE_EEE_SPDWN_RATIO); 634 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 635 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 636 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 637 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 638 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 639 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 640 URE_EEE_SPDWN_EN); 641 642 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 643 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 644 val |= URE_U2P3_ENABLE; 645 else 646 val &= ~URE_U2P3_ENABLE; 647 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 648 649 memset(u1u2, 0x00, sizeof(u1u2)); 650 ure_write_mem(un, URE_USB_TOLERANCE, 651 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 652 653 /* Disable ALDPS. */ 654 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 655 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 656 usbd_delay_ms(un->un_udev, 20); 657 658 ure_init_fifo(un); 659 660 /* Enable Rx aggregation. */ 661 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 662 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 663 ~URE_RX_AGG_DISABLE); 664 665 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 666 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 667 val |= URE_U2P3_ENABLE; 668 else 669 val &= ~URE_U2P3_ENABLE; 670 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 671 672 memset(u1u2, 0xff, sizeof(u1u2)); 673 ure_write_mem(un, URE_USB_TOLERANCE, 674 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 675 } 676 677 static void 678 ure_disable_teredo(struct usbnet *un) 679 { 680 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 681 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 682 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 683 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 684 URE_WDT6_SET_MODE); 685 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 686 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 687 } 688 689 static void 690 ure_init_fifo(struct usbnet *un) 691 { 692 uint32_t rxmode, rx_fifo1, rx_fifo2; 693 int i; 694 695 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 696 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 697 URE_RXDY_GATED_EN); 698 699 ure_disable_teredo(un); 700 701 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 702 rxmode &= ~URE_RCR_ACPT_ALL; 703 rxmode |= URE_RCR_APM | URE_RCR_AB; /* accept my own DA and bcast */ 704 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 705 706 if (!(un->un_flags & URE_FLAG_8152)) { 707 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 708 URE_FLAG_VER_5C20)) 709 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 710 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 711 if (un->un_flags & URE_FLAG_VER_5C00) 712 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 713 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 714 ~URE_CTAP_SHORT_EN); 715 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 716 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 717 URE_EEE_CLKDIV_EN); 718 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 719 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 720 URE_EN_10M_BGOFF); 721 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 722 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 723 URE_EN_10M_PLLOFF); 724 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 725 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 726 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 727 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 728 URE_PFM_PWM_SWITCH); 729 730 /* Enable LPF corner auto tune. */ 731 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 732 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 733 734 /* Adjust 10M amplitude. */ 735 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 736 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 737 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 738 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 739 } 740 741 ure_reset(un); 742 743 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 744 745 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 746 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 747 ~URE_NOW_IS_OOB); 748 749 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 750 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 751 ~URE_MCU_BORW_EN); 752 for (i = 0; i < URE_TIMEOUT; i++) { 753 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 754 URE_LINK_LIST_READY) 755 break; 756 usbd_delay_ms(un->un_udev, 10); 757 } 758 if (i == URE_TIMEOUT) 759 URE_PRINTF(un, "timeout waiting for OOB control\n"); 760 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 761 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 762 URE_RE_INIT_LL); 763 for (i = 0; i < URE_TIMEOUT; i++) { 764 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 765 URE_LINK_LIST_READY) 766 break; 767 usbd_delay_ms(un->un_udev, 10); 768 } 769 if (i == URE_TIMEOUT) 770 URE_PRINTF(un, "timeout waiting for OOB control\n"); 771 772 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 773 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 774 ~URE_CPCR_RX_VLAN); 775 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 776 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 777 URE_TCR0_AUTO_FIFO); 778 779 /* Configure Rx FIFO threshold and coalescing. */ 780 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 781 URE_RXFIFO_THR1_NORMAL); 782 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 783 rx_fifo1 = URE_RXFIFO_THR2_FULL; 784 rx_fifo2 = URE_RXFIFO_THR3_FULL; 785 } else { 786 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 787 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 788 } 789 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 790 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 791 792 /* Configure Tx FIFO threshold. */ 793 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 794 URE_TXFIFO_THR_NORMAL); 795 } 796 797 static int 798 ure_uno_ioctl(struct ifnet *ifp, u_long cmd, void *data) 799 { 800 struct usbnet * const un = ifp->if_softc; 801 802 usbnet_lock_core(un); 803 usbnet_busy(un); 804 805 switch (cmd) { 806 case SIOCADDMULTI: 807 case SIOCDELMULTI: 808 ure_rcvfilt_locked(un); 809 break; 810 default: 811 break; 812 } 813 814 usbnet_unbusy(un); 815 usbnet_unlock_core(un); 816 817 return 0; 818 } 819 820 static int 821 ure_match(device_t parent, cfdata_t match, void *aux) 822 { 823 struct usb_attach_arg *uaa = aux; 824 825 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 826 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 827 } 828 829 static void 830 ure_attach(device_t parent, device_t self, void *aux) 831 { 832 USBNET_MII_DECL_DEFAULT(unm); 833 struct usbnet * const un = device_private(self); 834 struct usb_attach_arg *uaa = aux; 835 struct usbd_device *dev = uaa->uaa_device; 836 usb_interface_descriptor_t *id; 837 usb_endpoint_descriptor_t *ed; 838 int error, i; 839 uint16_t ver; 840 uint8_t eaddr[8]; /* 2byte padded */ 841 char *devinfop; 842 uint32_t maclo, machi; 843 844 aprint_naive("\n"); 845 aprint_normal("\n"); 846 devinfop = usbd_devinfo_alloc(dev, 0); 847 aprint_normal_dev(self, "%s\n", devinfop); 848 usbd_devinfo_free(devinfop); 849 850 un->un_dev = self; 851 un->un_udev = dev; 852 un->un_sc = un; 853 un->un_ops = &ure_ops; 854 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 855 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 856 un->un_rx_list_cnt = URE_RX_LIST_CNT; 857 un->un_tx_list_cnt = URE_TX_LIST_CNT; 858 un->un_rx_bufsz = URE_BUFSZ; 859 un->un_tx_bufsz = URE_BUFSZ; 860 861 #define URE_CONFIG_NO 1 /* XXX */ 862 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 863 if (error) { 864 aprint_error_dev(self, "failed to set configuration: %s\n", 865 usbd_errstr(error)); 866 return; /* XXX */ 867 } 868 869 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 870 un->un_flags |= URE_FLAG_8152; 871 872 #define URE_IFACE_IDX 0 /* XXX */ 873 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 874 if (error) { 875 aprint_error_dev(self, "failed to get interface handle: %s\n", 876 usbd_errstr(error)); 877 return; /* XXX */ 878 } 879 880 id = usbd_get_interface_descriptor(un->un_iface); 881 for (i = 0; i < id->bNumEndpoints; i++) { 882 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 883 if (ed == NULL) { 884 aprint_error_dev(self, "couldn't get ep %d\n", i); 885 return; /* XXX */ 886 } 887 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 888 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 889 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 890 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 891 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 892 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 893 } 894 } 895 896 /* Set these up now for ure_ctl(). */ 897 usbnet_attach(un, "uredet"); 898 899 un->un_phyno = 0; 900 901 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 902 switch (ver) { 903 case 0x4c00: 904 un->un_flags |= URE_FLAG_VER_4C00; 905 break; 906 case 0x4c10: 907 un->un_flags |= URE_FLAG_VER_4C10; 908 break; 909 case 0x5c00: 910 un->un_flags |= URE_FLAG_VER_5C00; 911 break; 912 case 0x5c10: 913 un->un_flags |= URE_FLAG_VER_5C10; 914 break; 915 case 0x5c20: 916 un->un_flags |= URE_FLAG_VER_5C20; 917 break; 918 case 0x5c30: 919 un->un_flags |= URE_FLAG_VER_5C30; 920 break; 921 default: 922 /* fake addr? or just fail? */ 923 break; 924 } 925 aprint_normal_dev(self, "RTL%d %sver %04x\n", 926 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 927 (un->un_flags != 0) ? "" : "unknown ", 928 ver); 929 930 usbnet_lock_core(un); 931 if (un->un_flags & URE_FLAG_8152) 932 ure_rtl8152_init(un); 933 else 934 ure_rtl8153_init(un); 935 936 if ((un->un_flags & URE_FLAG_VER_4C00) || 937 (un->un_flags & URE_FLAG_VER_4C10)) 938 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 939 sizeof(eaddr)); 940 else 941 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 942 sizeof(eaddr)); 943 usbnet_unlock_core(un); 944 if (ETHER_IS_ZERO(eaddr)) { 945 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 946 machi = cprng_strong32() & 0xffff; 947 eaddr[0] = maclo & 0xff; 948 eaddr[1] = (maclo >> 8) & 0xff; 949 eaddr[2] = (maclo >> 16) & 0xff; 950 eaddr[3] = (maclo >> 24) & 0xff; 951 eaddr[4] = machi & 0xff; 952 eaddr[5] = (machi >> 8) & 0xff; 953 } 954 memcpy(un->un_eaddr, eaddr, sizeof(un->un_eaddr)); 955 956 struct ifnet *ifp = usbnet_ifp(un); 957 958 /* 959 * We don't support TSOv4 and v6 for now, that are required to 960 * be handled in software for some cases. 961 */ 962 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 963 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 964 #ifdef INET6 965 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 966 #endif 967 if (un->un_flags & ~URE_FLAG_VER_4C00) { 968 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 969 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 970 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 971 } 972 struct ethercom *ec = usbnet_ec(un); 973 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 974 #ifdef notyet 975 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 976 #endif 977 978 unm.un_mii_phyloc = un->un_phyno; 979 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 980 0, &unm); 981 } 982 983 static void 984 ure_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 985 { 986 struct ifnet *ifp = usbnet_ifp(un); 987 uint8_t *buf = c->unc_buf; 988 uint16_t pkt_len = 0; 989 uint16_t pkt_count = 0; 990 struct ure_rxpkt rxhdr; 991 992 do { 993 if (total_len < sizeof(rxhdr)) { 994 DPRINTF(("too few bytes left for a packet header\n")); 995 if_statinc(ifp, if_ierrors); 996 return; 997 } 998 999 buf += roundup(pkt_len, 8); 1000 1001 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1002 total_len -= sizeof(rxhdr); 1003 1004 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1005 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 1006 if (pkt_len > total_len) { 1007 DPRINTF(("not enough bytes left for next packet\n")); 1008 if_statinc(ifp, if_ierrors); 1009 return; 1010 } 1011 1012 total_len -= roundup(pkt_len, 8); 1013 buf += sizeof(rxhdr); 1014 1015 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1016 ure_rxcsum(ifp, &rxhdr), 0, 0); 1017 1018 pkt_count++; 1019 1020 } while (total_len > 0); 1021 1022 if (pkt_count) 1023 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 1024 } 1025 1026 static int 1027 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1028 { 1029 int enabled = ifp->if_csum_flags_rx, flags = 0; 1030 uint32_t csum, misc; 1031 1032 if (enabled == 0) 1033 return 0; 1034 1035 csum = le32toh(rp->ure_csum); 1036 misc = le32toh(rp->ure_misc); 1037 1038 if (csum & URE_RXPKT_IPV4_CS) { 1039 flags |= M_CSUM_IPv4; 1040 if (csum & URE_RXPKT_TCP_CS) 1041 flags |= M_CSUM_TCPv4; 1042 if (csum & URE_RXPKT_UDP_CS) 1043 flags |= M_CSUM_UDPv4; 1044 } else if (csum & URE_RXPKT_IPV6_CS) { 1045 flags = 0; 1046 if (csum & URE_RXPKT_TCP_CS) 1047 flags |= M_CSUM_TCPv6; 1048 if (csum & URE_RXPKT_UDP_CS) 1049 flags |= M_CSUM_UDPv6; 1050 } 1051 1052 flags &= enabled; 1053 if (__predict_false((flags & M_CSUM_IPv4) && 1054 (misc & URE_RXPKT_IP_F))) 1055 flags |= M_CSUM_IPv4_BAD; 1056 if (__predict_false( 1057 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1058 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1059 )) 1060 flags |= M_CSUM_TCP_UDP_BAD; 1061 1062 return flags; 1063 } 1064 1065 static unsigned 1066 ure_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1067 { 1068 struct ure_txpkt txhdr; 1069 uint32_t frm_len = 0; 1070 uint8_t *buf = c->unc_buf; 1071 1072 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1073 return 0; 1074 1075 /* header */ 1076 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1077 URE_TXPKT_TX_LS); 1078 txhdr.ure_csum = htole32(ure_txcsum(m)); 1079 memcpy(buf, &txhdr, sizeof(txhdr)); 1080 buf += sizeof(txhdr); 1081 frm_len = sizeof(txhdr); 1082 1083 /* packet */ 1084 m_copydata(m, 0, m->m_pkthdr.len, buf); 1085 frm_len += m->m_pkthdr.len; 1086 1087 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1088 1089 return frm_len; 1090 } 1091 1092 /* 1093 * We need to calculate L4 checksum in software, if the offset of 1094 * L4 header is larger than 0x7ff = 2047. 1095 */ 1096 static uint32_t 1097 ure_txcsum(struct mbuf *m) 1098 { 1099 struct ether_header *eh; 1100 int flags = m->m_pkthdr.csum_flags; 1101 uint32_t data = m->m_pkthdr.csum_data; 1102 uint32_t reg = 0; 1103 int l3off, l4off; 1104 uint16_t type; 1105 1106 if (flags == 0) 1107 return 0; 1108 1109 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1110 eh = mtod(m, struct ether_header *); 1111 type = eh->ether_type; 1112 } else 1113 m_copydata(m, offsetof(struct ether_header, ether_type), 1114 sizeof(type), &type); 1115 switch (type = htons(type)) { 1116 case ETHERTYPE_IP: 1117 case ETHERTYPE_IPV6: 1118 l3off = ETHER_HDR_LEN; 1119 break; 1120 case ETHERTYPE_VLAN: 1121 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1122 break; 1123 default: 1124 return 0; 1125 } 1126 1127 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1128 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1129 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1130 in_undefer_cksum(m, l3off, flags); 1131 return 0; 1132 } 1133 reg |= URE_TXPKT_IPV4_CS; 1134 if (flags & M_CSUM_TCPv4) 1135 reg |= URE_TXPKT_TCP_CS; 1136 else 1137 reg |= URE_TXPKT_UDP_CS; 1138 reg |= l4off << URE_L4_OFFSET_SHIFT; 1139 } 1140 #ifdef INET6 1141 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1142 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1143 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1144 in6_undefer_cksum(m, l3off, flags); 1145 return 0; 1146 } 1147 reg |= URE_TXPKT_IPV6_CS; 1148 if (flags & M_CSUM_TCPv6) 1149 reg |= URE_TXPKT_TCP_CS; 1150 else 1151 reg |= URE_TXPKT_UDP_CS; 1152 reg |= l4off << URE_L4_OFFSET_SHIFT; 1153 } 1154 #endif 1155 else if (flags & M_CSUM_IPv4) 1156 reg |= URE_TXPKT_IPV4_CS; 1157 1158 return reg; 1159 } 1160 1161 #ifdef _MODULE 1162 #include "ioconf.c" 1163 #endif 1164 1165 USBNET_MODULE(ure) 1166
Indexes created Mon Sep 29 18:09:42 GMT 2025