if_ure.c revision 1.44
1 /* $NetBSD: if_ure.c,v 1.44 2022/03/03 05:51:17 riastradh Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.44 2022/03/03 05:51:17 riastradh Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/cprng.h> 42 43 #include <net/route.h> 44 45 #include <dev/usb/usbnet.h> 46 47 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 48 #ifdef INET6 49 #include <netinet/in.h> 50 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 51 #endif 52 53 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54 #include <dev/usb/if_urereg.h> 55 #include <dev/usb/if_urevar.h> 56 57 #define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60 #define URE_DEBUG 61 #ifdef URE_DEBUG 62 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64 int uredebug = 0; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 #define ETHER_IS_ZERO(addr) \ 71 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 72 73 static const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 76 }; 77 78 #define URE_BUFSZ (16 * 1024) 79 80 static void ure_reset(struct usbnet *); 81 static uint32_t ure_txcsum(struct mbuf *); 82 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 83 static void ure_rtl8152_init(struct usbnet *); 84 static void ure_rtl8153_init(struct usbnet *); 85 static void ure_disable_teredo(struct usbnet *); 86 static void ure_init_fifo(struct usbnet *); 87 88 static void ure_uno_stop(struct ifnet *, int); 89 static void ure_uno_mcast(struct ifnet *); 90 static int ure_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 91 static int ure_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 92 static void ure_uno_miibus_statchg(struct ifnet *); 93 static unsigned ure_uno_tx_prepare(struct usbnet *, struct mbuf *, 94 struct usbnet_chain *); 95 static void ure_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 96 uint32_t); 97 static int ure_uno_init(struct ifnet *); 98 99 static int ure_match(device_t, cfdata_t, void *); 100 static void ure_attach(device_t, device_t, void *); 101 102 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 103 usbnet_detach, usbnet_activate); 104 105 static const struct usbnet_ops ure_ops = { 106 .uno_stop = ure_uno_stop, 107 .uno_mcast = ure_uno_mcast, 108 .uno_read_reg = ure_uno_mii_read_reg, 109 .uno_write_reg = ure_uno_mii_write_reg, 110 .uno_statchg = ure_uno_miibus_statchg, 111 .uno_tx_prepare = ure_uno_tx_prepare, 112 .uno_rx_loop = ure_uno_rx_loop, 113 .uno_init = ure_uno_init, 114 }; 115 116 static int 117 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 118 void *buf, int len) 119 { 120 usb_device_request_t req; 121 usbd_status err; 122 123 if (usbnet_isdying(un)) 124 return 0; 125 126 if (rw == URE_CTL_WRITE) 127 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 128 else 129 req.bmRequestType = UT_READ_VENDOR_DEVICE; 130 req.bRequest = UR_SET_ADDRESS; 131 USETW(req.wValue, val); 132 USETW(req.wIndex, index); 133 USETW(req.wLength, len); 134 135 DPRINTFN(5, ("ure_ctl: rw %d, val %04hu, index %04hu, len %d\n", 136 rw, val, index, len)); 137 err = usbd_do_request(un->un_udev, &req, buf); 138 if (err) { 139 DPRINTF(("ure_ctl: error %d\n", err)); 140 return -1; 141 } 142 143 return 0; 144 } 145 146 static int 147 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 148 void *buf, int len) 149 { 150 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 151 } 152 153 static int 154 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 155 void *buf, int len) 156 { 157 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 158 } 159 160 static uint8_t 161 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 162 { 163 uint32_t val; 164 uint8_t temp[4]; 165 uint8_t shift; 166 167 shift = (reg & 3) << 3; 168 reg &= ~3; 169 170 ure_read_mem(un, reg, index, &temp, 4); 171 val = UGETDW(temp); 172 val >>= shift; 173 174 return val & 0xff; 175 } 176 177 static uint16_t 178 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 179 { 180 uint32_t val; 181 uint8_t temp[4]; 182 uint8_t shift; 183 184 shift = (reg & 2) << 3; 185 reg &= ~3; 186 187 ure_read_mem(un, reg, index, &temp, 4); 188 val = UGETDW(temp); 189 val >>= shift; 190 191 return val & 0xffff; 192 } 193 194 static uint32_t 195 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 196 { 197 uint8_t temp[4]; 198 199 ure_read_mem(un, reg, index, &temp, 4); 200 return UGETDW(temp); 201 } 202 203 static int 204 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 205 { 206 uint16_t byen; 207 uint8_t temp[4]; 208 uint8_t shift; 209 210 byen = URE_BYTE_EN_BYTE; 211 shift = reg & 3; 212 val &= 0xff; 213 214 if (reg & 3) { 215 byen <<= shift; 216 val <<= (shift << 3); 217 reg &= ~3; 218 } 219 220 USETDW(temp, val); 221 return ure_write_mem(un, reg, index | byen, &temp, 4); 222 } 223 224 static int 225 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 226 { 227 uint16_t byen; 228 uint8_t temp[4]; 229 uint8_t shift; 230 231 byen = URE_BYTE_EN_WORD; 232 shift = reg & 2; 233 val &= 0xffff; 234 235 if (reg & 2) { 236 byen <<= shift; 237 val <<= (shift << 3); 238 reg &= ~3; 239 } 240 241 USETDW(temp, val); 242 return ure_write_mem(un, reg, index | byen, &temp, 4); 243 } 244 245 static int 246 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 247 { 248 uint8_t temp[4]; 249 250 USETDW(temp, val); 251 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 252 } 253 254 static uint16_t 255 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 256 { 257 uint16_t reg; 258 259 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 260 reg = (addr & 0x0fff) | 0xb000; 261 262 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 263 } 264 265 static void 266 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 267 { 268 uint16_t reg; 269 270 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 271 reg = (addr & 0x0fff) | 0xb000; 272 273 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 274 } 275 276 static int 277 ure_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 278 { 279 280 if (un->un_phyno != phy) 281 return EINVAL; 282 283 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 284 if (reg == RTK_GMEDIASTAT) { 285 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 286 return USBD_NORMAL_COMPLETION; 287 } 288 289 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 290 291 return 0; 292 } 293 294 static int 295 ure_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 296 { 297 298 if (un->un_phyno != phy) 299 return EINVAL; 300 301 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 302 303 return 0; 304 } 305 306 static void 307 ure_uno_miibus_statchg(struct ifnet *ifp) 308 { 309 struct usbnet * const un = ifp->if_softc; 310 struct mii_data * const mii = usbnet_mii(un); 311 312 if (usbnet_isdying(un)) 313 return; 314 315 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 316 (IFM_ACTIVE | IFM_AVALID)) { 317 switch (IFM_SUBTYPE(mii->mii_media_active)) { 318 case IFM_10_T: 319 case IFM_100_TX: 320 usbnet_set_link(un, true); 321 break; 322 case IFM_1000_T: 323 if ((un->un_flags & URE_FLAG_8152) != 0) 324 break; 325 usbnet_set_link(un, true); 326 break; 327 default: 328 break; 329 } 330 } 331 } 332 333 static void 334 ure_rcvfilt_locked(struct usbnet *un) 335 { 336 struct ethercom *ec = usbnet_ec(un); 337 struct ifnet *ifp = usbnet_ifp(un); 338 struct ether_multi *enm; 339 struct ether_multistep step; 340 uint32_t mchash[2] = { 0, 0 }; 341 uint32_t h = 0, rxmode; 342 343 usbnet_isowned_core(un); 344 345 if (usbnet_isdying(un)) 346 return; 347 348 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 349 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 350 /* continue to accept my own DA and bcast frames */ 351 352 ETHER_LOCK(ec); 353 if (ifp->if_flags & IFF_PROMISC) { 354 ec->ec_flags |= ETHER_F_ALLMULTI; 355 ETHER_UNLOCK(ec); 356 /* run promisc. mode */ 357 rxmode |= URE_RCR_AM; /* ??? */ 358 rxmode |= URE_RCR_AAP; 359 goto update; 360 } 361 ec->ec_flags &= ~ETHER_F_ALLMULTI; 362 ETHER_FIRST_MULTI(step, ec, enm); 363 while (enm != NULL) { 364 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 365 ec->ec_flags |= ETHER_F_ALLMULTI; 366 ETHER_UNLOCK(ec); 367 /* accept all mcast frames */ 368 rxmode |= URE_RCR_AM; 369 mchash[0] = mchash[1] = ~0U; /* necessary ?? */ 370 goto update; 371 } 372 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 373 mchash[h >> 31] |= 1 << ((h >> 26) & 0x1f); 374 ETHER_NEXT_MULTI(step, enm); 375 } 376 ETHER_UNLOCK(ec); 377 if (h != 0) { 378 rxmode |= URE_RCR_AM; /* activate mcast hash filter */ 379 h = bswap32(mchash[0]); 380 mchash[0] = bswap32(mchash[1]); 381 mchash[1] = h; 382 } 383 update: 384 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, mchash[0]); 385 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, mchash[1]); 386 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 387 } 388 389 static void 390 ure_reset(struct usbnet *un) 391 { 392 int i; 393 394 usbnet_isowned_core(un); 395 396 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 397 398 for (i = 0; i < URE_TIMEOUT; i++) { 399 if (usbnet_isdying(un)) 400 return; 401 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 402 URE_CR_RST)) 403 break; 404 usbd_delay_ms(un->un_udev, 10); 405 } 406 if (i == URE_TIMEOUT) 407 URE_PRINTF(un, "reset never completed\n"); 408 } 409 410 static int 411 ure_init_locked(struct ifnet *ifp) 412 { 413 struct usbnet * const un = ifp->if_softc; 414 uint8_t eaddr[8]; 415 416 usbnet_isowned_core(un); 417 418 if (usbnet_isdying(un)) 419 return EIO; 420 421 /* Cancel pending I/O. */ 422 if (ifp->if_flags & IFF_RUNNING) 423 usbnet_stop(un, ifp, 1); 424 425 /* Set MAC address. */ 426 memset(eaddr, 0, sizeof(eaddr)); 427 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 428 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 429 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 430 eaddr, 8); 431 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 432 433 /* Reset the packet filter. */ 434 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 435 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 436 ~URE_FMC_FCR_MCU_EN); 437 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 438 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 439 URE_FMC_FCR_MCU_EN); 440 441 /* Enable transmit and receive. */ 442 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 443 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 444 URE_CR_TE); 445 446 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 447 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 448 ~URE_RXDY_GATED_EN); 449 450 /* Accept multicast frame or run promisc. mode. */ 451 ure_rcvfilt_locked(un); 452 453 return usbnet_init_rx_tx(un); 454 } 455 456 static int 457 ure_uno_init(struct ifnet *ifp) 458 { 459 int ret = ure_init_locked(ifp); 460 461 return ret; 462 } 463 464 static void 465 ure_uno_stop(struct ifnet *ifp, int disable __unused) 466 { 467 struct usbnet * const un = ifp->if_softc; 468 469 ure_reset(un); 470 } 471 472 static void 473 ure_rtl8152_init(struct usbnet *un) 474 { 475 uint32_t pwrctrl; 476 477 /* Disable ALDPS. */ 478 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 479 URE_DIS_SDSAVE); 480 usbd_delay_ms(un->un_udev, 20); 481 482 if (un->un_flags & URE_FLAG_VER_4C00) { 483 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 484 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 485 ~URE_LED_MODE_MASK); 486 } 487 488 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 489 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 490 ~URE_POWER_CUT); 491 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 492 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 493 ~URE_RESUME_INDICATE); 494 495 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 496 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 497 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 498 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 499 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 500 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 501 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 502 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 503 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 504 URE_SPDWN_LINKCHG_MSK); 505 506 /* Enable Rx aggregation. */ 507 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 508 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 509 ~URE_RX_AGG_DISABLE); 510 511 /* Disable ALDPS. */ 512 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 513 URE_DIS_SDSAVE); 514 usbd_delay_ms(un->un_udev, 20); 515 516 ure_init_fifo(un); 517 518 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 519 URE_TX_AGG_MAX_THRESHOLD); 520 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 521 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 522 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 523 } 524 525 static void 526 ure_rtl8153_init(struct usbnet *un) 527 { 528 uint16_t val; 529 uint8_t u1u2[8]; 530 int i; 531 532 /* Disable ALDPS. */ 533 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 534 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 535 usbd_delay_ms(un->un_udev, 20); 536 537 memset(u1u2, 0x00, sizeof(u1u2)); 538 ure_write_mem(un, URE_USB_TOLERANCE, 539 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 540 541 for (i = 0; i < URE_TIMEOUT; i++) { 542 if (usbnet_isdying(un)) 543 return; 544 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 545 URE_AUTOLOAD_DONE) 546 break; 547 usbd_delay_ms(un->un_udev, 10); 548 } 549 if (i == URE_TIMEOUT) 550 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 551 552 for (i = 0; i < URE_TIMEOUT; i++) { 553 if (usbnet_isdying(un)) 554 return; 555 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 556 URE_PHY_STAT_MASK; 557 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 558 break; 559 usbd_delay_ms(un->un_udev, 10); 560 } 561 if (i == URE_TIMEOUT) 562 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 563 564 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 565 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 566 ~URE_U2P3_ENABLE); 567 568 if (un->un_flags & URE_FLAG_VER_5C10) { 569 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 570 val &= ~URE_PWD_DN_SCALE_MASK; 571 val |= URE_PWD_DN_SCALE(96); 572 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 573 574 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 575 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 576 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 577 } else if (un->un_flags & URE_FLAG_VER_5C20) { 578 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 579 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 580 ~URE_ECM_ALDPS); 581 } 582 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 583 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 584 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 585 0) 586 val &= ~URE_DYNAMIC_BURST; 587 else 588 val |= URE_DYNAMIC_BURST; 589 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 590 } 591 592 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 593 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 594 URE_EP4_FULL_FC); 595 596 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 597 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 598 ~URE_TIMER11_EN); 599 600 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 601 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 602 ~URE_LED_MODE_MASK); 603 604 if ((un->un_flags & URE_FLAG_VER_5C10) && 605 un->un_udev->ud_speed != USB_SPEED_SUPER) 606 val = URE_LPM_TIMER_500MS; 607 else 608 val = URE_LPM_TIMER_500US; 609 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 610 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 611 612 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 613 val &= ~URE_SEN_VAL_MASK; 614 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 615 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 616 617 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 618 619 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 620 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 621 ~(URE_PWR_EN | URE_PHASE2_EN)); 622 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 623 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 624 ~URE_PCUT_STATUS); 625 626 memset(u1u2, 0xff, sizeof(u1u2)); 627 ure_write_mem(un, URE_USB_TOLERANCE, 628 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 629 630 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 631 URE_ALDPS_SPDWN_RATIO); 632 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 633 URE_EEE_SPDWN_RATIO); 634 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 635 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 636 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 637 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 638 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 639 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 640 URE_EEE_SPDWN_EN); 641 642 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 643 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 644 val |= URE_U2P3_ENABLE; 645 else 646 val &= ~URE_U2P3_ENABLE; 647 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 648 649 memset(u1u2, 0x00, sizeof(u1u2)); 650 ure_write_mem(un, URE_USB_TOLERANCE, 651 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 652 653 /* Disable ALDPS. */ 654 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 655 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 656 usbd_delay_ms(un->un_udev, 20); 657 658 ure_init_fifo(un); 659 660 /* Enable Rx aggregation. */ 661 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 662 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 663 ~URE_RX_AGG_DISABLE); 664 665 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 666 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 667 val |= URE_U2P3_ENABLE; 668 else 669 val &= ~URE_U2P3_ENABLE; 670 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 671 672 memset(u1u2, 0xff, sizeof(u1u2)); 673 ure_write_mem(un, URE_USB_TOLERANCE, 674 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 675 } 676 677 static void 678 ure_disable_teredo(struct usbnet *un) 679 { 680 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 681 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 682 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 683 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 684 URE_WDT6_SET_MODE); 685 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 686 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 687 } 688 689 static void 690 ure_init_fifo(struct usbnet *un) 691 { 692 uint32_t rxmode, rx_fifo1, rx_fifo2; 693 int i; 694 695 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 696 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 697 URE_RXDY_GATED_EN); 698 699 ure_disable_teredo(un); 700 701 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 702 rxmode &= ~URE_RCR_ACPT_ALL; 703 rxmode |= URE_RCR_APM | URE_RCR_AB; /* accept my own DA and bcast */ 704 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 705 706 if (!(un->un_flags & URE_FLAG_8152)) { 707 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 708 URE_FLAG_VER_5C20)) 709 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 710 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 711 if (un->un_flags & URE_FLAG_VER_5C00) 712 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 713 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 714 ~URE_CTAP_SHORT_EN); 715 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 716 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 717 URE_EEE_CLKDIV_EN); 718 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 719 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 720 URE_EN_10M_BGOFF); 721 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 722 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 723 URE_EN_10M_PLLOFF); 724 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 725 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 726 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 727 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 728 URE_PFM_PWM_SWITCH); 729 730 /* Enable LPF corner auto tune. */ 731 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 732 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 733 734 /* Adjust 10M amplitude. */ 735 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 736 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 737 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 738 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 739 } 740 741 ure_reset(un); 742 743 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 744 745 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 746 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 747 ~URE_NOW_IS_OOB); 748 749 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 750 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 751 ~URE_MCU_BORW_EN); 752 for (i = 0; i < URE_TIMEOUT; i++) { 753 if (usbnet_isdying(un)) 754 return; 755 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 756 URE_LINK_LIST_READY) 757 break; 758 usbd_delay_ms(un->un_udev, 10); 759 } 760 if (i == URE_TIMEOUT) 761 URE_PRINTF(un, "timeout waiting for OOB control\n"); 762 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 763 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 764 URE_RE_INIT_LL); 765 for (i = 0; i < URE_TIMEOUT; i++) { 766 if (usbnet_isdying(un)) 767 return; 768 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 769 URE_LINK_LIST_READY) 770 break; 771 usbd_delay_ms(un->un_udev, 10); 772 } 773 if (i == URE_TIMEOUT) 774 URE_PRINTF(un, "timeout waiting for OOB control\n"); 775 776 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 777 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 778 ~URE_CPCR_RX_VLAN); 779 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 780 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 781 URE_TCR0_AUTO_FIFO); 782 783 /* Configure Rx FIFO threshold and coalescing. */ 784 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 785 URE_RXFIFO_THR1_NORMAL); 786 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 787 rx_fifo1 = URE_RXFIFO_THR2_FULL; 788 rx_fifo2 = URE_RXFIFO_THR3_FULL; 789 } else { 790 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 791 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 792 } 793 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 794 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 795 796 /* Configure Tx FIFO threshold. */ 797 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 798 URE_TXFIFO_THR_NORMAL); 799 } 800 801 static void 802 ure_uno_mcast(struct ifnet *ifp) 803 { 804 struct usbnet * const un = ifp->if_softc; 805 806 usbnet_lock_core(un); 807 usbnet_busy(un); 808 809 ure_rcvfilt_locked(un); 810 811 usbnet_unbusy(un); 812 usbnet_unlock_core(un); 813 } 814 815 static int 816 ure_match(device_t parent, cfdata_t match, void *aux) 817 { 818 struct usb_attach_arg *uaa = aux; 819 820 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 821 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 822 } 823 824 static void 825 ure_attach(device_t parent, device_t self, void *aux) 826 { 827 USBNET_MII_DECL_DEFAULT(unm); 828 struct usbnet * const un = device_private(self); 829 struct usb_attach_arg *uaa = aux; 830 struct usbd_device *dev = uaa->uaa_device; 831 usb_interface_descriptor_t *id; 832 usb_endpoint_descriptor_t *ed; 833 int error, i; 834 uint16_t ver; 835 uint8_t eaddr[8]; /* 2byte padded */ 836 char *devinfop; 837 uint32_t maclo, machi; 838 839 aprint_naive("\n"); 840 aprint_normal("\n"); 841 devinfop = usbd_devinfo_alloc(dev, 0); 842 aprint_normal_dev(self, "%s\n", devinfop); 843 usbd_devinfo_free(devinfop); 844 845 un->un_dev = self; 846 un->un_udev = dev; 847 un->un_sc = un; 848 un->un_ops = &ure_ops; 849 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 850 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 851 un->un_rx_list_cnt = URE_RX_LIST_CNT; 852 un->un_tx_list_cnt = URE_TX_LIST_CNT; 853 un->un_rx_bufsz = URE_BUFSZ; 854 un->un_tx_bufsz = URE_BUFSZ; 855 856 #define URE_CONFIG_NO 1 /* XXX */ 857 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 858 if (error) { 859 aprint_error_dev(self, "failed to set configuration: %s\n", 860 usbd_errstr(error)); 861 return; /* XXX */ 862 } 863 864 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 865 un->un_flags |= URE_FLAG_8152; 866 867 #define URE_IFACE_IDX 0 /* XXX */ 868 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 869 if (error) { 870 aprint_error_dev(self, "failed to get interface handle: %s\n", 871 usbd_errstr(error)); 872 return; /* XXX */ 873 } 874 875 id = usbd_get_interface_descriptor(un->un_iface); 876 for (i = 0; i < id->bNumEndpoints; i++) { 877 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 878 if (ed == NULL) { 879 aprint_error_dev(self, "couldn't get ep %d\n", i); 880 return; /* XXX */ 881 } 882 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 883 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 884 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 885 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 886 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 887 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 888 } 889 } 890 891 /* Set these up now for ure_ctl(). */ 892 usbnet_attach(un, "uredet"); 893 894 un->un_phyno = 0; 895 896 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 897 switch (ver) { 898 case 0x4c00: 899 un->un_flags |= URE_FLAG_VER_4C00; 900 break; 901 case 0x4c10: 902 un->un_flags |= URE_FLAG_VER_4C10; 903 break; 904 case 0x5c00: 905 un->un_flags |= URE_FLAG_VER_5C00; 906 break; 907 case 0x5c10: 908 un->un_flags |= URE_FLAG_VER_5C10; 909 break; 910 case 0x5c20: 911 un->un_flags |= URE_FLAG_VER_5C20; 912 break; 913 case 0x5c30: 914 un->un_flags |= URE_FLAG_VER_5C30; 915 break; 916 default: 917 /* fake addr? or just fail? */ 918 break; 919 } 920 aprint_normal_dev(self, "RTL%d %sver %04x\n", 921 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 922 (un->un_flags != 0) ? "" : "unknown ", 923 ver); 924 925 usbnet_lock_core(un); 926 if (un->un_flags & URE_FLAG_8152) 927 ure_rtl8152_init(un); 928 else 929 ure_rtl8153_init(un); 930 931 if ((un->un_flags & URE_FLAG_VER_4C00) || 932 (un->un_flags & URE_FLAG_VER_4C10)) 933 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 934 sizeof(eaddr)); 935 else 936 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 937 sizeof(eaddr)); 938 usbnet_unlock_core(un); 939 if (ETHER_IS_ZERO(eaddr)) { 940 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 941 machi = cprng_strong32() & 0xffff; 942 eaddr[0] = maclo & 0xff; 943 eaddr[1] = (maclo >> 8) & 0xff; 944 eaddr[2] = (maclo >> 16) & 0xff; 945 eaddr[3] = (maclo >> 24) & 0xff; 946 eaddr[4] = machi & 0xff; 947 eaddr[5] = (machi >> 8) & 0xff; 948 } 949 memcpy(un->un_eaddr, eaddr, sizeof(un->un_eaddr)); 950 951 struct ifnet *ifp = usbnet_ifp(un); 952 953 /* 954 * We don't support TSOv4 and v6 for now, that are required to 955 * be handled in software for some cases. 956 */ 957 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 958 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 959 #ifdef INET6 960 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 961 #endif 962 if (un->un_flags & ~URE_FLAG_VER_4C00) { 963 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 964 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 965 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 966 } 967 struct ethercom *ec = usbnet_ec(un); 968 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 969 #ifdef notyet 970 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 971 #endif 972 973 unm.un_mii_phyloc = un->un_phyno; 974 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 975 0, &unm); 976 } 977 978 static void 979 ure_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 980 { 981 struct ifnet *ifp = usbnet_ifp(un); 982 uint8_t *buf = c->unc_buf; 983 uint16_t pkt_len = 0; 984 uint16_t pkt_count = 0; 985 struct ure_rxpkt rxhdr; 986 987 do { 988 if (total_len < sizeof(rxhdr)) { 989 DPRINTF(("too few bytes left for a packet header\n")); 990 if_statinc(ifp, if_ierrors); 991 return; 992 } 993 994 buf += roundup(pkt_len, 8); 995 996 memcpy(&rxhdr, buf, sizeof(rxhdr)); 997 total_len -= sizeof(rxhdr); 998 999 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1000 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 1001 if (pkt_len > total_len) { 1002 DPRINTF(("not enough bytes left for next packet\n")); 1003 if_statinc(ifp, if_ierrors); 1004 return; 1005 } 1006 1007 total_len -= roundup(pkt_len, 8); 1008 buf += sizeof(rxhdr); 1009 1010 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 1011 ure_rxcsum(ifp, &rxhdr), 0, 0); 1012 1013 pkt_count++; 1014 1015 } while (total_len > 0); 1016 1017 if (pkt_count) 1018 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 1019 } 1020 1021 static int 1022 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 1023 { 1024 int enabled = ifp->if_csum_flags_rx, flags = 0; 1025 uint32_t csum, misc; 1026 1027 if (enabled == 0) 1028 return 0; 1029 1030 csum = le32toh(rp->ure_csum); 1031 misc = le32toh(rp->ure_misc); 1032 1033 if (csum & URE_RXPKT_IPV4_CS) { 1034 flags |= M_CSUM_IPv4; 1035 if (csum & URE_RXPKT_TCP_CS) 1036 flags |= M_CSUM_TCPv4; 1037 if (csum & URE_RXPKT_UDP_CS) 1038 flags |= M_CSUM_UDPv4; 1039 } else if (csum & URE_RXPKT_IPV6_CS) { 1040 flags = 0; 1041 if (csum & URE_RXPKT_TCP_CS) 1042 flags |= M_CSUM_TCPv6; 1043 if (csum & URE_RXPKT_UDP_CS) 1044 flags |= M_CSUM_UDPv6; 1045 } 1046 1047 flags &= enabled; 1048 if (__predict_false((flags & M_CSUM_IPv4) && 1049 (misc & URE_RXPKT_IP_F))) 1050 flags |= M_CSUM_IPv4_BAD; 1051 if (__predict_false( 1052 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1053 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1054 )) 1055 flags |= M_CSUM_TCP_UDP_BAD; 1056 1057 return flags; 1058 } 1059 1060 static unsigned 1061 ure_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1062 { 1063 struct ure_txpkt txhdr; 1064 uint32_t frm_len = 0; 1065 uint8_t *buf = c->unc_buf; 1066 1067 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1068 return 0; 1069 1070 /* header */ 1071 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1072 URE_TXPKT_TX_LS); 1073 txhdr.ure_csum = htole32(ure_txcsum(m)); 1074 memcpy(buf, &txhdr, sizeof(txhdr)); 1075 buf += sizeof(txhdr); 1076 frm_len = sizeof(txhdr); 1077 1078 /* packet */ 1079 m_copydata(m, 0, m->m_pkthdr.len, buf); 1080 frm_len += m->m_pkthdr.len; 1081 1082 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1083 1084 return frm_len; 1085 } 1086 1087 /* 1088 * We need to calculate L4 checksum in software, if the offset of 1089 * L4 header is larger than 0x7ff = 2047. 1090 */ 1091 static uint32_t 1092 ure_txcsum(struct mbuf *m) 1093 { 1094 struct ether_header *eh; 1095 int flags = m->m_pkthdr.csum_flags; 1096 uint32_t data = m->m_pkthdr.csum_data; 1097 uint32_t reg = 0; 1098 int l3off, l4off; 1099 uint16_t type; 1100 1101 if (flags == 0) 1102 return 0; 1103 1104 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1105 eh = mtod(m, struct ether_header *); 1106 type = eh->ether_type; 1107 } else 1108 m_copydata(m, offsetof(struct ether_header, ether_type), 1109 sizeof(type), &type); 1110 switch (type = htons(type)) { 1111 case ETHERTYPE_IP: 1112 case ETHERTYPE_IPV6: 1113 l3off = ETHER_HDR_LEN; 1114 break; 1115 case ETHERTYPE_VLAN: 1116 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1117 break; 1118 default: 1119 return 0; 1120 } 1121 1122 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1123 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1124 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1125 in_undefer_cksum(m, l3off, flags); 1126 return 0; 1127 } 1128 reg |= URE_TXPKT_IPV4_CS; 1129 if (flags & M_CSUM_TCPv4) 1130 reg |= URE_TXPKT_TCP_CS; 1131 else 1132 reg |= URE_TXPKT_UDP_CS; 1133 reg |= l4off << URE_L4_OFFSET_SHIFT; 1134 } 1135 #ifdef INET6 1136 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1137 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1138 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1139 in6_undefer_cksum(m, l3off, flags); 1140 return 0; 1141 } 1142 reg |= URE_TXPKT_IPV6_CS; 1143 if (flags & M_CSUM_TCPv6) 1144 reg |= URE_TXPKT_TCP_CS; 1145 else 1146 reg |= URE_TXPKT_UDP_CS; 1147 reg |= l4off << URE_L4_OFFSET_SHIFT; 1148 } 1149 #endif 1150 else if (flags & M_CSUM_IPv4) 1151 reg |= URE_TXPKT_IPV4_CS; 1152 1153 return reg; 1154 } 1155 1156 #ifdef _MODULE 1157 #include "ioconf.c" 1158 #endif 1159 1160 USBNET_MODULE(ure) 1161
Indexes created Thu Oct 02 01:09:59 GMT 2025