if_ure.c revision 1.58
1 /* $NetBSD: if_ure.c,v 1.58 2022/09/16 07:34:36 msaitoh Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.58 2022/09/16 07:34:36 msaitoh Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/cprng.h> 42 43 #include <net/route.h> 44 45 #include <dev/usb/usbnet.h> 46 47 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 48 #ifdef INET6 49 #include <netinet/in.h> 50 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 51 #endif 52 53 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54 #include <dev/usb/if_urereg.h> 55 #include <dev/usb/if_urevar.h> 56 57 #define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60 #define URE_DEBUG 61 #ifdef URE_DEBUG 62 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64 int uredebug = 0; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 #define ETHER_IS_ZERO(addr) \ 71 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 72 73 static const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 76 }; 77 78 #define URE_BUFSZ (16 * 1024) 79 80 static void ure_reset(struct usbnet *); 81 static uint32_t ure_txcsum(struct mbuf *); 82 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 83 static void ure_rtl8152_init(struct usbnet *); 84 static void ure_rtl8153_init(struct usbnet *); 85 static void ure_disable_teredo(struct usbnet *); 86 static void ure_init_fifo(struct usbnet *); 87 88 static void ure_uno_stop(struct ifnet *, int); 89 static void ure_uno_mcast(struct ifnet *); 90 static int ure_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 91 static int ure_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 92 static void ure_uno_miibus_statchg(struct ifnet *); 93 static unsigned ure_uno_tx_prepare(struct usbnet *, struct mbuf *, 94 struct usbnet_chain *); 95 static void ure_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 96 uint32_t); 97 static int ure_uno_init(struct ifnet *); 98 99 static int ure_match(device_t, cfdata_t, void *); 100 static void ure_attach(device_t, device_t, void *); 101 102 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 103 usbnet_detach, usbnet_activate); 104 105 static const struct usbnet_ops ure_ops = { 106 .uno_stop = ure_uno_stop, 107 .uno_mcast = ure_uno_mcast, 108 .uno_read_reg = ure_uno_mii_read_reg, 109 .uno_write_reg = ure_uno_mii_write_reg, 110 .uno_statchg = ure_uno_miibus_statchg, 111 .uno_tx_prepare = ure_uno_tx_prepare, 112 .uno_rx_loop = ure_uno_rx_loop, 113 .uno_init = ure_uno_init, 114 }; 115 116 static int 117 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 118 void *buf, int len) 119 { 120 usb_device_request_t req; 121 usbd_status err; 122 123 if (usbnet_isdying(un)) 124 return 0; 125 126 if (rw == URE_CTL_WRITE) 127 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 128 else 129 req.bmRequestType = UT_READ_VENDOR_DEVICE; 130 req.bRequest = UR_SET_ADDRESS; 131 USETW(req.wValue, val); 132 USETW(req.wIndex, index); 133 USETW(req.wLength, len); 134 135 DPRINTFN(5, ("ure_ctl: rw %d, val %04hu, index %04hu, len %d\n", 136 rw, val, index, len)); 137 err = usbd_do_request(un->un_udev, &req, buf); 138 if (err) { 139 DPRINTF(("ure_ctl: error %d\n", err)); 140 if (rw == URE_CTL_READ) 141 memset(buf, 0, len); 142 return -1; 143 } 144 145 return 0; 146 } 147 148 static int 149 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 150 void *buf, int len) 151 { 152 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 153 } 154 155 static int 156 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 157 void *buf, int len) 158 { 159 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 160 } 161 162 static uint8_t 163 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 164 { 165 uint32_t val; 166 uint8_t temp[4]; 167 uint8_t shift; 168 169 shift = (reg & 3) << 3; 170 reg &= ~3; 171 172 ure_read_mem(un, reg, index, &temp, 4); 173 val = UGETDW(temp); 174 val >>= shift; 175 176 return val & 0xff; 177 } 178 179 static uint16_t 180 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 181 { 182 uint32_t val; 183 uint8_t temp[4]; 184 uint8_t shift; 185 186 shift = (reg & 2) << 3; 187 reg &= ~3; 188 189 ure_read_mem(un, reg, index, &temp, 4); 190 val = UGETDW(temp); 191 val >>= shift; 192 193 return val & 0xffff; 194 } 195 196 static uint32_t 197 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 198 { 199 uint8_t temp[4]; 200 201 ure_read_mem(un, reg, index, &temp, 4); 202 return UGETDW(temp); 203 } 204 205 static int 206 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 207 { 208 uint16_t byen; 209 uint8_t temp[4]; 210 uint8_t shift; 211 212 byen = URE_BYTE_EN_BYTE; 213 shift = reg & 3; 214 val &= 0xff; 215 216 if (reg & 3) { 217 byen <<= shift; 218 val <<= (shift << 3); 219 reg &= ~3; 220 } 221 222 USETDW(temp, val); 223 return ure_write_mem(un, reg, index | byen, &temp, 4); 224 } 225 226 static int 227 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 228 { 229 uint16_t byen; 230 uint8_t temp[4]; 231 uint8_t shift; 232 233 byen = URE_BYTE_EN_WORD; 234 shift = reg & 2; 235 val &= 0xffff; 236 237 if (reg & 2) { 238 byen <<= shift; 239 val <<= (shift << 3); 240 reg &= ~3; 241 } 242 243 USETDW(temp, val); 244 return ure_write_mem(un, reg, index | byen, &temp, 4); 245 } 246 247 static int 248 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 249 { 250 uint8_t temp[4]; 251 252 USETDW(temp, val); 253 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 254 } 255 256 static uint16_t 257 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 258 { 259 uint16_t reg; 260 261 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 262 reg = (addr & 0x0fff) | 0xb000; 263 264 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 265 } 266 267 static void 268 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 269 { 270 uint16_t reg; 271 272 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 273 reg = (addr & 0x0fff) | 0xb000; 274 275 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 276 } 277 278 static int 279 ure_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 280 { 281 282 if (un->un_phyno != phy) { 283 *val = 0; 284 return EINVAL; 285 } 286 287 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 288 if (reg == RTK_GMEDIASTAT) { 289 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 290 return USBD_NORMAL_COMPLETION; 291 } 292 293 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 294 295 return 0; 296 } 297 298 static int 299 ure_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 300 { 301 302 if (un->un_phyno != phy) 303 return EINVAL; 304 305 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 306 307 return 0; 308 } 309 310 static void 311 ure_uno_miibus_statchg(struct ifnet *ifp) 312 { 313 struct usbnet * const un = ifp->if_softc; 314 struct mii_data * const mii = usbnet_mii(un); 315 316 if (usbnet_isdying(un)) 317 return; 318 319 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 320 (IFM_ACTIVE | IFM_AVALID)) { 321 switch (IFM_SUBTYPE(mii->mii_media_active)) { 322 case IFM_10_T: 323 case IFM_100_TX: 324 usbnet_set_link(un, true); 325 break; 326 case IFM_1000_T: 327 if ((un->un_flags & URE_FLAG_8152) != 0) 328 break; 329 usbnet_set_link(un, true); 330 break; 331 default: 332 break; 333 } 334 } 335 } 336 337 static void 338 ure_uno_mcast(struct ifnet *ifp) 339 { 340 struct usbnet *un = ifp->if_softc; 341 struct ethercom *ec = usbnet_ec(un); 342 struct ether_multi *enm; 343 struct ether_multistep step; 344 uint32_t mchash[2] = { 0, 0 }; 345 uint32_t h = 0, rxmode; 346 347 if (usbnet_isdying(un)) 348 return; 349 350 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 351 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 352 /* continue to accept my own DA and bcast frames */ 353 354 ETHER_LOCK(ec); 355 if (usbnet_ispromisc(un)) { 356 ec->ec_flags |= ETHER_F_ALLMULTI; 357 ETHER_UNLOCK(ec); 358 /* run promisc. mode */ 359 rxmode |= URE_RCR_AM; /* ??? */ 360 rxmode |= URE_RCR_AAP; 361 goto update; 362 } 363 ec->ec_flags &= ~ETHER_F_ALLMULTI; 364 ETHER_FIRST_MULTI(step, ec, enm); 365 while (enm != NULL) { 366 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 367 ec->ec_flags |= ETHER_F_ALLMULTI; 368 ETHER_UNLOCK(ec); 369 /* accept all mcast frames */ 370 rxmode |= URE_RCR_AM; 371 mchash[0] = mchash[1] = ~0U; /* necessary ?? */ 372 goto update; 373 } 374 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 375 mchash[h >> 31] |= 1U << ((h >> 26) & 0x1f); 376 ETHER_NEXT_MULTI(step, enm); 377 } 378 ETHER_UNLOCK(ec); 379 if (h != 0) { 380 rxmode |= URE_RCR_AM; /* activate mcast hash filter */ 381 h = bswap32(mchash[0]); 382 mchash[0] = bswap32(mchash[1]); 383 mchash[1] = h; 384 } 385 update: 386 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, mchash[0]); 387 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, mchash[1]); 388 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 389 } 390 391 static void 392 ure_reset(struct usbnet *un) 393 { 394 int i; 395 396 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 397 398 for (i = 0; i < URE_TIMEOUT; i++) { 399 if (usbnet_isdying(un)) 400 return; 401 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 402 URE_CR_RST)) 403 break; 404 usbd_delay_ms(un->un_udev, 10); 405 } 406 if (i == URE_TIMEOUT) 407 URE_PRINTF(un, "reset never completed\n"); 408 } 409 410 static int 411 ure_uno_init(struct ifnet *ifp) 412 { 413 struct usbnet * const un = ifp->if_softc; 414 uint8_t eaddr[8]; 415 416 /* Set MAC address. */ 417 memset(eaddr, 0, sizeof(eaddr)); 418 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 419 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 420 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 421 eaddr, 8); 422 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 423 424 /* Reset the packet filter. */ 425 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 426 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 427 ~URE_FMC_FCR_MCU_EN); 428 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 429 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 430 URE_FMC_FCR_MCU_EN); 431 432 /* Enable transmit and receive. */ 433 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 434 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 435 URE_CR_TE); 436 437 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 438 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 439 ~URE_RXDY_GATED_EN); 440 441 return 0; 442 } 443 444 static void 445 ure_uno_stop(struct ifnet *ifp, int disable __unused) 446 { 447 struct usbnet * const un = ifp->if_softc; 448 449 ure_reset(un); 450 } 451 452 static void 453 ure_rtl8152_init(struct usbnet *un) 454 { 455 uint32_t pwrctrl; 456 457 /* Disable ALDPS. */ 458 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 459 URE_DIS_SDSAVE); 460 usbd_delay_ms(un->un_udev, 20); 461 462 if (un->un_flags & URE_FLAG_VER_4C00) { 463 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 464 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 465 ~URE_LED_MODE_MASK); 466 } 467 468 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 469 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 470 ~URE_POWER_CUT); 471 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 472 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 473 ~URE_RESUME_INDICATE); 474 475 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 476 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 477 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 478 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 479 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 480 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 481 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 482 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 483 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 484 URE_SPDWN_LINKCHG_MSK); 485 486 /* Enable Rx aggregation. */ 487 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 488 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 489 ~URE_RX_AGG_DISABLE); 490 491 /* Disable ALDPS. */ 492 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 493 URE_DIS_SDSAVE); 494 usbd_delay_ms(un->un_udev, 20); 495 496 ure_init_fifo(un); 497 498 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 499 URE_TX_AGG_MAX_THRESHOLD); 500 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 501 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 502 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 503 } 504 505 static void 506 ure_rtl8153_init(struct usbnet *un) 507 { 508 uint16_t val; 509 uint8_t u1u2[8]; 510 int i; 511 512 /* Disable ALDPS. */ 513 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 514 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 515 usbd_delay_ms(un->un_udev, 20); 516 517 memset(u1u2, 0x00, sizeof(u1u2)); 518 ure_write_mem(un, URE_USB_TOLERANCE, 519 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 520 521 for (i = 0; i < URE_TIMEOUT; i++) { 522 if (usbnet_isdying(un)) 523 return; 524 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 525 URE_AUTOLOAD_DONE) 526 break; 527 usbd_delay_ms(un->un_udev, 10); 528 } 529 if (i == URE_TIMEOUT) 530 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 531 532 for (i = 0; i < URE_TIMEOUT; i++) { 533 if (usbnet_isdying(un)) 534 return; 535 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 536 URE_PHY_STAT_MASK; 537 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 538 break; 539 usbd_delay_ms(un->un_udev, 10); 540 } 541 if (i == URE_TIMEOUT) 542 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 543 544 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 545 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 546 ~URE_U2P3_ENABLE); 547 548 if (un->un_flags & URE_FLAG_VER_5C10) { 549 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 550 val &= ~URE_PWD_DN_SCALE_MASK; 551 val |= URE_PWD_DN_SCALE(96); 552 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 553 554 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 555 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 556 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 557 } else if (un->un_flags & URE_FLAG_VER_5C20) { 558 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 559 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 560 ~URE_ECM_ALDPS); 561 } 562 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 563 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 564 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 565 0) 566 val &= ~URE_DYNAMIC_BURST; 567 else 568 val |= URE_DYNAMIC_BURST; 569 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 570 } 571 572 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 573 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 574 URE_EP4_FULL_FC); 575 576 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 577 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 578 ~URE_TIMER11_EN); 579 580 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 581 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 582 ~URE_LED_MODE_MASK); 583 584 if ((un->un_flags & URE_FLAG_VER_5C10) && 585 un->un_udev->ud_speed != USB_SPEED_SUPER) 586 val = URE_LPM_TIMER_500MS; 587 else 588 val = URE_LPM_TIMER_500US; 589 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 590 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 591 592 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 593 val &= ~URE_SEN_VAL_MASK; 594 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 595 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 596 597 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 598 599 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 600 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 601 ~(URE_PWR_EN | URE_PHASE2_EN)); 602 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 603 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 604 ~URE_PCUT_STATUS); 605 606 memset(u1u2, 0xff, sizeof(u1u2)); 607 ure_write_mem(un, URE_USB_TOLERANCE, 608 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 609 610 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 611 URE_ALDPS_SPDWN_RATIO); 612 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 613 URE_EEE_SPDWN_RATIO); 614 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 615 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 616 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 617 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 618 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 619 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 620 URE_EEE_SPDWN_EN); 621 622 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 623 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 624 val |= URE_U2P3_ENABLE; 625 else 626 val &= ~URE_U2P3_ENABLE; 627 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 628 629 memset(u1u2, 0x00, sizeof(u1u2)); 630 ure_write_mem(un, URE_USB_TOLERANCE, 631 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 632 633 /* Disable ALDPS. */ 634 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 635 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 636 usbd_delay_ms(un->un_udev, 20); 637 638 ure_init_fifo(un); 639 640 /* Enable Rx aggregation. */ 641 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 642 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 643 ~URE_RX_AGG_DISABLE); 644 645 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 646 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 647 val |= URE_U2P3_ENABLE; 648 else 649 val &= ~URE_U2P3_ENABLE; 650 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 651 652 memset(u1u2, 0xff, sizeof(u1u2)); 653 ure_write_mem(un, URE_USB_TOLERANCE, 654 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 655 } 656 657 static void 658 ure_disable_teredo(struct usbnet *un) 659 { 660 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 661 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 662 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 663 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 664 URE_WDT6_SET_MODE); 665 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 666 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 667 } 668 669 static void 670 ure_init_fifo(struct usbnet *un) 671 { 672 uint32_t rxmode, rx_fifo1, rx_fifo2; 673 int i; 674 675 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 676 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 677 URE_RXDY_GATED_EN); 678 679 ure_disable_teredo(un); 680 681 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 682 rxmode &= ~URE_RCR_ACPT_ALL; 683 rxmode |= URE_RCR_APM | URE_RCR_AB; /* accept my own DA and bcast */ 684 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 685 686 if (!(un->un_flags & URE_FLAG_8152)) { 687 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 688 URE_FLAG_VER_5C20)) 689 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 690 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 691 if (un->un_flags & URE_FLAG_VER_5C00) 692 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 693 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 694 ~URE_CTAP_SHORT_EN); 695 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 696 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 697 URE_EEE_CLKDIV_EN); 698 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 699 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 700 URE_EN_10M_BGOFF); 701 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 702 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 703 URE_EN_10M_PLLOFF); 704 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 705 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 706 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 707 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 708 URE_PFM_PWM_SWITCH); 709 710 /* Enable LPF corner auto tune. */ 711 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 712 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 713 714 /* Adjust 10M amplitude. */ 715 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 716 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 717 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 718 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 719 } 720 721 ure_reset(un); 722 723 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 724 725 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 726 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 727 ~URE_NOW_IS_OOB); 728 729 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 730 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 731 ~URE_MCU_BORW_EN); 732 for (i = 0; i < URE_TIMEOUT; i++) { 733 if (usbnet_isdying(un)) 734 return; 735 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 736 URE_LINK_LIST_READY) 737 break; 738 usbd_delay_ms(un->un_udev, 10); 739 } 740 if (i == URE_TIMEOUT) 741 URE_PRINTF(un, "timeout waiting for OOB control\n"); 742 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 743 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 744 URE_RE_INIT_LL); 745 for (i = 0; i < URE_TIMEOUT; i++) { 746 if (usbnet_isdying(un)) 747 return; 748 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 749 URE_LINK_LIST_READY) 750 break; 751 usbd_delay_ms(un->un_udev, 10); 752 } 753 if (i == URE_TIMEOUT) 754 URE_PRINTF(un, "timeout waiting for OOB control\n"); 755 756 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 757 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 758 ~URE_CPCR_RX_VLAN); 759 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 760 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 761 URE_TCR0_AUTO_FIFO); 762 763 /* Configure Rx FIFO threshold and coalescing. */ 764 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 765 URE_RXFIFO_THR1_NORMAL); 766 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 767 rx_fifo1 = URE_RXFIFO_THR2_FULL; 768 rx_fifo2 = URE_RXFIFO_THR3_FULL; 769 } else { 770 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 771 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 772 } 773 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 774 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 775 776 /* Configure Tx FIFO threshold. */ 777 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 778 URE_TXFIFO_THR_NORMAL); 779 } 780 781 static int 782 ure_match(device_t parent, cfdata_t match, void *aux) 783 { 784 struct usb_attach_arg *uaa = aux; 785 786 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 787 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 788 } 789 790 static void 791 ure_attach(device_t parent, device_t self, void *aux) 792 { 793 USBNET_MII_DECL_DEFAULT(unm); 794 struct usbnet * const un = device_private(self); 795 struct usb_attach_arg *uaa = aux; 796 struct usbd_device *dev = uaa->uaa_device; 797 usb_interface_descriptor_t *id; 798 usb_endpoint_descriptor_t *ed; 799 int error, i; 800 uint16_t ver; 801 uint8_t eaddr[8]; /* 2byte padded */ 802 char *devinfop; 803 uint32_t maclo, machi; 804 805 aprint_naive("\n"); 806 aprint_normal("\n"); 807 devinfop = usbd_devinfo_alloc(dev, 0); 808 aprint_normal_dev(self, "%s\n", devinfop); 809 usbd_devinfo_free(devinfop); 810 811 un->un_dev = self; 812 un->un_udev = dev; 813 un->un_sc = un; 814 un->un_ops = &ure_ops; 815 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 816 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 817 un->un_rx_list_cnt = URE_RX_LIST_CNT; 818 un->un_tx_list_cnt = URE_TX_LIST_CNT; 819 un->un_rx_bufsz = URE_BUFSZ; 820 un->un_tx_bufsz = URE_BUFSZ; 821 822 #define URE_CONFIG_NO 1 /* XXX */ 823 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 824 if (error) { 825 aprint_error_dev(self, "failed to set configuration: %s\n", 826 usbd_errstr(error)); 827 return; /* XXX */ 828 } 829 830 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 831 un->un_flags |= URE_FLAG_8152; 832 833 #define URE_IFACE_IDX 0 /* XXX */ 834 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 835 if (error) { 836 aprint_error_dev(self, "failed to get interface handle: %s\n", 837 usbd_errstr(error)); 838 return; /* XXX */ 839 } 840 841 id = usbd_get_interface_descriptor(un->un_iface); 842 for (i = 0; i < id->bNumEndpoints; i++) { 843 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 844 if (ed == NULL) { 845 aprint_error_dev(self, "couldn't get ep %d\n", i); 846 return; /* XXX */ 847 } 848 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 849 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 850 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 851 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 852 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 853 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 854 } 855 } 856 857 /* Set these up now for ure_ctl(). */ 858 usbnet_attach(un); 859 860 un->un_phyno = 0; 861 862 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 863 switch (ver) { 864 case 0x4c00: 865 un->un_flags |= URE_FLAG_VER_4C00; 866 break; 867 case 0x4c10: 868 un->un_flags |= URE_FLAG_VER_4C10; 869 break; 870 case 0x5c00: 871 un->un_flags |= URE_FLAG_VER_5C00; 872 break; 873 case 0x5c10: 874 un->un_flags |= URE_FLAG_VER_5C10; 875 break; 876 case 0x5c20: 877 un->un_flags |= URE_FLAG_VER_5C20; 878 break; 879 case 0x5c30: 880 un->un_flags |= URE_FLAG_VER_5C30; 881 break; 882 default: 883 /* fake addr? or just fail? */ 884 break; 885 } 886 aprint_normal_dev(self, "RTL%d %sver %04x\n", 887 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 888 (un->un_flags != 0) ? "" : "unknown ", 889 ver); 890 891 if (un->un_flags & URE_FLAG_8152) 892 ure_rtl8152_init(un); 893 else 894 ure_rtl8153_init(un); 895 896 if ((un->un_flags & URE_FLAG_VER_4C00) || 897 (un->un_flags & URE_FLAG_VER_4C10)) 898 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 899 sizeof(eaddr)); 900 else 901 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 902 sizeof(eaddr)); 903 if (ETHER_IS_ZERO(eaddr)) { 904 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 905 machi = cprng_strong32() & 0xffff; 906 eaddr[0] = maclo & 0xff; 907 eaddr[1] = (maclo >> 8) & 0xff; 908 eaddr[2] = (maclo >> 16) & 0xff; 909 eaddr[3] = (maclo >> 24) & 0xff; 910 eaddr[4] = machi & 0xff; 911 eaddr[5] = (machi >> 8) & 0xff; 912 } 913 memcpy(un->un_eaddr, eaddr, sizeof(un->un_eaddr)); 914 915 struct ifnet *ifp = usbnet_ifp(un); 916 917 /* 918 * We don't support TSOv4 and v6 for now, that are required to 919 * be handled in software for some cases. 920 */ 921 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 922 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 923 #ifdef INET6 924 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 925 #endif 926 if (un->un_flags & ~URE_FLAG_VER_4C00) { 927 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 928 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 929 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 930 } 931 struct ethercom *ec = usbnet_ec(un); 932 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 933 #ifdef notyet 934 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 935 #endif 936 937 unm.un_mii_phyloc = un->un_phyno; 938 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 939 0, &unm); 940 } 941 942 static void 943 ure_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 944 { 945 struct ifnet *ifp = usbnet_ifp(un); 946 uint8_t *buf = c->unc_buf; 947 uint16_t pkt_len = 0; 948 uint16_t pkt_count = 0; 949 struct ure_rxpkt rxhdr; 950 951 do { 952 if (total_len < sizeof(rxhdr)) { 953 DPRINTF(("too few bytes left for a packet header\n")); 954 if_statinc(ifp, if_ierrors); 955 return; 956 } 957 958 buf += roundup(pkt_len, 8); 959 960 memcpy(&rxhdr, buf, sizeof(rxhdr)); 961 total_len -= sizeof(rxhdr); 962 963 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 964 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 965 if (pkt_len > total_len) { 966 DPRINTF(("not enough bytes left for next packet\n")); 967 if_statinc(ifp, if_ierrors); 968 return; 969 } 970 971 total_len -= roundup(pkt_len, 8); 972 buf += sizeof(rxhdr); 973 974 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 975 ure_rxcsum(ifp, &rxhdr), 0, 0); 976 977 pkt_count++; 978 979 } while (total_len > 0); 980 981 if (pkt_count) 982 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 983 } 984 985 static int 986 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 987 { 988 int enabled = ifp->if_csum_flags_rx, flags = 0; 989 uint32_t csum, misc; 990 991 if (enabled == 0) 992 return 0; 993 994 csum = le32toh(rp->ure_csum); 995 misc = le32toh(rp->ure_misc); 996 997 if (csum & URE_RXPKT_IPV4_CS) { 998 flags |= M_CSUM_IPv4; 999 if (csum & URE_RXPKT_TCP_CS) 1000 flags |= M_CSUM_TCPv4; 1001 if (csum & URE_RXPKT_UDP_CS) 1002 flags |= M_CSUM_UDPv4; 1003 } else if (csum & URE_RXPKT_IPV6_CS) { 1004 flags = 0; 1005 if (csum & URE_RXPKT_TCP_CS) 1006 flags |= M_CSUM_TCPv6; 1007 if (csum & URE_RXPKT_UDP_CS) 1008 flags |= M_CSUM_UDPv6; 1009 } 1010 1011 flags &= enabled; 1012 if (__predict_false((flags & M_CSUM_IPv4) && 1013 (misc & URE_RXPKT_IP_F))) 1014 flags |= M_CSUM_IPv4_BAD; 1015 if (__predict_false( 1016 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1017 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1018 )) 1019 flags |= M_CSUM_TCP_UDP_BAD; 1020 1021 return flags; 1022 } 1023 1024 static unsigned 1025 ure_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1026 { 1027 struct ure_txpkt txhdr; 1028 uint32_t frm_len = 0; 1029 uint8_t *buf = c->unc_buf; 1030 1031 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1032 return 0; 1033 1034 /* header */ 1035 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1036 URE_TXPKT_TX_LS); 1037 txhdr.ure_csum = htole32(ure_txcsum(m)); 1038 memcpy(buf, &txhdr, sizeof(txhdr)); 1039 buf += sizeof(txhdr); 1040 frm_len = sizeof(txhdr); 1041 1042 /* packet */ 1043 m_copydata(m, 0, m->m_pkthdr.len, buf); 1044 frm_len += m->m_pkthdr.len; 1045 1046 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1047 1048 return frm_len; 1049 } 1050 1051 /* 1052 * We need to calculate L4 checksum in software, if the offset of 1053 * L4 header is larger than 0x7ff = 2047. 1054 */ 1055 static uint32_t 1056 ure_txcsum(struct mbuf *m) 1057 { 1058 struct ether_header *eh; 1059 int flags = m->m_pkthdr.csum_flags; 1060 uint32_t data = m->m_pkthdr.csum_data; 1061 uint32_t reg = 0; 1062 int l3off, l4off; 1063 uint16_t type; 1064 1065 if (flags == 0) 1066 return 0; 1067 1068 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1069 eh = mtod(m, struct ether_header *); 1070 type = eh->ether_type; 1071 } else 1072 m_copydata(m, offsetof(struct ether_header, ether_type), 1073 sizeof(type), &type); 1074 switch (type = htons(type)) { 1075 case ETHERTYPE_IP: 1076 case ETHERTYPE_IPV6: 1077 l3off = ETHER_HDR_LEN; 1078 break; 1079 case ETHERTYPE_VLAN: 1080 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1081 break; 1082 default: 1083 return 0; 1084 } 1085 1086 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1087 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1088 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1089 in_undefer_cksum(m, l3off, flags); 1090 return 0; 1091 } 1092 reg |= URE_TXPKT_IPV4_CS; 1093 if (flags & M_CSUM_TCPv4) 1094 reg |= URE_TXPKT_TCP_CS; 1095 else 1096 reg |= URE_TXPKT_UDP_CS; 1097 reg |= l4off << URE_L4_OFFSET_SHIFT; 1098 } 1099 #ifdef INET6 1100 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1101 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1102 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1103 in6_undefer_cksum(m, l3off, flags); 1104 return 0; 1105 } 1106 reg |= URE_TXPKT_IPV6_CS; 1107 if (flags & M_CSUM_TCPv6) 1108 reg |= URE_TXPKT_TCP_CS; 1109 else 1110 reg |= URE_TXPKT_UDP_CS; 1111 reg |= l4off << URE_L4_OFFSET_SHIFT; 1112 } 1113 #endif 1114 else if (flags & M_CSUM_IPv4) 1115 reg |= URE_TXPKT_IPV4_CS; 1116 1117 return reg; 1118 } 1119 1120 #ifdef _MODULE 1121 #include "ioconf.c" 1122 #endif 1123 1124 USBNET_MODULE(ure) 1125
Indexes created Mon Sep 29 21:09:56 GMT 2025