if_ure.c revision 1.59
1 /* $NetBSD: if_ure.c,v 1.59 2023/10/09 11:28:05 riastradh Exp $ */ 2 /* $OpenBSD: if_ure.c,v 1.10 2018/11/02 21:32:30 jcs Exp $ */ 3 4 /*- 5 * Copyright (c) 2015-2016 Kevin Lo <kevlo (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* RealTek RTL8152/RTL8153 10/100/Gigabit USB Ethernet device */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ure.c,v 1.59 2023/10/09 11:28:05 riastradh Exp $"); 34 35 #ifdef _KERNEL_OPT 36 #include "opt_usb.h" 37 #include "opt_inet.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/cprng.h> 42 43 #include <net/route.h> 44 45 #include <dev/usb/usbnet.h> 46 47 #include <netinet/in_offload.h> /* XXX for in_undefer_cksum() */ 48 #ifdef INET6 49 #include <netinet/in.h> 50 #include <netinet6/in6_offload.h> /* XXX for in6_undefer_cksum() */ 51 #endif 52 53 #include <dev/ic/rtl81x9reg.h> /* XXX for RTK_GMEDIASTAT */ 54 #include <dev/usb/if_urereg.h> 55 #include <dev/usb/if_urevar.h> 56 57 #define URE_PRINTF(un, fmt, args...) \ 58 device_printf((un)->un_dev, "%s: " fmt, __func__, ##args); 59 60 #define URE_DEBUG 61 #ifdef URE_DEBUG 62 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 63 #define DPRINTFN(n, x) do { if (uredebug >= (n)) printf x; } while (0) 64 int uredebug = 0; 65 #else 66 #define DPRINTF(x) 67 #define DPRINTFN(n, x) 68 #endif 69 70 #define ETHER_IS_ZERO(addr) \ 71 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 72 73 static const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 76 }; 77 78 #define URE_BUFSZ (16 * 1024) 79 80 static void ure_reset(struct usbnet *); 81 static uint32_t ure_txcsum(struct mbuf *); 82 static int ure_rxcsum(struct ifnet *, struct ure_rxpkt *); 83 static void ure_rtl8152_init(struct usbnet *); 84 static void ure_rtl8153_init(struct usbnet *); 85 static void ure_disable_teredo(struct usbnet *); 86 static void ure_init_fifo(struct usbnet *); 87 88 static void ure_uno_stop(struct ifnet *, int); 89 static void ure_uno_mcast(struct ifnet *); 90 static int ure_uno_mii_read_reg(struct usbnet *, int, int, uint16_t *); 91 static int ure_uno_mii_write_reg(struct usbnet *, int, int, uint16_t); 92 static void ure_uno_miibus_statchg(struct ifnet *); 93 static unsigned ure_uno_tx_prepare(struct usbnet *, struct mbuf *, 94 struct usbnet_chain *); 95 static void ure_uno_rx_loop(struct usbnet *, struct usbnet_chain *, 96 uint32_t); 97 static int ure_uno_init(struct ifnet *); 98 99 static int ure_match(device_t, cfdata_t, void *); 100 static void ure_attach(device_t, device_t, void *); 101 102 CFATTACH_DECL_NEW(ure, sizeof(struct usbnet), ure_match, ure_attach, 103 usbnet_detach, usbnet_activate); 104 105 static const struct usbnet_ops ure_ops = { 106 .uno_stop = ure_uno_stop, 107 .uno_mcast = ure_uno_mcast, 108 .uno_read_reg = ure_uno_mii_read_reg, 109 .uno_write_reg = ure_uno_mii_write_reg, 110 .uno_statchg = ure_uno_miibus_statchg, 111 .uno_tx_prepare = ure_uno_tx_prepare, 112 .uno_rx_loop = ure_uno_rx_loop, 113 .uno_init = ure_uno_init, 114 }; 115 116 static int 117 ure_ctl(struct usbnet *un, uint8_t rw, uint16_t val, uint16_t index, 118 void *buf, int len) 119 { 120 usb_device_request_t req; 121 usbd_status err; 122 123 if (usbnet_isdying(un)) 124 return 0; 125 126 if (rw == URE_CTL_WRITE) 127 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 128 else 129 req.bmRequestType = UT_READ_VENDOR_DEVICE; 130 req.bRequest = UR_SET_ADDRESS; 131 USETW(req.wValue, val); 132 USETW(req.wIndex, index); 133 USETW(req.wLength, len); 134 135 DPRINTFN(5, ("ure_ctl: rw %d, val %04hu, index %04hu, len %d\n", 136 rw, val, index, len)); 137 err = usbd_do_request(un->un_udev, &req, buf); 138 if (err) { 139 DPRINTF(("ure_ctl: error %d\n", err)); 140 if (rw == URE_CTL_READ) 141 memset(buf, 0, len); 142 return -1; 143 } 144 145 return 0; 146 } 147 148 static int 149 ure_read_mem(struct usbnet *un, uint16_t addr, uint16_t index, 150 void *buf, int len) 151 { 152 return ure_ctl(un, URE_CTL_READ, addr, index, buf, len); 153 } 154 155 static int 156 ure_write_mem(struct usbnet *un, uint16_t addr, uint16_t index, 157 void *buf, int len) 158 { 159 return ure_ctl(un, URE_CTL_WRITE, addr, index, buf, len); 160 } 161 162 static uint8_t 163 ure_read_1(struct usbnet *un, uint16_t reg, uint16_t index) 164 { 165 uint32_t val; 166 uint8_t temp[4]; 167 uint8_t shift; 168 169 shift = (reg & 3) << 3; 170 reg &= ~3; 171 172 ure_read_mem(un, reg, index, &temp, 4); 173 val = UGETDW(temp); 174 val >>= shift; 175 176 return val & 0xff; 177 } 178 179 static uint16_t 180 ure_read_2(struct usbnet *un, uint16_t reg, uint16_t index) 181 { 182 uint32_t val; 183 uint8_t temp[4]; 184 uint8_t shift; 185 186 shift = (reg & 2) << 3; 187 reg &= ~3; 188 189 ure_read_mem(un, reg, index, &temp, 4); 190 val = UGETDW(temp); 191 val >>= shift; 192 193 return val & 0xffff; 194 } 195 196 static uint32_t 197 ure_read_4(struct usbnet *un, uint16_t reg, uint16_t index) 198 { 199 uint8_t temp[4]; 200 201 ure_read_mem(un, reg, index, &temp, 4); 202 return UGETDW(temp); 203 } 204 205 static int 206 ure_write_1(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 207 { 208 uint16_t byen; 209 uint8_t temp[4]; 210 uint8_t shift; 211 212 byen = URE_BYTE_EN_BYTE; 213 shift = reg & 3; 214 val &= 0xff; 215 216 if (reg & 3) { 217 byen <<= shift; 218 val <<= (shift << 3); 219 reg &= ~3; 220 } 221 222 USETDW(temp, val); 223 return ure_write_mem(un, reg, index | byen, &temp, 4); 224 } 225 226 static int 227 ure_write_2(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 228 { 229 uint16_t byen; 230 uint8_t temp[4]; 231 uint8_t shift; 232 233 byen = URE_BYTE_EN_WORD; 234 shift = reg & 2; 235 val &= 0xffff; 236 237 if (reg & 2) { 238 byen <<= shift; 239 val <<= (shift << 3); 240 reg &= ~3; 241 } 242 243 USETDW(temp, val); 244 return ure_write_mem(un, reg, index | byen, &temp, 4); 245 } 246 247 static int 248 ure_write_4(struct usbnet *un, uint16_t reg, uint16_t index, uint32_t val) 249 { 250 uint8_t temp[4]; 251 252 USETDW(temp, val); 253 return ure_write_mem(un, reg, index | URE_BYTE_EN_DWORD, &temp, 4); 254 } 255 256 static uint16_t 257 ure_ocp_reg_read(struct usbnet *un, uint16_t addr) 258 { 259 uint16_t reg; 260 261 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 262 reg = (addr & 0x0fff) | 0xb000; 263 264 return ure_read_2(un, reg, URE_MCU_TYPE_PLA); 265 } 266 267 static void 268 ure_ocp_reg_write(struct usbnet *un, uint16_t addr, uint16_t data) 269 { 270 uint16_t reg; 271 272 ure_write_2(un, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 273 reg = (addr & 0x0fff) | 0xb000; 274 275 ure_write_2(un, reg, URE_MCU_TYPE_PLA, data); 276 } 277 278 static int 279 ure_uno_mii_read_reg(struct usbnet *un, int phy, int reg, uint16_t *val) 280 { 281 282 if (un->un_phyno != phy) { 283 *val = 0; 284 return EINVAL; 285 } 286 287 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 288 if (reg == RTK_GMEDIASTAT) { 289 *val = ure_read_1(un, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 290 return USBD_NORMAL_COMPLETION; 291 } 292 293 *val = ure_ocp_reg_read(un, URE_OCP_BASE_MII + reg * 2); 294 295 return 0; 296 } 297 298 static int 299 ure_uno_mii_write_reg(struct usbnet *un, int phy, int reg, uint16_t val) 300 { 301 302 if (un->un_phyno != phy) 303 return EINVAL; 304 305 ure_ocp_reg_write(un, URE_OCP_BASE_MII + reg * 2, val); 306 307 return 0; 308 } 309 310 static void 311 ure_uno_miibus_statchg(struct ifnet *ifp) 312 { 313 struct usbnet * const un = ifp->if_softc; 314 struct mii_data * const mii = usbnet_mii(un); 315 316 if (usbnet_isdying(un)) 317 return; 318 319 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 320 (IFM_ACTIVE | IFM_AVALID)) { 321 switch (IFM_SUBTYPE(mii->mii_media_active)) { 322 case IFM_10_T: 323 case IFM_100_TX: 324 usbnet_set_link(un, true); 325 break; 326 case IFM_1000_T: 327 if ((un->un_flags & URE_FLAG_8152) != 0) 328 break; 329 usbnet_set_link(un, true); 330 break; 331 default: 332 break; 333 } 334 } 335 } 336 337 static void 338 ure_uno_mcast(struct ifnet *ifp) 339 { 340 struct usbnet *un = ifp->if_softc; 341 struct ethercom *ec = usbnet_ec(un); 342 struct ether_multi *enm; 343 struct ether_multistep step; 344 uint32_t mchash[2] = { 0, 0 }; 345 uint32_t h = 0, rxmode; 346 347 if (usbnet_isdying(un)) 348 return; 349 350 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 351 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 352 /* continue to accept my own DA and bcast frames */ 353 354 ETHER_LOCK(ec); 355 if (usbnet_ispromisc(un)) { 356 ec->ec_flags |= ETHER_F_ALLMULTI; 357 ETHER_UNLOCK(ec); 358 /* run promisc. mode */ 359 rxmode |= URE_RCR_AM; /* ??? */ 360 rxmode |= URE_RCR_AAP; 361 mchash[0] = mchash[1] = 0xffffffff; 362 goto update; 363 } 364 ec->ec_flags &= ~ETHER_F_ALLMULTI; 365 ETHER_FIRST_MULTI(step, ec, enm); 366 while (enm != NULL) { 367 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 368 ec->ec_flags |= ETHER_F_ALLMULTI; 369 ETHER_UNLOCK(ec); 370 /* accept all mcast frames */ 371 rxmode |= URE_RCR_AM; 372 mchash[0] = mchash[1] = ~0U; /* necessary ?? */ 373 goto update; 374 } 375 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 376 mchash[h >> 31] |= 1U << ((h >> 26) & 0x1f); 377 ETHER_NEXT_MULTI(step, enm); 378 } 379 ETHER_UNLOCK(ec); 380 if (h != 0) { 381 rxmode |= URE_RCR_AM; /* activate mcast hash filter */ 382 h = bswap32(mchash[0]); 383 mchash[0] = bswap32(mchash[1]); 384 mchash[1] = h; 385 } 386 update: 387 ure_write_4(un, URE_PLA_MAR0, URE_MCU_TYPE_PLA, mchash[0]); 388 ure_write_4(un, URE_PLA_MAR4, URE_MCU_TYPE_PLA, mchash[1]); 389 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 390 } 391 392 static void 393 ure_reset(struct usbnet *un) 394 { 395 int i; 396 397 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 398 399 for (i = 0; i < URE_TIMEOUT; i++) { 400 if (usbnet_isdying(un)) 401 return; 402 if (!(ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) & 403 URE_CR_RST)) 404 break; 405 usbd_delay_ms(un->un_udev, 10); 406 } 407 if (i == URE_TIMEOUT) 408 URE_PRINTF(un, "reset never completed\n"); 409 } 410 411 static int 412 ure_uno_init(struct ifnet *ifp) 413 { 414 struct usbnet * const un = ifp->if_softc; 415 uint8_t eaddr[8]; 416 417 /* Set MAC address. */ 418 memset(eaddr, 0, sizeof(eaddr)); 419 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 420 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 421 ure_write_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 422 eaddr, 8); 423 ure_write_1(un, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 424 425 /* Reset the packet filter. */ 426 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 427 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 428 ~URE_FMC_FCR_MCU_EN); 429 ure_write_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA, 430 ure_read_2(un, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 431 URE_FMC_FCR_MCU_EN); 432 433 /* Enable transmit and receive. */ 434 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 435 ure_read_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 436 URE_CR_TE); 437 438 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 439 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 440 ~URE_RXDY_GATED_EN); 441 442 return 0; 443 } 444 445 static void 446 ure_uno_stop(struct ifnet *ifp, int disable __unused) 447 { 448 struct usbnet * const un = ifp->if_softc; 449 450 ure_reset(un); 451 } 452 453 static void 454 ure_rtl8152_init(struct usbnet *un) 455 { 456 uint32_t pwrctrl; 457 458 /* Disable ALDPS. */ 459 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 460 URE_DIS_SDSAVE); 461 usbd_delay_ms(un->un_udev, 20); 462 463 if (un->un_flags & URE_FLAG_VER_4C00) { 464 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 465 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 466 ~URE_LED_MODE_MASK); 467 } 468 469 ure_write_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 470 ure_read_2(un, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 471 ~URE_POWER_CUT); 472 ure_write_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 473 ure_read_2(un, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 474 ~URE_RESUME_INDICATE); 475 476 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 477 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 478 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 479 pwrctrl = ure_read_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 480 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 481 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 482 ure_write_4(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 483 ure_write_2(un, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 484 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 485 URE_SPDWN_LINKCHG_MSK); 486 487 /* Enable Rx aggregation. */ 488 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 489 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 490 ~URE_RX_AGG_DISABLE); 491 492 /* Disable ALDPS. */ 493 ure_ocp_reg_write(un, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 494 URE_DIS_SDSAVE); 495 usbd_delay_ms(un->un_udev, 20); 496 497 ure_init_fifo(un); 498 499 ure_write_1(un, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 500 URE_TX_AGG_MAX_THRESHOLD); 501 ure_write_4(un, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 502 ure_write_4(un, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 503 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 504 } 505 506 static void 507 ure_rtl8153_init(struct usbnet *un) 508 { 509 uint16_t val; 510 uint8_t u1u2[8]; 511 int i; 512 513 /* Disable ALDPS. */ 514 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 515 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 516 usbd_delay_ms(un->un_udev, 20); 517 518 memset(u1u2, 0x00, sizeof(u1u2)); 519 ure_write_mem(un, URE_USB_TOLERANCE, 520 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 521 522 for (i = 0; i < URE_TIMEOUT; i++) { 523 if (usbnet_isdying(un)) 524 return; 525 if (ure_read_2(un, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 526 URE_AUTOLOAD_DONE) 527 break; 528 usbd_delay_ms(un->un_udev, 10); 529 } 530 if (i == URE_TIMEOUT) 531 URE_PRINTF(un, "timeout waiting for chip autoload\n"); 532 533 for (i = 0; i < URE_TIMEOUT; i++) { 534 if (usbnet_isdying(un)) 535 return; 536 val = ure_ocp_reg_read(un, URE_OCP_PHY_STATUS) & 537 URE_PHY_STAT_MASK; 538 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 539 break; 540 usbd_delay_ms(un->un_udev, 10); 541 } 542 if (i == URE_TIMEOUT) 543 URE_PRINTF(un, "timeout waiting for phy to stabilize\n"); 544 545 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 546 ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 547 ~URE_U2P3_ENABLE); 548 549 if (un->un_flags & URE_FLAG_VER_5C10) { 550 val = ure_read_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 551 val &= ~URE_PWD_DN_SCALE_MASK; 552 val |= URE_PWD_DN_SCALE(96); 553 ure_write_2(un, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 554 555 ure_write_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 556 ure_read_1(un, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 557 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 558 } else if (un->un_flags & URE_FLAG_VER_5C20) { 559 ure_write_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 560 ure_read_1(un, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 561 ~URE_ECM_ALDPS); 562 } 563 if (un->un_flags & (URE_FLAG_VER_5C20 | URE_FLAG_VER_5C30)) { 564 val = ure_read_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 565 if (ure_read_2(un, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 566 0) 567 val &= ~URE_DYNAMIC_BURST; 568 else 569 val |= URE_DYNAMIC_BURST; 570 ure_write_1(un, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 571 } 572 573 ure_write_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 574 ure_read_1(un, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 575 URE_EP4_FULL_FC); 576 577 ure_write_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 578 ure_read_2(un, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 579 ~URE_TIMER11_EN); 580 581 ure_write_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 582 ure_read_2(un, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 583 ~URE_LED_MODE_MASK); 584 585 if ((un->un_flags & URE_FLAG_VER_5C10) && 586 un->un_udev->ud_speed != USB_SPEED_SUPER) 587 val = URE_LPM_TIMER_500MS; 588 else 589 val = URE_LPM_TIMER_500US; 590 ure_write_1(un, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 591 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 592 593 val = ure_read_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 594 val &= ~URE_SEN_VAL_MASK; 595 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 596 ure_write_2(un, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 597 598 ure_write_2(un, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 599 600 ure_write_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 601 ure_read_2(un, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 602 ~(URE_PWR_EN | URE_PHASE2_EN)); 603 ure_write_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB, 604 ure_read_2(un, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 605 ~URE_PCUT_STATUS); 606 607 memset(u1u2, 0xff, sizeof(u1u2)); 608 ure_write_mem(un, URE_USB_TOLERANCE, 609 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 610 611 ure_write_2(un, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 612 URE_ALDPS_SPDWN_RATIO); 613 ure_write_2(un, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 614 URE_EEE_SPDWN_RATIO); 615 ure_write_2(un, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 616 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 617 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 618 ure_write_2(un, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 619 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 620 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 621 URE_EEE_SPDWN_EN); 622 623 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 624 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 625 val |= URE_U2P3_ENABLE; 626 else 627 val &= ~URE_U2P3_ENABLE; 628 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 629 630 memset(u1u2, 0x00, sizeof(u1u2)); 631 ure_write_mem(un, URE_USB_TOLERANCE, 632 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 633 634 /* Disable ALDPS. */ 635 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 636 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 637 usbd_delay_ms(un->un_udev, 20); 638 639 ure_init_fifo(un); 640 641 /* Enable Rx aggregation. */ 642 ure_write_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 643 ure_read_2(un, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 644 ~URE_RX_AGG_DISABLE); 645 646 val = ure_read_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 647 if (!(un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10))) 648 val |= URE_U2P3_ENABLE; 649 else 650 val &= ~URE_U2P3_ENABLE; 651 ure_write_2(un, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 652 653 memset(u1u2, 0xff, sizeof(u1u2)); 654 ure_write_mem(un, URE_USB_TOLERANCE, 655 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 656 } 657 658 static void 659 ure_disable_teredo(struct usbnet *un) 660 { 661 ure_write_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 662 ure_read_4(un, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 663 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 664 ure_write_2(un, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 665 URE_WDT6_SET_MODE); 666 ure_write_2(un, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 667 ure_write_4(un, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 668 } 669 670 static void 671 ure_init_fifo(struct usbnet *un) 672 { 673 uint32_t rxmode, rx_fifo1, rx_fifo2; 674 int i; 675 676 ure_write_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 677 ure_read_2(un, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 678 URE_RXDY_GATED_EN); 679 680 ure_disable_teredo(un); 681 682 rxmode = ure_read_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA); 683 rxmode &= ~URE_RCR_ACPT_ALL; 684 rxmode |= URE_RCR_APM | URE_RCR_AB; /* accept my own DA and bcast */ 685 ure_write_4(un, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 686 687 if (!(un->un_flags & URE_FLAG_8152)) { 688 if (un->un_flags & (URE_FLAG_VER_5C00 | URE_FLAG_VER_5C10 | 689 URE_FLAG_VER_5C20)) 690 ure_ocp_reg_write(un, URE_OCP_ADC_CFG, 691 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 692 if (un->un_flags & URE_FLAG_VER_5C00) 693 ure_ocp_reg_write(un, URE_OCP_EEE_CFG, 694 ure_ocp_reg_read(un, URE_OCP_EEE_CFG) & 695 ~URE_CTAP_SHORT_EN); 696 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 697 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 698 URE_EEE_CLKDIV_EN); 699 ure_ocp_reg_write(un, URE_OCP_DOWN_SPEED, 700 ure_ocp_reg_read(un, URE_OCP_DOWN_SPEED) | 701 URE_EN_10M_BGOFF); 702 ure_ocp_reg_write(un, URE_OCP_POWER_CFG, 703 ure_ocp_reg_read(un, URE_OCP_POWER_CFG) | 704 URE_EN_10M_PLLOFF); 705 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 706 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0b13); 707 ure_write_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 708 ure_read_2(un, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 709 URE_PFM_PWM_SWITCH); 710 711 /* Enable LPF corner auto tune. */ 712 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 713 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0xf70f); 714 715 /* Adjust 10M amplitude. */ 716 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 717 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x00af); 718 ure_ocp_reg_write(un, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 719 ure_ocp_reg_write(un, URE_OCP_SRAM_DATA, 0x0208); 720 } 721 722 ure_reset(un); 723 724 ure_write_1(un, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 725 726 ure_write_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 727 ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 728 ~URE_NOW_IS_OOB); 729 730 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 731 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 732 ~URE_MCU_BORW_EN); 733 for (i = 0; i < URE_TIMEOUT; i++) { 734 if (usbnet_isdying(un)) 735 return; 736 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 737 URE_LINK_LIST_READY) 738 break; 739 usbd_delay_ms(un->un_udev, 10); 740 } 741 if (i == URE_TIMEOUT) 742 URE_PRINTF(un, "timeout waiting for OOB control\n"); 743 ure_write_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 744 ure_read_2(un, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 745 URE_RE_INIT_LL); 746 for (i = 0; i < URE_TIMEOUT; i++) { 747 if (usbnet_isdying(un)) 748 return; 749 if (ure_read_1(un, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 750 URE_LINK_LIST_READY) 751 break; 752 usbd_delay_ms(un->un_udev, 10); 753 } 754 if (i == URE_TIMEOUT) 755 URE_PRINTF(un, "timeout waiting for OOB control\n"); 756 757 ure_write_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 758 ure_read_2(un, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 759 ~URE_CPCR_RX_VLAN); 760 ure_write_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 761 ure_read_2(un, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 762 URE_TCR0_AUTO_FIFO); 763 764 /* Configure Rx FIFO threshold and coalescing. */ 765 ure_write_4(un, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 766 URE_RXFIFO_THR1_NORMAL); 767 if (un->un_udev->ud_speed == USB_SPEED_FULL) { 768 rx_fifo1 = URE_RXFIFO_THR2_FULL; 769 rx_fifo2 = URE_RXFIFO_THR3_FULL; 770 } else { 771 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 772 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 773 } 774 ure_write_4(un, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 775 ure_write_4(un, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 776 777 /* Configure Tx FIFO threshold. */ 778 ure_write_4(un, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 779 URE_TXFIFO_THR_NORMAL); 780 } 781 782 static int 783 ure_match(device_t parent, cfdata_t match, void *aux) 784 { 785 struct usb_attach_arg *uaa = aux; 786 787 return usb_lookup(ure_devs, uaa->uaa_vendor, uaa->uaa_product) != NULL ? 788 UMATCH_VENDOR_PRODUCT : UMATCH_NONE; 789 } 790 791 static void 792 ure_attach(device_t parent, device_t self, void *aux) 793 { 794 USBNET_MII_DECL_DEFAULT(unm); 795 struct usbnet * const un = device_private(self); 796 struct usb_attach_arg *uaa = aux; 797 struct usbd_device *dev = uaa->uaa_device; 798 usb_interface_descriptor_t *id; 799 usb_endpoint_descriptor_t *ed; 800 int error, i; 801 uint16_t ver; 802 uint8_t eaddr[8]; /* 2byte padded */ 803 char *devinfop; 804 uint32_t maclo, machi; 805 806 aprint_naive("\n"); 807 aprint_normal("\n"); 808 devinfop = usbd_devinfo_alloc(dev, 0); 809 aprint_normal_dev(self, "%s\n", devinfop); 810 usbd_devinfo_free(devinfop); 811 812 un->un_dev = self; 813 un->un_udev = dev; 814 un->un_sc = un; 815 un->un_ops = &ure_ops; 816 un->un_rx_xfer_flags = USBD_SHORT_XFER_OK; 817 un->un_tx_xfer_flags = USBD_FORCE_SHORT_XFER; 818 un->un_rx_list_cnt = URE_RX_LIST_CNT; 819 un->un_tx_list_cnt = URE_TX_LIST_CNT; 820 un->un_rx_bufsz = URE_BUFSZ; 821 un->un_tx_bufsz = URE_BUFSZ; 822 823 #define URE_CONFIG_NO 1 /* XXX */ 824 error = usbd_set_config_no(dev, URE_CONFIG_NO, 1); 825 if (error) { 826 aprint_error_dev(self, "failed to set configuration: %s\n", 827 usbd_errstr(error)); 828 return; /* XXX */ 829 } 830 831 if (uaa->uaa_product == USB_PRODUCT_REALTEK_RTL8152) 832 un->un_flags |= URE_FLAG_8152; 833 834 #define URE_IFACE_IDX 0 /* XXX */ 835 error = usbd_device2interface_handle(dev, URE_IFACE_IDX, &un->un_iface); 836 if (error) { 837 aprint_error_dev(self, "failed to get interface handle: %s\n", 838 usbd_errstr(error)); 839 return; /* XXX */ 840 } 841 842 id = usbd_get_interface_descriptor(un->un_iface); 843 for (i = 0; i < id->bNumEndpoints; i++) { 844 ed = usbd_interface2endpoint_descriptor(un->un_iface, i); 845 if (ed == NULL) { 846 aprint_error_dev(self, "couldn't get ep %d\n", i); 847 return; /* XXX */ 848 } 849 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 850 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 851 un->un_ed[USBNET_ENDPT_RX] = ed->bEndpointAddress; 852 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 853 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 854 un->un_ed[USBNET_ENDPT_TX] = ed->bEndpointAddress; 855 } 856 } 857 858 /* Set these up now for ure_ctl(). */ 859 usbnet_attach(un); 860 861 un->un_phyno = 0; 862 863 ver = ure_read_2(un, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 864 switch (ver) { 865 case 0x4c00: 866 un->un_flags |= URE_FLAG_VER_4C00; 867 break; 868 case 0x4c10: 869 un->un_flags |= URE_FLAG_VER_4C10; 870 break; 871 case 0x5c00: 872 un->un_flags |= URE_FLAG_VER_5C00; 873 break; 874 case 0x5c10: 875 un->un_flags |= URE_FLAG_VER_5C10; 876 break; 877 case 0x5c20: 878 un->un_flags |= URE_FLAG_VER_5C20; 879 break; 880 case 0x5c30: 881 un->un_flags |= URE_FLAG_VER_5C30; 882 break; 883 default: 884 /* fake addr? or just fail? */ 885 break; 886 } 887 aprint_normal_dev(self, "RTL%d %sver %04x\n", 888 (un->un_flags & URE_FLAG_8152) ? 8152 : 8153, 889 (un->un_flags != 0) ? "" : "unknown ", 890 ver); 891 892 if (un->un_flags & URE_FLAG_8152) 893 ure_rtl8152_init(un); 894 else 895 ure_rtl8153_init(un); 896 897 if ((un->un_flags & URE_FLAG_VER_4C00) || 898 (un->un_flags & URE_FLAG_VER_4C10)) 899 ure_read_mem(un, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 900 sizeof(eaddr)); 901 else 902 ure_read_mem(un, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 903 sizeof(eaddr)); 904 if (ETHER_IS_ZERO(eaddr)) { 905 maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); 906 machi = cprng_strong32() & 0xffff; 907 eaddr[0] = maclo & 0xff; 908 eaddr[1] = (maclo >> 8) & 0xff; 909 eaddr[2] = (maclo >> 16) & 0xff; 910 eaddr[3] = (maclo >> 24) & 0xff; 911 eaddr[4] = machi & 0xff; 912 eaddr[5] = (machi >> 8) & 0xff; 913 } 914 memcpy(un->un_eaddr, eaddr, sizeof(un->un_eaddr)); 915 916 struct ifnet *ifp = usbnet_ifp(un); 917 918 /* 919 * We don't support TSOv4 and v6 for now, that are required to 920 * be handled in software for some cases. 921 */ 922 ifp->if_capabilities = IFCAP_CSUM_IPv4_Tx | 923 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx; 924 #ifdef INET6 925 ifp->if_capabilities |= IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx; 926 #endif 927 if (un->un_flags & ~URE_FLAG_VER_4C00) { 928 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Rx | 929 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx | 930 IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx; 931 } 932 struct ethercom *ec = usbnet_ec(un); 933 ec->ec_capabilities = ETHERCAP_VLAN_MTU; 934 #ifdef notyet 935 ec->ec_capabilities |= ETHERCAP_JUMBO_MTU; 936 #endif 937 938 unm.un_mii_phyloc = un->un_phyno; 939 usbnet_attach_ifp(un, IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST, 940 0, &unm); 941 } 942 943 static void 944 ure_uno_rx_loop(struct usbnet *un, struct usbnet_chain *c, uint32_t total_len) 945 { 946 struct ifnet *ifp = usbnet_ifp(un); 947 uint8_t *buf = c->unc_buf; 948 uint16_t pkt_len = 0; 949 uint16_t pkt_count = 0; 950 struct ure_rxpkt rxhdr; 951 952 do { 953 if (total_len < sizeof(rxhdr)) { 954 DPRINTF(("too few bytes left for a packet header\n")); 955 if_statinc(ifp, if_ierrors); 956 return; 957 } 958 959 buf += roundup(pkt_len, 8); 960 961 memcpy(&rxhdr, buf, sizeof(rxhdr)); 962 total_len -= sizeof(rxhdr); 963 964 pkt_len = le32toh(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 965 DPRINTFN(4, ("next packet is %d bytes\n", pkt_len)); 966 if (pkt_len > total_len) { 967 DPRINTF(("not enough bytes left for next packet\n")); 968 if_statinc(ifp, if_ierrors); 969 return; 970 } 971 972 total_len -= roundup(pkt_len, 8); 973 buf += sizeof(rxhdr); 974 975 usbnet_enqueue(un, buf, pkt_len - ETHER_CRC_LEN, 976 ure_rxcsum(ifp, &rxhdr), 0, 0); 977 978 pkt_count++; 979 980 } while (total_len > 0); 981 982 if (pkt_count) 983 rnd_add_uint32(usbnet_rndsrc(un), pkt_count); 984 } 985 986 static int 987 ure_rxcsum(struct ifnet *ifp, struct ure_rxpkt *rp) 988 { 989 int enabled = ifp->if_csum_flags_rx, flags = 0; 990 uint32_t csum, misc; 991 992 if (enabled == 0) 993 return 0; 994 995 csum = le32toh(rp->ure_csum); 996 misc = le32toh(rp->ure_misc); 997 998 if (csum & URE_RXPKT_IPV4_CS) { 999 flags |= M_CSUM_IPv4; 1000 if (csum & URE_RXPKT_TCP_CS) 1001 flags |= M_CSUM_TCPv4; 1002 if (csum & URE_RXPKT_UDP_CS) 1003 flags |= M_CSUM_UDPv4; 1004 } else if (csum & URE_RXPKT_IPV6_CS) { 1005 flags = 0; 1006 if (csum & URE_RXPKT_TCP_CS) 1007 flags |= M_CSUM_TCPv6; 1008 if (csum & URE_RXPKT_UDP_CS) 1009 flags |= M_CSUM_UDPv6; 1010 } 1011 1012 flags &= enabled; 1013 if (__predict_false((flags & M_CSUM_IPv4) && 1014 (misc & URE_RXPKT_IP_F))) 1015 flags |= M_CSUM_IPv4_BAD; 1016 if (__predict_false( 1017 ((flags & (M_CSUM_TCPv4 | M_CSUM_TCPv6)) && (misc & URE_RXPKT_TCP_F)) 1018 || ((flags & (M_CSUM_UDPv4 | M_CSUM_UDPv6)) && (misc & URE_RXPKT_UDP_F)) 1019 )) 1020 flags |= M_CSUM_TCP_UDP_BAD; 1021 1022 return flags; 1023 } 1024 1025 static unsigned 1026 ure_uno_tx_prepare(struct usbnet *un, struct mbuf *m, struct usbnet_chain *c) 1027 { 1028 struct ure_txpkt txhdr; 1029 uint32_t frm_len = 0; 1030 uint8_t *buf = c->unc_buf; 1031 1032 if ((unsigned)m->m_pkthdr.len > un->un_tx_bufsz - sizeof(txhdr)) 1033 return 0; 1034 1035 /* header */ 1036 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1037 URE_TXPKT_TX_LS); 1038 txhdr.ure_csum = htole32(ure_txcsum(m)); 1039 memcpy(buf, &txhdr, sizeof(txhdr)); 1040 buf += sizeof(txhdr); 1041 frm_len = sizeof(txhdr); 1042 1043 /* packet */ 1044 m_copydata(m, 0, m->m_pkthdr.len, buf); 1045 frm_len += m->m_pkthdr.len; 1046 1047 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1048 1049 return frm_len; 1050 } 1051 1052 /* 1053 * We need to calculate L4 checksum in software, if the offset of 1054 * L4 header is larger than 0x7ff = 2047. 1055 */ 1056 static uint32_t 1057 ure_txcsum(struct mbuf *m) 1058 { 1059 struct ether_header *eh; 1060 int flags = m->m_pkthdr.csum_flags; 1061 uint32_t data = m->m_pkthdr.csum_data; 1062 uint32_t reg = 0; 1063 int l3off, l4off; 1064 uint16_t type; 1065 1066 if (flags == 0) 1067 return 0; 1068 1069 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1070 eh = mtod(m, struct ether_header *); 1071 type = eh->ether_type; 1072 } else 1073 m_copydata(m, offsetof(struct ether_header, ether_type), 1074 sizeof(type), &type); 1075 switch (type = htons(type)) { 1076 case ETHERTYPE_IP: 1077 case ETHERTYPE_IPV6: 1078 l3off = ETHER_HDR_LEN; 1079 break; 1080 case ETHERTYPE_VLAN: 1081 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1082 break; 1083 default: 1084 return 0; 1085 } 1086 1087 if (flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 1088 l4off = l3off + M_CSUM_DATA_IPv4_IPHL(data); 1089 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1090 in_undefer_cksum(m, l3off, flags); 1091 return 0; 1092 } 1093 reg |= URE_TXPKT_IPV4_CS; 1094 if (flags & M_CSUM_TCPv4) 1095 reg |= URE_TXPKT_TCP_CS; 1096 else 1097 reg |= URE_TXPKT_UDP_CS; 1098 reg |= l4off << URE_L4_OFFSET_SHIFT; 1099 } 1100 #ifdef INET6 1101 else if (flags & (M_CSUM_TCPv6 | M_CSUM_UDPv6)) { 1102 l4off = l3off + M_CSUM_DATA_IPv6_IPHL(data); 1103 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) { 1104 in6_undefer_cksum(m, l3off, flags); 1105 return 0; 1106 } 1107 reg |= URE_TXPKT_IPV6_CS; 1108 if (flags & M_CSUM_TCPv6) 1109 reg |= URE_TXPKT_TCP_CS; 1110 else 1111 reg |= URE_TXPKT_UDP_CS; 1112 reg |= l4off << URE_L4_OFFSET_SHIFT; 1113 } 1114 #endif 1115 else if (flags & M_CSUM_IPv4) 1116 reg |= URE_TXPKT_IPV4_CS; 1117 1118 return reg; 1119 } 1120 1121 #ifdef _MODULE 1122 #include "ioconf.c" 1123 #endif 1124 1125 USBNET_MODULE(ure) 1126
Indexes created Tue Sep 30 11:09:46 GMT 2025