if_url.c revision 1.24.10.4 1 1.24.10.4 itohy /* $NetBSD: if_url.c,v 1.24.10.4 2007/06/18 13:44:15 itohy Exp $ */
2 1.1 ichiro /*
3 1.1 ichiro * Copyright (c) 2001, 2002
4 1.1 ichiro * Shingo WATANABE <nabe (at) nabechan.org>. All rights reserved.
5 1.1 ichiro *
6 1.1 ichiro * Redistribution and use in source and binary forms, with or without
7 1.1 ichiro * modification, are permitted provided that the following conditions
8 1.1 ichiro * are met:
9 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
10 1.1 ichiro * notice, this list of conditions and the following disclaimer.
11 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
13 1.1 ichiro * documentation and/or other materials provided with the distribution.
14 1.8 tsutsui * 3. Neither the name of the author nor the names of any co-contributors
15 1.1 ichiro * may be used to endorse or promote products derived from this software
16 1.1 ichiro * without specific prior written permission.
17 1.1 ichiro *
18 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 1.1 ichiro * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 ichiro * SUCH DAMAGE.
29 1.1 ichiro *
30 1.1 ichiro */
31 1.1 ichiro
32 1.1 ichiro /*
33 1.1 ichiro * The RTL8150L(Realtek USB to fast ethernet controller) spec can be found at
34 1.1 ichiro * ftp://ftp.realtek.com.tw/lancard/data_sheet/8150/8150v14.pdf
35 1.1 ichiro * ftp://152.104.125.40/lancard/data_sheet/8150/8150v14.pdf
36 1.1 ichiro */
37 1.1 ichiro
38 1.1 ichiro /*
39 1.1 ichiro * TODO:
40 1.1 ichiro * Interrupt Endpoint support
41 1.1 ichiro * External PHYs
42 1.1 ichiro * powerhook() support?
43 1.1 ichiro */
44 1.1 ichiro
45 1.1 ichiro #include <sys/cdefs.h>
46 1.24.10.4 itohy __KERNEL_RCSID(0, "$NetBSD: if_url.c,v 1.24.10.4 2007/06/18 13:44:15 itohy Exp $");
47 1.1 ichiro
48 1.1 ichiro #include "opt_inet.h"
49 1.1 ichiro #include "bpfilter.h"
50 1.1 ichiro #include "rnd.h"
51 1.1 ichiro
52 1.1 ichiro #include <sys/param.h>
53 1.1 ichiro #include <sys/systm.h>
54 1.1 ichiro #include <sys/lock.h>
55 1.1 ichiro #include <sys/mbuf.h>
56 1.1 ichiro #include <sys/kernel.h>
57 1.1 ichiro #include <sys/socket.h>
58 1.1 ichiro
59 1.1 ichiro #include <sys/device.h>
60 1.1 ichiro #if NRND > 0
61 1.1 ichiro #include <sys/rnd.h>
62 1.1 ichiro #endif
63 1.1 ichiro
64 1.1 ichiro #include <net/if.h>
65 1.1 ichiro #include <net/if_arp.h>
66 1.1 ichiro #include <net/if_dl.h>
67 1.1 ichiro #include <net/if_media.h>
68 1.1 ichiro
69 1.1 ichiro #if NBPFILTER > 0
70 1.1 ichiro #include <net/bpf.h>
71 1.1 ichiro #endif
72 1.1 ichiro #define BPF_MTAP(ifp, m) bpf_mtap((ifp)->if_bpf, (m))
73 1.1 ichiro
74 1.1 ichiro #include <net/if_ether.h>
75 1.1 ichiro #ifdef INET
76 1.1 ichiro #include <netinet/in.h>
77 1.1 ichiro #include <netinet/if_inarp.h>
78 1.1 ichiro #endif
79 1.1 ichiro
80 1.1 ichiro #include <dev/mii/mii.h>
81 1.1 ichiro #include <dev/mii/miivar.h>
82 1.1 ichiro #include <dev/mii/urlphyreg.h>
83 1.1 ichiro
84 1.1 ichiro #include <dev/usb/usb.h>
85 1.1 ichiro #include <dev/usb/usbdi.h>
86 1.1 ichiro #include <dev/usb/usbdi_util.h>
87 1.1 ichiro #include <dev/usb/usbdevs.h>
88 1.24.10.2 itohy #include <dev/usb/usb_ethersubr.h>
89 1.1 ichiro
90 1.1 ichiro #include <dev/usb/if_urlreg.h>
91 1.1 ichiro
92 1.1 ichiro
93 1.1 ichiro /* Function declarations */
94 1.1 ichiro USB_DECLARE_DRIVER(url);
95 1.1 ichiro
96 1.1 ichiro Static int url_openpipes(struct url_softc *);
97 1.1 ichiro Static void url_start(struct ifnet *);
98 1.1 ichiro Static int url_send(struct url_softc *, struct mbuf *, int);
99 1.1 ichiro Static void url_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status);
100 1.1 ichiro Static void url_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status);
101 1.1 ichiro Static void url_tick(void *);
102 1.1 ichiro Static void url_tick_task(void *);
103 1.24.10.3 itohy Static int url_ioctl(struct ifnet *, u_long, usb_ioctlarg_t);
104 1.1 ichiro Static void url_stop_task(struct url_softc *);
105 1.1 ichiro Static void url_stop(struct ifnet *, int);
106 1.1 ichiro Static void url_watchdog(struct ifnet *);
107 1.1 ichiro Static int url_ifmedia_change(struct ifnet *);
108 1.1 ichiro Static void url_ifmedia_status(struct ifnet *, struct ifmediareq *);
109 1.1 ichiro Static void url_lock_mii(struct url_softc *);
110 1.1 ichiro Static void url_unlock_mii(struct url_softc *);
111 1.1 ichiro Static int url_int_miibus_readreg(device_ptr_t, int, int);
112 1.1 ichiro Static void url_int_miibus_writereg(device_ptr_t, int, int, int);
113 1.1 ichiro Static void url_miibus_statchg(device_ptr_t);
114 1.1 ichiro Static int url_init(struct ifnet *);
115 1.1 ichiro Static void url_setmulti(struct url_softc *);
116 1.1 ichiro Static void url_reset(struct url_softc *);
117 1.1 ichiro
118 1.1 ichiro Static int url_csr_read_1(struct url_softc *, int);
119 1.1 ichiro Static int url_csr_read_2(struct url_softc *, int);
120 1.1 ichiro Static int url_csr_write_1(struct url_softc *, int, int);
121 1.1 ichiro Static int url_csr_write_2(struct url_softc *, int, int);
122 1.1 ichiro Static int url_csr_write_4(struct url_softc *, int, int);
123 1.1 ichiro Static int url_mem(struct url_softc *, int, int, void *, int);
124 1.1 ichiro
125 1.1 ichiro /* Macros */
126 1.1 ichiro #ifdef URL_DEBUG
127 1.2 ichiro #define DPRINTF(x) if (urldebug) logprintf x
128 1.2 ichiro #define DPRINTFN(n,x) if (urldebug >= (n)) logprintf x
129 1.2 ichiro int urldebug = 0;
130 1.1 ichiro #else
131 1.1 ichiro #define DPRINTF(x)
132 1.1 ichiro #define DPRINTFN(n,x)
133 1.1 ichiro #endif
134 1.1 ichiro
135 1.1 ichiro #define URL_SETBIT(sc, reg, x) \
136 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) | (x))
137 1.1 ichiro
138 1.1 ichiro #define URL_SETBIT2(sc, reg, x) \
139 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) | (x))
140 1.1 ichiro
141 1.1 ichiro #define URL_CLRBIT(sc, reg, x) \
142 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) & ~(x))
143 1.1 ichiro
144 1.1 ichiro #define URL_CLRBIT2(sc, reg, x) \
145 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) & ~(x))
146 1.1 ichiro
147 1.1 ichiro static const struct url_type {
148 1.1 ichiro struct usb_devno url_dev;
149 1.1 ichiro u_int16_t url_flags;
150 1.1 ichiro #define URL_EXT_PHY 0x0001
151 1.1 ichiro } url_devs [] = {
152 1.1 ichiro /* MELCO LUA-KTX */
153 1.1 ichiro {{ USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAKTX }, 0},
154 1.10 mycroft /* Realtek RTL8150L Generic (GREEN HOUSE USBKR100) */
155 1.11 augustss {{ USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8150L}, 0},
156 1.11 augustss /* Longshine LCS-8138TX */
157 1.11 augustss {{ USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_LCS8138TX}, 0},
158 1.11 augustss /* Micronet SP128AR */
159 1.11 augustss {{ USB_VENDOR_MICRONET, USB_PRODUCT_MICRONET_SP128AR}, 0},
160 1.13 itojun /* OQO model 01 */
161 1.13 itojun {{ USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01}, 0},
162 1.1 ichiro };
163 1.17 christos #define url_lookup(v, p) ((const struct url_type *)usb_lookup(url_devs, v, p))
164 1.1 ichiro
165 1.24.10.2 itohy char zeros[URL_MIN_FRAME_LEN]; /* XXX */
166 1.1 ichiro
167 1.1 ichiro /* Probe */
168 1.1 ichiro USB_MATCH(url)
169 1.1 ichiro {
170 1.1 ichiro USB_MATCH_START(url, uaa);
171 1.1 ichiro
172 1.24.10.4 itohy #ifndef USB_USE_IFATTACH
173 1.1 ichiro if (uaa->iface != NULL)
174 1.1 ichiro return (UMATCH_NONE);
175 1.24.10.4 itohy #endif /* USB_USE_IFATTACH */
176 1.1 ichiro
177 1.1 ichiro return (url_lookup(uaa->vendor, uaa->product) != NULL ?
178 1.1 ichiro UMATCH_VENDOR_PRODUCT : UMATCH_NONE);
179 1.1 ichiro }
180 1.1 ichiro /* Attach */
181 1.1 ichiro USB_ATTACH(url)
182 1.1 ichiro {
183 1.1 ichiro USB_ATTACH_START(url, sc, uaa);
184 1.1 ichiro usbd_device_handle dev = uaa->device;
185 1.1 ichiro usbd_interface_handle iface;
186 1.1 ichiro usbd_status err;
187 1.1 ichiro usb_interface_descriptor_t *id;
188 1.1 ichiro usb_endpoint_descriptor_t *ed;
189 1.16 augustss char *devinfop;
190 1.1 ichiro char *devname = USBDEVNAME(sc->sc_dev);
191 1.1 ichiro struct ifnet *ifp;
192 1.1 ichiro struct mii_data *mii;
193 1.1 ichiro u_char eaddr[ETHER_ADDR_LEN];
194 1.1 ichiro int i, s;
195 1.1 ichiro
196 1.16 augustss devinfop = usbd_devinfo_alloc(dev, 0);
197 1.1 ichiro USB_ATTACH_SETUP;
198 1.16 augustss printf("%s: %s\n", devname, devinfop);
199 1.16 augustss usbd_devinfo_free(devinfop);
200 1.1 ichiro
201 1.1 ichiro /* Move the device into the configured state. */
202 1.1 ichiro err = usbd_set_config_no(dev, URL_CONFIG_NO, 1);
203 1.1 ichiro if (err) {
204 1.1 ichiro printf("%s: setting config no failed\n", devname);
205 1.1 ichiro goto bad;
206 1.1 ichiro }
207 1.1 ichiro
208 1.1 ichiro usb_init_task(&sc->sc_tick_task, url_tick_task, sc);
209 1.1 ichiro lockinit(&sc->sc_mii_lock, PZERO, "urlmii", 0, 0);
210 1.1 ichiro usb_init_task(&sc->sc_stop_task, (void (*)(void *)) url_stop_task, sc);
211 1.1 ichiro
212 1.1 ichiro /* get control interface */
213 1.1 ichiro err = usbd_device2interface_handle(dev, URL_IFACE_INDEX, &iface);
214 1.1 ichiro if (err) {
215 1.1 ichiro printf("%s: failed to get interface, err=%s\n", devname,
216 1.1 ichiro usbd_errstr(err));
217 1.1 ichiro goto bad;
218 1.1 ichiro }
219 1.1 ichiro
220 1.1 ichiro sc->sc_udev = dev;
221 1.1 ichiro sc->sc_ctl_iface = iface;
222 1.1 ichiro sc->sc_flags = url_lookup(uaa->vendor, uaa->product)->url_flags;
223 1.1 ichiro
224 1.1 ichiro /* get interface descriptor */
225 1.1 ichiro id = usbd_get_interface_descriptor(sc->sc_ctl_iface);
226 1.1 ichiro
227 1.1 ichiro /* find endpoints */
228 1.1 ichiro sc->sc_bulkin_no = sc->sc_bulkout_no = sc->sc_intrin_no = -1;
229 1.1 ichiro for (i = 0; i < id->bNumEndpoints; i++) {
230 1.1 ichiro ed = usbd_interface2endpoint_descriptor(sc->sc_ctl_iface, i);
231 1.1 ichiro if (ed == NULL) {
232 1.1 ichiro printf("%s: couldn't get endpoint %d\n", devname, i);
233 1.1 ichiro goto bad;
234 1.1 ichiro }
235 1.1 ichiro if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
236 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
237 1.1 ichiro sc->sc_bulkin_no = ed->bEndpointAddress; /* RX */
238 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
239 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)
240 1.1 ichiro sc->sc_bulkout_no = ed->bEndpointAddress; /* TX */
241 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_INTERRUPT &&
242 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
243 1.1 ichiro sc->sc_intrin_no = ed->bEndpointAddress; /* Status */
244 1.1 ichiro }
245 1.1 ichiro
246 1.1 ichiro if (sc->sc_bulkin_no == -1 || sc->sc_bulkout_no == -1 ||
247 1.1 ichiro sc->sc_intrin_no == -1) {
248 1.1 ichiro printf("%s: missing endpoint\n", devname);
249 1.1 ichiro goto bad;
250 1.1 ichiro }
251 1.1 ichiro
252 1.1 ichiro s = splnet();
253 1.1 ichiro
254 1.1 ichiro /* reset the adapter */
255 1.1 ichiro url_reset(sc);
256 1.1 ichiro
257 1.1 ichiro /* Get Ethernet Address */
258 1.1 ichiro err = url_mem(sc, URL_CMD_READMEM, URL_IDR0, (void *)eaddr,
259 1.1 ichiro ETHER_ADDR_LEN);
260 1.1 ichiro if (err) {
261 1.3 augustss printf("%s: read MAC address failed\n", devname);
262 1.1 ichiro splx(s);
263 1.1 ichiro goto bad;
264 1.1 ichiro }
265 1.1 ichiro
266 1.1 ichiro /* Print Ethernet Address */
267 1.1 ichiro printf("%s: Ethernet address %s\n", devname, ether_sprintf(eaddr));
268 1.1 ichiro
269 1.19 wiz /* initialize interface information */
270 1.1 ichiro ifp = GET_IFP(sc);
271 1.1 ichiro ifp->if_softc = sc;
272 1.3 augustss ifp->if_mtu = ETHERMTU;
273 1.1 ichiro strncpy(ifp->if_xname, devname, IFNAMSIZ);
274 1.1 ichiro ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
275 1.1 ichiro ifp->if_start = url_start;
276 1.1 ichiro ifp->if_ioctl = url_ioctl;
277 1.1 ichiro ifp->if_watchdog = url_watchdog;
278 1.1 ichiro ifp->if_init = url_init;
279 1.1 ichiro ifp->if_stop = url_stop;
280 1.1 ichiro
281 1.1 ichiro IFQ_SET_READY(&ifp->if_snd);
282 1.1 ichiro
283 1.1 ichiro /*
284 1.1 ichiro * Do ifmedia setup.
285 1.1 ichiro */
286 1.1 ichiro mii = &sc->sc_mii;
287 1.1 ichiro mii->mii_ifp = ifp;
288 1.1 ichiro mii->mii_readreg = url_int_miibus_readreg;
289 1.1 ichiro mii->mii_writereg = url_int_miibus_writereg;
290 1.1 ichiro #if 0
291 1.1 ichiro if (sc->sc_flags & URL_EXT_PHY) {
292 1.1 ichiro mii->mii_readreg = url_ext_miibus_readreg;
293 1.1 ichiro mii->mii_writereg = url_ext_miibus_writereg;
294 1.1 ichiro }
295 1.1 ichiro #endif
296 1.1 ichiro mii->mii_statchg = url_miibus_statchg;
297 1.1 ichiro mii->mii_flags = MIIF_AUTOTSLEEP;
298 1.1 ichiro ifmedia_init(&mii->mii_media, 0,
299 1.1 ichiro url_ifmedia_change, url_ifmedia_status);
300 1.1 ichiro mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
301 1.1 ichiro if (LIST_FIRST(&mii->mii_phys) == NULL) {
302 1.1 ichiro ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
303 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
304 1.1 ichiro } else
305 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
306 1.1 ichiro
307 1.1 ichiro /* attach the interface */
308 1.1 ichiro if_attach(ifp);
309 1.1 ichiro Ether_ifattach(ifp, eaddr);
310 1.1 ichiro
311 1.1 ichiro #if NRND > 0
312 1.1 ichiro rnd_attach_source(&sc->rnd_source, devname, RND_TYPE_NET, 0);
313 1.1 ichiro #endif
314 1.1 ichiro
315 1.1 ichiro usb_callout_init(sc->sc_stat_ch);
316 1.1 ichiro sc->sc_attached = 1;
317 1.1 ichiro splx(s);
318 1.1 ichiro
319 1.1 ichiro usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, dev, USBDEV(sc->sc_dev));
320 1.1 ichiro
321 1.1 ichiro USB_ATTACH_SUCCESS_RETURN;
322 1.1 ichiro
323 1.1 ichiro bad:
324 1.1 ichiro sc->sc_dying = 1;
325 1.1 ichiro USB_ATTACH_ERROR_RETURN;
326 1.1 ichiro }
327 1.1 ichiro
328 1.1 ichiro /* detach */
329 1.1 ichiro USB_DETACH(url)
330 1.1 ichiro {
331 1.1 ichiro USB_DETACH_START(url, sc);
332 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
333 1.1 ichiro int s;
334 1.1 ichiro
335 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
336 1.1 ichiro
337 1.1 ichiro /* Detached before attached finished */
338 1.1 ichiro if (!sc->sc_attached)
339 1.1 ichiro return (0);
340 1.1 ichiro
341 1.1 ichiro usb_uncallout(sc->sc_stat_ch, url_tick, sc);
342 1.1 ichiro
343 1.1 ichiro /* Remove any pending tasks */
344 1.1 ichiro usb_rem_task(sc->sc_udev, &sc->sc_tick_task);
345 1.1 ichiro usb_rem_task(sc->sc_udev, &sc->sc_stop_task);
346 1.1 ichiro
347 1.1 ichiro s = splusb();
348 1.1 ichiro
349 1.1 ichiro if (--sc->sc_refcnt >= 0) {
350 1.1 ichiro /* Wait for processes to go away */
351 1.1 ichiro usb_detach_wait(USBDEV(sc->sc_dev));
352 1.1 ichiro }
353 1.1 ichiro
354 1.1 ichiro if (ifp->if_flags & IFF_RUNNING)
355 1.24.10.2 itohy url_stop(ifp, 1);
356 1.1 ichiro
357 1.1 ichiro #if NRND > 0
358 1.1 ichiro rnd_detach_source(&sc->rnd_source);
359 1.1 ichiro #endif
360 1.1 ichiro mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
361 1.1 ichiro ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
362 1.1 ichiro ether_ifdetach(ifp);
363 1.1 ichiro if_detach(ifp);
364 1.1 ichiro
365 1.1 ichiro #ifdef DIAGNOSTIC
366 1.1 ichiro if (sc->sc_pipe_tx != NULL)
367 1.1 ichiro printf("%s: detach has active tx endpoint.\n",
368 1.1 ichiro USBDEVNAME(sc->sc_dev));
369 1.1 ichiro if (sc->sc_pipe_rx != NULL)
370 1.1 ichiro printf("%s: detach has active rx endpoint.\n",
371 1.1 ichiro USBDEVNAME(sc->sc_dev));
372 1.1 ichiro if (sc->sc_pipe_intr != NULL)
373 1.1 ichiro printf("%s: detach has active intr endpoint.\n",
374 1.1 ichiro USBDEVNAME(sc->sc_dev));
375 1.1 ichiro #endif
376 1.1 ichiro
377 1.1 ichiro sc->sc_attached = 0;
378 1.1 ichiro
379 1.1 ichiro splx(s);
380 1.1 ichiro
381 1.1 ichiro usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev,
382 1.1 ichiro USBDEV(sc->sc_dev));
383 1.1 ichiro
384 1.1 ichiro return (0);
385 1.1 ichiro }
386 1.1 ichiro
387 1.1 ichiro /* read/write memory */
388 1.1 ichiro Static int
389 1.1 ichiro url_mem(struct url_softc *sc, int cmd, int offset, void *buf, int len)
390 1.1 ichiro {
391 1.1 ichiro usb_device_request_t req;
392 1.1 ichiro usbd_status err;
393 1.1 ichiro
394 1.1 ichiro if (sc == NULL)
395 1.1 ichiro return (0);
396 1.1 ichiro
397 1.1 ichiro DPRINTFN(0x200,
398 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
399 1.1 ichiro
400 1.1 ichiro if (sc->sc_dying)
401 1.1 ichiro return (0);
402 1.1 ichiro
403 1.1 ichiro if (cmd == URL_CMD_READMEM)
404 1.1 ichiro req.bmRequestType = UT_READ_VENDOR_DEVICE;
405 1.1 ichiro else
406 1.1 ichiro req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
407 1.1 ichiro req.bRequest = URL_REQ_MEM;
408 1.1 ichiro USETW(req.wValue, offset);
409 1.1 ichiro USETW(req.wIndex, 0x0000);
410 1.1 ichiro USETW(req.wLength, len);
411 1.1 ichiro
412 1.1 ichiro sc->sc_refcnt++;
413 1.1 ichiro err = usbd_do_request(sc->sc_udev, &req, buf);
414 1.1 ichiro if (--sc->sc_refcnt < 0)
415 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
416 1.1 ichiro if (err) {
417 1.1 ichiro DPRINTF(("%s: url_mem(): %s failed. off=%04x, err=%d\n",
418 1.1 ichiro USBDEVNAME(sc->sc_dev),
419 1.1 ichiro cmd == URL_CMD_READMEM ? "read" : "write",
420 1.1 ichiro offset, err));
421 1.5 augustss }
422 1.1 ichiro
423 1.1 ichiro return (err);
424 1.1 ichiro }
425 1.1 ichiro
426 1.1 ichiro /* read 1byte from register */
427 1.1 ichiro Static int
428 1.1 ichiro url_csr_read_1(struct url_softc *sc, int reg)
429 1.1 ichiro {
430 1.1 ichiro u_int8_t val = 0;
431 1.1 ichiro
432 1.1 ichiro DPRINTFN(0x100,
433 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
434 1.1 ichiro
435 1.1 ichiro if (sc->sc_dying)
436 1.1 ichiro return (0);
437 1.5 augustss
438 1.1 ichiro return (url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val);
439 1.1 ichiro }
440 1.1 ichiro
441 1.1 ichiro /* read 2bytes from register */
442 1.1 ichiro Static int
443 1.1 ichiro url_csr_read_2(struct url_softc *sc, int reg)
444 1.1 ichiro {
445 1.1 ichiro uWord val;
446 1.1 ichiro
447 1.1 ichiro DPRINTFN(0x100,
448 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
449 1.1 ichiro
450 1.1 ichiro if (sc->sc_dying)
451 1.1 ichiro return (0);
452 1.5 augustss
453 1.1 ichiro USETW(val, 0);
454 1.1 ichiro return (url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val));
455 1.1 ichiro }
456 1.1 ichiro
457 1.1 ichiro /* write 1byte to register */
458 1.1 ichiro Static int
459 1.1 ichiro url_csr_write_1(struct url_softc *sc, int reg, int aval)
460 1.1 ichiro {
461 1.1 ichiro u_int8_t val = aval;
462 1.1 ichiro
463 1.1 ichiro DPRINTFN(0x100,
464 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
465 1.1 ichiro
466 1.1 ichiro if (sc->sc_dying)
467 1.1 ichiro return (0);
468 1.5 augustss
469 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0);
470 1.1 ichiro }
471 1.1 ichiro
472 1.1 ichiro /* write 2bytes to register */
473 1.1 ichiro Static int
474 1.1 ichiro url_csr_write_2(struct url_softc *sc, int reg, int aval)
475 1.1 ichiro {
476 1.1 ichiro uWord val;
477 1.1 ichiro
478 1.1 ichiro DPRINTFN(0x100,
479 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
480 1.1 ichiro
481 1.1 ichiro USETW(val, aval);
482 1.1 ichiro
483 1.1 ichiro if (sc->sc_dying)
484 1.1 ichiro return (0);
485 1.5 augustss
486 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0);
487 1.1 ichiro }
488 1.1 ichiro
489 1.1 ichiro /* write 4bytes to register */
490 1.1 ichiro Static int
491 1.1 ichiro url_csr_write_4(struct url_softc *sc, int reg, int aval)
492 1.1 ichiro {
493 1.1 ichiro uDWord val;
494 1.1 ichiro
495 1.1 ichiro DPRINTFN(0x100,
496 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
497 1.1 ichiro
498 1.1 ichiro USETDW(val, aval);
499 1.1 ichiro
500 1.1 ichiro if (sc->sc_dying)
501 1.1 ichiro return (0);
502 1.5 augustss
503 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0);
504 1.1 ichiro }
505 1.1 ichiro
506 1.1 ichiro Static int
507 1.1 ichiro url_init(struct ifnet *ifp)
508 1.1 ichiro {
509 1.1 ichiro struct url_softc *sc = ifp->if_softc;
510 1.1 ichiro struct mii_data *mii = GET_MII(sc);
511 1.1 ichiro u_char *eaddr;
512 1.1 ichiro int i, s;
513 1.24.10.2 itohy struct ue_chain *c;
514 1.1 ichiro
515 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
516 1.5 augustss
517 1.1 ichiro if (sc->sc_dying)
518 1.1 ichiro return (EIO);
519 1.1 ichiro
520 1.1 ichiro s = splnet();
521 1.1 ichiro
522 1.1 ichiro /* Cancel pending I/O and free all TX/RX buffers */
523 1.1 ichiro url_stop(ifp, 1);
524 1.1 ichiro
525 1.1 ichiro eaddr = LLADDR(ifp->if_sadl);
526 1.1 ichiro for (i = 0; i < ETHER_ADDR_LEN; i++)
527 1.1 ichiro url_csr_write_1(sc, URL_IDR0 + i, eaddr[i]);
528 1.1 ichiro
529 1.1 ichiro /* Init transmission control register */
530 1.1 ichiro URL_CLRBIT(sc, URL_TCR,
531 1.1 ichiro URL_TCR_TXRR1 | URL_TCR_TXRR0 |
532 1.1 ichiro URL_TCR_IFG1 | URL_TCR_IFG0 |
533 1.1 ichiro URL_TCR_NOCRC);
534 1.1 ichiro
535 1.1 ichiro /* Init receive control register */
536 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_TAIL | URL_RCR_AD);
537 1.1 ichiro if (ifp->if_flags & IFF_BROADCAST)
538 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AB);
539 1.1 ichiro else
540 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AB);
541 1.1 ichiro
542 1.1 ichiro /* If we want promiscuous mode, accept all physical frames. */
543 1.1 ichiro if (ifp->if_flags & IFF_PROMISC)
544 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
545 1.1 ichiro else
546 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
547 1.1 ichiro
548 1.24.10.2 itohy if (sc->sc_pipe_tx == NULL || sc->sc_pipe_rx == NULL) {
549 1.24.10.2 itohy if (url_openpipes(sc)) {
550 1.24.10.2 itohy splx(s);
551 1.24.10.2 itohy return (EIO);
552 1.24.10.2 itohy }
553 1.24.10.2 itohy }
554 1.5 augustss
555 1.1 ichiro /* Initialize transmit ring */
556 1.24.10.2 itohy if (usb_ether_tx_list_init(USBDEV(sc->sc_dev),
557 1.24.10.2 itohy sc->sc_cdata.url_tx_chain, URL_TX_LIST_CNT,
558 1.24.10.2 itohy sc->sc_udev, sc->sc_pipe_tx, NULL)) {
559 1.1 ichiro printf("%s: tx list init failed\n", USBDEVNAME(sc->sc_dev));
560 1.1 ichiro splx(s);
561 1.1 ichiro return (EIO);
562 1.1 ichiro }
563 1.1 ichiro
564 1.1 ichiro /* Initialize receive ring */
565 1.24.10.2 itohy if (usb_ether_rx_list_init(USBDEV(sc->sc_dev),
566 1.24.10.2 itohy sc->sc_cdata.url_rx_chain, URL_RX_LIST_CNT,
567 1.24.10.2 itohy sc->sc_udev, sc->sc_pipe_rx)) {
568 1.1 ichiro printf("%s: rx list init failed\n", USBDEVNAME(sc->sc_dev));
569 1.1 ichiro splx(s);
570 1.1 ichiro return (EIO);
571 1.1 ichiro }
572 1.1 ichiro
573 1.1 ichiro /* Load the multicast filter */
574 1.1 ichiro url_setmulti(sc);
575 1.1 ichiro
576 1.1 ichiro /* Enable RX and TX */
577 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_TE | URL_CR_RE);
578 1.1 ichiro
579 1.1 ichiro mii_mediachg(mii);
580 1.1 ichiro
581 1.24.10.2 itohy /* Start up the receive pipe. */
582 1.24.10.2 itohy for (i = 0; i < URL_RX_LIST_CNT; i++) {
583 1.24.10.2 itohy c = &sc->sc_cdata.url_rx_chain[i];
584 1.24.10.2 itohy (void)usbd_map_buffer_mbuf(c->ue_xfer, c->ue_mbuf);
585 1.24.10.2 itohy usbd_setup_xfer(c->ue_xfer, sc->sc_pipe_rx,
586 1.24.10.2 itohy c, NULL /* XXX buf */, URL_BUFSZ,
587 1.24.10.2 itohy USBD_SHORT_XFER_OK | USBD_NO_COPY,
588 1.24.10.2 itohy USBD_NO_TIMEOUT, url_rxeof);
589 1.24.10.2 itohy (void)usbd_transfer(c->ue_xfer);
590 1.24.10.2 itohy DPRINTF(("%s: %s: start read\n", USBDEVNAME(sc->sc_dev),
591 1.24.10.2 itohy __func__));
592 1.1 ichiro }
593 1.1 ichiro
594 1.1 ichiro ifp->if_flags |= IFF_RUNNING;
595 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
596 1.1 ichiro
597 1.1 ichiro splx(s);
598 1.1 ichiro
599 1.1 ichiro usb_callout(sc->sc_stat_ch, hz, url_tick, sc);
600 1.1 ichiro
601 1.1 ichiro return (0);
602 1.1 ichiro }
603 1.1 ichiro
604 1.1 ichiro Static void
605 1.1 ichiro url_reset(struct url_softc *sc)
606 1.1 ichiro {
607 1.1 ichiro int i;
608 1.5 augustss
609 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
610 1.1 ichiro
611 1.1 ichiro if (sc->sc_dying)
612 1.1 ichiro return;
613 1.1 ichiro
614 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_SOFT_RST);
615 1.1 ichiro
616 1.1 ichiro for (i = 0; i < URL_TX_TIMEOUT; i++) {
617 1.1 ichiro if (!(url_csr_read_1(sc, URL_CR) & URL_CR_SOFT_RST))
618 1.1 ichiro break;
619 1.1 ichiro delay(10); /* XXX */
620 1.1 ichiro }
621 1.1 ichiro
622 1.1 ichiro delay(10000); /* XXX */
623 1.1 ichiro }
624 1.1 ichiro
625 1.1 ichiro int
626 1.1 ichiro url_activate(device_ptr_t self, enum devact act)
627 1.1 ichiro {
628 1.1 ichiro struct url_softc *sc = (struct url_softc *)self;
629 1.1 ichiro
630 1.1 ichiro DPRINTF(("%s: %s: enter, act=%d\n", USBDEVNAME(sc->sc_dev),
631 1.4 augustss __func__, act));
632 1.1 ichiro
633 1.1 ichiro switch (act) {
634 1.1 ichiro case DVACT_ACTIVATE:
635 1.1 ichiro return (EOPNOTSUPP);
636 1.1 ichiro break;
637 1.1 ichiro
638 1.1 ichiro case DVACT_DEACTIVATE:
639 1.1 ichiro if_deactivate(&sc->sc_ec.ec_if);
640 1.1 ichiro sc->sc_dying = 1;
641 1.1 ichiro break;
642 1.1 ichiro }
643 1.1 ichiro
644 1.1 ichiro return (0);
645 1.1 ichiro }
646 1.1 ichiro
647 1.1 ichiro #define url_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
648 1.1 ichiro
649 1.1 ichiro
650 1.1 ichiro Static void
651 1.1 ichiro url_setmulti(struct url_softc *sc)
652 1.1 ichiro {
653 1.1 ichiro struct ifnet *ifp;
654 1.1 ichiro struct ether_multi *enm;
655 1.1 ichiro struct ether_multistep step;
656 1.1 ichiro u_int32_t hashes[2] = { 0, 0 };
657 1.1 ichiro int h = 0;
658 1.1 ichiro int mcnt = 0;
659 1.1 ichiro
660 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
661 1.1 ichiro
662 1.1 ichiro if (sc->sc_dying)
663 1.1 ichiro return;
664 1.1 ichiro
665 1.1 ichiro ifp = GET_IFP(sc);
666 1.1 ichiro
667 1.1 ichiro if (ifp->if_flags & IFF_PROMISC) {
668 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
669 1.1 ichiro return;
670 1.1 ichiro } else if (ifp->if_flags & IFF_ALLMULTI) {
671 1.1 ichiro allmulti:
672 1.1 ichiro ifp->if_flags |= IFF_ALLMULTI;
673 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM);
674 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAP);
675 1.1 ichiro return;
676 1.1 ichiro }
677 1.1 ichiro
678 1.1 ichiro /* first, zot all the existing hash bits */
679 1.1 ichiro url_csr_write_4(sc, URL_MAR0, 0);
680 1.1 ichiro url_csr_write_4(sc, URL_MAR4, 0);
681 1.1 ichiro
682 1.1 ichiro /* now program new ones */
683 1.1 ichiro ETHER_FIRST_MULTI(step, &sc->sc_ec, enm);
684 1.1 ichiro while (enm != NULL) {
685 1.1 ichiro if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
686 1.1 ichiro ETHER_ADDR_LEN) != 0)
687 1.1 ichiro goto allmulti;
688 1.1 ichiro
689 1.1 ichiro h = url_calchash(enm->enm_addrlo);
690 1.1 ichiro if (h < 32)
691 1.1 ichiro hashes[0] |= (1 << h);
692 1.1 ichiro else
693 1.1 ichiro hashes[1] |= (1 << (h -32));
694 1.1 ichiro mcnt++;
695 1.1 ichiro ETHER_NEXT_MULTI(step, enm);
696 1.1 ichiro }
697 1.1 ichiro
698 1.1 ichiro ifp->if_flags &= ~IFF_ALLMULTI;
699 1.1 ichiro
700 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
701 1.1 ichiro
702 1.1 ichiro if (mcnt){
703 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AM);
704 1.1 ichiro } else {
705 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AM);
706 1.1 ichiro }
707 1.1 ichiro url_csr_write_4(sc, URL_MAR0, hashes[0]);
708 1.1 ichiro url_csr_write_4(sc, URL_MAR4, hashes[1]);
709 1.1 ichiro }
710 1.1 ichiro
711 1.1 ichiro Static int
712 1.1 ichiro url_openpipes(struct url_softc *sc)
713 1.1 ichiro {
714 1.1 ichiro usbd_status err;
715 1.1 ichiro int error = 0;
716 1.1 ichiro
717 1.1 ichiro if (sc->sc_dying)
718 1.1 ichiro return (EIO);
719 1.5 augustss
720 1.1 ichiro sc->sc_refcnt++;
721 1.1 ichiro
722 1.1 ichiro /* Open RX pipe */
723 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkin_no,
724 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_rx);
725 1.1 ichiro if (err) {
726 1.1 ichiro printf("%s: open rx pipe failed: %s\n",
727 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
728 1.1 ichiro error = EIO;
729 1.1 ichiro goto done;
730 1.1 ichiro }
731 1.5 augustss
732 1.1 ichiro /* Open TX pipe */
733 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkout_no,
734 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_tx);
735 1.1 ichiro if (err) {
736 1.1 ichiro printf("%s: open tx pipe failed: %s\n",
737 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
738 1.1 ichiro error = EIO;
739 1.1 ichiro goto done;
740 1.1 ichiro }
741 1.1 ichiro
742 1.1 ichiro #if 0
743 1.1 ichiro /* XXX: interrupt endpoint is not yet supported */
744 1.1 ichiro /* Open Interrupt pipe */
745 1.1 ichiro err = usbd_open_pipe_intr(sc->sc_ctl_iface, sc->sc_intrin_no,
746 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_intr, sc,
747 1.1 ichiro &sc->sc_cdata.url_ibuf, URL_INTR_PKGLEN,
748 1.24 drochner url_intr, USBD_DEFAULT_INTERVAL);
749 1.1 ichiro if (err) {
750 1.1 ichiro printf("%s: open intr pipe failed: %s\n",
751 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
752 1.1 ichiro error = EIO;
753 1.1 ichiro goto done;
754 1.1 ichiro }
755 1.1 ichiro #endif
756 1.1 ichiro
757 1.1 ichiro done:
758 1.1 ichiro if (--sc->sc_refcnt < 0)
759 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
760 1.5 augustss
761 1.1 ichiro return (error);
762 1.1 ichiro }
763 1.1 ichiro
764 1.1 ichiro Static void
765 1.1 ichiro url_start(struct ifnet *ifp)
766 1.1 ichiro {
767 1.1 ichiro struct url_softc *sc = ifp->if_softc;
768 1.1 ichiro struct mbuf *m_head = NULL;
769 1.5 augustss
770 1.1 ichiro DPRINTF(("%s: %s: enter, link=%d\n", USBDEVNAME(sc->sc_dev),
771 1.4 augustss __func__, sc->sc_link));
772 1.1 ichiro
773 1.1 ichiro if (sc->sc_dying)
774 1.1 ichiro return;
775 1.1 ichiro
776 1.1 ichiro if (!sc->sc_link)
777 1.1 ichiro return;
778 1.1 ichiro
779 1.1 ichiro if (ifp->if_flags & IFF_OACTIVE)
780 1.1 ichiro return;
781 1.1 ichiro
782 1.1 ichiro IFQ_POLL(&ifp->if_snd, m_head);
783 1.1 ichiro if (m_head == NULL)
784 1.1 ichiro return;
785 1.1 ichiro
786 1.1 ichiro IFQ_DEQUEUE(&ifp->if_snd, m_head);
787 1.1 ichiro
788 1.1 ichiro #if NBPFILTER > 0
789 1.1 ichiro if (ifp->if_bpf)
790 1.1 ichiro bpf_mtap(ifp->if_bpf, m_head);
791 1.1 ichiro #endif
792 1.1 ichiro
793 1.24.10.2 itohy if (url_send(sc, m_head, 0)) {
794 1.24.10.2 itohy ifp->if_flags |= IFF_OACTIVE;
795 1.24.10.2 itohy return;
796 1.24.10.2 itohy }
797 1.24.10.2 itohy
798 1.1 ichiro ifp->if_flags |= IFF_OACTIVE;
799 1.1 ichiro
800 1.1 ichiro /* Set a timeout in case the chip goes out to lunch. */
801 1.1 ichiro ifp->if_timer = 5;
802 1.1 ichiro }
803 1.1 ichiro
804 1.1 ichiro Static int
805 1.1 ichiro url_send(struct url_softc *sc, struct mbuf *m, int idx)
806 1.1 ichiro {
807 1.1 ichiro int total_len;
808 1.24.10.2 itohy struct ue_chain *c;
809 1.1 ichiro usbd_status err;
810 1.24.10.2 itohy int ret;
811 1.1 ichiro
812 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),__func__));
813 1.1 ichiro
814 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[idx];
815 1.1 ichiro
816 1.1 ichiro total_len = m->m_pkthdr.len;
817 1.1 ichiro
818 1.7 bouyer if (total_len < URL_MIN_FRAME_LEN) {
819 1.24.10.2 itohy /* expand mbuf chain with zeros */
820 1.24.10.2 itohy m_copyback(m, total_len, URL_MIN_FRAME_LEN - total_len,
821 1.24.10.2 itohy zeros);
822 1.1 ichiro total_len = URL_MIN_FRAME_LEN;
823 1.24.10.2 itohy if (m->m_pkthdr.len != total_len) {
824 1.24.10.2 itohy m_freem(m);
825 1.24.10.2 itohy return (ENOBUFS);
826 1.24.10.2 itohy }
827 1.7 bouyer }
828 1.24.10.2 itohy
829 1.24.10.2 itohy ret = usb_ether_map_tx_buffer_mbuf(c, m);
830 1.24.10.2 itohy if (ret) {
831 1.24.10.2 itohy m_freem(m);
832 1.24.10.2 itohy return (ret);
833 1.24.10.2 itohy }
834 1.24.10.2 itohy
835 1.24.10.2 itohy usbd_setup_xfer(c->ue_xfer, sc->sc_pipe_tx, c, NULL /* XXX buf */, total_len,
836 1.1 ichiro USBD_FORCE_SHORT_XFER | USBD_NO_COPY,
837 1.1 ichiro URL_TX_TIMEOUT, url_txeof);
838 1.1 ichiro
839 1.1 ichiro /* Transmit */
840 1.1 ichiro sc->sc_refcnt++;
841 1.24.10.2 itohy err = usbd_transfer(c->ue_xfer);
842 1.1 ichiro if (--sc->sc_refcnt < 0)
843 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
844 1.1 ichiro if (err != USBD_IN_PROGRESS) {
845 1.24.10.2 itohy c->ue_mbuf = NULL;
846 1.24.10.2 itohy m_freem(m);
847 1.1 ichiro printf("%s: url_send error=%s\n", USBDEVNAME(sc->sc_dev),
848 1.1 ichiro usbd_errstr(err));
849 1.1 ichiro /* Stop the interface */
850 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_stop_task,
851 1.22 joerg USB_TASKQ_DRIVER);
852 1.1 ichiro return (EIO);
853 1.1 ichiro }
854 1.1 ichiro
855 1.1 ichiro DPRINTF(("%s: %s: send %d bytes\n", USBDEVNAME(sc->sc_dev),
856 1.4 augustss __func__, total_len));
857 1.1 ichiro
858 1.1 ichiro sc->sc_cdata.url_tx_cnt++;
859 1.1 ichiro
860 1.1 ichiro return (0);
861 1.1 ichiro }
862 1.1 ichiro
863 1.1 ichiro Static void
864 1.23 christos url_txeof(usbd_xfer_handle xfer, usbd_private_handle priv,
865 1.21 christos usbd_status status)
866 1.1 ichiro {
867 1.24.10.2 itohy struct ue_chain *c = priv;
868 1.24.10.2 itohy struct url_softc *sc = (void *)c->ue_dev;
869 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
870 1.1 ichiro int s;
871 1.1 ichiro
872 1.1 ichiro if (sc->sc_dying)
873 1.1 ichiro return;
874 1.1 ichiro
875 1.1 ichiro s = splnet();
876 1.1 ichiro
877 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
878 1.1 ichiro
879 1.1 ichiro ifp->if_timer = 0;
880 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
881 1.1 ichiro
882 1.24.10.2 itohy usbd_unmap_buffer(xfer);
883 1.24.10.2 itohy
884 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
885 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
886 1.1 ichiro splx(s);
887 1.1 ichiro return;
888 1.1 ichiro }
889 1.1 ichiro ifp->if_oerrors++;
890 1.1 ichiro printf("%s: usb error on tx: %s\n", USBDEVNAME(sc->sc_dev),
891 1.1 ichiro usbd_errstr(status));
892 1.1 ichiro if (status == USBD_STALLED) {
893 1.1 ichiro sc->sc_refcnt++;
894 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_tx);
895 1.1 ichiro if (--sc->sc_refcnt < 0)
896 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
897 1.1 ichiro }
898 1.1 ichiro splx(s);
899 1.1 ichiro return;
900 1.1 ichiro }
901 1.1 ichiro
902 1.1 ichiro ifp->if_opackets++;
903 1.1 ichiro
904 1.24.10.2 itohy m_freem(c->ue_mbuf);
905 1.24.10.2 itohy c->ue_mbuf = NULL;
906 1.1 ichiro
907 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
908 1.1 ichiro url_start(ifp);
909 1.1 ichiro
910 1.1 ichiro splx(s);
911 1.1 ichiro }
912 1.1 ichiro
913 1.1 ichiro Static void
914 1.1 ichiro url_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status)
915 1.1 ichiro {
916 1.24.10.2 itohy struct ue_chain *c = priv;
917 1.24.10.2 itohy struct url_softc *sc = (void *)c->ue_dev;
918 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
919 1.1 ichiro struct mbuf *m;
920 1.1 ichiro u_int32_t total_len;
921 1.1 ichiro url_rxhdr_t rxhdr;
922 1.1 ichiro int s;
923 1.1 ichiro
924 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),__func__));
925 1.1 ichiro
926 1.1 ichiro if (sc->sc_dying)
927 1.1 ichiro return;
928 1.1 ichiro
929 1.24.10.2 itohy usbd_unmap_buffer(xfer);
930 1.24.10.2 itohy
931 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
932 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
933 1.1 ichiro return;
934 1.1 ichiro sc->sc_rx_errs++;
935 1.1 ichiro if (usbd_ratecheck(&sc->sc_rx_notice)) {
936 1.1 ichiro printf("%s: %u usb errors on rx: %s\n",
937 1.1 ichiro USBDEVNAME(sc->sc_dev), sc->sc_rx_errs,
938 1.1 ichiro usbd_errstr(status));
939 1.1 ichiro sc->sc_rx_errs = 0;
940 1.1 ichiro }
941 1.1 ichiro if (status == USBD_STALLED) {
942 1.1 ichiro sc->sc_refcnt++;
943 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_rx);
944 1.1 ichiro if (--sc->sc_refcnt < 0)
945 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
946 1.1 ichiro }
947 1.1 ichiro goto done;
948 1.1 ichiro }
949 1.1 ichiro
950 1.1 ichiro usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
951 1.1 ichiro
952 1.1 ichiro if (total_len <= ETHER_CRC_LEN) {
953 1.1 ichiro ifp->if_ierrors++;
954 1.1 ichiro goto done;
955 1.1 ichiro }
956 1.1 ichiro
957 1.24.10.2 itohy m = c->ue_mbuf;
958 1.24.10.2 itohy
959 1.24.10.2 itohy memcpy(&rxhdr, mtod(m, char *) + total_len - ETHER_CRC_LEN,
960 1.24.10.2 itohy sizeof(rxhdr));
961 1.1 ichiro
962 1.1 ichiro DPRINTF(("%s: RX Status: %dbytes%s%s%s%s packets\n",
963 1.1 ichiro USBDEVNAME(sc->sc_dev),
964 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_BYTEC_MASK,
965 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_VALID_MASK ? ", Valid" : "",
966 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_RUNTPKT_MASK ? ", Runt" : "",
967 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_PHYPKT_MASK ? ", Physical match" : "",
968 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_MCASTPKT_MASK ? ", Multicast" : ""));
969 1.1 ichiro
970 1.1 ichiro if ((UGETW(rxhdr) & URL_RXHDR_VALID_MASK) == 0) {
971 1.1 ichiro ifp->if_ierrors++;
972 1.1 ichiro goto done;
973 1.1 ichiro }
974 1.1 ichiro
975 1.24.10.2 itohy /*
976 1.24.10.2 itohy * Allocate new mbuf cluster for the next transfer.
977 1.24.10.2 itohy * If that failed, discard current packet and recycle the mbuf.
978 1.24.10.2 itohy */
979 1.24.10.2 itohy if ((c->ue_mbuf = usb_ether_newbuf(NULL)) == NULL) {
980 1.24.10.2 itohy printf("%s: no memory for rx list -- packet dropped!\n",
981 1.24.10.2 itohy USBDEVNAME(sc->sc_dev));
982 1.24.10.2 itohy ifp->if_ierrors++;
983 1.24.10.2 itohy c->ue_mbuf = usb_ether_newbuf(m);
984 1.24.10.2 itohy goto done;
985 1.24.10.2 itohy }
986 1.24.10.2 itohy
987 1.1 ichiro ifp->if_ipackets++;
988 1.1 ichiro total_len -= ETHER_CRC_LEN;
989 1.1 ichiro
990 1.1 ichiro m->m_pkthdr.len = m->m_len = total_len;
991 1.1 ichiro m->m_pkthdr.rcvif = ifp;
992 1.1 ichiro
993 1.1 ichiro s = splnet();
994 1.1 ichiro
995 1.1 ichiro #if NBPFILTER > 0
996 1.1 ichiro if (ifp->if_bpf)
997 1.1 ichiro BPF_MTAP(ifp, m);
998 1.1 ichiro #endif
999 1.1 ichiro
1000 1.1 ichiro DPRINTF(("%s: %s: deliver %d\n", USBDEVNAME(sc->sc_dev),
1001 1.4 augustss __func__, m->m_len));
1002 1.1 ichiro IF_INPUT(ifp, m);
1003 1.1 ichiro
1004 1.1 ichiro splx(s);
1005 1.1 ichiro
1006 1.1 ichiro done:
1007 1.1 ichiro /* Setup new transfer */
1008 1.24.10.2 itohy (void)usbd_map_buffer_mbuf(xfer, c->ue_mbuf);
1009 1.24.10.2 itohy usbd_setup_xfer(xfer, sc->sc_pipe_rx, c, NULL /* XXX buf */, URL_BUFSZ,
1010 1.1 ichiro USBD_SHORT_XFER_OK | USBD_NO_COPY,
1011 1.1 ichiro USBD_NO_TIMEOUT, url_rxeof);
1012 1.1 ichiro sc->sc_refcnt++;
1013 1.1 ichiro usbd_transfer(xfer);
1014 1.1 ichiro if (--sc->sc_refcnt < 0)
1015 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
1016 1.1 ichiro
1017 1.4 augustss DPRINTF(("%s: %s: start rx\n", USBDEVNAME(sc->sc_dev), __func__));
1018 1.1 ichiro }
1019 1.1 ichiro
1020 1.1 ichiro #if 0
1021 1.1 ichiro Static void url_intr()
1022 1.1 ichiro {
1023 1.1 ichiro }
1024 1.1 ichiro #endif
1025 1.1 ichiro
1026 1.1 ichiro Static int
1027 1.24.10.3 itohy url_ioctl(struct ifnet *ifp, u_long cmd, usb_ioctlarg_t data)
1028 1.1 ichiro {
1029 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1030 1.1 ichiro struct ifreq *ifr = (struct ifreq *)data;
1031 1.1 ichiro struct mii_data *mii;
1032 1.1 ichiro int s, error = 0;
1033 1.1 ichiro
1034 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1035 1.1 ichiro
1036 1.1 ichiro if (sc->sc_dying)
1037 1.1 ichiro return (EIO);
1038 1.1 ichiro
1039 1.1 ichiro s = splnet();
1040 1.1 ichiro
1041 1.1 ichiro switch (cmd) {
1042 1.1 ichiro case SIOCGIFMEDIA:
1043 1.1 ichiro case SIOCSIFMEDIA:
1044 1.1 ichiro mii = GET_MII(sc);
1045 1.1 ichiro error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1046 1.1 ichiro break;
1047 1.1 ichiro
1048 1.1 ichiro default:
1049 1.1 ichiro error = ether_ioctl(ifp, cmd, data);
1050 1.1 ichiro if (error == ENETRESET) {
1051 1.12 thorpej if (ifp->if_flags & IFF_RUNNING)
1052 1.12 thorpej url_setmulti(sc);
1053 1.1 ichiro error = 0;
1054 1.1 ichiro }
1055 1.1 ichiro break;
1056 1.1 ichiro }
1057 1.1 ichiro
1058 1.1 ichiro splx(s);
1059 1.1 ichiro
1060 1.1 ichiro return (error);
1061 1.1 ichiro }
1062 1.1 ichiro
1063 1.1 ichiro Static void
1064 1.1 ichiro url_watchdog(struct ifnet *ifp)
1065 1.1 ichiro {
1066 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1067 1.24.10.2 itohy struct ue_chain *c;
1068 1.1 ichiro usbd_status stat;
1069 1.1 ichiro int s;
1070 1.5 augustss
1071 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1072 1.1 ichiro
1073 1.1 ichiro ifp->if_oerrors++;
1074 1.1 ichiro printf("%s: watchdog timeout\n", USBDEVNAME(sc->sc_dev));
1075 1.1 ichiro
1076 1.1 ichiro s = splusb();
1077 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[0];
1078 1.24.10.2 itohy usbd_get_xfer_status(c->ue_xfer, NULL, NULL, NULL, &stat);
1079 1.24.10.2 itohy url_txeof(c->ue_xfer, c, stat);
1080 1.1 ichiro
1081 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1082 1.1 ichiro url_start(ifp);
1083 1.1 ichiro splx(s);
1084 1.1 ichiro }
1085 1.1 ichiro
1086 1.1 ichiro Static void
1087 1.1 ichiro url_stop_task(struct url_softc *sc)
1088 1.1 ichiro {
1089 1.1 ichiro url_stop(GET_IFP(sc), 1);
1090 1.1 ichiro }
1091 1.1 ichiro
1092 1.1 ichiro /* Stop the adapter and free any mbufs allocated to the RX and TX lists. */
1093 1.1 ichiro Static void
1094 1.23 christos url_stop(struct ifnet *ifp, int disable)
1095 1.1 ichiro {
1096 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1097 1.1 ichiro usbd_status err;
1098 1.5 augustss
1099 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1100 1.1 ichiro
1101 1.1 ichiro ifp->if_timer = 0;
1102 1.1 ichiro
1103 1.1 ichiro url_reset(sc);
1104 1.1 ichiro
1105 1.1 ichiro usb_uncallout(sc->sc_stat_ch, url_tick, sc);
1106 1.1 ichiro
1107 1.1 ichiro /* Stop transfers */
1108 1.1 ichiro /* RX endpoint */
1109 1.1 ichiro if (sc->sc_pipe_rx != NULL) {
1110 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_rx);
1111 1.1 ichiro if (err)
1112 1.1 ichiro printf("%s: abort rx pipe failed: %s\n",
1113 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1114 1.24.10.2 itohy }
1115 1.24.10.2 itohy
1116 1.24.10.2 itohy /* TX endpoint */
1117 1.24.10.2 itohy if (sc->sc_pipe_tx != NULL) {
1118 1.24.10.2 itohy err = usbd_abort_pipe(sc->sc_pipe_tx);
1119 1.24.10.2 itohy if (err)
1120 1.24.10.2 itohy printf("%s: abort tx pipe failed: %s\n",
1121 1.24.10.2 itohy USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1122 1.24.10.2 itohy }
1123 1.24.10.2 itohy
1124 1.24.10.2 itohy #if 0
1125 1.24.10.2 itohy /* XXX: Interrupt endpoint is not yet supported!! */
1126 1.24.10.2 itohy /* Interrupt endpoint */
1127 1.24.10.2 itohy if (sc->sc_pipe_intr != NULL) {
1128 1.24.10.2 itohy err = usbd_abort_pipe(sc->sc_pipe_intr);
1129 1.24.10.2 itohy if (err)
1130 1.24.10.2 itohy printf("%s: abort intr pipe failed: %s\n",
1131 1.24.10.2 itohy USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1132 1.24.10.2 itohy #endif
1133 1.24.10.2 itohy
1134 1.24.10.2 itohy /* Free RX/TX resources. */
1135 1.24.10.2 itohy usb_ether_rx_list_free(sc->sc_cdata.url_rx_chain, URL_RX_LIST_CNT);
1136 1.24.10.2 itohy usb_ether_tx_list_free(sc->sc_cdata.url_tx_chain, URL_TX_LIST_CNT);
1137 1.24.10.2 itohy
1138 1.24.10.2 itohy /* Close pipes. */
1139 1.24.10.2 itohy /* RX endpoint */
1140 1.24.10.2 itohy if (sc->sc_pipe_rx != NULL) {
1141 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_rx);
1142 1.1 ichiro if (err)
1143 1.1 ichiro printf("%s: close rx pipe failed: %s\n",
1144 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1145 1.1 ichiro sc->sc_pipe_rx = NULL;
1146 1.1 ichiro }
1147 1.1 ichiro
1148 1.1 ichiro /* TX endpoint */
1149 1.1 ichiro if (sc->sc_pipe_tx != NULL) {
1150 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_tx);
1151 1.1 ichiro if (err)
1152 1.1 ichiro printf("%s: close tx pipe failed: %s\n",
1153 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1154 1.1 ichiro sc->sc_pipe_tx = NULL;
1155 1.1 ichiro }
1156 1.1 ichiro
1157 1.1 ichiro #if 0
1158 1.1 ichiro /* XXX: Interrupt endpoint is not yet supported!! */
1159 1.1 ichiro /* Interrupt endpoint */
1160 1.1 ichiro if (sc->sc_pipe_intr != NULL) {
1161 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_intr);
1162 1.1 ichiro if (err)
1163 1.1 ichiro printf("%s: close intr pipe failed: %s\n",
1164 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1165 1.1 ichiro sc->sc_pipe_intr = NULL;
1166 1.1 ichiro }
1167 1.1 ichiro #endif
1168 1.1 ichiro
1169 1.1 ichiro sc->sc_link = 0;
1170 1.1 ichiro ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1171 1.1 ichiro }
1172 1.1 ichiro
1173 1.1 ichiro /* Set media options */
1174 1.1 ichiro Static int
1175 1.1 ichiro url_ifmedia_change(struct ifnet *ifp)
1176 1.1 ichiro {
1177 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1178 1.1 ichiro struct mii_data *mii = GET_MII(sc);
1179 1.1 ichiro
1180 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1181 1.1 ichiro
1182 1.1 ichiro if (sc->sc_dying)
1183 1.1 ichiro return (0);
1184 1.1 ichiro
1185 1.1 ichiro sc->sc_link = 0;
1186 1.1 ichiro if (mii->mii_instance) {
1187 1.1 ichiro struct mii_softc *miisc;
1188 1.1 ichiro for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1189 1.1 ichiro miisc = LIST_NEXT(miisc, mii_list))
1190 1.1 ichiro mii_phy_reset(miisc);
1191 1.1 ichiro }
1192 1.1 ichiro
1193 1.1 ichiro return (mii_mediachg(mii));
1194 1.1 ichiro }
1195 1.1 ichiro
1196 1.1 ichiro /* Report current media status. */
1197 1.1 ichiro Static void
1198 1.1 ichiro url_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1199 1.1 ichiro {
1200 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1201 1.1 ichiro struct mii_data *mii = GET_MII(sc);
1202 1.1 ichiro
1203 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1204 1.1 ichiro
1205 1.1 ichiro if (sc->sc_dying)
1206 1.1 ichiro return;
1207 1.1 ichiro
1208 1.1 ichiro if ((ifp->if_flags & IFF_RUNNING) == 0) {
1209 1.1 ichiro ifmr->ifm_active = IFM_ETHER | IFM_NONE;
1210 1.1 ichiro ifmr->ifm_status = 0;
1211 1.1 ichiro return;
1212 1.1 ichiro }
1213 1.1 ichiro
1214 1.1 ichiro mii_pollstat(mii);
1215 1.1 ichiro ifmr->ifm_active = mii->mii_media_active;
1216 1.1 ichiro ifmr->ifm_status = mii->mii_media_status;
1217 1.1 ichiro }
1218 1.1 ichiro
1219 1.1 ichiro Static void
1220 1.1 ichiro url_tick(void *xsc)
1221 1.1 ichiro {
1222 1.1 ichiro struct url_softc *sc = xsc;
1223 1.1 ichiro
1224 1.1 ichiro if (sc == NULL)
1225 1.1 ichiro return;
1226 1.1 ichiro
1227 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1228 1.4 augustss __func__));
1229 1.1 ichiro
1230 1.1 ichiro if (sc->sc_dying)
1231 1.1 ichiro return;
1232 1.1 ichiro
1233 1.1 ichiro /* Perform periodic stuff in process context */
1234 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_tick_task, USB_TASKQ_DRIVER);
1235 1.1 ichiro }
1236 1.1 ichiro
1237 1.1 ichiro Static void
1238 1.1 ichiro url_tick_task(void *xsc)
1239 1.1 ichiro {
1240 1.1 ichiro struct url_softc *sc = xsc;
1241 1.1 ichiro struct ifnet *ifp;
1242 1.1 ichiro struct mii_data *mii;
1243 1.1 ichiro int s;
1244 1.1 ichiro
1245 1.1 ichiro if (sc == NULL)
1246 1.1 ichiro return;
1247 1.1 ichiro
1248 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1249 1.4 augustss __func__));
1250 1.1 ichiro
1251 1.1 ichiro if (sc->sc_dying)
1252 1.1 ichiro return;
1253 1.1 ichiro
1254 1.1 ichiro ifp = GET_IFP(sc);
1255 1.1 ichiro mii = GET_MII(sc);
1256 1.1 ichiro
1257 1.1 ichiro if (mii == NULL)
1258 1.1 ichiro return;
1259 1.1 ichiro
1260 1.1 ichiro s = splnet();
1261 1.1 ichiro
1262 1.1 ichiro mii_tick(mii);
1263 1.1 ichiro if (!sc->sc_link) {
1264 1.1 ichiro mii_pollstat(mii);
1265 1.1 ichiro if (mii->mii_media_status & IFM_ACTIVE &&
1266 1.1 ichiro IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1267 1.1 ichiro DPRINTF(("%s: %s: got link\n",
1268 1.4 augustss USBDEVNAME(sc->sc_dev), __func__));
1269 1.1 ichiro sc->sc_link++;
1270 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1271 1.1 ichiro url_start(ifp);
1272 1.1 ichiro }
1273 1.1 ichiro }
1274 1.1 ichiro
1275 1.1 ichiro usb_callout(sc->sc_stat_ch, hz, url_tick, sc);
1276 1.1 ichiro
1277 1.1 ichiro splx(s);
1278 1.1 ichiro }
1279 1.1 ichiro
1280 1.1 ichiro /* Get exclusive access to the MII registers */
1281 1.1 ichiro Static void
1282 1.1 ichiro url_lock_mii(struct url_softc *sc)
1283 1.1 ichiro {
1284 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1285 1.4 augustss __func__));
1286 1.1 ichiro
1287 1.1 ichiro sc->sc_refcnt++;
1288 1.1 ichiro lockmgr(&sc->sc_mii_lock, LK_EXCLUSIVE, NULL);
1289 1.1 ichiro }
1290 1.1 ichiro
1291 1.1 ichiro Static void
1292 1.1 ichiro url_unlock_mii(struct url_softc *sc)
1293 1.1 ichiro {
1294 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1295 1.4 augustss __func__));
1296 1.1 ichiro
1297 1.1 ichiro lockmgr(&sc->sc_mii_lock, LK_RELEASE, NULL);
1298 1.1 ichiro if (--sc->sc_refcnt < 0)
1299 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
1300 1.1 ichiro }
1301 1.1 ichiro
1302 1.1 ichiro Static int
1303 1.1 ichiro url_int_miibus_readreg(device_ptr_t dev, int phy, int reg)
1304 1.1 ichiro {
1305 1.1 ichiro struct url_softc *sc;
1306 1.1 ichiro u_int16_t val;
1307 1.1 ichiro
1308 1.1 ichiro if (dev == NULL)
1309 1.1 ichiro return (0);
1310 1.1 ichiro
1311 1.1 ichiro sc = USBGETSOFTC(dev);
1312 1.1 ichiro
1313 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x\n",
1314 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg));
1315 1.1 ichiro
1316 1.1 ichiro if (sc->sc_dying) {
1317 1.1 ichiro #ifdef DIAGNOSTIC
1318 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1319 1.4 augustss __func__);
1320 1.1 ichiro #endif
1321 1.1 ichiro return (0);
1322 1.1 ichiro }
1323 1.1 ichiro
1324 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1325 1.1 ichiro if (phy != 0) {
1326 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1327 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy));
1328 1.1 ichiro return (0);
1329 1.1 ichiro }
1330 1.1 ichiro
1331 1.1 ichiro url_lock_mii(sc);
1332 1.1 ichiro
1333 1.1 ichiro switch (reg) {
1334 1.1 ichiro case MII_BMCR: /* Control Register */
1335 1.1 ichiro reg = URL_BMCR;
1336 1.1 ichiro break;
1337 1.1 ichiro case MII_BMSR: /* Status Register */
1338 1.1 ichiro reg = URL_BMSR;
1339 1.1 ichiro break;
1340 1.1 ichiro case MII_PHYIDR1:
1341 1.1 ichiro case MII_PHYIDR2:
1342 1.1 ichiro val = 0;
1343 1.1 ichiro goto R_DONE;
1344 1.1 ichiro break;
1345 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1346 1.1 ichiro reg = URL_ANAR;
1347 1.1 ichiro break;
1348 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1349 1.1 ichiro reg = URL_ANLP;
1350 1.1 ichiro break;
1351 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1352 1.1 ichiro reg = URL_MSR;
1353 1.1 ichiro break;
1354 1.1 ichiro default:
1355 1.1 ichiro printf("%s: %s: bad register %04x\n",
1356 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, reg);
1357 1.1 ichiro val = 0;
1358 1.1 ichiro goto R_DONE;
1359 1.1 ichiro break;
1360 1.1 ichiro }
1361 1.1 ichiro
1362 1.1 ichiro if (reg == URL_MSR)
1363 1.1 ichiro val = url_csr_read_1(sc, reg);
1364 1.1 ichiro else
1365 1.1 ichiro val = url_csr_read_2(sc, reg);
1366 1.1 ichiro
1367 1.1 ichiro R_DONE:
1368 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1369 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, val));
1370 1.1 ichiro
1371 1.1 ichiro url_unlock_mii(sc);
1372 1.1 ichiro return (val);
1373 1.1 ichiro }
1374 1.1 ichiro
1375 1.1 ichiro Static void
1376 1.1 ichiro url_int_miibus_writereg(device_ptr_t dev, int phy, int reg, int data)
1377 1.1 ichiro {
1378 1.1 ichiro struct url_softc *sc;
1379 1.1 ichiro
1380 1.1 ichiro if (dev == NULL)
1381 1.1 ichiro return;
1382 1.1 ichiro
1383 1.1 ichiro sc = USBGETSOFTC(dev);
1384 1.1 ichiro
1385 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1386 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, data));
1387 1.1 ichiro
1388 1.1 ichiro if (sc->sc_dying) {
1389 1.1 ichiro #ifdef DIAGNOSTIC
1390 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1391 1.4 augustss __func__);
1392 1.1 ichiro #endif
1393 1.1 ichiro return;
1394 1.1 ichiro }
1395 1.1 ichiro
1396 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1397 1.1 ichiro if (phy != 0) {
1398 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1399 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy));
1400 1.1 ichiro return;
1401 1.1 ichiro }
1402 1.1 ichiro
1403 1.1 ichiro url_lock_mii(sc);
1404 1.1 ichiro
1405 1.1 ichiro switch (reg) {
1406 1.1 ichiro case MII_BMCR: /* Control Register */
1407 1.1 ichiro reg = URL_BMCR;
1408 1.1 ichiro break;
1409 1.1 ichiro case MII_BMSR: /* Status Register */
1410 1.1 ichiro reg = URL_BMSR;
1411 1.1 ichiro break;
1412 1.1 ichiro case MII_PHYIDR1:
1413 1.1 ichiro case MII_PHYIDR2:
1414 1.1 ichiro goto W_DONE;
1415 1.1 ichiro break;
1416 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1417 1.1 ichiro reg = URL_ANAR;
1418 1.1 ichiro break;
1419 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1420 1.1 ichiro reg = URL_ANLP;
1421 1.1 ichiro break;
1422 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1423 1.1 ichiro reg = URL_MSR;
1424 1.1 ichiro break;
1425 1.1 ichiro default:
1426 1.1 ichiro printf("%s: %s: bad register %04x\n",
1427 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, reg);
1428 1.1 ichiro goto W_DONE;
1429 1.1 ichiro break;
1430 1.1 ichiro }
1431 1.1 ichiro
1432 1.1 ichiro if (reg == URL_MSR)
1433 1.1 ichiro url_csr_write_1(sc, reg, data);
1434 1.1 ichiro else
1435 1.1 ichiro url_csr_write_2(sc, reg, data);
1436 1.1 ichiro W_DONE:
1437 1.1 ichiro
1438 1.1 ichiro url_unlock_mii(sc);
1439 1.1 ichiro return;
1440 1.1 ichiro }
1441 1.1 ichiro
1442 1.1 ichiro Static void
1443 1.23 christos url_miibus_statchg(device_ptr_t dev)
1444 1.1 ichiro {
1445 1.1 ichiro #ifdef URL_DEBUG
1446 1.1 ichiro struct url_softc *sc;
1447 1.1 ichiro
1448 1.1 ichiro if (dev == NULL)
1449 1.1 ichiro return;
1450 1.1 ichiro
1451 1.1 ichiro sc = USBGETSOFTC(dev);
1452 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1453 1.1 ichiro #endif
1454 1.1 ichiro /* Nothing to do */
1455 1.1 ichiro }
1456 1.1 ichiro
1457 1.1 ichiro #if 0
1458 1.1 ichiro /*
1459 1.1 ichiro * external PHYs support, but not test.
1460 1.1 ichiro */
1461 1.1 ichiro Static int
1462 1.1 ichiro url_ext_miibus_redreg(device_ptr_t dev, int phy, int reg)
1463 1.1 ichiro {
1464 1.1 ichiro struct url_softc *sc = USBGETSOFTC(dev);
1465 1.1 ichiro u_int16_t val;
1466 1.1 ichiro
1467 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x\n",
1468 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg));
1469 1.1 ichiro
1470 1.1 ichiro if (sc->sc_dying) {
1471 1.1 ichiro #ifdef DIAGNOSTIC
1472 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1473 1.4 augustss __func__);
1474 1.1 ichiro #endif
1475 1.1 ichiro return (0);
1476 1.1 ichiro }
1477 1.1 ichiro
1478 1.1 ichiro url_lock_mii(sc);
1479 1.1 ichiro
1480 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy & URL_PHYADD_MASK);
1481 1.1 ichiro /*
1482 1.1 ichiro * RTL8150L will initiate a MII management data transaction
1483 1.1 ichiro * if PHYCNT_OWN bit is set 1 by software. After transaction,
1484 1.1 ichiro * this bit is auto cleared by TRL8150L.
1485 1.1 ichiro */
1486 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT,
1487 1.1 ichiro (reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
1488 1.1 ichiro for (i = 0; i < URL_TIMEOUT; i++) {
1489 1.1 ichiro if ((url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN) == 0)
1490 1.1 ichiro break;
1491 1.1 ichiro }
1492 1.1 ichiro if (i == URL_TIMEOUT) {
1493 1.1 ichiro printf("%s: MII read timed out\n", USBDEVNAME(sc->sc_dev));
1494 1.1 ichiro }
1495 1.5 augustss
1496 1.1 ichiro val = url_csr_read_2(sc, URL_PHYDAT);
1497 1.1 ichiro
1498 1.1 ichiro DPRINTF(("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1499 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, val));
1500 1.1 ichiro
1501 1.1 ichiro url_unlock_mii(sc);
1502 1.1 ichiro return (val);
1503 1.1 ichiro }
1504 1.1 ichiro
1505 1.1 ichiro Static void
1506 1.1 ichiro url_ext_miibus_writereg(device_ptr_t dev, int phy, int reg, int data)
1507 1.1 ichiro {
1508 1.1 ichiro struct url_softc *sc = USBGETSOFTC(dev);
1509 1.1 ichiro
1510 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1511 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, data));
1512 1.1 ichiro
1513 1.1 ichiro if (sc->sc_dying) {
1514 1.1 ichiro #ifdef DIAGNOSTIC
1515 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1516 1.4 augustss __func__);
1517 1.1 ichiro #endif
1518 1.1 ichiro return;
1519 1.1 ichiro }
1520 1.1 ichiro
1521 1.1 ichiro url_lock_mii(sc);
1522 1.1 ichiro
1523 1.1 ichiro url_csr_write_2(sc, URL_PHYDAT, data);
1524 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy);
1525 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */
1526 1.1 ichiro
1527 1.1 ichiro for (i=0; i < URL_TIMEOUT; i++) {
1528 1.1 ichiro if (url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN)
1529 1.1 ichiro break;
1530 1.1 ichiro }
1531 1.1 ichiro
1532 1.1 ichiro if (i == URL_TIMEOUT) {
1533 1.1 ichiro printf("%s: MII write timed out\n",
1534 1.1 ichiro USBDEVNAME(sc->sc_dev));
1535 1.1 ichiro }
1536 1.1 ichiro
1537 1.1 ichiro url_unlock_mii(sc);
1538 1.1 ichiro return;
1539 1.1 ichiro }
1540 1.1 ichiro #endif
1541 1.1 ichiro
1542