if_url.c revision 1.24.10.6 1 1.24.10.4 itohy /* $NetBSD: if_url.c,v 1.24.10.6 2007/06/25 09:26:31 itohy Exp $ */
2 1.1 ichiro /*
3 1.1 ichiro * Copyright (c) 2001, 2002
4 1.1 ichiro * Shingo WATANABE <nabe (at) nabechan.org>. All rights reserved.
5 1.1 ichiro *
6 1.1 ichiro * Redistribution and use in source and binary forms, with or without
7 1.1 ichiro * modification, are permitted provided that the following conditions
8 1.1 ichiro * are met:
9 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
10 1.1 ichiro * notice, this list of conditions and the following disclaimer.
11 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
13 1.1 ichiro * documentation and/or other materials provided with the distribution.
14 1.8 tsutsui * 3. Neither the name of the author nor the names of any co-contributors
15 1.1 ichiro * may be used to endorse or promote products derived from this software
16 1.1 ichiro * without specific prior written permission.
17 1.1 ichiro *
18 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 1.1 ichiro * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 ichiro * SUCH DAMAGE.
29 1.1 ichiro *
30 1.1 ichiro */
31 1.1 ichiro
32 1.1 ichiro /*
33 1.1 ichiro * The RTL8150L(Realtek USB to fast ethernet controller) spec can be found at
34 1.1 ichiro * ftp://ftp.realtek.com.tw/lancard/data_sheet/8150/8150v14.pdf
35 1.1 ichiro * ftp://152.104.125.40/lancard/data_sheet/8150/8150v14.pdf
36 1.1 ichiro */
37 1.1 ichiro
38 1.1 ichiro /*
39 1.1 ichiro * TODO:
40 1.1 ichiro * Interrupt Endpoint support
41 1.1 ichiro * External PHYs
42 1.1 ichiro * powerhook() support?
43 1.1 ichiro */
44 1.1 ichiro
45 1.1 ichiro #include <sys/cdefs.h>
46 1.24.10.4 itohy __KERNEL_RCSID(0, "$NetBSD: if_url.c,v 1.24.10.6 2007/06/25 09:26:31 itohy Exp $");
47 1.1 ichiro
48 1.1 ichiro #include "opt_inet.h"
49 1.1 ichiro #include "bpfilter.h"
50 1.1 ichiro #include "rnd.h"
51 1.1 ichiro
52 1.1 ichiro #include <sys/param.h>
53 1.1 ichiro #include <sys/systm.h>
54 1.1 ichiro #include <sys/lock.h>
55 1.1 ichiro #include <sys/mbuf.h>
56 1.1 ichiro #include <sys/kernel.h>
57 1.1 ichiro #include <sys/socket.h>
58 1.1 ichiro
59 1.1 ichiro #include <sys/device.h>
60 1.1 ichiro #if NRND > 0
61 1.1 ichiro #include <sys/rnd.h>
62 1.1 ichiro #endif
63 1.1 ichiro
64 1.1 ichiro #include <net/if.h>
65 1.1 ichiro #include <net/if_arp.h>
66 1.1 ichiro #include <net/if_dl.h>
67 1.1 ichiro #include <net/if_media.h>
68 1.1 ichiro
69 1.1 ichiro #if NBPFILTER > 0
70 1.1 ichiro #include <net/bpf.h>
71 1.1 ichiro #endif
72 1.1 ichiro #define BPF_MTAP(ifp, m) bpf_mtap((ifp)->if_bpf, (m))
73 1.1 ichiro
74 1.1 ichiro #include <net/if_ether.h>
75 1.1 ichiro #ifdef INET
76 1.1 ichiro #include <netinet/in.h>
77 1.1 ichiro #include <netinet/if_inarp.h>
78 1.1 ichiro #endif
79 1.1 ichiro
80 1.1 ichiro #include <dev/mii/mii.h>
81 1.1 ichiro #include <dev/mii/miivar.h>
82 1.1 ichiro #include <dev/mii/urlphyreg.h>
83 1.1 ichiro
84 1.1 ichiro #include <dev/usb/usb.h>
85 1.1 ichiro #include <dev/usb/usbdi.h>
86 1.1 ichiro #include <dev/usb/usbdi_util.h>
87 1.1 ichiro #include <dev/usb/usbdevs.h>
88 1.24.10.2 itohy #include <dev/usb/usb_ethersubr.h>
89 1.1 ichiro
90 1.1 ichiro #include <dev/usb/if_urlreg.h>
91 1.1 ichiro
92 1.1 ichiro
93 1.1 ichiro /* Function declarations */
94 1.1 ichiro USB_DECLARE_DRIVER(url);
95 1.1 ichiro
96 1.1 ichiro Static int url_openpipes(struct url_softc *);
97 1.1 ichiro Static void url_start(struct ifnet *);
98 1.1 ichiro Static int url_send(struct url_softc *, struct mbuf *, int);
99 1.1 ichiro Static void url_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status);
100 1.1 ichiro Static void url_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status);
101 1.1 ichiro Static void url_tick(void *);
102 1.1 ichiro Static void url_tick_task(void *);
103 1.24.10.3 itohy Static int url_ioctl(struct ifnet *, u_long, usb_ioctlarg_t);
104 1.1 ichiro Static void url_stop_task(struct url_softc *);
105 1.1 ichiro Static void url_stop(struct ifnet *, int);
106 1.1 ichiro Static void url_watchdog(struct ifnet *);
107 1.1 ichiro Static int url_ifmedia_change(struct ifnet *);
108 1.1 ichiro Static void url_ifmedia_status(struct ifnet *, struct ifmediareq *);
109 1.1 ichiro Static void url_lock_mii(struct url_softc *);
110 1.1 ichiro Static void url_unlock_mii(struct url_softc *);
111 1.1 ichiro Static int url_int_miibus_readreg(device_ptr_t, int, int);
112 1.1 ichiro Static void url_int_miibus_writereg(device_ptr_t, int, int, int);
113 1.1 ichiro Static void url_miibus_statchg(device_ptr_t);
114 1.1 ichiro Static int url_init(struct ifnet *);
115 1.1 ichiro Static void url_setmulti(struct url_softc *);
116 1.1 ichiro Static void url_reset(struct url_softc *);
117 1.1 ichiro
118 1.1 ichiro Static int url_csr_read_1(struct url_softc *, int);
119 1.1 ichiro Static int url_csr_read_2(struct url_softc *, int);
120 1.1 ichiro Static int url_csr_write_1(struct url_softc *, int, int);
121 1.1 ichiro Static int url_csr_write_2(struct url_softc *, int, int);
122 1.1 ichiro Static int url_csr_write_4(struct url_softc *, int, int);
123 1.1 ichiro Static int url_mem(struct url_softc *, int, int, void *, int);
124 1.1 ichiro
125 1.1 ichiro /* Macros */
126 1.1 ichiro #ifdef URL_DEBUG
127 1.2 ichiro #define DPRINTF(x) if (urldebug) logprintf x
128 1.2 ichiro #define DPRINTFN(n,x) if (urldebug >= (n)) logprintf x
129 1.2 ichiro int urldebug = 0;
130 1.1 ichiro #else
131 1.1 ichiro #define DPRINTF(x)
132 1.1 ichiro #define DPRINTFN(n,x)
133 1.1 ichiro #endif
134 1.1 ichiro
135 1.1 ichiro #define URL_SETBIT(sc, reg, x) \
136 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) | (x))
137 1.1 ichiro
138 1.1 ichiro #define URL_SETBIT2(sc, reg, x) \
139 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) | (x))
140 1.1 ichiro
141 1.1 ichiro #define URL_CLRBIT(sc, reg, x) \
142 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) & ~(x))
143 1.1 ichiro
144 1.1 ichiro #define URL_CLRBIT2(sc, reg, x) \
145 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) & ~(x))
146 1.1 ichiro
147 1.1 ichiro static const struct url_type {
148 1.1 ichiro struct usb_devno url_dev;
149 1.1 ichiro u_int16_t url_flags;
150 1.1 ichiro #define URL_EXT_PHY 0x0001
151 1.1 ichiro } url_devs [] = {
152 1.1 ichiro /* MELCO LUA-KTX */
153 1.1 ichiro {{ USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAKTX }, 0},
154 1.10 mycroft /* Realtek RTL8150L Generic (GREEN HOUSE USBKR100) */
155 1.11 augustss {{ USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8150L}, 0},
156 1.24.10.6 itohy /* Realtek RTL8151 Generic */
157 1.24.10.6 itohy {{ USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8151}, 0},
158 1.11 augustss /* Longshine LCS-8138TX */
159 1.11 augustss {{ USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_LCS8138TX}, 0},
160 1.11 augustss /* Micronet SP128AR */
161 1.11 augustss {{ USB_VENDOR_MICRONET, USB_PRODUCT_MICRONET_SP128AR}, 0},
162 1.13 itojun /* OQO model 01 */
163 1.13 itojun {{ USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01}, 0},
164 1.24.10.6 itohy /* ZyXEL Prestige */
165 1.24.10.6 itohy {{ USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_PRESTIGE}, 0}
166 1.1 ichiro };
167 1.17 christos #define url_lookup(v, p) ((const struct url_type *)usb_lookup(url_devs, v, p))
168 1.1 ichiro
169 1.24.10.2 itohy char zeros[URL_MIN_FRAME_LEN]; /* XXX */
170 1.1 ichiro
171 1.1 ichiro /* Probe */
172 1.1 ichiro USB_MATCH(url)
173 1.1 ichiro {
174 1.1 ichiro USB_MATCH_START(url, uaa);
175 1.1 ichiro
176 1.24.10.4 itohy #ifndef USB_USE_IFATTACH
177 1.1 ichiro if (uaa->iface != NULL)
178 1.1 ichiro return (UMATCH_NONE);
179 1.24.10.4 itohy #endif /* USB_USE_IFATTACH */
180 1.1 ichiro
181 1.1 ichiro return (url_lookup(uaa->vendor, uaa->product) != NULL ?
182 1.1 ichiro UMATCH_VENDOR_PRODUCT : UMATCH_NONE);
183 1.1 ichiro }
184 1.1 ichiro /* Attach */
185 1.1 ichiro USB_ATTACH(url)
186 1.1 ichiro {
187 1.1 ichiro USB_ATTACH_START(url, sc, uaa);
188 1.1 ichiro usbd_device_handle dev = uaa->device;
189 1.1 ichiro usbd_interface_handle iface;
190 1.1 ichiro usbd_status err;
191 1.1 ichiro usb_interface_descriptor_t *id;
192 1.1 ichiro usb_endpoint_descriptor_t *ed;
193 1.16 augustss char *devinfop;
194 1.1 ichiro char *devname = USBDEVNAME(sc->sc_dev);
195 1.1 ichiro struct ifnet *ifp;
196 1.1 ichiro struct mii_data *mii;
197 1.1 ichiro u_char eaddr[ETHER_ADDR_LEN];
198 1.1 ichiro int i, s;
199 1.1 ichiro
200 1.16 augustss devinfop = usbd_devinfo_alloc(dev, 0);
201 1.1 ichiro USB_ATTACH_SETUP;
202 1.16 augustss printf("%s: %s\n", devname, devinfop);
203 1.16 augustss usbd_devinfo_free(devinfop);
204 1.1 ichiro
205 1.1 ichiro /* Move the device into the configured state. */
206 1.1 ichiro err = usbd_set_config_no(dev, URL_CONFIG_NO, 1);
207 1.1 ichiro if (err) {
208 1.1 ichiro printf("%s: setting config no failed\n", devname);
209 1.1 ichiro goto bad;
210 1.1 ichiro }
211 1.1 ichiro
212 1.1 ichiro usb_init_task(&sc->sc_tick_task, url_tick_task, sc);
213 1.1 ichiro lockinit(&sc->sc_mii_lock, PZERO, "urlmii", 0, 0);
214 1.1 ichiro usb_init_task(&sc->sc_stop_task, (void (*)(void *)) url_stop_task, sc);
215 1.1 ichiro
216 1.1 ichiro /* get control interface */
217 1.1 ichiro err = usbd_device2interface_handle(dev, URL_IFACE_INDEX, &iface);
218 1.1 ichiro if (err) {
219 1.1 ichiro printf("%s: failed to get interface, err=%s\n", devname,
220 1.1 ichiro usbd_errstr(err));
221 1.1 ichiro goto bad;
222 1.1 ichiro }
223 1.1 ichiro
224 1.1 ichiro sc->sc_udev = dev;
225 1.1 ichiro sc->sc_ctl_iface = iface;
226 1.1 ichiro sc->sc_flags = url_lookup(uaa->vendor, uaa->product)->url_flags;
227 1.1 ichiro
228 1.1 ichiro /* get interface descriptor */
229 1.1 ichiro id = usbd_get_interface_descriptor(sc->sc_ctl_iface);
230 1.1 ichiro
231 1.1 ichiro /* find endpoints */
232 1.1 ichiro sc->sc_bulkin_no = sc->sc_bulkout_no = sc->sc_intrin_no = -1;
233 1.1 ichiro for (i = 0; i < id->bNumEndpoints; i++) {
234 1.1 ichiro ed = usbd_interface2endpoint_descriptor(sc->sc_ctl_iface, i);
235 1.1 ichiro if (ed == NULL) {
236 1.1 ichiro printf("%s: couldn't get endpoint %d\n", devname, i);
237 1.1 ichiro goto bad;
238 1.1 ichiro }
239 1.1 ichiro if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
240 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
241 1.1 ichiro sc->sc_bulkin_no = ed->bEndpointAddress; /* RX */
242 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
243 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)
244 1.1 ichiro sc->sc_bulkout_no = ed->bEndpointAddress; /* TX */
245 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_INTERRUPT &&
246 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
247 1.1 ichiro sc->sc_intrin_no = ed->bEndpointAddress; /* Status */
248 1.1 ichiro }
249 1.1 ichiro
250 1.1 ichiro if (sc->sc_bulkin_no == -1 || sc->sc_bulkout_no == -1 ||
251 1.1 ichiro sc->sc_intrin_no == -1) {
252 1.1 ichiro printf("%s: missing endpoint\n", devname);
253 1.1 ichiro goto bad;
254 1.1 ichiro }
255 1.1 ichiro
256 1.1 ichiro s = splnet();
257 1.1 ichiro
258 1.1 ichiro /* reset the adapter */
259 1.1 ichiro url_reset(sc);
260 1.1 ichiro
261 1.1 ichiro /* Get Ethernet Address */
262 1.1 ichiro err = url_mem(sc, URL_CMD_READMEM, URL_IDR0, (void *)eaddr,
263 1.1 ichiro ETHER_ADDR_LEN);
264 1.1 ichiro if (err) {
265 1.3 augustss printf("%s: read MAC address failed\n", devname);
266 1.1 ichiro splx(s);
267 1.1 ichiro goto bad;
268 1.1 ichiro }
269 1.1 ichiro
270 1.1 ichiro /* Print Ethernet Address */
271 1.1 ichiro printf("%s: Ethernet address %s\n", devname, ether_sprintf(eaddr));
272 1.1 ichiro
273 1.19 wiz /* initialize interface information */
274 1.1 ichiro ifp = GET_IFP(sc);
275 1.1 ichiro ifp->if_softc = sc;
276 1.3 augustss ifp->if_mtu = ETHERMTU;
277 1.1 ichiro strncpy(ifp->if_xname, devname, IFNAMSIZ);
278 1.1 ichiro ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
279 1.1 ichiro ifp->if_start = url_start;
280 1.1 ichiro ifp->if_ioctl = url_ioctl;
281 1.1 ichiro ifp->if_watchdog = url_watchdog;
282 1.1 ichiro ifp->if_init = url_init;
283 1.1 ichiro ifp->if_stop = url_stop;
284 1.1 ichiro
285 1.1 ichiro IFQ_SET_READY(&ifp->if_snd);
286 1.1 ichiro
287 1.1 ichiro /*
288 1.1 ichiro * Do ifmedia setup.
289 1.1 ichiro */
290 1.1 ichiro mii = &sc->sc_mii;
291 1.1 ichiro mii->mii_ifp = ifp;
292 1.1 ichiro mii->mii_readreg = url_int_miibus_readreg;
293 1.1 ichiro mii->mii_writereg = url_int_miibus_writereg;
294 1.1 ichiro #if 0
295 1.1 ichiro if (sc->sc_flags & URL_EXT_PHY) {
296 1.1 ichiro mii->mii_readreg = url_ext_miibus_readreg;
297 1.1 ichiro mii->mii_writereg = url_ext_miibus_writereg;
298 1.1 ichiro }
299 1.1 ichiro #endif
300 1.1 ichiro mii->mii_statchg = url_miibus_statchg;
301 1.1 ichiro mii->mii_flags = MIIF_AUTOTSLEEP;
302 1.1 ichiro ifmedia_init(&mii->mii_media, 0,
303 1.1 ichiro url_ifmedia_change, url_ifmedia_status);
304 1.1 ichiro mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
305 1.1 ichiro if (LIST_FIRST(&mii->mii_phys) == NULL) {
306 1.1 ichiro ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
307 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
308 1.1 ichiro } else
309 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
310 1.1 ichiro
311 1.1 ichiro /* attach the interface */
312 1.1 ichiro if_attach(ifp);
313 1.1 ichiro Ether_ifattach(ifp, eaddr);
314 1.1 ichiro
315 1.1 ichiro #if NRND > 0
316 1.1 ichiro rnd_attach_source(&sc->rnd_source, devname, RND_TYPE_NET, 0);
317 1.1 ichiro #endif
318 1.1 ichiro
319 1.1 ichiro usb_callout_init(sc->sc_stat_ch);
320 1.1 ichiro sc->sc_attached = 1;
321 1.1 ichiro splx(s);
322 1.1 ichiro
323 1.1 ichiro usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, dev, USBDEV(sc->sc_dev));
324 1.1 ichiro
325 1.1 ichiro USB_ATTACH_SUCCESS_RETURN;
326 1.1 ichiro
327 1.1 ichiro bad:
328 1.1 ichiro sc->sc_dying = 1;
329 1.1 ichiro USB_ATTACH_ERROR_RETURN;
330 1.1 ichiro }
331 1.1 ichiro
332 1.1 ichiro /* detach */
333 1.1 ichiro USB_DETACH(url)
334 1.1 ichiro {
335 1.1 ichiro USB_DETACH_START(url, sc);
336 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
337 1.1 ichiro int s;
338 1.1 ichiro
339 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
340 1.1 ichiro
341 1.1 ichiro /* Detached before attached finished */
342 1.1 ichiro if (!sc->sc_attached)
343 1.1 ichiro return (0);
344 1.1 ichiro
345 1.1 ichiro usb_uncallout(sc->sc_stat_ch, url_tick, sc);
346 1.1 ichiro
347 1.1 ichiro /* Remove any pending tasks */
348 1.1 ichiro usb_rem_task(sc->sc_udev, &sc->sc_tick_task);
349 1.1 ichiro usb_rem_task(sc->sc_udev, &sc->sc_stop_task);
350 1.1 ichiro
351 1.1 ichiro s = splusb();
352 1.1 ichiro
353 1.1 ichiro if (--sc->sc_refcnt >= 0) {
354 1.1 ichiro /* Wait for processes to go away */
355 1.1 ichiro usb_detach_wait(USBDEV(sc->sc_dev));
356 1.1 ichiro }
357 1.1 ichiro
358 1.1 ichiro if (ifp->if_flags & IFF_RUNNING)
359 1.24.10.2 itohy url_stop(ifp, 1);
360 1.1 ichiro
361 1.1 ichiro #if NRND > 0
362 1.1 ichiro rnd_detach_source(&sc->rnd_source);
363 1.1 ichiro #endif
364 1.1 ichiro mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
365 1.1 ichiro ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
366 1.1 ichiro ether_ifdetach(ifp);
367 1.1 ichiro if_detach(ifp);
368 1.1 ichiro
369 1.1 ichiro #ifdef DIAGNOSTIC
370 1.1 ichiro if (sc->sc_pipe_tx != NULL)
371 1.1 ichiro printf("%s: detach has active tx endpoint.\n",
372 1.1 ichiro USBDEVNAME(sc->sc_dev));
373 1.1 ichiro if (sc->sc_pipe_rx != NULL)
374 1.1 ichiro printf("%s: detach has active rx endpoint.\n",
375 1.1 ichiro USBDEVNAME(sc->sc_dev));
376 1.1 ichiro if (sc->sc_pipe_intr != NULL)
377 1.1 ichiro printf("%s: detach has active intr endpoint.\n",
378 1.1 ichiro USBDEVNAME(sc->sc_dev));
379 1.1 ichiro #endif
380 1.1 ichiro
381 1.1 ichiro sc->sc_attached = 0;
382 1.1 ichiro
383 1.1 ichiro splx(s);
384 1.1 ichiro
385 1.1 ichiro usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev,
386 1.1 ichiro USBDEV(sc->sc_dev));
387 1.1 ichiro
388 1.1 ichiro return (0);
389 1.1 ichiro }
390 1.1 ichiro
391 1.1 ichiro /* read/write memory */
392 1.1 ichiro Static int
393 1.1 ichiro url_mem(struct url_softc *sc, int cmd, int offset, void *buf, int len)
394 1.1 ichiro {
395 1.1 ichiro usb_device_request_t req;
396 1.1 ichiro usbd_status err;
397 1.1 ichiro
398 1.1 ichiro if (sc == NULL)
399 1.1 ichiro return (0);
400 1.1 ichiro
401 1.1 ichiro DPRINTFN(0x200,
402 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
403 1.1 ichiro
404 1.1 ichiro if (sc->sc_dying)
405 1.1 ichiro return (0);
406 1.1 ichiro
407 1.1 ichiro if (cmd == URL_CMD_READMEM)
408 1.1 ichiro req.bmRequestType = UT_READ_VENDOR_DEVICE;
409 1.1 ichiro else
410 1.1 ichiro req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
411 1.1 ichiro req.bRequest = URL_REQ_MEM;
412 1.1 ichiro USETW(req.wValue, offset);
413 1.1 ichiro USETW(req.wIndex, 0x0000);
414 1.1 ichiro USETW(req.wLength, len);
415 1.1 ichiro
416 1.1 ichiro sc->sc_refcnt++;
417 1.1 ichiro err = usbd_do_request(sc->sc_udev, &req, buf);
418 1.1 ichiro if (--sc->sc_refcnt < 0)
419 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
420 1.1 ichiro if (err) {
421 1.1 ichiro DPRINTF(("%s: url_mem(): %s failed. off=%04x, err=%d\n",
422 1.1 ichiro USBDEVNAME(sc->sc_dev),
423 1.1 ichiro cmd == URL_CMD_READMEM ? "read" : "write",
424 1.1 ichiro offset, err));
425 1.5 augustss }
426 1.1 ichiro
427 1.1 ichiro return (err);
428 1.1 ichiro }
429 1.1 ichiro
430 1.1 ichiro /* read 1byte from register */
431 1.1 ichiro Static int
432 1.1 ichiro url_csr_read_1(struct url_softc *sc, int reg)
433 1.1 ichiro {
434 1.1 ichiro u_int8_t val = 0;
435 1.1 ichiro
436 1.1 ichiro DPRINTFN(0x100,
437 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
438 1.1 ichiro
439 1.1 ichiro if (sc->sc_dying)
440 1.1 ichiro return (0);
441 1.5 augustss
442 1.1 ichiro return (url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val);
443 1.1 ichiro }
444 1.1 ichiro
445 1.1 ichiro /* read 2bytes from register */
446 1.1 ichiro Static int
447 1.1 ichiro url_csr_read_2(struct url_softc *sc, int reg)
448 1.1 ichiro {
449 1.1 ichiro uWord val;
450 1.1 ichiro
451 1.1 ichiro DPRINTFN(0x100,
452 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
453 1.1 ichiro
454 1.1 ichiro if (sc->sc_dying)
455 1.1 ichiro return (0);
456 1.5 augustss
457 1.1 ichiro USETW(val, 0);
458 1.1 ichiro return (url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val));
459 1.1 ichiro }
460 1.1 ichiro
461 1.1 ichiro /* write 1byte to register */
462 1.1 ichiro Static int
463 1.1 ichiro url_csr_write_1(struct url_softc *sc, int reg, int aval)
464 1.1 ichiro {
465 1.1 ichiro u_int8_t val = aval;
466 1.1 ichiro
467 1.1 ichiro DPRINTFN(0x100,
468 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
469 1.1 ichiro
470 1.1 ichiro if (sc->sc_dying)
471 1.1 ichiro return (0);
472 1.5 augustss
473 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0);
474 1.1 ichiro }
475 1.1 ichiro
476 1.1 ichiro /* write 2bytes to register */
477 1.1 ichiro Static int
478 1.1 ichiro url_csr_write_2(struct url_softc *sc, int reg, int aval)
479 1.1 ichiro {
480 1.1 ichiro uWord val;
481 1.1 ichiro
482 1.1 ichiro DPRINTFN(0x100,
483 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
484 1.1 ichiro
485 1.1 ichiro USETW(val, aval);
486 1.1 ichiro
487 1.1 ichiro if (sc->sc_dying)
488 1.1 ichiro return (0);
489 1.5 augustss
490 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0);
491 1.1 ichiro }
492 1.1 ichiro
493 1.1 ichiro /* write 4bytes to register */
494 1.1 ichiro Static int
495 1.1 ichiro url_csr_write_4(struct url_softc *sc, int reg, int aval)
496 1.1 ichiro {
497 1.1 ichiro uDWord val;
498 1.1 ichiro
499 1.1 ichiro DPRINTFN(0x100,
500 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
501 1.1 ichiro
502 1.1 ichiro USETDW(val, aval);
503 1.1 ichiro
504 1.1 ichiro if (sc->sc_dying)
505 1.1 ichiro return (0);
506 1.5 augustss
507 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0);
508 1.1 ichiro }
509 1.1 ichiro
510 1.1 ichiro Static int
511 1.1 ichiro url_init(struct ifnet *ifp)
512 1.1 ichiro {
513 1.1 ichiro struct url_softc *sc = ifp->if_softc;
514 1.1 ichiro struct mii_data *mii = GET_MII(sc);
515 1.1 ichiro u_char *eaddr;
516 1.1 ichiro int i, s;
517 1.24.10.2 itohy struct ue_chain *c;
518 1.1 ichiro
519 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
520 1.5 augustss
521 1.1 ichiro if (sc->sc_dying)
522 1.1 ichiro return (EIO);
523 1.1 ichiro
524 1.1 ichiro s = splnet();
525 1.1 ichiro
526 1.1 ichiro /* Cancel pending I/O and free all TX/RX buffers */
527 1.1 ichiro url_stop(ifp, 1);
528 1.1 ichiro
529 1.1 ichiro eaddr = LLADDR(ifp->if_sadl);
530 1.1 ichiro for (i = 0; i < ETHER_ADDR_LEN; i++)
531 1.1 ichiro url_csr_write_1(sc, URL_IDR0 + i, eaddr[i]);
532 1.1 ichiro
533 1.1 ichiro /* Init transmission control register */
534 1.1 ichiro URL_CLRBIT(sc, URL_TCR,
535 1.1 ichiro URL_TCR_TXRR1 | URL_TCR_TXRR0 |
536 1.1 ichiro URL_TCR_IFG1 | URL_TCR_IFG0 |
537 1.1 ichiro URL_TCR_NOCRC);
538 1.1 ichiro
539 1.1 ichiro /* Init receive control register */
540 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_TAIL | URL_RCR_AD);
541 1.1 ichiro if (ifp->if_flags & IFF_BROADCAST)
542 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AB);
543 1.1 ichiro else
544 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AB);
545 1.1 ichiro
546 1.1 ichiro /* If we want promiscuous mode, accept all physical frames. */
547 1.1 ichiro if (ifp->if_flags & IFF_PROMISC)
548 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
549 1.1 ichiro else
550 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
551 1.1 ichiro
552 1.24.10.2 itohy if (sc->sc_pipe_tx == NULL || sc->sc_pipe_rx == NULL) {
553 1.24.10.2 itohy if (url_openpipes(sc)) {
554 1.24.10.2 itohy splx(s);
555 1.24.10.2 itohy return (EIO);
556 1.24.10.2 itohy }
557 1.24.10.2 itohy }
558 1.5 augustss
559 1.1 ichiro /* Initialize transmit ring */
560 1.24.10.2 itohy if (usb_ether_tx_list_init(USBDEV(sc->sc_dev),
561 1.24.10.2 itohy sc->sc_cdata.url_tx_chain, URL_TX_LIST_CNT,
562 1.24.10.2 itohy sc->sc_udev, sc->sc_pipe_tx, NULL)) {
563 1.1 ichiro printf("%s: tx list init failed\n", USBDEVNAME(sc->sc_dev));
564 1.1 ichiro splx(s);
565 1.1 ichiro return (EIO);
566 1.1 ichiro }
567 1.1 ichiro
568 1.1 ichiro /* Initialize receive ring */
569 1.24.10.2 itohy if (usb_ether_rx_list_init(USBDEV(sc->sc_dev),
570 1.24.10.2 itohy sc->sc_cdata.url_rx_chain, URL_RX_LIST_CNT,
571 1.24.10.2 itohy sc->sc_udev, sc->sc_pipe_rx)) {
572 1.1 ichiro printf("%s: rx list init failed\n", USBDEVNAME(sc->sc_dev));
573 1.1 ichiro splx(s);
574 1.1 ichiro return (EIO);
575 1.1 ichiro }
576 1.1 ichiro
577 1.1 ichiro /* Load the multicast filter */
578 1.1 ichiro url_setmulti(sc);
579 1.1 ichiro
580 1.1 ichiro /* Enable RX and TX */
581 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_TE | URL_CR_RE);
582 1.1 ichiro
583 1.1 ichiro mii_mediachg(mii);
584 1.1 ichiro
585 1.24.10.2 itohy /* Start up the receive pipe. */
586 1.24.10.2 itohy for (i = 0; i < URL_RX_LIST_CNT; i++) {
587 1.24.10.2 itohy c = &sc->sc_cdata.url_rx_chain[i];
588 1.24.10.2 itohy (void)usbd_map_buffer_mbuf(c->ue_xfer, c->ue_mbuf);
589 1.24.10.2 itohy usbd_setup_xfer(c->ue_xfer, sc->sc_pipe_rx,
590 1.24.10.2 itohy c, NULL /* XXX buf */, URL_BUFSZ,
591 1.24.10.5 itohy USBD_SHORT_XFER_OK | USBD_NO_COPY
592 1.24.10.5 itohy #ifdef __FreeBSD__ /* callback needs context */
593 1.24.10.5 itohy | USBD_CALLBACK_AS_TASK
594 1.24.10.5 itohy #endif
595 1.24.10.5 itohy ,
596 1.24.10.2 itohy USBD_NO_TIMEOUT, url_rxeof);
597 1.24.10.2 itohy (void)usbd_transfer(c->ue_xfer);
598 1.24.10.2 itohy DPRINTF(("%s: %s: start read\n", USBDEVNAME(sc->sc_dev),
599 1.24.10.2 itohy __func__));
600 1.1 ichiro }
601 1.1 ichiro
602 1.1 ichiro ifp->if_flags |= IFF_RUNNING;
603 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
604 1.1 ichiro
605 1.1 ichiro splx(s);
606 1.1 ichiro
607 1.1 ichiro usb_callout(sc->sc_stat_ch, hz, url_tick, sc);
608 1.1 ichiro
609 1.1 ichiro return (0);
610 1.1 ichiro }
611 1.1 ichiro
612 1.1 ichiro Static void
613 1.1 ichiro url_reset(struct url_softc *sc)
614 1.1 ichiro {
615 1.1 ichiro int i;
616 1.5 augustss
617 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
618 1.1 ichiro
619 1.1 ichiro if (sc->sc_dying)
620 1.1 ichiro return;
621 1.1 ichiro
622 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_SOFT_RST);
623 1.1 ichiro
624 1.1 ichiro for (i = 0; i < URL_TX_TIMEOUT; i++) {
625 1.1 ichiro if (!(url_csr_read_1(sc, URL_CR) & URL_CR_SOFT_RST))
626 1.1 ichiro break;
627 1.1 ichiro delay(10); /* XXX */
628 1.1 ichiro }
629 1.1 ichiro
630 1.1 ichiro delay(10000); /* XXX */
631 1.1 ichiro }
632 1.1 ichiro
633 1.1 ichiro int
634 1.1 ichiro url_activate(device_ptr_t self, enum devact act)
635 1.1 ichiro {
636 1.1 ichiro struct url_softc *sc = (struct url_softc *)self;
637 1.1 ichiro
638 1.1 ichiro DPRINTF(("%s: %s: enter, act=%d\n", USBDEVNAME(sc->sc_dev),
639 1.4 augustss __func__, act));
640 1.1 ichiro
641 1.1 ichiro switch (act) {
642 1.1 ichiro case DVACT_ACTIVATE:
643 1.1 ichiro return (EOPNOTSUPP);
644 1.1 ichiro break;
645 1.1 ichiro
646 1.1 ichiro case DVACT_DEACTIVATE:
647 1.1 ichiro if_deactivate(&sc->sc_ec.ec_if);
648 1.1 ichiro sc->sc_dying = 1;
649 1.1 ichiro break;
650 1.1 ichiro }
651 1.1 ichiro
652 1.1 ichiro return (0);
653 1.1 ichiro }
654 1.1 ichiro
655 1.1 ichiro #define url_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
656 1.1 ichiro
657 1.1 ichiro
658 1.1 ichiro Static void
659 1.1 ichiro url_setmulti(struct url_softc *sc)
660 1.1 ichiro {
661 1.1 ichiro struct ifnet *ifp;
662 1.1 ichiro struct ether_multi *enm;
663 1.1 ichiro struct ether_multistep step;
664 1.1 ichiro u_int32_t hashes[2] = { 0, 0 };
665 1.1 ichiro int h = 0;
666 1.1 ichiro int mcnt = 0;
667 1.1 ichiro
668 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
669 1.1 ichiro
670 1.1 ichiro if (sc->sc_dying)
671 1.1 ichiro return;
672 1.1 ichiro
673 1.1 ichiro ifp = GET_IFP(sc);
674 1.1 ichiro
675 1.1 ichiro if (ifp->if_flags & IFF_PROMISC) {
676 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
677 1.1 ichiro return;
678 1.1 ichiro } else if (ifp->if_flags & IFF_ALLMULTI) {
679 1.1 ichiro allmulti:
680 1.1 ichiro ifp->if_flags |= IFF_ALLMULTI;
681 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM);
682 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAP);
683 1.1 ichiro return;
684 1.1 ichiro }
685 1.1 ichiro
686 1.1 ichiro /* first, zot all the existing hash bits */
687 1.1 ichiro url_csr_write_4(sc, URL_MAR0, 0);
688 1.1 ichiro url_csr_write_4(sc, URL_MAR4, 0);
689 1.1 ichiro
690 1.1 ichiro /* now program new ones */
691 1.1 ichiro ETHER_FIRST_MULTI(step, &sc->sc_ec, enm);
692 1.1 ichiro while (enm != NULL) {
693 1.1 ichiro if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
694 1.1 ichiro ETHER_ADDR_LEN) != 0)
695 1.1 ichiro goto allmulti;
696 1.1 ichiro
697 1.1 ichiro h = url_calchash(enm->enm_addrlo);
698 1.1 ichiro if (h < 32)
699 1.1 ichiro hashes[0] |= (1 << h);
700 1.1 ichiro else
701 1.1 ichiro hashes[1] |= (1 << (h -32));
702 1.1 ichiro mcnt++;
703 1.1 ichiro ETHER_NEXT_MULTI(step, enm);
704 1.1 ichiro }
705 1.1 ichiro
706 1.1 ichiro ifp->if_flags &= ~IFF_ALLMULTI;
707 1.1 ichiro
708 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
709 1.1 ichiro
710 1.1 ichiro if (mcnt){
711 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AM);
712 1.1 ichiro } else {
713 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AM);
714 1.1 ichiro }
715 1.1 ichiro url_csr_write_4(sc, URL_MAR0, hashes[0]);
716 1.1 ichiro url_csr_write_4(sc, URL_MAR4, hashes[1]);
717 1.1 ichiro }
718 1.1 ichiro
719 1.1 ichiro Static int
720 1.1 ichiro url_openpipes(struct url_softc *sc)
721 1.1 ichiro {
722 1.1 ichiro usbd_status err;
723 1.1 ichiro int error = 0;
724 1.1 ichiro
725 1.1 ichiro if (sc->sc_dying)
726 1.1 ichiro return (EIO);
727 1.5 augustss
728 1.1 ichiro sc->sc_refcnt++;
729 1.1 ichiro
730 1.1 ichiro /* Open RX pipe */
731 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkin_no,
732 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_rx);
733 1.1 ichiro if (err) {
734 1.1 ichiro printf("%s: open rx pipe failed: %s\n",
735 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
736 1.1 ichiro error = EIO;
737 1.1 ichiro goto done;
738 1.1 ichiro }
739 1.5 augustss
740 1.1 ichiro /* Open TX pipe */
741 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkout_no,
742 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_tx);
743 1.1 ichiro if (err) {
744 1.1 ichiro printf("%s: open tx pipe failed: %s\n",
745 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
746 1.1 ichiro error = EIO;
747 1.1 ichiro goto done;
748 1.1 ichiro }
749 1.1 ichiro
750 1.1 ichiro #if 0
751 1.1 ichiro /* XXX: interrupt endpoint is not yet supported */
752 1.1 ichiro /* Open Interrupt pipe */
753 1.1 ichiro err = usbd_open_pipe_intr(sc->sc_ctl_iface, sc->sc_intrin_no,
754 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_intr, sc,
755 1.1 ichiro &sc->sc_cdata.url_ibuf, URL_INTR_PKGLEN,
756 1.24 drochner url_intr, USBD_DEFAULT_INTERVAL);
757 1.1 ichiro if (err) {
758 1.1 ichiro printf("%s: open intr pipe failed: %s\n",
759 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
760 1.1 ichiro error = EIO;
761 1.1 ichiro goto done;
762 1.1 ichiro }
763 1.1 ichiro #endif
764 1.1 ichiro
765 1.1 ichiro done:
766 1.1 ichiro if (--sc->sc_refcnt < 0)
767 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
768 1.5 augustss
769 1.1 ichiro return (error);
770 1.1 ichiro }
771 1.1 ichiro
772 1.1 ichiro Static void
773 1.1 ichiro url_start(struct ifnet *ifp)
774 1.1 ichiro {
775 1.1 ichiro struct url_softc *sc = ifp->if_softc;
776 1.1 ichiro struct mbuf *m_head = NULL;
777 1.5 augustss
778 1.1 ichiro DPRINTF(("%s: %s: enter, link=%d\n", USBDEVNAME(sc->sc_dev),
779 1.4 augustss __func__, sc->sc_link));
780 1.1 ichiro
781 1.1 ichiro if (sc->sc_dying)
782 1.1 ichiro return;
783 1.1 ichiro
784 1.1 ichiro if (!sc->sc_link)
785 1.1 ichiro return;
786 1.1 ichiro
787 1.1 ichiro if (ifp->if_flags & IFF_OACTIVE)
788 1.1 ichiro return;
789 1.1 ichiro
790 1.1 ichiro IFQ_POLL(&ifp->if_snd, m_head);
791 1.1 ichiro if (m_head == NULL)
792 1.1 ichiro return;
793 1.1 ichiro
794 1.1 ichiro IFQ_DEQUEUE(&ifp->if_snd, m_head);
795 1.1 ichiro
796 1.1 ichiro #if NBPFILTER > 0
797 1.1 ichiro if (ifp->if_bpf)
798 1.1 ichiro bpf_mtap(ifp->if_bpf, m_head);
799 1.1 ichiro #endif
800 1.1 ichiro
801 1.24.10.2 itohy if (url_send(sc, m_head, 0)) {
802 1.24.10.2 itohy ifp->if_flags |= IFF_OACTIVE;
803 1.24.10.2 itohy return;
804 1.24.10.2 itohy }
805 1.24.10.2 itohy
806 1.1 ichiro ifp->if_flags |= IFF_OACTIVE;
807 1.1 ichiro
808 1.1 ichiro /* Set a timeout in case the chip goes out to lunch. */
809 1.1 ichiro ifp->if_timer = 5;
810 1.1 ichiro }
811 1.1 ichiro
812 1.1 ichiro Static int
813 1.1 ichiro url_send(struct url_softc *sc, struct mbuf *m, int idx)
814 1.1 ichiro {
815 1.1 ichiro int total_len;
816 1.24.10.2 itohy struct ue_chain *c;
817 1.1 ichiro usbd_status err;
818 1.24.10.2 itohy int ret;
819 1.1 ichiro
820 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),__func__));
821 1.1 ichiro
822 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[idx];
823 1.1 ichiro
824 1.1 ichiro total_len = m->m_pkthdr.len;
825 1.1 ichiro
826 1.7 bouyer if (total_len < URL_MIN_FRAME_LEN) {
827 1.24.10.2 itohy /* expand mbuf chain with zeros */
828 1.24.10.2 itohy m_copyback(m, total_len, URL_MIN_FRAME_LEN - total_len,
829 1.24.10.2 itohy zeros);
830 1.1 ichiro total_len = URL_MIN_FRAME_LEN;
831 1.24.10.2 itohy if (m->m_pkthdr.len != total_len) {
832 1.24.10.2 itohy m_freem(m);
833 1.24.10.2 itohy return (ENOBUFS);
834 1.24.10.2 itohy }
835 1.7 bouyer }
836 1.24.10.2 itohy
837 1.24.10.2 itohy ret = usb_ether_map_tx_buffer_mbuf(c, m);
838 1.24.10.2 itohy if (ret) {
839 1.24.10.2 itohy m_freem(m);
840 1.24.10.2 itohy return (ret);
841 1.24.10.2 itohy }
842 1.24.10.2 itohy
843 1.24.10.2 itohy usbd_setup_xfer(c->ue_xfer, sc->sc_pipe_tx, c, NULL /* XXX buf */, total_len,
844 1.24.10.5 itohy USBD_FORCE_SHORT_XFER | USBD_NO_COPY
845 1.24.10.5 itohy #ifdef __FreeBSD__ /* callback needs context */
846 1.24.10.5 itohy | USBD_CALLBACK_AS_TASK
847 1.24.10.5 itohy #endif
848 1.24.10.5 itohy ,
849 1.1 ichiro URL_TX_TIMEOUT, url_txeof);
850 1.1 ichiro
851 1.1 ichiro /* Transmit */
852 1.1 ichiro sc->sc_refcnt++;
853 1.24.10.2 itohy err = usbd_transfer(c->ue_xfer);
854 1.1 ichiro if (--sc->sc_refcnt < 0)
855 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
856 1.1 ichiro if (err != USBD_IN_PROGRESS) {
857 1.24.10.2 itohy c->ue_mbuf = NULL;
858 1.24.10.2 itohy m_freem(m);
859 1.1 ichiro printf("%s: url_send error=%s\n", USBDEVNAME(sc->sc_dev),
860 1.1 ichiro usbd_errstr(err));
861 1.1 ichiro /* Stop the interface */
862 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_stop_task,
863 1.22 joerg USB_TASKQ_DRIVER);
864 1.1 ichiro return (EIO);
865 1.1 ichiro }
866 1.1 ichiro
867 1.1 ichiro DPRINTF(("%s: %s: send %d bytes\n", USBDEVNAME(sc->sc_dev),
868 1.4 augustss __func__, total_len));
869 1.1 ichiro
870 1.1 ichiro sc->sc_cdata.url_tx_cnt++;
871 1.1 ichiro
872 1.1 ichiro return (0);
873 1.1 ichiro }
874 1.1 ichiro
875 1.1 ichiro Static void
876 1.23 christos url_txeof(usbd_xfer_handle xfer, usbd_private_handle priv,
877 1.21 christos usbd_status status)
878 1.1 ichiro {
879 1.24.10.2 itohy struct ue_chain *c = priv;
880 1.24.10.2 itohy struct url_softc *sc = (void *)c->ue_dev;
881 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
882 1.1 ichiro int s;
883 1.1 ichiro
884 1.1 ichiro if (sc->sc_dying)
885 1.1 ichiro return;
886 1.1 ichiro
887 1.1 ichiro s = splnet();
888 1.1 ichiro
889 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
890 1.1 ichiro
891 1.1 ichiro ifp->if_timer = 0;
892 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
893 1.1 ichiro
894 1.24.10.2 itohy usbd_unmap_buffer(xfer);
895 1.24.10.2 itohy
896 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
897 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
898 1.1 ichiro splx(s);
899 1.1 ichiro return;
900 1.1 ichiro }
901 1.1 ichiro ifp->if_oerrors++;
902 1.1 ichiro printf("%s: usb error on tx: %s\n", USBDEVNAME(sc->sc_dev),
903 1.1 ichiro usbd_errstr(status));
904 1.1 ichiro if (status == USBD_STALLED) {
905 1.1 ichiro sc->sc_refcnt++;
906 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_tx);
907 1.1 ichiro if (--sc->sc_refcnt < 0)
908 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
909 1.1 ichiro }
910 1.1 ichiro splx(s);
911 1.1 ichiro return;
912 1.1 ichiro }
913 1.1 ichiro
914 1.1 ichiro ifp->if_opackets++;
915 1.1 ichiro
916 1.24.10.2 itohy m_freem(c->ue_mbuf);
917 1.24.10.2 itohy c->ue_mbuf = NULL;
918 1.1 ichiro
919 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
920 1.1 ichiro url_start(ifp);
921 1.1 ichiro
922 1.1 ichiro splx(s);
923 1.1 ichiro }
924 1.1 ichiro
925 1.1 ichiro Static void
926 1.1 ichiro url_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status)
927 1.1 ichiro {
928 1.24.10.2 itohy struct ue_chain *c = priv;
929 1.24.10.2 itohy struct url_softc *sc = (void *)c->ue_dev;
930 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
931 1.1 ichiro struct mbuf *m;
932 1.1 ichiro u_int32_t total_len;
933 1.1 ichiro url_rxhdr_t rxhdr;
934 1.1 ichiro int s;
935 1.1 ichiro
936 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),__func__));
937 1.1 ichiro
938 1.1 ichiro if (sc->sc_dying)
939 1.1 ichiro return;
940 1.1 ichiro
941 1.24.10.2 itohy usbd_unmap_buffer(xfer);
942 1.24.10.2 itohy
943 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
944 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
945 1.1 ichiro return;
946 1.1 ichiro sc->sc_rx_errs++;
947 1.1 ichiro if (usbd_ratecheck(&sc->sc_rx_notice)) {
948 1.1 ichiro printf("%s: %u usb errors on rx: %s\n",
949 1.1 ichiro USBDEVNAME(sc->sc_dev), sc->sc_rx_errs,
950 1.1 ichiro usbd_errstr(status));
951 1.1 ichiro sc->sc_rx_errs = 0;
952 1.1 ichiro }
953 1.1 ichiro if (status == USBD_STALLED) {
954 1.1 ichiro sc->sc_refcnt++;
955 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_rx);
956 1.1 ichiro if (--sc->sc_refcnt < 0)
957 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
958 1.1 ichiro }
959 1.1 ichiro goto done;
960 1.1 ichiro }
961 1.1 ichiro
962 1.1 ichiro usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
963 1.1 ichiro
964 1.1 ichiro if (total_len <= ETHER_CRC_LEN) {
965 1.1 ichiro ifp->if_ierrors++;
966 1.1 ichiro goto done;
967 1.1 ichiro }
968 1.1 ichiro
969 1.24.10.2 itohy m = c->ue_mbuf;
970 1.24.10.2 itohy
971 1.24.10.2 itohy memcpy(&rxhdr, mtod(m, char *) + total_len - ETHER_CRC_LEN,
972 1.24.10.2 itohy sizeof(rxhdr));
973 1.1 ichiro
974 1.1 ichiro DPRINTF(("%s: RX Status: %dbytes%s%s%s%s packets\n",
975 1.1 ichiro USBDEVNAME(sc->sc_dev),
976 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_BYTEC_MASK,
977 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_VALID_MASK ? ", Valid" : "",
978 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_RUNTPKT_MASK ? ", Runt" : "",
979 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_PHYPKT_MASK ? ", Physical match" : "",
980 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_MCASTPKT_MASK ? ", Multicast" : ""));
981 1.1 ichiro
982 1.1 ichiro if ((UGETW(rxhdr) & URL_RXHDR_VALID_MASK) == 0) {
983 1.1 ichiro ifp->if_ierrors++;
984 1.1 ichiro goto done;
985 1.1 ichiro }
986 1.1 ichiro
987 1.24.10.2 itohy /*
988 1.24.10.2 itohy * Allocate new mbuf cluster for the next transfer.
989 1.24.10.2 itohy * If that failed, discard current packet and recycle the mbuf.
990 1.24.10.2 itohy */
991 1.24.10.2 itohy if ((c->ue_mbuf = usb_ether_newbuf(NULL)) == NULL) {
992 1.24.10.2 itohy printf("%s: no memory for rx list -- packet dropped!\n",
993 1.24.10.2 itohy USBDEVNAME(sc->sc_dev));
994 1.24.10.2 itohy ifp->if_ierrors++;
995 1.24.10.2 itohy c->ue_mbuf = usb_ether_newbuf(m);
996 1.24.10.2 itohy goto done;
997 1.24.10.2 itohy }
998 1.24.10.2 itohy
999 1.1 ichiro ifp->if_ipackets++;
1000 1.1 ichiro total_len -= ETHER_CRC_LEN;
1001 1.1 ichiro
1002 1.1 ichiro m->m_pkthdr.len = m->m_len = total_len;
1003 1.1 ichiro m->m_pkthdr.rcvif = ifp;
1004 1.1 ichiro
1005 1.1 ichiro s = splnet();
1006 1.1 ichiro
1007 1.1 ichiro #if NBPFILTER > 0
1008 1.1 ichiro if (ifp->if_bpf)
1009 1.1 ichiro BPF_MTAP(ifp, m);
1010 1.1 ichiro #endif
1011 1.1 ichiro
1012 1.1 ichiro DPRINTF(("%s: %s: deliver %d\n", USBDEVNAME(sc->sc_dev),
1013 1.4 augustss __func__, m->m_len));
1014 1.1 ichiro IF_INPUT(ifp, m);
1015 1.1 ichiro
1016 1.1 ichiro splx(s);
1017 1.1 ichiro
1018 1.1 ichiro done:
1019 1.1 ichiro /* Setup new transfer */
1020 1.24.10.2 itohy (void)usbd_map_buffer_mbuf(xfer, c->ue_mbuf);
1021 1.24.10.2 itohy usbd_setup_xfer(xfer, sc->sc_pipe_rx, c, NULL /* XXX buf */, URL_BUFSZ,
1022 1.24.10.5 itohy USBD_SHORT_XFER_OK | USBD_NO_COPY
1023 1.24.10.5 itohy #ifdef __FreeBSD__ /* callback needs context */
1024 1.24.10.5 itohy | USBD_CALLBACK_AS_TASK
1025 1.24.10.5 itohy #endif
1026 1.24.10.5 itohy ,
1027 1.1 ichiro USBD_NO_TIMEOUT, url_rxeof);
1028 1.1 ichiro sc->sc_refcnt++;
1029 1.1 ichiro usbd_transfer(xfer);
1030 1.1 ichiro if (--sc->sc_refcnt < 0)
1031 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
1032 1.1 ichiro
1033 1.4 augustss DPRINTF(("%s: %s: start rx\n", USBDEVNAME(sc->sc_dev), __func__));
1034 1.1 ichiro }
1035 1.1 ichiro
1036 1.1 ichiro #if 0
1037 1.1 ichiro Static void url_intr()
1038 1.1 ichiro {
1039 1.1 ichiro }
1040 1.1 ichiro #endif
1041 1.1 ichiro
1042 1.1 ichiro Static int
1043 1.24.10.3 itohy url_ioctl(struct ifnet *ifp, u_long cmd, usb_ioctlarg_t data)
1044 1.1 ichiro {
1045 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1046 1.1 ichiro struct ifreq *ifr = (struct ifreq *)data;
1047 1.1 ichiro struct mii_data *mii;
1048 1.1 ichiro int s, error = 0;
1049 1.1 ichiro
1050 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1051 1.1 ichiro
1052 1.1 ichiro if (sc->sc_dying)
1053 1.1 ichiro return (EIO);
1054 1.1 ichiro
1055 1.1 ichiro s = splnet();
1056 1.1 ichiro
1057 1.1 ichiro switch (cmd) {
1058 1.1 ichiro case SIOCGIFMEDIA:
1059 1.1 ichiro case SIOCSIFMEDIA:
1060 1.1 ichiro mii = GET_MII(sc);
1061 1.1 ichiro error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1062 1.1 ichiro break;
1063 1.1 ichiro
1064 1.1 ichiro default:
1065 1.1 ichiro error = ether_ioctl(ifp, cmd, data);
1066 1.1 ichiro if (error == ENETRESET) {
1067 1.12 thorpej if (ifp->if_flags & IFF_RUNNING)
1068 1.12 thorpej url_setmulti(sc);
1069 1.1 ichiro error = 0;
1070 1.1 ichiro }
1071 1.1 ichiro break;
1072 1.1 ichiro }
1073 1.1 ichiro
1074 1.1 ichiro splx(s);
1075 1.1 ichiro
1076 1.1 ichiro return (error);
1077 1.1 ichiro }
1078 1.1 ichiro
1079 1.1 ichiro Static void
1080 1.1 ichiro url_watchdog(struct ifnet *ifp)
1081 1.1 ichiro {
1082 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1083 1.24.10.2 itohy struct ue_chain *c;
1084 1.1 ichiro usbd_status stat;
1085 1.1 ichiro int s;
1086 1.5 augustss
1087 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1088 1.1 ichiro
1089 1.1 ichiro ifp->if_oerrors++;
1090 1.1 ichiro printf("%s: watchdog timeout\n", USBDEVNAME(sc->sc_dev));
1091 1.1 ichiro
1092 1.1 ichiro s = splusb();
1093 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[0];
1094 1.24.10.2 itohy usbd_get_xfer_status(c->ue_xfer, NULL, NULL, NULL, &stat);
1095 1.24.10.2 itohy url_txeof(c->ue_xfer, c, stat);
1096 1.1 ichiro
1097 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1098 1.1 ichiro url_start(ifp);
1099 1.1 ichiro splx(s);
1100 1.1 ichiro }
1101 1.1 ichiro
1102 1.1 ichiro Static void
1103 1.1 ichiro url_stop_task(struct url_softc *sc)
1104 1.1 ichiro {
1105 1.1 ichiro url_stop(GET_IFP(sc), 1);
1106 1.1 ichiro }
1107 1.1 ichiro
1108 1.1 ichiro /* Stop the adapter and free any mbufs allocated to the RX and TX lists. */
1109 1.1 ichiro Static void
1110 1.23 christos url_stop(struct ifnet *ifp, int disable)
1111 1.1 ichiro {
1112 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1113 1.1 ichiro usbd_status err;
1114 1.5 augustss
1115 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1116 1.1 ichiro
1117 1.1 ichiro ifp->if_timer = 0;
1118 1.1 ichiro
1119 1.1 ichiro url_reset(sc);
1120 1.1 ichiro
1121 1.1 ichiro usb_uncallout(sc->sc_stat_ch, url_tick, sc);
1122 1.1 ichiro
1123 1.1 ichiro /* Stop transfers */
1124 1.1 ichiro /* RX endpoint */
1125 1.1 ichiro if (sc->sc_pipe_rx != NULL) {
1126 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_rx);
1127 1.1 ichiro if (err)
1128 1.1 ichiro printf("%s: abort rx pipe failed: %s\n",
1129 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1130 1.24.10.2 itohy }
1131 1.24.10.2 itohy
1132 1.24.10.2 itohy /* TX endpoint */
1133 1.24.10.2 itohy if (sc->sc_pipe_tx != NULL) {
1134 1.24.10.2 itohy err = usbd_abort_pipe(sc->sc_pipe_tx);
1135 1.24.10.2 itohy if (err)
1136 1.24.10.2 itohy printf("%s: abort tx pipe failed: %s\n",
1137 1.24.10.2 itohy USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1138 1.24.10.2 itohy }
1139 1.24.10.2 itohy
1140 1.24.10.2 itohy #if 0
1141 1.24.10.2 itohy /* XXX: Interrupt endpoint is not yet supported!! */
1142 1.24.10.2 itohy /* Interrupt endpoint */
1143 1.24.10.2 itohy if (sc->sc_pipe_intr != NULL) {
1144 1.24.10.2 itohy err = usbd_abort_pipe(sc->sc_pipe_intr);
1145 1.24.10.2 itohy if (err)
1146 1.24.10.2 itohy printf("%s: abort intr pipe failed: %s\n",
1147 1.24.10.2 itohy USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1148 1.24.10.2 itohy #endif
1149 1.24.10.2 itohy
1150 1.24.10.2 itohy /* Free RX/TX resources. */
1151 1.24.10.2 itohy usb_ether_rx_list_free(sc->sc_cdata.url_rx_chain, URL_RX_LIST_CNT);
1152 1.24.10.2 itohy usb_ether_tx_list_free(sc->sc_cdata.url_tx_chain, URL_TX_LIST_CNT);
1153 1.24.10.2 itohy
1154 1.24.10.2 itohy /* Close pipes. */
1155 1.24.10.2 itohy /* RX endpoint */
1156 1.24.10.2 itohy if (sc->sc_pipe_rx != NULL) {
1157 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_rx);
1158 1.1 ichiro if (err)
1159 1.1 ichiro printf("%s: close rx pipe failed: %s\n",
1160 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1161 1.1 ichiro sc->sc_pipe_rx = NULL;
1162 1.1 ichiro }
1163 1.1 ichiro
1164 1.1 ichiro /* TX endpoint */
1165 1.1 ichiro if (sc->sc_pipe_tx != NULL) {
1166 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_tx);
1167 1.1 ichiro if (err)
1168 1.1 ichiro printf("%s: close tx pipe failed: %s\n",
1169 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1170 1.1 ichiro sc->sc_pipe_tx = NULL;
1171 1.1 ichiro }
1172 1.1 ichiro
1173 1.1 ichiro #if 0
1174 1.1 ichiro /* XXX: Interrupt endpoint is not yet supported!! */
1175 1.1 ichiro /* Interrupt endpoint */
1176 1.1 ichiro if (sc->sc_pipe_intr != NULL) {
1177 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_intr);
1178 1.1 ichiro if (err)
1179 1.1 ichiro printf("%s: close intr pipe failed: %s\n",
1180 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1181 1.1 ichiro sc->sc_pipe_intr = NULL;
1182 1.1 ichiro }
1183 1.1 ichiro #endif
1184 1.1 ichiro
1185 1.1 ichiro sc->sc_link = 0;
1186 1.1 ichiro ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1187 1.1 ichiro }
1188 1.1 ichiro
1189 1.1 ichiro /* Set media options */
1190 1.1 ichiro Static int
1191 1.1 ichiro url_ifmedia_change(struct ifnet *ifp)
1192 1.1 ichiro {
1193 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1194 1.1 ichiro struct mii_data *mii = GET_MII(sc);
1195 1.1 ichiro
1196 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1197 1.1 ichiro
1198 1.1 ichiro if (sc->sc_dying)
1199 1.1 ichiro return (0);
1200 1.1 ichiro
1201 1.1 ichiro sc->sc_link = 0;
1202 1.1 ichiro if (mii->mii_instance) {
1203 1.1 ichiro struct mii_softc *miisc;
1204 1.1 ichiro for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1205 1.1 ichiro miisc = LIST_NEXT(miisc, mii_list))
1206 1.1 ichiro mii_phy_reset(miisc);
1207 1.1 ichiro }
1208 1.1 ichiro
1209 1.1 ichiro return (mii_mediachg(mii));
1210 1.1 ichiro }
1211 1.1 ichiro
1212 1.1 ichiro /* Report current media status. */
1213 1.1 ichiro Static void
1214 1.1 ichiro url_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1215 1.1 ichiro {
1216 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1217 1.1 ichiro struct mii_data *mii = GET_MII(sc);
1218 1.1 ichiro
1219 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1220 1.1 ichiro
1221 1.1 ichiro if (sc->sc_dying)
1222 1.1 ichiro return;
1223 1.1 ichiro
1224 1.1 ichiro if ((ifp->if_flags & IFF_RUNNING) == 0) {
1225 1.1 ichiro ifmr->ifm_active = IFM_ETHER | IFM_NONE;
1226 1.1 ichiro ifmr->ifm_status = 0;
1227 1.1 ichiro return;
1228 1.1 ichiro }
1229 1.1 ichiro
1230 1.1 ichiro mii_pollstat(mii);
1231 1.1 ichiro ifmr->ifm_active = mii->mii_media_active;
1232 1.1 ichiro ifmr->ifm_status = mii->mii_media_status;
1233 1.1 ichiro }
1234 1.1 ichiro
1235 1.1 ichiro Static void
1236 1.1 ichiro url_tick(void *xsc)
1237 1.1 ichiro {
1238 1.1 ichiro struct url_softc *sc = xsc;
1239 1.1 ichiro
1240 1.1 ichiro if (sc == NULL)
1241 1.1 ichiro return;
1242 1.1 ichiro
1243 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1244 1.4 augustss __func__));
1245 1.1 ichiro
1246 1.1 ichiro if (sc->sc_dying)
1247 1.1 ichiro return;
1248 1.1 ichiro
1249 1.1 ichiro /* Perform periodic stuff in process context */
1250 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_tick_task, USB_TASKQ_DRIVER);
1251 1.1 ichiro }
1252 1.1 ichiro
1253 1.1 ichiro Static void
1254 1.1 ichiro url_tick_task(void *xsc)
1255 1.1 ichiro {
1256 1.1 ichiro struct url_softc *sc = xsc;
1257 1.1 ichiro struct ifnet *ifp;
1258 1.1 ichiro struct mii_data *mii;
1259 1.1 ichiro int s;
1260 1.1 ichiro
1261 1.1 ichiro if (sc == NULL)
1262 1.1 ichiro return;
1263 1.1 ichiro
1264 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1265 1.4 augustss __func__));
1266 1.1 ichiro
1267 1.1 ichiro if (sc->sc_dying)
1268 1.1 ichiro return;
1269 1.1 ichiro
1270 1.1 ichiro ifp = GET_IFP(sc);
1271 1.1 ichiro mii = GET_MII(sc);
1272 1.1 ichiro
1273 1.1 ichiro if (mii == NULL)
1274 1.1 ichiro return;
1275 1.1 ichiro
1276 1.1 ichiro s = splnet();
1277 1.1 ichiro
1278 1.1 ichiro mii_tick(mii);
1279 1.1 ichiro if (!sc->sc_link) {
1280 1.1 ichiro mii_pollstat(mii);
1281 1.1 ichiro if (mii->mii_media_status & IFM_ACTIVE &&
1282 1.1 ichiro IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1283 1.1 ichiro DPRINTF(("%s: %s: got link\n",
1284 1.4 augustss USBDEVNAME(sc->sc_dev), __func__));
1285 1.1 ichiro sc->sc_link++;
1286 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1287 1.1 ichiro url_start(ifp);
1288 1.1 ichiro }
1289 1.1 ichiro }
1290 1.1 ichiro
1291 1.1 ichiro usb_callout(sc->sc_stat_ch, hz, url_tick, sc);
1292 1.1 ichiro
1293 1.1 ichiro splx(s);
1294 1.1 ichiro }
1295 1.1 ichiro
1296 1.1 ichiro /* Get exclusive access to the MII registers */
1297 1.1 ichiro Static void
1298 1.1 ichiro url_lock_mii(struct url_softc *sc)
1299 1.1 ichiro {
1300 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1301 1.4 augustss __func__));
1302 1.1 ichiro
1303 1.1 ichiro sc->sc_refcnt++;
1304 1.1 ichiro lockmgr(&sc->sc_mii_lock, LK_EXCLUSIVE, NULL);
1305 1.1 ichiro }
1306 1.1 ichiro
1307 1.1 ichiro Static void
1308 1.1 ichiro url_unlock_mii(struct url_softc *sc)
1309 1.1 ichiro {
1310 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1311 1.4 augustss __func__));
1312 1.1 ichiro
1313 1.1 ichiro lockmgr(&sc->sc_mii_lock, LK_RELEASE, NULL);
1314 1.1 ichiro if (--sc->sc_refcnt < 0)
1315 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
1316 1.1 ichiro }
1317 1.1 ichiro
1318 1.1 ichiro Static int
1319 1.1 ichiro url_int_miibus_readreg(device_ptr_t dev, int phy, int reg)
1320 1.1 ichiro {
1321 1.1 ichiro struct url_softc *sc;
1322 1.1 ichiro u_int16_t val;
1323 1.1 ichiro
1324 1.1 ichiro if (dev == NULL)
1325 1.1 ichiro return (0);
1326 1.1 ichiro
1327 1.1 ichiro sc = USBGETSOFTC(dev);
1328 1.1 ichiro
1329 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x\n",
1330 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg));
1331 1.1 ichiro
1332 1.1 ichiro if (sc->sc_dying) {
1333 1.1 ichiro #ifdef DIAGNOSTIC
1334 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1335 1.4 augustss __func__);
1336 1.1 ichiro #endif
1337 1.1 ichiro return (0);
1338 1.1 ichiro }
1339 1.1 ichiro
1340 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1341 1.1 ichiro if (phy != 0) {
1342 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1343 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy));
1344 1.1 ichiro return (0);
1345 1.1 ichiro }
1346 1.1 ichiro
1347 1.1 ichiro url_lock_mii(sc);
1348 1.1 ichiro
1349 1.1 ichiro switch (reg) {
1350 1.1 ichiro case MII_BMCR: /* Control Register */
1351 1.1 ichiro reg = URL_BMCR;
1352 1.1 ichiro break;
1353 1.1 ichiro case MII_BMSR: /* Status Register */
1354 1.1 ichiro reg = URL_BMSR;
1355 1.1 ichiro break;
1356 1.1 ichiro case MII_PHYIDR1:
1357 1.1 ichiro case MII_PHYIDR2:
1358 1.1 ichiro val = 0;
1359 1.1 ichiro goto R_DONE;
1360 1.1 ichiro break;
1361 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1362 1.1 ichiro reg = URL_ANAR;
1363 1.1 ichiro break;
1364 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1365 1.1 ichiro reg = URL_ANLP;
1366 1.1 ichiro break;
1367 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1368 1.1 ichiro reg = URL_MSR;
1369 1.1 ichiro break;
1370 1.1 ichiro default:
1371 1.1 ichiro printf("%s: %s: bad register %04x\n",
1372 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, reg);
1373 1.1 ichiro val = 0;
1374 1.1 ichiro goto R_DONE;
1375 1.1 ichiro break;
1376 1.1 ichiro }
1377 1.1 ichiro
1378 1.1 ichiro if (reg == URL_MSR)
1379 1.1 ichiro val = url_csr_read_1(sc, reg);
1380 1.1 ichiro else
1381 1.1 ichiro val = url_csr_read_2(sc, reg);
1382 1.1 ichiro
1383 1.1 ichiro R_DONE:
1384 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1385 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, val));
1386 1.1 ichiro
1387 1.1 ichiro url_unlock_mii(sc);
1388 1.1 ichiro return (val);
1389 1.1 ichiro }
1390 1.1 ichiro
1391 1.1 ichiro Static void
1392 1.1 ichiro url_int_miibus_writereg(device_ptr_t dev, int phy, int reg, int data)
1393 1.1 ichiro {
1394 1.1 ichiro struct url_softc *sc;
1395 1.1 ichiro
1396 1.1 ichiro if (dev == NULL)
1397 1.1 ichiro return;
1398 1.1 ichiro
1399 1.1 ichiro sc = USBGETSOFTC(dev);
1400 1.1 ichiro
1401 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1402 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, data));
1403 1.1 ichiro
1404 1.1 ichiro if (sc->sc_dying) {
1405 1.1 ichiro #ifdef DIAGNOSTIC
1406 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1407 1.4 augustss __func__);
1408 1.1 ichiro #endif
1409 1.1 ichiro return;
1410 1.1 ichiro }
1411 1.1 ichiro
1412 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1413 1.1 ichiro if (phy != 0) {
1414 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1415 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy));
1416 1.1 ichiro return;
1417 1.1 ichiro }
1418 1.1 ichiro
1419 1.1 ichiro url_lock_mii(sc);
1420 1.1 ichiro
1421 1.1 ichiro switch (reg) {
1422 1.1 ichiro case MII_BMCR: /* Control Register */
1423 1.1 ichiro reg = URL_BMCR;
1424 1.1 ichiro break;
1425 1.1 ichiro case MII_BMSR: /* Status Register */
1426 1.1 ichiro reg = URL_BMSR;
1427 1.1 ichiro break;
1428 1.1 ichiro case MII_PHYIDR1:
1429 1.1 ichiro case MII_PHYIDR2:
1430 1.1 ichiro goto W_DONE;
1431 1.1 ichiro break;
1432 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1433 1.1 ichiro reg = URL_ANAR;
1434 1.1 ichiro break;
1435 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1436 1.1 ichiro reg = URL_ANLP;
1437 1.1 ichiro break;
1438 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1439 1.1 ichiro reg = URL_MSR;
1440 1.1 ichiro break;
1441 1.1 ichiro default:
1442 1.1 ichiro printf("%s: %s: bad register %04x\n",
1443 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, reg);
1444 1.1 ichiro goto W_DONE;
1445 1.1 ichiro break;
1446 1.1 ichiro }
1447 1.1 ichiro
1448 1.1 ichiro if (reg == URL_MSR)
1449 1.1 ichiro url_csr_write_1(sc, reg, data);
1450 1.1 ichiro else
1451 1.1 ichiro url_csr_write_2(sc, reg, data);
1452 1.1 ichiro W_DONE:
1453 1.1 ichiro
1454 1.1 ichiro url_unlock_mii(sc);
1455 1.1 ichiro return;
1456 1.1 ichiro }
1457 1.1 ichiro
1458 1.1 ichiro Static void
1459 1.23 christos url_miibus_statchg(device_ptr_t dev)
1460 1.1 ichiro {
1461 1.1 ichiro #ifdef URL_DEBUG
1462 1.1 ichiro struct url_softc *sc;
1463 1.1 ichiro
1464 1.1 ichiro if (dev == NULL)
1465 1.1 ichiro return;
1466 1.1 ichiro
1467 1.1 ichiro sc = USBGETSOFTC(dev);
1468 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1469 1.1 ichiro #endif
1470 1.1 ichiro /* Nothing to do */
1471 1.1 ichiro }
1472 1.1 ichiro
1473 1.1 ichiro #if 0
1474 1.1 ichiro /*
1475 1.1 ichiro * external PHYs support, but not test.
1476 1.1 ichiro */
1477 1.1 ichiro Static int
1478 1.1 ichiro url_ext_miibus_redreg(device_ptr_t dev, int phy, int reg)
1479 1.1 ichiro {
1480 1.1 ichiro struct url_softc *sc = USBGETSOFTC(dev);
1481 1.1 ichiro u_int16_t val;
1482 1.1 ichiro
1483 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x\n",
1484 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg));
1485 1.1 ichiro
1486 1.1 ichiro if (sc->sc_dying) {
1487 1.1 ichiro #ifdef DIAGNOSTIC
1488 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1489 1.4 augustss __func__);
1490 1.1 ichiro #endif
1491 1.1 ichiro return (0);
1492 1.1 ichiro }
1493 1.1 ichiro
1494 1.1 ichiro url_lock_mii(sc);
1495 1.1 ichiro
1496 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy & URL_PHYADD_MASK);
1497 1.1 ichiro /*
1498 1.1 ichiro * RTL8150L will initiate a MII management data transaction
1499 1.1 ichiro * if PHYCNT_OWN bit is set 1 by software. After transaction,
1500 1.1 ichiro * this bit is auto cleared by TRL8150L.
1501 1.1 ichiro */
1502 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT,
1503 1.1 ichiro (reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
1504 1.1 ichiro for (i = 0; i < URL_TIMEOUT; i++) {
1505 1.1 ichiro if ((url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN) == 0)
1506 1.1 ichiro break;
1507 1.1 ichiro }
1508 1.1 ichiro if (i == URL_TIMEOUT) {
1509 1.1 ichiro printf("%s: MII read timed out\n", USBDEVNAME(sc->sc_dev));
1510 1.1 ichiro }
1511 1.5 augustss
1512 1.1 ichiro val = url_csr_read_2(sc, URL_PHYDAT);
1513 1.1 ichiro
1514 1.1 ichiro DPRINTF(("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1515 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, val));
1516 1.1 ichiro
1517 1.1 ichiro url_unlock_mii(sc);
1518 1.1 ichiro return (val);
1519 1.1 ichiro }
1520 1.1 ichiro
1521 1.1 ichiro Static void
1522 1.1 ichiro url_ext_miibus_writereg(device_ptr_t dev, int phy, int reg, int data)
1523 1.1 ichiro {
1524 1.1 ichiro struct url_softc *sc = USBGETSOFTC(dev);
1525 1.1 ichiro
1526 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1527 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, data));
1528 1.1 ichiro
1529 1.1 ichiro if (sc->sc_dying) {
1530 1.1 ichiro #ifdef DIAGNOSTIC
1531 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1532 1.4 augustss __func__);
1533 1.1 ichiro #endif
1534 1.1 ichiro return;
1535 1.1 ichiro }
1536 1.1 ichiro
1537 1.1 ichiro url_lock_mii(sc);
1538 1.1 ichiro
1539 1.1 ichiro url_csr_write_2(sc, URL_PHYDAT, data);
1540 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy);
1541 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */
1542 1.1 ichiro
1543 1.1 ichiro for (i=0; i < URL_TIMEOUT; i++) {
1544 1.1 ichiro if (url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN)
1545 1.1 ichiro break;
1546 1.1 ichiro }
1547 1.1 ichiro
1548 1.1 ichiro if (i == URL_TIMEOUT) {
1549 1.1 ichiro printf("%s: MII write timed out\n",
1550 1.1 ichiro USBDEVNAME(sc->sc_dev));
1551 1.1 ichiro }
1552 1.1 ichiro
1553 1.1 ichiro url_unlock_mii(sc);
1554 1.1 ichiro return;
1555 1.1 ichiro }
1556 1.1 ichiro #endif
1557 1.1 ichiro
1558