if_url.c revision 1.37 1 1.37 joerg /* $NetBSD: if_url.c,v 1.37 2010/04/05 07:21:48 joerg Exp $ */
2 1.1 ichiro /*
3 1.1 ichiro * Copyright (c) 2001, 2002
4 1.1 ichiro * Shingo WATANABE <nabe (at) nabechan.org>. All rights reserved.
5 1.1 ichiro *
6 1.1 ichiro * Redistribution and use in source and binary forms, with or without
7 1.1 ichiro * modification, are permitted provided that the following conditions
8 1.1 ichiro * are met:
9 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
10 1.1 ichiro * notice, this list of conditions and the following disclaimer.
11 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
13 1.1 ichiro * documentation and/or other materials provided with the distribution.
14 1.8 tsutsui * 3. Neither the name of the author nor the names of any co-contributors
15 1.1 ichiro * may be used to endorse or promote products derived from this software
16 1.1 ichiro * without specific prior written permission.
17 1.1 ichiro *
18 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 1.1 ichiro * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 ichiro * SUCH DAMAGE.
29 1.1 ichiro *
30 1.1 ichiro */
31 1.1 ichiro
32 1.1 ichiro /*
33 1.1 ichiro * The RTL8150L(Realtek USB to fast ethernet controller) spec can be found at
34 1.1 ichiro * ftp://ftp.realtek.com.tw/lancard/data_sheet/8150/8150v14.pdf
35 1.1 ichiro * ftp://152.104.125.40/lancard/data_sheet/8150/8150v14.pdf
36 1.1 ichiro */
37 1.1 ichiro
38 1.1 ichiro /*
39 1.1 ichiro * TODO:
40 1.1 ichiro * Interrupt Endpoint support
41 1.1 ichiro * External PHYs
42 1.1 ichiro * powerhook() support?
43 1.1 ichiro */
44 1.1 ichiro
45 1.1 ichiro #include <sys/cdefs.h>
46 1.37 joerg __KERNEL_RCSID(0, "$NetBSD: if_url.c,v 1.37 2010/04/05 07:21:48 joerg Exp $");
47 1.1 ichiro
48 1.1 ichiro #include "opt_inet.h"
49 1.1 ichiro #include "rnd.h"
50 1.1 ichiro
51 1.1 ichiro #include <sys/param.h>
52 1.1 ichiro #include <sys/systm.h>
53 1.27 xtraeme #include <sys/rwlock.h>
54 1.1 ichiro #include <sys/mbuf.h>
55 1.1 ichiro #include <sys/kernel.h>
56 1.1 ichiro #include <sys/socket.h>
57 1.1 ichiro
58 1.1 ichiro #include <sys/device.h>
59 1.1 ichiro #if NRND > 0
60 1.1 ichiro #include <sys/rnd.h>
61 1.1 ichiro #endif
62 1.1 ichiro
63 1.1 ichiro #include <net/if.h>
64 1.1 ichiro #include <net/if_arp.h>
65 1.1 ichiro #include <net/if_dl.h>
66 1.1 ichiro #include <net/if_media.h>
67 1.1 ichiro
68 1.1 ichiro #include <net/bpf.h>
69 1.1 ichiro
70 1.1 ichiro #include <net/if_ether.h>
71 1.1 ichiro #ifdef INET
72 1.1 ichiro #include <netinet/in.h>
73 1.1 ichiro #include <netinet/if_inarp.h>
74 1.1 ichiro #endif
75 1.1 ichiro
76 1.1 ichiro #include <dev/mii/mii.h>
77 1.1 ichiro #include <dev/mii/miivar.h>
78 1.1 ichiro #include <dev/mii/urlphyreg.h>
79 1.1 ichiro
80 1.1 ichiro #include <dev/usb/usb.h>
81 1.1 ichiro #include <dev/usb/usbdi.h>
82 1.1 ichiro #include <dev/usb/usbdi_util.h>
83 1.1 ichiro #include <dev/usb/usbdevs.h>
84 1.1 ichiro
85 1.1 ichiro #include <dev/usb/if_urlreg.h>
86 1.1 ichiro
87 1.1 ichiro
88 1.1 ichiro /* Function declarations */
89 1.1 ichiro USB_DECLARE_DRIVER(url);
90 1.1 ichiro
91 1.1 ichiro Static int url_openpipes(struct url_softc *);
92 1.1 ichiro Static int url_rx_list_init(struct url_softc *);
93 1.1 ichiro Static int url_tx_list_init(struct url_softc *);
94 1.1 ichiro Static int url_newbuf(struct url_softc *, struct url_chain *, struct mbuf *);
95 1.1 ichiro Static void url_start(struct ifnet *);
96 1.1 ichiro Static int url_send(struct url_softc *, struct mbuf *, int);
97 1.1 ichiro Static void url_txeof(usbd_xfer_handle, usbd_private_handle, usbd_status);
98 1.1 ichiro Static void url_rxeof(usbd_xfer_handle, usbd_private_handle, usbd_status);
99 1.1 ichiro Static void url_tick(void *);
100 1.1 ichiro Static void url_tick_task(void *);
101 1.25 christos Static int url_ioctl(struct ifnet *, u_long, void *);
102 1.1 ichiro Static void url_stop_task(struct url_softc *);
103 1.1 ichiro Static void url_stop(struct ifnet *, int);
104 1.1 ichiro Static void url_watchdog(struct ifnet *);
105 1.1 ichiro Static int url_ifmedia_change(struct ifnet *);
106 1.1 ichiro Static void url_ifmedia_status(struct ifnet *, struct ifmediareq *);
107 1.1 ichiro Static void url_lock_mii(struct url_softc *);
108 1.1 ichiro Static void url_unlock_mii(struct url_softc *);
109 1.1 ichiro Static int url_int_miibus_readreg(device_ptr_t, int, int);
110 1.1 ichiro Static void url_int_miibus_writereg(device_ptr_t, int, int, int);
111 1.1 ichiro Static void url_miibus_statchg(device_ptr_t);
112 1.1 ichiro Static int url_init(struct ifnet *);
113 1.1 ichiro Static void url_setmulti(struct url_softc *);
114 1.1 ichiro Static void url_reset(struct url_softc *);
115 1.1 ichiro
116 1.1 ichiro Static int url_csr_read_1(struct url_softc *, int);
117 1.1 ichiro Static int url_csr_read_2(struct url_softc *, int);
118 1.1 ichiro Static int url_csr_write_1(struct url_softc *, int, int);
119 1.1 ichiro Static int url_csr_write_2(struct url_softc *, int, int);
120 1.1 ichiro Static int url_csr_write_4(struct url_softc *, int, int);
121 1.1 ichiro Static int url_mem(struct url_softc *, int, int, void *, int);
122 1.1 ichiro
123 1.1 ichiro /* Macros */
124 1.1 ichiro #ifdef URL_DEBUG
125 1.2 ichiro #define DPRINTF(x) if (urldebug) logprintf x
126 1.2 ichiro #define DPRINTFN(n,x) if (urldebug >= (n)) logprintf x
127 1.2 ichiro int urldebug = 0;
128 1.1 ichiro #else
129 1.1 ichiro #define DPRINTF(x)
130 1.1 ichiro #define DPRINTFN(n,x)
131 1.1 ichiro #endif
132 1.1 ichiro
133 1.1 ichiro #define URL_SETBIT(sc, reg, x) \
134 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) | (x))
135 1.1 ichiro
136 1.1 ichiro #define URL_SETBIT2(sc, reg, x) \
137 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) | (x))
138 1.1 ichiro
139 1.1 ichiro #define URL_CLRBIT(sc, reg, x) \
140 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) & ~(x))
141 1.1 ichiro
142 1.1 ichiro #define URL_CLRBIT2(sc, reg, x) \
143 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) & ~(x))
144 1.1 ichiro
145 1.1 ichiro static const struct url_type {
146 1.1 ichiro struct usb_devno url_dev;
147 1.1 ichiro u_int16_t url_flags;
148 1.1 ichiro #define URL_EXT_PHY 0x0001
149 1.1 ichiro } url_devs [] = {
150 1.1 ichiro /* MELCO LUA-KTX */
151 1.1 ichiro {{ USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAKTX }, 0},
152 1.10 mycroft /* Realtek RTL8150L Generic (GREEN HOUSE USBKR100) */
153 1.11 augustss {{ USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8150L}, 0},
154 1.11 augustss /* Longshine LCS-8138TX */
155 1.11 augustss {{ USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_LCS8138TX}, 0},
156 1.11 augustss /* Micronet SP128AR */
157 1.11 augustss {{ USB_VENDOR_MICRONET, USB_PRODUCT_MICRONET_SP128AR}, 0},
158 1.13 itojun /* OQO model 01 */
159 1.13 itojun {{ USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01}, 0},
160 1.1 ichiro };
161 1.17 christos #define url_lookup(v, p) ((const struct url_type *)usb_lookup(url_devs, v, p))
162 1.1 ichiro
163 1.1 ichiro
164 1.1 ichiro /* Probe */
165 1.1 ichiro USB_MATCH(url)
166 1.1 ichiro {
167 1.1 ichiro USB_MATCH_START(url, uaa);
168 1.1 ichiro
169 1.1 ichiro return (url_lookup(uaa->vendor, uaa->product) != NULL ?
170 1.1 ichiro UMATCH_VENDOR_PRODUCT : UMATCH_NONE);
171 1.1 ichiro }
172 1.1 ichiro /* Attach */
173 1.1 ichiro USB_ATTACH(url)
174 1.1 ichiro {
175 1.1 ichiro USB_ATTACH_START(url, sc, uaa);
176 1.1 ichiro usbd_device_handle dev = uaa->device;
177 1.1 ichiro usbd_interface_handle iface;
178 1.1 ichiro usbd_status err;
179 1.1 ichiro usb_interface_descriptor_t *id;
180 1.1 ichiro usb_endpoint_descriptor_t *ed;
181 1.16 augustss char *devinfop;
182 1.1 ichiro struct ifnet *ifp;
183 1.1 ichiro struct mii_data *mii;
184 1.1 ichiro u_char eaddr[ETHER_ADDR_LEN];
185 1.1 ichiro int i, s;
186 1.1 ichiro
187 1.32 cube sc->sc_dev = self;
188 1.32 cube
189 1.34 plunky aprint_naive("\n");
190 1.34 plunky aprint_normal("\n");
191 1.34 plunky
192 1.16 augustss devinfop = usbd_devinfo_alloc(dev, 0);
193 1.32 cube aprint_normal_dev(self, "%s\n", devinfop);
194 1.16 augustss usbd_devinfo_free(devinfop);
195 1.1 ichiro
196 1.1 ichiro /* Move the device into the configured state. */
197 1.1 ichiro err = usbd_set_config_no(dev, URL_CONFIG_NO, 1);
198 1.1 ichiro if (err) {
199 1.32 cube aprint_error_dev(self, "setting config no failed\n");
200 1.1 ichiro goto bad;
201 1.1 ichiro }
202 1.1 ichiro
203 1.1 ichiro usb_init_task(&sc->sc_tick_task, url_tick_task, sc);
204 1.27 xtraeme rw_init(&sc->sc_mii_rwlock);
205 1.1 ichiro usb_init_task(&sc->sc_stop_task, (void (*)(void *)) url_stop_task, sc);
206 1.1 ichiro
207 1.1 ichiro /* get control interface */
208 1.1 ichiro err = usbd_device2interface_handle(dev, URL_IFACE_INDEX, &iface);
209 1.1 ichiro if (err) {
210 1.32 cube aprint_error_dev(self, "failed to get interface, err=%s\n",
211 1.1 ichiro usbd_errstr(err));
212 1.1 ichiro goto bad;
213 1.1 ichiro }
214 1.1 ichiro
215 1.1 ichiro sc->sc_udev = dev;
216 1.1 ichiro sc->sc_ctl_iface = iface;
217 1.1 ichiro sc->sc_flags = url_lookup(uaa->vendor, uaa->product)->url_flags;
218 1.1 ichiro
219 1.1 ichiro /* get interface descriptor */
220 1.1 ichiro id = usbd_get_interface_descriptor(sc->sc_ctl_iface);
221 1.1 ichiro
222 1.1 ichiro /* find endpoints */
223 1.1 ichiro sc->sc_bulkin_no = sc->sc_bulkout_no = sc->sc_intrin_no = -1;
224 1.1 ichiro for (i = 0; i < id->bNumEndpoints; i++) {
225 1.1 ichiro ed = usbd_interface2endpoint_descriptor(sc->sc_ctl_iface, i);
226 1.1 ichiro if (ed == NULL) {
227 1.32 cube aprint_error_dev(self,
228 1.32 cube "couldn't get endpoint %d\n", i);
229 1.1 ichiro goto bad;
230 1.1 ichiro }
231 1.1 ichiro if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
232 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
233 1.1 ichiro sc->sc_bulkin_no = ed->bEndpointAddress; /* RX */
234 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
235 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)
236 1.1 ichiro sc->sc_bulkout_no = ed->bEndpointAddress; /* TX */
237 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_INTERRUPT &&
238 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
239 1.1 ichiro sc->sc_intrin_no = ed->bEndpointAddress; /* Status */
240 1.1 ichiro }
241 1.1 ichiro
242 1.1 ichiro if (sc->sc_bulkin_no == -1 || sc->sc_bulkout_no == -1 ||
243 1.1 ichiro sc->sc_intrin_no == -1) {
244 1.32 cube aprint_error_dev(self, "missing endpoint\n");
245 1.1 ichiro goto bad;
246 1.1 ichiro }
247 1.1 ichiro
248 1.1 ichiro s = splnet();
249 1.1 ichiro
250 1.1 ichiro /* reset the adapter */
251 1.1 ichiro url_reset(sc);
252 1.1 ichiro
253 1.1 ichiro /* Get Ethernet Address */
254 1.1 ichiro err = url_mem(sc, URL_CMD_READMEM, URL_IDR0, (void *)eaddr,
255 1.1 ichiro ETHER_ADDR_LEN);
256 1.1 ichiro if (err) {
257 1.32 cube aprint_error_dev(self, "read MAC address failed\n");
258 1.1 ichiro splx(s);
259 1.1 ichiro goto bad;
260 1.1 ichiro }
261 1.1 ichiro
262 1.1 ichiro /* Print Ethernet Address */
263 1.32 cube aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
264 1.1 ichiro
265 1.19 wiz /* initialize interface information */
266 1.1 ichiro ifp = GET_IFP(sc);
267 1.1 ichiro ifp->if_softc = sc;
268 1.3 augustss ifp->if_mtu = ETHERMTU;
269 1.32 cube strncpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
270 1.1 ichiro ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
271 1.1 ichiro ifp->if_start = url_start;
272 1.1 ichiro ifp->if_ioctl = url_ioctl;
273 1.1 ichiro ifp->if_watchdog = url_watchdog;
274 1.1 ichiro ifp->if_init = url_init;
275 1.1 ichiro ifp->if_stop = url_stop;
276 1.1 ichiro
277 1.1 ichiro IFQ_SET_READY(&ifp->if_snd);
278 1.1 ichiro
279 1.1 ichiro /*
280 1.1 ichiro * Do ifmedia setup.
281 1.1 ichiro */
282 1.1 ichiro mii = &sc->sc_mii;
283 1.1 ichiro mii->mii_ifp = ifp;
284 1.1 ichiro mii->mii_readreg = url_int_miibus_readreg;
285 1.1 ichiro mii->mii_writereg = url_int_miibus_writereg;
286 1.1 ichiro #if 0
287 1.1 ichiro if (sc->sc_flags & URL_EXT_PHY) {
288 1.1 ichiro mii->mii_readreg = url_ext_miibus_readreg;
289 1.1 ichiro mii->mii_writereg = url_ext_miibus_writereg;
290 1.1 ichiro }
291 1.1 ichiro #endif
292 1.1 ichiro mii->mii_statchg = url_miibus_statchg;
293 1.1 ichiro mii->mii_flags = MIIF_AUTOTSLEEP;
294 1.30 dyoung sc->sc_ec.ec_mii = mii;
295 1.1 ichiro ifmedia_init(&mii->mii_media, 0,
296 1.1 ichiro url_ifmedia_change, url_ifmedia_status);
297 1.1 ichiro mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
298 1.1 ichiro if (LIST_FIRST(&mii->mii_phys) == NULL) {
299 1.1 ichiro ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
300 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
301 1.1 ichiro } else
302 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
303 1.1 ichiro
304 1.1 ichiro /* attach the interface */
305 1.1 ichiro if_attach(ifp);
306 1.1 ichiro Ether_ifattach(ifp, eaddr);
307 1.1 ichiro
308 1.1 ichiro #if NRND > 0
309 1.32 cube rnd_attach_source(&sc->rnd_source, device_xname(self),
310 1.32 cube RND_TYPE_NET, 0);
311 1.1 ichiro #endif
312 1.1 ichiro
313 1.1 ichiro usb_callout_init(sc->sc_stat_ch);
314 1.1 ichiro sc->sc_attached = 1;
315 1.1 ichiro splx(s);
316 1.1 ichiro
317 1.1 ichiro usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, dev, USBDEV(sc->sc_dev));
318 1.1 ichiro
319 1.1 ichiro USB_ATTACH_SUCCESS_RETURN;
320 1.1 ichiro
321 1.1 ichiro bad:
322 1.1 ichiro sc->sc_dying = 1;
323 1.1 ichiro USB_ATTACH_ERROR_RETURN;
324 1.1 ichiro }
325 1.1 ichiro
326 1.1 ichiro /* detach */
327 1.1 ichiro USB_DETACH(url)
328 1.1 ichiro {
329 1.1 ichiro USB_DETACH_START(url, sc);
330 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
331 1.1 ichiro int s;
332 1.1 ichiro
333 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
334 1.1 ichiro
335 1.1 ichiro /* Detached before attached finished */
336 1.1 ichiro if (!sc->sc_attached)
337 1.1 ichiro return (0);
338 1.1 ichiro
339 1.1 ichiro usb_uncallout(sc->sc_stat_ch, url_tick, sc);
340 1.1 ichiro
341 1.1 ichiro /* Remove any pending tasks */
342 1.1 ichiro usb_rem_task(sc->sc_udev, &sc->sc_tick_task);
343 1.1 ichiro usb_rem_task(sc->sc_udev, &sc->sc_stop_task);
344 1.1 ichiro
345 1.1 ichiro s = splusb();
346 1.1 ichiro
347 1.1 ichiro if (--sc->sc_refcnt >= 0) {
348 1.1 ichiro /* Wait for processes to go away */
349 1.1 ichiro usb_detach_wait(USBDEV(sc->sc_dev));
350 1.1 ichiro }
351 1.1 ichiro
352 1.1 ichiro if (ifp->if_flags & IFF_RUNNING)
353 1.1 ichiro url_stop(GET_IFP(sc), 1);
354 1.1 ichiro
355 1.1 ichiro #if NRND > 0
356 1.1 ichiro rnd_detach_source(&sc->rnd_source);
357 1.1 ichiro #endif
358 1.1 ichiro mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
359 1.1 ichiro ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
360 1.1 ichiro ether_ifdetach(ifp);
361 1.1 ichiro if_detach(ifp);
362 1.1 ichiro
363 1.1 ichiro #ifdef DIAGNOSTIC
364 1.1 ichiro if (sc->sc_pipe_tx != NULL)
365 1.32 cube aprint_debug_dev(self, "detach has active tx endpoint.\n");
366 1.1 ichiro if (sc->sc_pipe_rx != NULL)
367 1.32 cube aprint_debug_dev(self, "detach has active rx endpoint.\n");
368 1.1 ichiro if (sc->sc_pipe_intr != NULL)
369 1.32 cube aprint_debug_dev(self, "detach has active intr endpoint.\n");
370 1.1 ichiro #endif
371 1.1 ichiro
372 1.1 ichiro sc->sc_attached = 0;
373 1.1 ichiro
374 1.1 ichiro splx(s);
375 1.1 ichiro
376 1.28 xtraeme rw_destroy(&sc->sc_mii_rwlock);
377 1.1 ichiro usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev,
378 1.1 ichiro USBDEV(sc->sc_dev));
379 1.1 ichiro
380 1.1 ichiro return (0);
381 1.1 ichiro }
382 1.1 ichiro
383 1.1 ichiro /* read/write memory */
384 1.1 ichiro Static int
385 1.1 ichiro url_mem(struct url_softc *sc, int cmd, int offset, void *buf, int len)
386 1.1 ichiro {
387 1.1 ichiro usb_device_request_t req;
388 1.1 ichiro usbd_status err;
389 1.1 ichiro
390 1.1 ichiro if (sc == NULL)
391 1.1 ichiro return (0);
392 1.1 ichiro
393 1.1 ichiro DPRINTFN(0x200,
394 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
395 1.1 ichiro
396 1.1 ichiro if (sc->sc_dying)
397 1.1 ichiro return (0);
398 1.1 ichiro
399 1.1 ichiro if (cmd == URL_CMD_READMEM)
400 1.1 ichiro req.bmRequestType = UT_READ_VENDOR_DEVICE;
401 1.1 ichiro else
402 1.1 ichiro req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
403 1.1 ichiro req.bRequest = URL_REQ_MEM;
404 1.1 ichiro USETW(req.wValue, offset);
405 1.1 ichiro USETW(req.wIndex, 0x0000);
406 1.1 ichiro USETW(req.wLength, len);
407 1.1 ichiro
408 1.1 ichiro sc->sc_refcnt++;
409 1.1 ichiro err = usbd_do_request(sc->sc_udev, &req, buf);
410 1.1 ichiro if (--sc->sc_refcnt < 0)
411 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
412 1.1 ichiro if (err) {
413 1.1 ichiro DPRINTF(("%s: url_mem(): %s failed. off=%04x, err=%d\n",
414 1.1 ichiro USBDEVNAME(sc->sc_dev),
415 1.1 ichiro cmd == URL_CMD_READMEM ? "read" : "write",
416 1.1 ichiro offset, err));
417 1.5 augustss }
418 1.1 ichiro
419 1.1 ichiro return (err);
420 1.1 ichiro }
421 1.1 ichiro
422 1.1 ichiro /* read 1byte from register */
423 1.1 ichiro Static int
424 1.1 ichiro url_csr_read_1(struct url_softc *sc, int reg)
425 1.1 ichiro {
426 1.1 ichiro u_int8_t val = 0;
427 1.1 ichiro
428 1.1 ichiro DPRINTFN(0x100,
429 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
430 1.1 ichiro
431 1.1 ichiro if (sc->sc_dying)
432 1.1 ichiro return (0);
433 1.5 augustss
434 1.1 ichiro return (url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val);
435 1.1 ichiro }
436 1.1 ichiro
437 1.1 ichiro /* read 2bytes from register */
438 1.1 ichiro Static int
439 1.1 ichiro url_csr_read_2(struct url_softc *sc, int reg)
440 1.1 ichiro {
441 1.1 ichiro uWord val;
442 1.1 ichiro
443 1.1 ichiro DPRINTFN(0x100,
444 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
445 1.1 ichiro
446 1.1 ichiro if (sc->sc_dying)
447 1.1 ichiro return (0);
448 1.5 augustss
449 1.1 ichiro USETW(val, 0);
450 1.1 ichiro return (url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val));
451 1.1 ichiro }
452 1.1 ichiro
453 1.1 ichiro /* write 1byte to register */
454 1.1 ichiro Static int
455 1.1 ichiro url_csr_write_1(struct url_softc *sc, int reg, int aval)
456 1.1 ichiro {
457 1.1 ichiro u_int8_t val = aval;
458 1.1 ichiro
459 1.1 ichiro DPRINTFN(0x100,
460 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
461 1.1 ichiro
462 1.1 ichiro if (sc->sc_dying)
463 1.1 ichiro return (0);
464 1.5 augustss
465 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0);
466 1.1 ichiro }
467 1.1 ichiro
468 1.1 ichiro /* write 2bytes to register */
469 1.1 ichiro Static int
470 1.1 ichiro url_csr_write_2(struct url_softc *sc, int reg, int aval)
471 1.1 ichiro {
472 1.1 ichiro uWord val;
473 1.1 ichiro
474 1.1 ichiro DPRINTFN(0x100,
475 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
476 1.1 ichiro
477 1.1 ichiro USETW(val, aval);
478 1.1 ichiro
479 1.1 ichiro if (sc->sc_dying)
480 1.1 ichiro return (0);
481 1.5 augustss
482 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0);
483 1.1 ichiro }
484 1.1 ichiro
485 1.1 ichiro /* write 4bytes to register */
486 1.1 ichiro Static int
487 1.1 ichiro url_csr_write_4(struct url_softc *sc, int reg, int aval)
488 1.1 ichiro {
489 1.1 ichiro uDWord val;
490 1.1 ichiro
491 1.1 ichiro DPRINTFN(0x100,
492 1.4 augustss ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
493 1.1 ichiro
494 1.1 ichiro USETDW(val, aval);
495 1.1 ichiro
496 1.1 ichiro if (sc->sc_dying)
497 1.1 ichiro return (0);
498 1.5 augustss
499 1.1 ichiro return (url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0);
500 1.1 ichiro }
501 1.1 ichiro
502 1.1 ichiro Static int
503 1.1 ichiro url_init(struct ifnet *ifp)
504 1.1 ichiro {
505 1.1 ichiro struct url_softc *sc = ifp->if_softc;
506 1.1 ichiro struct mii_data *mii = GET_MII(sc);
507 1.29 dyoung const u_char *eaddr;
508 1.30 dyoung int i, rc, s;
509 1.1 ichiro
510 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
511 1.5 augustss
512 1.1 ichiro if (sc->sc_dying)
513 1.1 ichiro return (EIO);
514 1.1 ichiro
515 1.1 ichiro s = splnet();
516 1.1 ichiro
517 1.1 ichiro /* Cancel pending I/O and free all TX/RX buffers */
518 1.1 ichiro url_stop(ifp, 1);
519 1.1 ichiro
520 1.29 dyoung eaddr = CLLADDR(ifp->if_sadl);
521 1.1 ichiro for (i = 0; i < ETHER_ADDR_LEN; i++)
522 1.1 ichiro url_csr_write_1(sc, URL_IDR0 + i, eaddr[i]);
523 1.1 ichiro
524 1.1 ichiro /* Init transmission control register */
525 1.1 ichiro URL_CLRBIT(sc, URL_TCR,
526 1.1 ichiro URL_TCR_TXRR1 | URL_TCR_TXRR0 |
527 1.1 ichiro URL_TCR_IFG1 | URL_TCR_IFG0 |
528 1.1 ichiro URL_TCR_NOCRC);
529 1.1 ichiro
530 1.1 ichiro /* Init receive control register */
531 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_TAIL | URL_RCR_AD);
532 1.1 ichiro if (ifp->if_flags & IFF_BROADCAST)
533 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AB);
534 1.1 ichiro else
535 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AB);
536 1.1 ichiro
537 1.1 ichiro /* If we want promiscuous mode, accept all physical frames. */
538 1.1 ichiro if (ifp->if_flags & IFF_PROMISC)
539 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
540 1.1 ichiro else
541 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
542 1.1 ichiro
543 1.5 augustss
544 1.1 ichiro /* Initialize transmit ring */
545 1.1 ichiro if (url_tx_list_init(sc) == ENOBUFS) {
546 1.1 ichiro printf("%s: tx list init failed\n", USBDEVNAME(sc->sc_dev));
547 1.1 ichiro splx(s);
548 1.1 ichiro return (EIO);
549 1.1 ichiro }
550 1.1 ichiro
551 1.1 ichiro /* Initialize receive ring */
552 1.1 ichiro if (url_rx_list_init(sc) == ENOBUFS) {
553 1.1 ichiro printf("%s: rx list init failed\n", USBDEVNAME(sc->sc_dev));
554 1.1 ichiro splx(s);
555 1.1 ichiro return (EIO);
556 1.1 ichiro }
557 1.1 ichiro
558 1.1 ichiro /* Load the multicast filter */
559 1.1 ichiro url_setmulti(sc);
560 1.1 ichiro
561 1.1 ichiro /* Enable RX and TX */
562 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_TE | URL_CR_RE);
563 1.1 ichiro
564 1.30 dyoung if ((rc = mii_mediachg(mii)) == ENXIO)
565 1.30 dyoung rc = 0;
566 1.30 dyoung else if (rc != 0)
567 1.30 dyoung goto out;
568 1.1 ichiro
569 1.1 ichiro if (sc->sc_pipe_tx == NULL || sc->sc_pipe_rx == NULL) {
570 1.1 ichiro if (url_openpipes(sc)) {
571 1.1 ichiro splx(s);
572 1.1 ichiro return (EIO);
573 1.1 ichiro }
574 1.1 ichiro }
575 1.1 ichiro
576 1.1 ichiro ifp->if_flags |= IFF_RUNNING;
577 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
578 1.1 ichiro
579 1.1 ichiro usb_callout(sc->sc_stat_ch, hz, url_tick, sc);
580 1.1 ichiro
581 1.30 dyoung out:
582 1.30 dyoung splx(s);
583 1.30 dyoung return rc;
584 1.1 ichiro }
585 1.1 ichiro
586 1.1 ichiro Static void
587 1.1 ichiro url_reset(struct url_softc *sc)
588 1.1 ichiro {
589 1.1 ichiro int i;
590 1.5 augustss
591 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
592 1.1 ichiro
593 1.1 ichiro if (sc->sc_dying)
594 1.1 ichiro return;
595 1.1 ichiro
596 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_SOFT_RST);
597 1.1 ichiro
598 1.1 ichiro for (i = 0; i < URL_TX_TIMEOUT; i++) {
599 1.1 ichiro if (!(url_csr_read_1(sc, URL_CR) & URL_CR_SOFT_RST))
600 1.1 ichiro break;
601 1.1 ichiro delay(10); /* XXX */
602 1.1 ichiro }
603 1.1 ichiro
604 1.1 ichiro delay(10000); /* XXX */
605 1.1 ichiro }
606 1.1 ichiro
607 1.1 ichiro int
608 1.1 ichiro url_activate(device_ptr_t self, enum devact act)
609 1.1 ichiro {
610 1.32 cube struct url_softc *sc = device_private(self);
611 1.1 ichiro
612 1.1 ichiro DPRINTF(("%s: %s: enter, act=%d\n", USBDEVNAME(sc->sc_dev),
613 1.4 augustss __func__, act));
614 1.1 ichiro
615 1.1 ichiro switch (act) {
616 1.1 ichiro case DVACT_DEACTIVATE:
617 1.1 ichiro if_deactivate(&sc->sc_ec.ec_if);
618 1.1 ichiro sc->sc_dying = 1;
619 1.35 dyoung return 0;
620 1.35 dyoung default:
621 1.35 dyoung return EOPNOTSUPP;
622 1.1 ichiro }
623 1.1 ichiro }
624 1.1 ichiro
625 1.1 ichiro #define url_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
626 1.1 ichiro
627 1.1 ichiro
628 1.1 ichiro Static void
629 1.1 ichiro url_setmulti(struct url_softc *sc)
630 1.1 ichiro {
631 1.1 ichiro struct ifnet *ifp;
632 1.1 ichiro struct ether_multi *enm;
633 1.1 ichiro struct ether_multistep step;
634 1.1 ichiro u_int32_t hashes[2] = { 0, 0 };
635 1.1 ichiro int h = 0;
636 1.1 ichiro int mcnt = 0;
637 1.1 ichiro
638 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
639 1.1 ichiro
640 1.1 ichiro if (sc->sc_dying)
641 1.1 ichiro return;
642 1.1 ichiro
643 1.1 ichiro ifp = GET_IFP(sc);
644 1.1 ichiro
645 1.1 ichiro if (ifp->if_flags & IFF_PROMISC) {
646 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
647 1.1 ichiro return;
648 1.1 ichiro } else if (ifp->if_flags & IFF_ALLMULTI) {
649 1.1 ichiro allmulti:
650 1.1 ichiro ifp->if_flags |= IFF_ALLMULTI;
651 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM);
652 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAP);
653 1.1 ichiro return;
654 1.1 ichiro }
655 1.1 ichiro
656 1.1 ichiro /* first, zot all the existing hash bits */
657 1.1 ichiro url_csr_write_4(sc, URL_MAR0, 0);
658 1.1 ichiro url_csr_write_4(sc, URL_MAR4, 0);
659 1.1 ichiro
660 1.1 ichiro /* now program new ones */
661 1.1 ichiro ETHER_FIRST_MULTI(step, &sc->sc_ec, enm);
662 1.1 ichiro while (enm != NULL) {
663 1.1 ichiro if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
664 1.1 ichiro ETHER_ADDR_LEN) != 0)
665 1.1 ichiro goto allmulti;
666 1.1 ichiro
667 1.1 ichiro h = url_calchash(enm->enm_addrlo);
668 1.1 ichiro if (h < 32)
669 1.1 ichiro hashes[0] |= (1 << h);
670 1.1 ichiro else
671 1.1 ichiro hashes[1] |= (1 << (h -32));
672 1.1 ichiro mcnt++;
673 1.1 ichiro ETHER_NEXT_MULTI(step, enm);
674 1.1 ichiro }
675 1.1 ichiro
676 1.1 ichiro ifp->if_flags &= ~IFF_ALLMULTI;
677 1.1 ichiro
678 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
679 1.1 ichiro
680 1.1 ichiro if (mcnt){
681 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AM);
682 1.1 ichiro } else {
683 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AM);
684 1.1 ichiro }
685 1.1 ichiro url_csr_write_4(sc, URL_MAR0, hashes[0]);
686 1.1 ichiro url_csr_write_4(sc, URL_MAR4, hashes[1]);
687 1.1 ichiro }
688 1.1 ichiro
689 1.1 ichiro Static int
690 1.1 ichiro url_openpipes(struct url_softc *sc)
691 1.1 ichiro {
692 1.1 ichiro struct url_chain *c;
693 1.1 ichiro usbd_status err;
694 1.1 ichiro int i;
695 1.1 ichiro int error = 0;
696 1.1 ichiro
697 1.1 ichiro if (sc->sc_dying)
698 1.1 ichiro return (EIO);
699 1.5 augustss
700 1.1 ichiro sc->sc_refcnt++;
701 1.1 ichiro
702 1.1 ichiro /* Open RX pipe */
703 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkin_no,
704 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_rx);
705 1.1 ichiro if (err) {
706 1.1 ichiro printf("%s: open rx pipe failed: %s\n",
707 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
708 1.1 ichiro error = EIO;
709 1.1 ichiro goto done;
710 1.1 ichiro }
711 1.5 augustss
712 1.1 ichiro /* Open TX pipe */
713 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkout_no,
714 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_tx);
715 1.1 ichiro if (err) {
716 1.1 ichiro printf("%s: open tx pipe failed: %s\n",
717 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
718 1.1 ichiro error = EIO;
719 1.1 ichiro goto done;
720 1.1 ichiro }
721 1.1 ichiro
722 1.1 ichiro #if 0
723 1.1 ichiro /* XXX: interrupt endpoint is not yet supported */
724 1.1 ichiro /* Open Interrupt pipe */
725 1.1 ichiro err = usbd_open_pipe_intr(sc->sc_ctl_iface, sc->sc_intrin_no,
726 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_intr, sc,
727 1.1 ichiro &sc->sc_cdata.url_ibuf, URL_INTR_PKGLEN,
728 1.24 drochner url_intr, USBD_DEFAULT_INTERVAL);
729 1.1 ichiro if (err) {
730 1.1 ichiro printf("%s: open intr pipe failed: %s\n",
731 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
732 1.1 ichiro error = EIO;
733 1.1 ichiro goto done;
734 1.1 ichiro }
735 1.1 ichiro #endif
736 1.1 ichiro
737 1.1 ichiro
738 1.1 ichiro /* Start up the receive pipe. */
739 1.1 ichiro for (i = 0; i < URL_RX_LIST_CNT; i++) {
740 1.1 ichiro c = &sc->sc_cdata.url_rx_chain[i];
741 1.1 ichiro usbd_setup_xfer(c->url_xfer, sc->sc_pipe_rx,
742 1.1 ichiro c, c->url_buf, URL_BUFSZ,
743 1.1 ichiro USBD_SHORT_XFER_OK | USBD_NO_COPY,
744 1.1 ichiro USBD_NO_TIMEOUT, url_rxeof);
745 1.1 ichiro (void)usbd_transfer(c->url_xfer);
746 1.1 ichiro DPRINTF(("%s: %s: start read\n", USBDEVNAME(sc->sc_dev),
747 1.4 augustss __func__));
748 1.1 ichiro }
749 1.1 ichiro
750 1.1 ichiro done:
751 1.1 ichiro if (--sc->sc_refcnt < 0)
752 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
753 1.5 augustss
754 1.1 ichiro return (error);
755 1.1 ichiro }
756 1.1 ichiro
757 1.1 ichiro Static int
758 1.1 ichiro url_newbuf(struct url_softc *sc, struct url_chain *c, struct mbuf *m)
759 1.1 ichiro {
760 1.1 ichiro struct mbuf *m_new = NULL;
761 1.1 ichiro
762 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
763 1.1 ichiro
764 1.1 ichiro if (m == NULL) {
765 1.1 ichiro MGETHDR(m_new, M_DONTWAIT, MT_DATA);
766 1.1 ichiro if (m_new == NULL) {
767 1.1 ichiro printf("%s: no memory for rx list "
768 1.1 ichiro "-- packet dropped!\n", USBDEVNAME(sc->sc_dev));
769 1.1 ichiro return (ENOBUFS);
770 1.1 ichiro }
771 1.1 ichiro MCLGET(m_new, M_DONTWAIT);
772 1.1 ichiro if (!(m_new->m_flags & M_EXT)) {
773 1.1 ichiro printf("%s: no memory for rx list "
774 1.1 ichiro "-- packet dropped!\n", USBDEVNAME(sc->sc_dev));
775 1.1 ichiro m_freem(m_new);
776 1.1 ichiro return (ENOBUFS);
777 1.1 ichiro }
778 1.1 ichiro m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
779 1.1 ichiro } else {
780 1.1 ichiro m_new = m;
781 1.1 ichiro m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
782 1.1 ichiro m_new->m_data = m_new->m_ext.ext_buf;
783 1.1 ichiro }
784 1.1 ichiro
785 1.1 ichiro m_adj(m_new, ETHER_ALIGN);
786 1.1 ichiro c->url_mbuf = m_new;
787 1.1 ichiro
788 1.1 ichiro return (0);
789 1.1 ichiro }
790 1.5 augustss
791 1.1 ichiro
792 1.1 ichiro Static int
793 1.1 ichiro url_rx_list_init(struct url_softc *sc)
794 1.1 ichiro {
795 1.1 ichiro struct url_cdata *cd;
796 1.1 ichiro struct url_chain *c;
797 1.1 ichiro int i;
798 1.1 ichiro
799 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
800 1.1 ichiro
801 1.1 ichiro cd = &sc->sc_cdata;
802 1.1 ichiro for (i = 0; i < URL_RX_LIST_CNT; i++) {
803 1.1 ichiro c = &cd->url_rx_chain[i];
804 1.1 ichiro c->url_sc = sc;
805 1.1 ichiro c->url_idx = i;
806 1.1 ichiro if (url_newbuf(sc, c, NULL) == ENOBUFS)
807 1.1 ichiro return (ENOBUFS);
808 1.1 ichiro if (c->url_xfer == NULL) {
809 1.1 ichiro c->url_xfer = usbd_alloc_xfer(sc->sc_udev);
810 1.1 ichiro if (c->url_xfer == NULL)
811 1.1 ichiro return (ENOBUFS);
812 1.1 ichiro c->url_buf = usbd_alloc_buffer(c->url_xfer, URL_BUFSZ);
813 1.1 ichiro if (c->url_buf == NULL) {
814 1.1 ichiro usbd_free_xfer(c->url_xfer);
815 1.1 ichiro return (ENOBUFS);
816 1.1 ichiro }
817 1.1 ichiro }
818 1.1 ichiro }
819 1.5 augustss
820 1.1 ichiro return (0);
821 1.1 ichiro }
822 1.1 ichiro
823 1.1 ichiro Static int
824 1.1 ichiro url_tx_list_init(struct url_softc *sc)
825 1.1 ichiro {
826 1.1 ichiro struct url_cdata *cd;
827 1.1 ichiro struct url_chain *c;
828 1.1 ichiro int i;
829 1.1 ichiro
830 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
831 1.1 ichiro
832 1.1 ichiro cd = &sc->sc_cdata;
833 1.1 ichiro for (i = 0; i < URL_TX_LIST_CNT; i++) {
834 1.1 ichiro c = &cd->url_tx_chain[i];
835 1.1 ichiro c->url_sc = sc;
836 1.1 ichiro c->url_idx = i;
837 1.1 ichiro c->url_mbuf = NULL;
838 1.1 ichiro if (c->url_xfer == NULL) {
839 1.1 ichiro c->url_xfer = usbd_alloc_xfer(sc->sc_udev);
840 1.1 ichiro if (c->url_xfer == NULL)
841 1.1 ichiro return (ENOBUFS);
842 1.1 ichiro c->url_buf = usbd_alloc_buffer(c->url_xfer, URL_BUFSZ);
843 1.1 ichiro if (c->url_buf == NULL) {
844 1.1 ichiro usbd_free_xfer(c->url_xfer);
845 1.1 ichiro return (ENOBUFS);
846 1.1 ichiro }
847 1.1 ichiro }
848 1.1 ichiro }
849 1.5 augustss
850 1.1 ichiro return (0);
851 1.1 ichiro }
852 1.1 ichiro
853 1.1 ichiro Static void
854 1.1 ichiro url_start(struct ifnet *ifp)
855 1.1 ichiro {
856 1.1 ichiro struct url_softc *sc = ifp->if_softc;
857 1.1 ichiro struct mbuf *m_head = NULL;
858 1.5 augustss
859 1.1 ichiro DPRINTF(("%s: %s: enter, link=%d\n", USBDEVNAME(sc->sc_dev),
860 1.4 augustss __func__, sc->sc_link));
861 1.1 ichiro
862 1.1 ichiro if (sc->sc_dying)
863 1.1 ichiro return;
864 1.1 ichiro
865 1.1 ichiro if (!sc->sc_link)
866 1.1 ichiro return;
867 1.1 ichiro
868 1.1 ichiro if (ifp->if_flags & IFF_OACTIVE)
869 1.1 ichiro return;
870 1.1 ichiro
871 1.1 ichiro IFQ_POLL(&ifp->if_snd, m_head);
872 1.1 ichiro if (m_head == NULL)
873 1.1 ichiro return;
874 1.1 ichiro
875 1.1 ichiro if (url_send(sc, m_head, 0)) {
876 1.1 ichiro ifp->if_flags |= IFF_OACTIVE;
877 1.1 ichiro return;
878 1.1 ichiro }
879 1.1 ichiro
880 1.1 ichiro IFQ_DEQUEUE(&ifp->if_snd, m_head);
881 1.1 ichiro
882 1.37 joerg bpf_mtap(ifp, m_head);
883 1.1 ichiro
884 1.1 ichiro ifp->if_flags |= IFF_OACTIVE;
885 1.1 ichiro
886 1.1 ichiro /* Set a timeout in case the chip goes out to lunch. */
887 1.1 ichiro ifp->if_timer = 5;
888 1.1 ichiro }
889 1.1 ichiro
890 1.1 ichiro Static int
891 1.1 ichiro url_send(struct url_softc *sc, struct mbuf *m, int idx)
892 1.1 ichiro {
893 1.1 ichiro int total_len;
894 1.1 ichiro struct url_chain *c;
895 1.1 ichiro usbd_status err;
896 1.1 ichiro
897 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),__func__));
898 1.1 ichiro
899 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[idx];
900 1.1 ichiro
901 1.1 ichiro /* Copy the mbuf data into a contiguous buffer */
902 1.1 ichiro m_copydata(m, 0, m->m_pkthdr.len, c->url_buf);
903 1.1 ichiro c->url_mbuf = m;
904 1.1 ichiro total_len = m->m_pkthdr.len;
905 1.1 ichiro
906 1.7 bouyer if (total_len < URL_MIN_FRAME_LEN) {
907 1.7 bouyer memset(c->url_buf + total_len, 0,
908 1.7 bouyer URL_MIN_FRAME_LEN - total_len);
909 1.1 ichiro total_len = URL_MIN_FRAME_LEN;
910 1.7 bouyer }
911 1.1 ichiro usbd_setup_xfer(c->url_xfer, sc->sc_pipe_tx, c, c->url_buf, total_len,
912 1.1 ichiro USBD_FORCE_SHORT_XFER | USBD_NO_COPY,
913 1.1 ichiro URL_TX_TIMEOUT, url_txeof);
914 1.1 ichiro
915 1.1 ichiro /* Transmit */
916 1.1 ichiro sc->sc_refcnt++;
917 1.1 ichiro err = usbd_transfer(c->url_xfer);
918 1.1 ichiro if (--sc->sc_refcnt < 0)
919 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
920 1.1 ichiro if (err != USBD_IN_PROGRESS) {
921 1.1 ichiro printf("%s: url_send error=%s\n", USBDEVNAME(sc->sc_dev),
922 1.1 ichiro usbd_errstr(err));
923 1.1 ichiro /* Stop the interface */
924 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_stop_task,
925 1.22 joerg USB_TASKQ_DRIVER);
926 1.1 ichiro return (EIO);
927 1.1 ichiro }
928 1.1 ichiro
929 1.1 ichiro DPRINTF(("%s: %s: send %d bytes\n", USBDEVNAME(sc->sc_dev),
930 1.4 augustss __func__, total_len));
931 1.1 ichiro
932 1.1 ichiro sc->sc_cdata.url_tx_cnt++;
933 1.1 ichiro
934 1.1 ichiro return (0);
935 1.1 ichiro }
936 1.1 ichiro
937 1.1 ichiro Static void
938 1.23 christos url_txeof(usbd_xfer_handle xfer, usbd_private_handle priv,
939 1.21 christos usbd_status status)
940 1.1 ichiro {
941 1.1 ichiro struct url_chain *c = priv;
942 1.1 ichiro struct url_softc *sc = c->url_sc;
943 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
944 1.1 ichiro int s;
945 1.1 ichiro
946 1.1 ichiro if (sc->sc_dying)
947 1.1 ichiro return;
948 1.1 ichiro
949 1.1 ichiro s = splnet();
950 1.1 ichiro
951 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
952 1.1 ichiro
953 1.1 ichiro ifp->if_timer = 0;
954 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
955 1.1 ichiro
956 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
957 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
958 1.1 ichiro splx(s);
959 1.1 ichiro return;
960 1.1 ichiro }
961 1.1 ichiro ifp->if_oerrors++;
962 1.1 ichiro printf("%s: usb error on tx: %s\n", USBDEVNAME(sc->sc_dev),
963 1.1 ichiro usbd_errstr(status));
964 1.1 ichiro if (status == USBD_STALLED) {
965 1.1 ichiro sc->sc_refcnt++;
966 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_tx);
967 1.1 ichiro if (--sc->sc_refcnt < 0)
968 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
969 1.1 ichiro }
970 1.1 ichiro splx(s);
971 1.1 ichiro return;
972 1.1 ichiro }
973 1.1 ichiro
974 1.1 ichiro ifp->if_opackets++;
975 1.1 ichiro
976 1.6 martin m_freem(c->url_mbuf);
977 1.1 ichiro c->url_mbuf = NULL;
978 1.1 ichiro
979 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
980 1.1 ichiro url_start(ifp);
981 1.1 ichiro
982 1.1 ichiro splx(s);
983 1.1 ichiro }
984 1.1 ichiro
985 1.1 ichiro Static void
986 1.1 ichiro url_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status)
987 1.1 ichiro {
988 1.1 ichiro struct url_chain *c = priv;
989 1.1 ichiro struct url_softc *sc = c->url_sc;
990 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
991 1.1 ichiro struct mbuf *m;
992 1.1 ichiro u_int32_t total_len;
993 1.1 ichiro url_rxhdr_t rxhdr;
994 1.1 ichiro int s;
995 1.1 ichiro
996 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),__func__));
997 1.1 ichiro
998 1.1 ichiro if (sc->sc_dying)
999 1.1 ichiro return;
1000 1.1 ichiro
1001 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
1002 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
1003 1.1 ichiro return;
1004 1.1 ichiro sc->sc_rx_errs++;
1005 1.1 ichiro if (usbd_ratecheck(&sc->sc_rx_notice)) {
1006 1.1 ichiro printf("%s: %u usb errors on rx: %s\n",
1007 1.1 ichiro USBDEVNAME(sc->sc_dev), sc->sc_rx_errs,
1008 1.1 ichiro usbd_errstr(status));
1009 1.1 ichiro sc->sc_rx_errs = 0;
1010 1.1 ichiro }
1011 1.1 ichiro if (status == USBD_STALLED) {
1012 1.1 ichiro sc->sc_refcnt++;
1013 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_rx);
1014 1.1 ichiro if (--sc->sc_refcnt < 0)
1015 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
1016 1.1 ichiro }
1017 1.1 ichiro goto done;
1018 1.1 ichiro }
1019 1.1 ichiro
1020 1.1 ichiro usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
1021 1.1 ichiro
1022 1.1 ichiro memcpy(mtod(c->url_mbuf, char *), c->url_buf, total_len);
1023 1.1 ichiro
1024 1.1 ichiro if (total_len <= ETHER_CRC_LEN) {
1025 1.1 ichiro ifp->if_ierrors++;
1026 1.1 ichiro goto done;
1027 1.1 ichiro }
1028 1.1 ichiro
1029 1.1 ichiro memcpy(&rxhdr, c->url_buf + total_len - ETHER_CRC_LEN, sizeof(rxhdr));
1030 1.1 ichiro
1031 1.1 ichiro DPRINTF(("%s: RX Status: %dbytes%s%s%s%s packets\n",
1032 1.1 ichiro USBDEVNAME(sc->sc_dev),
1033 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_BYTEC_MASK,
1034 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_VALID_MASK ? ", Valid" : "",
1035 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_RUNTPKT_MASK ? ", Runt" : "",
1036 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_PHYPKT_MASK ? ", Physical match" : "",
1037 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_MCASTPKT_MASK ? ", Multicast" : ""));
1038 1.1 ichiro
1039 1.1 ichiro if ((UGETW(rxhdr) & URL_RXHDR_VALID_MASK) == 0) {
1040 1.1 ichiro ifp->if_ierrors++;
1041 1.1 ichiro goto done;
1042 1.1 ichiro }
1043 1.1 ichiro
1044 1.1 ichiro ifp->if_ipackets++;
1045 1.1 ichiro total_len -= ETHER_CRC_LEN;
1046 1.1 ichiro
1047 1.1 ichiro m = c->url_mbuf;
1048 1.1 ichiro m->m_pkthdr.len = m->m_len = total_len;
1049 1.1 ichiro m->m_pkthdr.rcvif = ifp;
1050 1.1 ichiro
1051 1.1 ichiro s = splnet();
1052 1.1 ichiro
1053 1.1 ichiro if (url_newbuf(sc, c, NULL) == ENOBUFS) {
1054 1.1 ichiro ifp->if_ierrors++;
1055 1.1 ichiro goto done1;
1056 1.1 ichiro }
1057 1.1 ichiro
1058 1.37 joerg bpf_mtap(ifp, m);
1059 1.1 ichiro
1060 1.1 ichiro DPRINTF(("%s: %s: deliver %d\n", USBDEVNAME(sc->sc_dev),
1061 1.4 augustss __func__, m->m_len));
1062 1.1 ichiro IF_INPUT(ifp, m);
1063 1.1 ichiro
1064 1.1 ichiro done1:
1065 1.1 ichiro splx(s);
1066 1.1 ichiro
1067 1.1 ichiro done:
1068 1.1 ichiro /* Setup new transfer */
1069 1.1 ichiro usbd_setup_xfer(xfer, sc->sc_pipe_rx, c, c->url_buf, URL_BUFSZ,
1070 1.1 ichiro USBD_SHORT_XFER_OK | USBD_NO_COPY,
1071 1.1 ichiro USBD_NO_TIMEOUT, url_rxeof);
1072 1.1 ichiro sc->sc_refcnt++;
1073 1.1 ichiro usbd_transfer(xfer);
1074 1.1 ichiro if (--sc->sc_refcnt < 0)
1075 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
1076 1.1 ichiro
1077 1.4 augustss DPRINTF(("%s: %s: start rx\n", USBDEVNAME(sc->sc_dev), __func__));
1078 1.1 ichiro }
1079 1.1 ichiro
1080 1.1 ichiro #if 0
1081 1.33 cegger Static void url_intr(void)
1082 1.1 ichiro {
1083 1.1 ichiro }
1084 1.1 ichiro #endif
1085 1.1 ichiro
1086 1.1 ichiro Static int
1087 1.25 christos url_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1088 1.1 ichiro {
1089 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1090 1.1 ichiro int s, error = 0;
1091 1.1 ichiro
1092 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1093 1.1 ichiro
1094 1.1 ichiro if (sc->sc_dying)
1095 1.1 ichiro return (EIO);
1096 1.1 ichiro
1097 1.1 ichiro s = splnet();
1098 1.1 ichiro
1099 1.30 dyoung error = ether_ioctl(ifp, cmd, data);
1100 1.30 dyoung if (error == ENETRESET) {
1101 1.30 dyoung if (ifp->if_flags & IFF_RUNNING)
1102 1.30 dyoung url_setmulti(sc);
1103 1.30 dyoung error = 0;
1104 1.1 ichiro }
1105 1.1 ichiro
1106 1.1 ichiro splx(s);
1107 1.1 ichiro
1108 1.1 ichiro return (error);
1109 1.1 ichiro }
1110 1.1 ichiro
1111 1.1 ichiro Static void
1112 1.1 ichiro url_watchdog(struct ifnet *ifp)
1113 1.1 ichiro {
1114 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1115 1.1 ichiro struct url_chain *c;
1116 1.1 ichiro usbd_status stat;
1117 1.1 ichiro int s;
1118 1.5 augustss
1119 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1120 1.1 ichiro
1121 1.1 ichiro ifp->if_oerrors++;
1122 1.1 ichiro printf("%s: watchdog timeout\n", USBDEVNAME(sc->sc_dev));
1123 1.1 ichiro
1124 1.1 ichiro s = splusb();
1125 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[0];
1126 1.1 ichiro usbd_get_xfer_status(c->url_xfer, NULL, NULL, NULL, &stat);
1127 1.1 ichiro url_txeof(c->url_xfer, c, stat);
1128 1.1 ichiro
1129 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1130 1.1 ichiro url_start(ifp);
1131 1.1 ichiro splx(s);
1132 1.1 ichiro }
1133 1.1 ichiro
1134 1.1 ichiro Static void
1135 1.1 ichiro url_stop_task(struct url_softc *sc)
1136 1.1 ichiro {
1137 1.1 ichiro url_stop(GET_IFP(sc), 1);
1138 1.1 ichiro }
1139 1.1 ichiro
1140 1.1 ichiro /* Stop the adapter and free any mbufs allocated to the RX and TX lists. */
1141 1.1 ichiro Static void
1142 1.23 christos url_stop(struct ifnet *ifp, int disable)
1143 1.1 ichiro {
1144 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1145 1.1 ichiro usbd_status err;
1146 1.1 ichiro int i;
1147 1.5 augustss
1148 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1149 1.1 ichiro
1150 1.1 ichiro ifp->if_timer = 0;
1151 1.1 ichiro
1152 1.1 ichiro url_reset(sc);
1153 1.1 ichiro
1154 1.1 ichiro usb_uncallout(sc->sc_stat_ch, url_tick, sc);
1155 1.1 ichiro
1156 1.1 ichiro /* Stop transfers */
1157 1.1 ichiro /* RX endpoint */
1158 1.1 ichiro if (sc->sc_pipe_rx != NULL) {
1159 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_rx);
1160 1.1 ichiro if (err)
1161 1.1 ichiro printf("%s: abort rx pipe failed: %s\n",
1162 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1163 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_rx);
1164 1.1 ichiro if (err)
1165 1.1 ichiro printf("%s: close rx pipe failed: %s\n",
1166 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1167 1.1 ichiro sc->sc_pipe_rx = NULL;
1168 1.1 ichiro }
1169 1.1 ichiro
1170 1.1 ichiro /* TX endpoint */
1171 1.1 ichiro if (sc->sc_pipe_tx != NULL) {
1172 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_tx);
1173 1.1 ichiro if (err)
1174 1.1 ichiro printf("%s: abort tx pipe failed: %s\n",
1175 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1176 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_tx);
1177 1.1 ichiro if (err)
1178 1.1 ichiro printf("%s: close tx pipe failed: %s\n",
1179 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1180 1.1 ichiro sc->sc_pipe_tx = NULL;
1181 1.1 ichiro }
1182 1.1 ichiro
1183 1.1 ichiro #if 0
1184 1.1 ichiro /* XXX: Interrupt endpoint is not yet supported!! */
1185 1.1 ichiro /* Interrupt endpoint */
1186 1.1 ichiro if (sc->sc_pipe_intr != NULL) {
1187 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_intr);
1188 1.1 ichiro if (err)
1189 1.1 ichiro printf("%s: abort intr pipe failed: %s\n",
1190 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1191 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_intr);
1192 1.1 ichiro if (err)
1193 1.1 ichiro printf("%s: close intr pipe failed: %s\n",
1194 1.1 ichiro USBDEVNAME(sc->sc_dev), usbd_errstr(err));
1195 1.1 ichiro sc->sc_pipe_intr = NULL;
1196 1.1 ichiro }
1197 1.1 ichiro #endif
1198 1.1 ichiro
1199 1.1 ichiro /* Free RX resources. */
1200 1.1 ichiro for (i = 0; i < URL_RX_LIST_CNT; i++) {
1201 1.1 ichiro if (sc->sc_cdata.url_rx_chain[i].url_mbuf != NULL) {
1202 1.1 ichiro m_freem(sc->sc_cdata.url_rx_chain[i].url_mbuf);
1203 1.1 ichiro sc->sc_cdata.url_rx_chain[i].url_mbuf = NULL;
1204 1.1 ichiro }
1205 1.1 ichiro if (sc->sc_cdata.url_rx_chain[i].url_xfer != NULL) {
1206 1.1 ichiro usbd_free_xfer(sc->sc_cdata.url_rx_chain[i].url_xfer);
1207 1.1 ichiro sc->sc_cdata.url_rx_chain[i].url_xfer = NULL;
1208 1.1 ichiro }
1209 1.1 ichiro }
1210 1.1 ichiro
1211 1.1 ichiro /* Free TX resources. */
1212 1.1 ichiro for (i = 0; i < URL_TX_LIST_CNT; i++) {
1213 1.1 ichiro if (sc->sc_cdata.url_tx_chain[i].url_mbuf != NULL) {
1214 1.1 ichiro m_freem(sc->sc_cdata.url_tx_chain[i].url_mbuf);
1215 1.1 ichiro sc->sc_cdata.url_tx_chain[i].url_mbuf = NULL;
1216 1.1 ichiro }
1217 1.1 ichiro if (sc->sc_cdata.url_tx_chain[i].url_xfer != NULL) {
1218 1.1 ichiro usbd_free_xfer(sc->sc_cdata.url_tx_chain[i].url_xfer);
1219 1.1 ichiro sc->sc_cdata.url_tx_chain[i].url_xfer = NULL;
1220 1.1 ichiro }
1221 1.1 ichiro }
1222 1.1 ichiro
1223 1.1 ichiro sc->sc_link = 0;
1224 1.1 ichiro ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1225 1.1 ichiro }
1226 1.1 ichiro
1227 1.1 ichiro /* Set media options */
1228 1.1 ichiro Static int
1229 1.1 ichiro url_ifmedia_change(struct ifnet *ifp)
1230 1.1 ichiro {
1231 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1232 1.1 ichiro struct mii_data *mii = GET_MII(sc);
1233 1.30 dyoung int rc;
1234 1.1 ichiro
1235 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1236 1.1 ichiro
1237 1.1 ichiro if (sc->sc_dying)
1238 1.1 ichiro return (0);
1239 1.1 ichiro
1240 1.1 ichiro sc->sc_link = 0;
1241 1.30 dyoung if ((rc = mii_mediachg(mii)) == ENXIO)
1242 1.30 dyoung return 0;
1243 1.30 dyoung return rc;
1244 1.1 ichiro }
1245 1.1 ichiro
1246 1.1 ichiro /* Report current media status. */
1247 1.1 ichiro Static void
1248 1.1 ichiro url_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1249 1.1 ichiro {
1250 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1251 1.1 ichiro
1252 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1253 1.1 ichiro
1254 1.1 ichiro if (sc->sc_dying)
1255 1.1 ichiro return;
1256 1.1 ichiro
1257 1.30 dyoung ether_mediastatus(ifp, ifmr);
1258 1.1 ichiro }
1259 1.1 ichiro
1260 1.1 ichiro Static void
1261 1.1 ichiro url_tick(void *xsc)
1262 1.1 ichiro {
1263 1.1 ichiro struct url_softc *sc = xsc;
1264 1.1 ichiro
1265 1.1 ichiro if (sc == NULL)
1266 1.1 ichiro return;
1267 1.1 ichiro
1268 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1269 1.4 augustss __func__));
1270 1.1 ichiro
1271 1.1 ichiro if (sc->sc_dying)
1272 1.1 ichiro return;
1273 1.1 ichiro
1274 1.1 ichiro /* Perform periodic stuff in process context */
1275 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_tick_task, USB_TASKQ_DRIVER);
1276 1.1 ichiro }
1277 1.1 ichiro
1278 1.1 ichiro Static void
1279 1.1 ichiro url_tick_task(void *xsc)
1280 1.1 ichiro {
1281 1.1 ichiro struct url_softc *sc = xsc;
1282 1.1 ichiro struct ifnet *ifp;
1283 1.1 ichiro struct mii_data *mii;
1284 1.1 ichiro int s;
1285 1.1 ichiro
1286 1.1 ichiro if (sc == NULL)
1287 1.1 ichiro return;
1288 1.1 ichiro
1289 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1290 1.4 augustss __func__));
1291 1.1 ichiro
1292 1.1 ichiro if (sc->sc_dying)
1293 1.1 ichiro return;
1294 1.1 ichiro
1295 1.1 ichiro ifp = GET_IFP(sc);
1296 1.1 ichiro mii = GET_MII(sc);
1297 1.1 ichiro
1298 1.1 ichiro if (mii == NULL)
1299 1.1 ichiro return;
1300 1.1 ichiro
1301 1.1 ichiro s = splnet();
1302 1.1 ichiro
1303 1.1 ichiro mii_tick(mii);
1304 1.1 ichiro if (!sc->sc_link) {
1305 1.1 ichiro mii_pollstat(mii);
1306 1.1 ichiro if (mii->mii_media_status & IFM_ACTIVE &&
1307 1.1 ichiro IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1308 1.1 ichiro DPRINTF(("%s: %s: got link\n",
1309 1.4 augustss USBDEVNAME(sc->sc_dev), __func__));
1310 1.1 ichiro sc->sc_link++;
1311 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1312 1.1 ichiro url_start(ifp);
1313 1.1 ichiro }
1314 1.1 ichiro }
1315 1.1 ichiro
1316 1.1 ichiro usb_callout(sc->sc_stat_ch, hz, url_tick, sc);
1317 1.1 ichiro
1318 1.1 ichiro splx(s);
1319 1.1 ichiro }
1320 1.1 ichiro
1321 1.1 ichiro /* Get exclusive access to the MII registers */
1322 1.1 ichiro Static void
1323 1.1 ichiro url_lock_mii(struct url_softc *sc)
1324 1.1 ichiro {
1325 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1326 1.4 augustss __func__));
1327 1.1 ichiro
1328 1.1 ichiro sc->sc_refcnt++;
1329 1.27 xtraeme rw_enter(&sc->sc_mii_rwlock, RW_WRITER);
1330 1.1 ichiro }
1331 1.1 ichiro
1332 1.1 ichiro Static void
1333 1.1 ichiro url_unlock_mii(struct url_softc *sc)
1334 1.1 ichiro {
1335 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter\n", USBDEVNAME(sc->sc_dev),
1336 1.4 augustss __func__));
1337 1.1 ichiro
1338 1.27 xtraeme rw_exit(&sc->sc_mii_rwlock);
1339 1.1 ichiro if (--sc->sc_refcnt < 0)
1340 1.1 ichiro usb_detach_wakeup(USBDEV(sc->sc_dev));
1341 1.1 ichiro }
1342 1.1 ichiro
1343 1.1 ichiro Static int
1344 1.1 ichiro url_int_miibus_readreg(device_ptr_t dev, int phy, int reg)
1345 1.1 ichiro {
1346 1.1 ichiro struct url_softc *sc;
1347 1.1 ichiro u_int16_t val;
1348 1.1 ichiro
1349 1.1 ichiro if (dev == NULL)
1350 1.1 ichiro return (0);
1351 1.1 ichiro
1352 1.1 ichiro sc = USBGETSOFTC(dev);
1353 1.1 ichiro
1354 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x\n",
1355 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg));
1356 1.1 ichiro
1357 1.1 ichiro if (sc->sc_dying) {
1358 1.1 ichiro #ifdef DIAGNOSTIC
1359 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1360 1.4 augustss __func__);
1361 1.1 ichiro #endif
1362 1.1 ichiro return (0);
1363 1.1 ichiro }
1364 1.1 ichiro
1365 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1366 1.1 ichiro if (phy != 0) {
1367 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1368 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy));
1369 1.1 ichiro return (0);
1370 1.1 ichiro }
1371 1.1 ichiro
1372 1.1 ichiro url_lock_mii(sc);
1373 1.1 ichiro
1374 1.1 ichiro switch (reg) {
1375 1.1 ichiro case MII_BMCR: /* Control Register */
1376 1.1 ichiro reg = URL_BMCR;
1377 1.1 ichiro break;
1378 1.1 ichiro case MII_BMSR: /* Status Register */
1379 1.1 ichiro reg = URL_BMSR;
1380 1.1 ichiro break;
1381 1.1 ichiro case MII_PHYIDR1:
1382 1.1 ichiro case MII_PHYIDR2:
1383 1.1 ichiro val = 0;
1384 1.1 ichiro goto R_DONE;
1385 1.1 ichiro break;
1386 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1387 1.1 ichiro reg = URL_ANAR;
1388 1.1 ichiro break;
1389 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1390 1.1 ichiro reg = URL_ANLP;
1391 1.1 ichiro break;
1392 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1393 1.1 ichiro reg = URL_MSR;
1394 1.1 ichiro break;
1395 1.1 ichiro default:
1396 1.1 ichiro printf("%s: %s: bad register %04x\n",
1397 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, reg);
1398 1.1 ichiro val = 0;
1399 1.1 ichiro goto R_DONE;
1400 1.1 ichiro break;
1401 1.1 ichiro }
1402 1.1 ichiro
1403 1.1 ichiro if (reg == URL_MSR)
1404 1.1 ichiro val = url_csr_read_1(sc, reg);
1405 1.1 ichiro else
1406 1.1 ichiro val = url_csr_read_2(sc, reg);
1407 1.1 ichiro
1408 1.1 ichiro R_DONE:
1409 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1410 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, val));
1411 1.1 ichiro
1412 1.1 ichiro url_unlock_mii(sc);
1413 1.1 ichiro return (val);
1414 1.1 ichiro }
1415 1.1 ichiro
1416 1.1 ichiro Static void
1417 1.1 ichiro url_int_miibus_writereg(device_ptr_t dev, int phy, int reg, int data)
1418 1.1 ichiro {
1419 1.1 ichiro struct url_softc *sc;
1420 1.1 ichiro
1421 1.1 ichiro if (dev == NULL)
1422 1.1 ichiro return;
1423 1.1 ichiro
1424 1.1 ichiro sc = USBGETSOFTC(dev);
1425 1.1 ichiro
1426 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1427 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, data));
1428 1.1 ichiro
1429 1.1 ichiro if (sc->sc_dying) {
1430 1.1 ichiro #ifdef DIAGNOSTIC
1431 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1432 1.4 augustss __func__);
1433 1.1 ichiro #endif
1434 1.1 ichiro return;
1435 1.1 ichiro }
1436 1.1 ichiro
1437 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1438 1.1 ichiro if (phy != 0) {
1439 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1440 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy));
1441 1.1 ichiro return;
1442 1.1 ichiro }
1443 1.1 ichiro
1444 1.1 ichiro url_lock_mii(sc);
1445 1.1 ichiro
1446 1.1 ichiro switch (reg) {
1447 1.1 ichiro case MII_BMCR: /* Control Register */
1448 1.1 ichiro reg = URL_BMCR;
1449 1.1 ichiro break;
1450 1.1 ichiro case MII_BMSR: /* Status Register */
1451 1.1 ichiro reg = URL_BMSR;
1452 1.1 ichiro break;
1453 1.1 ichiro case MII_PHYIDR1:
1454 1.1 ichiro case MII_PHYIDR2:
1455 1.1 ichiro goto W_DONE;
1456 1.1 ichiro break;
1457 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1458 1.1 ichiro reg = URL_ANAR;
1459 1.1 ichiro break;
1460 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1461 1.1 ichiro reg = URL_ANLP;
1462 1.1 ichiro break;
1463 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1464 1.1 ichiro reg = URL_MSR;
1465 1.1 ichiro break;
1466 1.1 ichiro default:
1467 1.1 ichiro printf("%s: %s: bad register %04x\n",
1468 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, reg);
1469 1.1 ichiro goto W_DONE;
1470 1.1 ichiro break;
1471 1.1 ichiro }
1472 1.1 ichiro
1473 1.1 ichiro if (reg == URL_MSR)
1474 1.1 ichiro url_csr_write_1(sc, reg, data);
1475 1.1 ichiro else
1476 1.1 ichiro url_csr_write_2(sc, reg, data);
1477 1.1 ichiro W_DONE:
1478 1.1 ichiro
1479 1.1 ichiro url_unlock_mii(sc);
1480 1.1 ichiro return;
1481 1.1 ichiro }
1482 1.1 ichiro
1483 1.1 ichiro Static void
1484 1.23 christos url_miibus_statchg(device_ptr_t dev)
1485 1.1 ichiro {
1486 1.1 ichiro #ifdef URL_DEBUG
1487 1.1 ichiro struct url_softc *sc;
1488 1.1 ichiro
1489 1.1 ichiro if (dev == NULL)
1490 1.1 ichiro return;
1491 1.1 ichiro
1492 1.1 ichiro sc = USBGETSOFTC(dev);
1493 1.4 augustss DPRINTF(("%s: %s: enter\n", USBDEVNAME(sc->sc_dev), __func__));
1494 1.1 ichiro #endif
1495 1.1 ichiro /* Nothing to do */
1496 1.1 ichiro }
1497 1.1 ichiro
1498 1.1 ichiro #if 0
1499 1.1 ichiro /*
1500 1.1 ichiro * external PHYs support, but not test.
1501 1.1 ichiro */
1502 1.1 ichiro Static int
1503 1.1 ichiro url_ext_miibus_redreg(device_ptr_t dev, int phy, int reg)
1504 1.1 ichiro {
1505 1.1 ichiro struct url_softc *sc = USBGETSOFTC(dev);
1506 1.1 ichiro u_int16_t val;
1507 1.1 ichiro
1508 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x\n",
1509 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg));
1510 1.1 ichiro
1511 1.1 ichiro if (sc->sc_dying) {
1512 1.1 ichiro #ifdef DIAGNOSTIC
1513 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1514 1.4 augustss __func__);
1515 1.1 ichiro #endif
1516 1.1 ichiro return (0);
1517 1.1 ichiro }
1518 1.1 ichiro
1519 1.1 ichiro url_lock_mii(sc);
1520 1.1 ichiro
1521 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy & URL_PHYADD_MASK);
1522 1.1 ichiro /*
1523 1.1 ichiro * RTL8150L will initiate a MII management data transaction
1524 1.1 ichiro * if PHYCNT_OWN bit is set 1 by software. After transaction,
1525 1.1 ichiro * this bit is auto cleared by TRL8150L.
1526 1.1 ichiro */
1527 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT,
1528 1.1 ichiro (reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
1529 1.1 ichiro for (i = 0; i < URL_TIMEOUT; i++) {
1530 1.1 ichiro if ((url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN) == 0)
1531 1.1 ichiro break;
1532 1.1 ichiro }
1533 1.1 ichiro if (i == URL_TIMEOUT) {
1534 1.1 ichiro printf("%s: MII read timed out\n", USBDEVNAME(sc->sc_dev));
1535 1.1 ichiro }
1536 1.5 augustss
1537 1.1 ichiro val = url_csr_read_2(sc, URL_PHYDAT);
1538 1.1 ichiro
1539 1.1 ichiro DPRINTF(("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1540 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, val));
1541 1.1 ichiro
1542 1.1 ichiro url_unlock_mii(sc);
1543 1.1 ichiro return (val);
1544 1.1 ichiro }
1545 1.1 ichiro
1546 1.1 ichiro Static void
1547 1.1 ichiro url_ext_miibus_writereg(device_ptr_t dev, int phy, int reg, int data)
1548 1.1 ichiro {
1549 1.1 ichiro struct url_softc *sc = USBGETSOFTC(dev);
1550 1.1 ichiro
1551 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1552 1.4 augustss USBDEVNAME(sc->sc_dev), __func__, phy, reg, data));
1553 1.1 ichiro
1554 1.1 ichiro if (sc->sc_dying) {
1555 1.1 ichiro #ifdef DIAGNOSTIC
1556 1.1 ichiro printf("%s: %s: dying\n", USBDEVNAME(sc->sc_dev),
1557 1.4 augustss __func__);
1558 1.1 ichiro #endif
1559 1.1 ichiro return;
1560 1.1 ichiro }
1561 1.1 ichiro
1562 1.1 ichiro url_lock_mii(sc);
1563 1.1 ichiro
1564 1.1 ichiro url_csr_write_2(sc, URL_PHYDAT, data);
1565 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy);
1566 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */
1567 1.1 ichiro
1568 1.1 ichiro for (i=0; i < URL_TIMEOUT; i++) {
1569 1.1 ichiro if (url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN)
1570 1.1 ichiro break;
1571 1.1 ichiro }
1572 1.1 ichiro
1573 1.1 ichiro if (i == URL_TIMEOUT) {
1574 1.1 ichiro printf("%s: MII write timed out\n",
1575 1.1 ichiro USBDEVNAME(sc->sc_dev));
1576 1.1 ichiro }
1577 1.1 ichiro
1578 1.1 ichiro url_unlock_mii(sc);
1579 1.1 ichiro return;
1580 1.1 ichiro }
1581 1.1 ichiro #endif
1582 1.1 ichiro
1583