if_url.c revision 1.56 1 1.56 maya /* $NetBSD: if_url.c,v 1.56 2017/01/12 18:26:08 maya Exp $ */
2 1.43 mrg
3 1.1 ichiro /*
4 1.1 ichiro * Copyright (c) 2001, 2002
5 1.1 ichiro * Shingo WATANABE <nabe (at) nabechan.org>. All rights reserved.
6 1.1 ichiro *
7 1.1 ichiro * Redistribution and use in source and binary forms, with or without
8 1.1 ichiro * modification, are permitted provided that the following conditions
9 1.1 ichiro * are met:
10 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
11 1.1 ichiro * notice, this list of conditions and the following disclaimer.
12 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
14 1.1 ichiro * documentation and/or other materials provided with the distribution.
15 1.8 tsutsui * 3. Neither the name of the author nor the names of any co-contributors
16 1.1 ichiro * may be used to endorse or promote products derived from this software
17 1.1 ichiro * without specific prior written permission.
18 1.1 ichiro *
19 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 1.1 ichiro * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 1.1 ichiro * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 1.1 ichiro * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 1.1 ichiro * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 1.1 ichiro * SUCH DAMAGE.
30 1.1 ichiro *
31 1.1 ichiro */
32 1.1 ichiro
33 1.1 ichiro /*
34 1.1 ichiro * The RTL8150L(Realtek USB to fast ethernet controller) spec can be found at
35 1.1 ichiro * ftp://ftp.realtek.com.tw/lancard/data_sheet/8150/8150v14.pdf
36 1.1 ichiro * ftp://152.104.125.40/lancard/data_sheet/8150/8150v14.pdf
37 1.1 ichiro */
38 1.1 ichiro
39 1.1 ichiro /*
40 1.1 ichiro * TODO:
41 1.1 ichiro * Interrupt Endpoint support
42 1.1 ichiro * External PHYs
43 1.1 ichiro * powerhook() support?
44 1.1 ichiro */
45 1.1 ichiro
46 1.1 ichiro #include <sys/cdefs.h>
47 1.56 maya __KERNEL_RCSID(0, "$NetBSD: if_url.c,v 1.56 2017/01/12 18:26:08 maya Exp $");
48 1.1 ichiro
49 1.46 christos #ifdef _KERNEL_OPT
50 1.1 ichiro #include "opt_inet.h"
51 1.54 skrll #include "opt_usb.h"
52 1.46 christos #endif
53 1.1 ichiro
54 1.1 ichiro #include <sys/param.h>
55 1.1 ichiro #include <sys/systm.h>
56 1.27 xtraeme #include <sys/rwlock.h>
57 1.1 ichiro #include <sys/mbuf.h>
58 1.1 ichiro #include <sys/kernel.h>
59 1.1 ichiro #include <sys/socket.h>
60 1.1 ichiro
61 1.1 ichiro #include <sys/device.h>
62 1.49 riastrad #include <sys/rndsource.h>
63 1.1 ichiro
64 1.1 ichiro #include <net/if.h>
65 1.1 ichiro #include <net/if_arp.h>
66 1.1 ichiro #include <net/if_dl.h>
67 1.1 ichiro #include <net/if_media.h>
68 1.1 ichiro
69 1.1 ichiro #include <net/bpf.h>
70 1.1 ichiro
71 1.1 ichiro #include <net/if_ether.h>
72 1.1 ichiro #ifdef INET
73 1.1 ichiro #include <netinet/in.h>
74 1.1 ichiro #include <netinet/if_inarp.h>
75 1.1 ichiro #endif
76 1.1 ichiro
77 1.1 ichiro #include <dev/mii/mii.h>
78 1.1 ichiro #include <dev/mii/miivar.h>
79 1.1 ichiro #include <dev/mii/urlphyreg.h>
80 1.1 ichiro
81 1.1 ichiro #include <dev/usb/usb.h>
82 1.1 ichiro #include <dev/usb/usbdi.h>
83 1.1 ichiro #include <dev/usb/usbdi_util.h>
84 1.1 ichiro #include <dev/usb/usbdevs.h>
85 1.1 ichiro
86 1.1 ichiro #include <dev/usb/if_urlreg.h>
87 1.1 ichiro
88 1.1 ichiro
89 1.1 ichiro /* Function declarations */
90 1.53 msaitoh int url_match(device_t, cfdata_t, void *);
91 1.53 msaitoh void url_attach(device_t, device_t, void *);
92 1.53 msaitoh int url_detach(device_t, int);
93 1.53 msaitoh int url_activate(device_t, enum devact);
94 1.38 dyoung extern struct cfdriver url_cd;
95 1.53 msaitoh CFATTACH_DECL_NEW(url, sizeof(struct url_softc), url_match, url_attach,
96 1.53 msaitoh url_detach, url_activate);
97 1.1 ichiro
98 1.1 ichiro Static int url_openpipes(struct url_softc *);
99 1.1 ichiro Static int url_rx_list_init(struct url_softc *);
100 1.1 ichiro Static int url_tx_list_init(struct url_softc *);
101 1.1 ichiro Static int url_newbuf(struct url_softc *, struct url_chain *, struct mbuf *);
102 1.1 ichiro Static void url_start(struct ifnet *);
103 1.1 ichiro Static int url_send(struct url_softc *, struct mbuf *, int);
104 1.51 skrll Static void url_txeof(struct usbd_xfer *, void *, usbd_status);
105 1.51 skrll Static void url_rxeof(struct usbd_xfer *, void *, usbd_status);
106 1.1 ichiro Static void url_tick(void *);
107 1.1 ichiro Static void url_tick_task(void *);
108 1.25 christos Static int url_ioctl(struct ifnet *, u_long, void *);
109 1.1 ichiro Static void url_stop_task(struct url_softc *);
110 1.1 ichiro Static void url_stop(struct ifnet *, int);
111 1.1 ichiro Static void url_watchdog(struct ifnet *);
112 1.1 ichiro Static int url_ifmedia_change(struct ifnet *);
113 1.1 ichiro Static void url_ifmedia_status(struct ifnet *, struct ifmediareq *);
114 1.1 ichiro Static void url_lock_mii(struct url_softc *);
115 1.1 ichiro Static void url_unlock_mii(struct url_softc *);
116 1.38 dyoung Static int url_int_miibus_readreg(device_t, int, int);
117 1.38 dyoung Static void url_int_miibus_writereg(device_t, int, int, int);
118 1.44 matt Static void url_miibus_statchg(struct ifnet *);
119 1.1 ichiro Static int url_init(struct ifnet *);
120 1.1 ichiro Static void url_setmulti(struct url_softc *);
121 1.1 ichiro Static void url_reset(struct url_softc *);
122 1.1 ichiro
123 1.1 ichiro Static int url_csr_read_1(struct url_softc *, int);
124 1.1 ichiro Static int url_csr_read_2(struct url_softc *, int);
125 1.1 ichiro Static int url_csr_write_1(struct url_softc *, int, int);
126 1.1 ichiro Static int url_csr_write_2(struct url_softc *, int, int);
127 1.1 ichiro Static int url_csr_write_4(struct url_softc *, int, int);
128 1.1 ichiro Static int url_mem(struct url_softc *, int, int, void *, int);
129 1.1 ichiro
130 1.1 ichiro /* Macros */
131 1.1 ichiro #ifdef URL_DEBUG
132 1.38 dyoung #define DPRINTF(x) if (urldebug) printf x
133 1.38 dyoung #define DPRINTFN(n,x) if (urldebug >= (n)) printf x
134 1.2 ichiro int urldebug = 0;
135 1.1 ichiro #else
136 1.1 ichiro #define DPRINTF(x)
137 1.1 ichiro #define DPRINTFN(n,x)
138 1.1 ichiro #endif
139 1.1 ichiro
140 1.1 ichiro #define URL_SETBIT(sc, reg, x) \
141 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) | (x))
142 1.1 ichiro
143 1.1 ichiro #define URL_SETBIT2(sc, reg, x) \
144 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) | (x))
145 1.1 ichiro
146 1.1 ichiro #define URL_CLRBIT(sc, reg, x) \
147 1.1 ichiro url_csr_write_1(sc, reg, url_csr_read_1(sc, reg) & ~(x))
148 1.1 ichiro
149 1.1 ichiro #define URL_CLRBIT2(sc, reg, x) \
150 1.1 ichiro url_csr_write_2(sc, reg, url_csr_read_2(sc, reg) & ~(x))
151 1.1 ichiro
152 1.1 ichiro static const struct url_type {
153 1.1 ichiro struct usb_devno url_dev;
154 1.51 skrll uint16_t url_flags;
155 1.1 ichiro #define URL_EXT_PHY 0x0001
156 1.1 ichiro } url_devs [] = {
157 1.1 ichiro /* MELCO LUA-KTX */
158 1.1 ichiro {{ USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAKTX }, 0},
159 1.10 mycroft /* Realtek RTL8150L Generic (GREEN HOUSE USBKR100) */
160 1.11 augustss {{ USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8150L}, 0},
161 1.11 augustss /* Longshine LCS-8138TX */
162 1.11 augustss {{ USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_LCS8138TX}, 0},
163 1.11 augustss /* Micronet SP128AR */
164 1.11 augustss {{ USB_VENDOR_MICRONET, USB_PRODUCT_MICRONET_SP128AR}, 0},
165 1.13 itojun /* OQO model 01 */
166 1.13 itojun {{ USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01}, 0},
167 1.1 ichiro };
168 1.17 christos #define url_lookup(v, p) ((const struct url_type *)usb_lookup(url_devs, v, p))
169 1.1 ichiro
170 1.1 ichiro
171 1.1 ichiro /* Probe */
172 1.46 christos int
173 1.38 dyoung url_match(device_t parent, cfdata_t match, void *aux)
174 1.1 ichiro {
175 1.38 dyoung struct usb_attach_arg *uaa = aux;
176 1.1 ichiro
177 1.51 skrll return url_lookup(uaa->uaa_vendor, uaa->uaa_product) != NULL ?
178 1.51 skrll UMATCH_VENDOR_PRODUCT : UMATCH_NONE;
179 1.1 ichiro }
180 1.1 ichiro /* Attach */
181 1.46 christos void
182 1.38 dyoung url_attach(device_t parent, device_t self, void *aux)
183 1.1 ichiro {
184 1.38 dyoung struct url_softc *sc = device_private(self);
185 1.38 dyoung struct usb_attach_arg *uaa = aux;
186 1.51 skrll struct usbd_device *dev = uaa->uaa_device;
187 1.51 skrll struct usbd_interface *iface;
188 1.1 ichiro usbd_status err;
189 1.1 ichiro usb_interface_descriptor_t *id;
190 1.1 ichiro usb_endpoint_descriptor_t *ed;
191 1.16 augustss char *devinfop;
192 1.1 ichiro struct ifnet *ifp;
193 1.1 ichiro struct mii_data *mii;
194 1.1 ichiro u_char eaddr[ETHER_ADDR_LEN];
195 1.1 ichiro int i, s;
196 1.1 ichiro
197 1.32 cube sc->sc_dev = self;
198 1.32 cube
199 1.34 plunky aprint_naive("\n");
200 1.34 plunky aprint_normal("\n");
201 1.34 plunky
202 1.16 augustss devinfop = usbd_devinfo_alloc(dev, 0);
203 1.32 cube aprint_normal_dev(self, "%s\n", devinfop);
204 1.16 augustss usbd_devinfo_free(devinfop);
205 1.1 ichiro
206 1.1 ichiro /* Move the device into the configured state. */
207 1.1 ichiro err = usbd_set_config_no(dev, URL_CONFIG_NO, 1);
208 1.1 ichiro if (err) {
209 1.45 skrll aprint_error_dev(self, "failed to set configuration"
210 1.45 skrll ", err=%s\n", usbd_errstr(err));
211 1.1 ichiro goto bad;
212 1.1 ichiro }
213 1.1 ichiro
214 1.47 jmcneill usb_init_task(&sc->sc_tick_task, url_tick_task, sc, 0);
215 1.27 xtraeme rw_init(&sc->sc_mii_rwlock);
216 1.47 jmcneill usb_init_task(&sc->sc_stop_task, (void (*)(void *))url_stop_task, sc, 0);
217 1.1 ichiro
218 1.1 ichiro /* get control interface */
219 1.1 ichiro err = usbd_device2interface_handle(dev, URL_IFACE_INDEX, &iface);
220 1.1 ichiro if (err) {
221 1.32 cube aprint_error_dev(self, "failed to get interface, err=%s\n",
222 1.1 ichiro usbd_errstr(err));
223 1.1 ichiro goto bad;
224 1.1 ichiro }
225 1.1 ichiro
226 1.1 ichiro sc->sc_udev = dev;
227 1.1 ichiro sc->sc_ctl_iface = iface;
228 1.51 skrll sc->sc_flags = url_lookup(uaa->uaa_vendor, uaa->uaa_product)->url_flags;
229 1.1 ichiro
230 1.1 ichiro /* get interface descriptor */
231 1.1 ichiro id = usbd_get_interface_descriptor(sc->sc_ctl_iface);
232 1.1 ichiro
233 1.1 ichiro /* find endpoints */
234 1.1 ichiro sc->sc_bulkin_no = sc->sc_bulkout_no = sc->sc_intrin_no = -1;
235 1.1 ichiro for (i = 0; i < id->bNumEndpoints; i++) {
236 1.1 ichiro ed = usbd_interface2endpoint_descriptor(sc->sc_ctl_iface, i);
237 1.1 ichiro if (ed == NULL) {
238 1.32 cube aprint_error_dev(self,
239 1.32 cube "couldn't get endpoint %d\n", i);
240 1.1 ichiro goto bad;
241 1.1 ichiro }
242 1.1 ichiro if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
243 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
244 1.1 ichiro sc->sc_bulkin_no = ed->bEndpointAddress; /* RX */
245 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_BULK &&
246 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)
247 1.1 ichiro sc->sc_bulkout_no = ed->bEndpointAddress; /* TX */
248 1.1 ichiro else if ((ed->bmAttributes & UE_XFERTYPE) == UE_INTERRUPT &&
249 1.1 ichiro UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
250 1.1 ichiro sc->sc_intrin_no = ed->bEndpointAddress; /* Status */
251 1.1 ichiro }
252 1.1 ichiro
253 1.1 ichiro if (sc->sc_bulkin_no == -1 || sc->sc_bulkout_no == -1 ||
254 1.1 ichiro sc->sc_intrin_no == -1) {
255 1.32 cube aprint_error_dev(self, "missing endpoint\n");
256 1.1 ichiro goto bad;
257 1.1 ichiro }
258 1.1 ichiro
259 1.1 ichiro s = splnet();
260 1.1 ichiro
261 1.1 ichiro /* reset the adapter */
262 1.1 ichiro url_reset(sc);
263 1.1 ichiro
264 1.1 ichiro /* Get Ethernet Address */
265 1.1 ichiro err = url_mem(sc, URL_CMD_READMEM, URL_IDR0, (void *)eaddr,
266 1.1 ichiro ETHER_ADDR_LEN);
267 1.1 ichiro if (err) {
268 1.32 cube aprint_error_dev(self, "read MAC address failed\n");
269 1.1 ichiro splx(s);
270 1.1 ichiro goto bad;
271 1.1 ichiro }
272 1.1 ichiro
273 1.1 ichiro /* Print Ethernet Address */
274 1.32 cube aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
275 1.1 ichiro
276 1.19 wiz /* initialize interface information */
277 1.1 ichiro ifp = GET_IFP(sc);
278 1.1 ichiro ifp->if_softc = sc;
279 1.3 augustss ifp->if_mtu = ETHERMTU;
280 1.56 maya strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
281 1.1 ichiro ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
282 1.1 ichiro ifp->if_start = url_start;
283 1.1 ichiro ifp->if_ioctl = url_ioctl;
284 1.1 ichiro ifp->if_watchdog = url_watchdog;
285 1.1 ichiro ifp->if_init = url_init;
286 1.1 ichiro ifp->if_stop = url_stop;
287 1.1 ichiro
288 1.1 ichiro IFQ_SET_READY(&ifp->if_snd);
289 1.1 ichiro
290 1.1 ichiro /*
291 1.1 ichiro * Do ifmedia setup.
292 1.1 ichiro */
293 1.1 ichiro mii = &sc->sc_mii;
294 1.1 ichiro mii->mii_ifp = ifp;
295 1.1 ichiro mii->mii_readreg = url_int_miibus_readreg;
296 1.1 ichiro mii->mii_writereg = url_int_miibus_writereg;
297 1.1 ichiro #if 0
298 1.1 ichiro if (sc->sc_flags & URL_EXT_PHY) {
299 1.1 ichiro mii->mii_readreg = url_ext_miibus_readreg;
300 1.1 ichiro mii->mii_writereg = url_ext_miibus_writereg;
301 1.1 ichiro }
302 1.1 ichiro #endif
303 1.1 ichiro mii->mii_statchg = url_miibus_statchg;
304 1.1 ichiro mii->mii_flags = MIIF_AUTOTSLEEP;
305 1.30 dyoung sc->sc_ec.ec_mii = mii;
306 1.1 ichiro ifmedia_init(&mii->mii_media, 0,
307 1.1 ichiro url_ifmedia_change, url_ifmedia_status);
308 1.1 ichiro mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
309 1.1 ichiro if (LIST_FIRST(&mii->mii_phys) == NULL) {
310 1.1 ichiro ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
311 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
312 1.1 ichiro } else
313 1.1 ichiro ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
314 1.1 ichiro
315 1.1 ichiro /* attach the interface */
316 1.1 ichiro if_attach(ifp);
317 1.38 dyoung ether_ifattach(ifp, eaddr);
318 1.1 ichiro
319 1.32 cube rnd_attach_source(&sc->rnd_source, device_xname(self),
320 1.48 tls RND_TYPE_NET, RND_FLAG_DEFAULT);
321 1.1 ichiro
322 1.38 dyoung callout_init(&sc->sc_stat_ch, 0);
323 1.1 ichiro sc->sc_attached = 1;
324 1.1 ichiro splx(s);
325 1.1 ichiro
326 1.38 dyoung usbd_add_drv_event(USB_EVENT_DRIVER_ATTACH, dev, sc->sc_dev);
327 1.1 ichiro
328 1.38 dyoung return;
329 1.1 ichiro
330 1.1 ichiro bad:
331 1.1 ichiro sc->sc_dying = 1;
332 1.38 dyoung return;
333 1.1 ichiro }
334 1.1 ichiro
335 1.1 ichiro /* detach */
336 1.46 christos int
337 1.38 dyoung url_detach(device_t self, int flags)
338 1.1 ichiro {
339 1.38 dyoung struct url_softc *sc = device_private(self);
340 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
341 1.1 ichiro int s;
342 1.1 ichiro
343 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
344 1.1 ichiro
345 1.1 ichiro /* Detached before attached finished */
346 1.1 ichiro if (!sc->sc_attached)
347 1.51 skrll return 0;
348 1.1 ichiro
349 1.38 dyoung callout_stop(&sc->sc_stat_ch);
350 1.1 ichiro
351 1.1 ichiro /* Remove any pending tasks */
352 1.1 ichiro usb_rem_task(sc->sc_udev, &sc->sc_tick_task);
353 1.1 ichiro usb_rem_task(sc->sc_udev, &sc->sc_stop_task);
354 1.1 ichiro
355 1.1 ichiro s = splusb();
356 1.1 ichiro
357 1.1 ichiro if (--sc->sc_refcnt >= 0) {
358 1.1 ichiro /* Wait for processes to go away */
359 1.42 mrg usb_detach_waitold(sc->sc_dev);
360 1.1 ichiro }
361 1.1 ichiro
362 1.1 ichiro if (ifp->if_flags & IFF_RUNNING)
363 1.1 ichiro url_stop(GET_IFP(sc), 1);
364 1.1 ichiro
365 1.1 ichiro rnd_detach_source(&sc->rnd_source);
366 1.1 ichiro mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
367 1.1 ichiro ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
368 1.1 ichiro ether_ifdetach(ifp);
369 1.1 ichiro if_detach(ifp);
370 1.1 ichiro
371 1.1 ichiro #ifdef DIAGNOSTIC
372 1.1 ichiro if (sc->sc_pipe_tx != NULL)
373 1.32 cube aprint_debug_dev(self, "detach has active tx endpoint.\n");
374 1.1 ichiro if (sc->sc_pipe_rx != NULL)
375 1.32 cube aprint_debug_dev(self, "detach has active rx endpoint.\n");
376 1.1 ichiro if (sc->sc_pipe_intr != NULL)
377 1.32 cube aprint_debug_dev(self, "detach has active intr endpoint.\n");
378 1.1 ichiro #endif
379 1.1 ichiro
380 1.1 ichiro sc->sc_attached = 0;
381 1.1 ichiro
382 1.1 ichiro splx(s);
383 1.1 ichiro
384 1.28 xtraeme rw_destroy(&sc->sc_mii_rwlock);
385 1.53 msaitoh usbd_add_drv_event(USB_EVENT_DRIVER_DETACH, sc->sc_udev, sc->sc_dev);
386 1.1 ichiro
387 1.51 skrll return 0;
388 1.1 ichiro }
389 1.1 ichiro
390 1.1 ichiro /* read/write memory */
391 1.1 ichiro Static int
392 1.1 ichiro url_mem(struct url_softc *sc, int cmd, int offset, void *buf, int len)
393 1.1 ichiro {
394 1.1 ichiro usb_device_request_t req;
395 1.1 ichiro usbd_status err;
396 1.1 ichiro
397 1.1 ichiro if (sc == NULL)
398 1.51 skrll return 0;
399 1.1 ichiro
400 1.1 ichiro DPRINTFN(0x200,
401 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
402 1.1 ichiro
403 1.1 ichiro if (sc->sc_dying)
404 1.51 skrll return 0;
405 1.1 ichiro
406 1.1 ichiro if (cmd == URL_CMD_READMEM)
407 1.1 ichiro req.bmRequestType = UT_READ_VENDOR_DEVICE;
408 1.1 ichiro else
409 1.1 ichiro req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
410 1.1 ichiro req.bRequest = URL_REQ_MEM;
411 1.1 ichiro USETW(req.wValue, offset);
412 1.1 ichiro USETW(req.wIndex, 0x0000);
413 1.1 ichiro USETW(req.wLength, len);
414 1.1 ichiro
415 1.1 ichiro sc->sc_refcnt++;
416 1.1 ichiro err = usbd_do_request(sc->sc_udev, &req, buf);
417 1.1 ichiro if (--sc->sc_refcnt < 0)
418 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
419 1.1 ichiro if (err) {
420 1.1 ichiro DPRINTF(("%s: url_mem(): %s failed. off=%04x, err=%d\n",
421 1.38 dyoung device_xname(sc->sc_dev),
422 1.1 ichiro cmd == URL_CMD_READMEM ? "read" : "write",
423 1.1 ichiro offset, err));
424 1.5 augustss }
425 1.1 ichiro
426 1.51 skrll return err;
427 1.1 ichiro }
428 1.1 ichiro
429 1.1 ichiro /* read 1byte from register */
430 1.1 ichiro Static int
431 1.1 ichiro url_csr_read_1(struct url_softc *sc, int reg)
432 1.1 ichiro {
433 1.51 skrll uint8_t val = 0;
434 1.1 ichiro
435 1.1 ichiro DPRINTFN(0x100,
436 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
437 1.1 ichiro
438 1.1 ichiro if (sc->sc_dying)
439 1.51 skrll return 0;
440 1.5 augustss
441 1.51 skrll return url_mem(sc, URL_CMD_READMEM, reg, &val, 1) ? 0 : val;
442 1.1 ichiro }
443 1.1 ichiro
444 1.1 ichiro /* read 2bytes from register */
445 1.1 ichiro Static int
446 1.1 ichiro url_csr_read_2(struct url_softc *sc, int reg)
447 1.1 ichiro {
448 1.1 ichiro uWord val;
449 1.1 ichiro
450 1.1 ichiro DPRINTFN(0x100,
451 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
452 1.1 ichiro
453 1.1 ichiro if (sc->sc_dying)
454 1.51 skrll return 0;
455 1.5 augustss
456 1.1 ichiro USETW(val, 0);
457 1.51 skrll return url_mem(sc, URL_CMD_READMEM, reg, &val, 2) ? 0 : UGETW(val);
458 1.1 ichiro }
459 1.1 ichiro
460 1.1 ichiro /* write 1byte to register */
461 1.1 ichiro Static int
462 1.1 ichiro url_csr_write_1(struct url_softc *sc, int reg, int aval)
463 1.1 ichiro {
464 1.51 skrll uint8_t val = aval;
465 1.1 ichiro
466 1.1 ichiro DPRINTFN(0x100,
467 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
468 1.1 ichiro
469 1.1 ichiro if (sc->sc_dying)
470 1.51 skrll return 0;
471 1.5 augustss
472 1.51 skrll return url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 1) ? -1 : 0;
473 1.1 ichiro }
474 1.1 ichiro
475 1.1 ichiro /* write 2bytes to register */
476 1.1 ichiro Static int
477 1.1 ichiro url_csr_write_2(struct url_softc *sc, int reg, int aval)
478 1.1 ichiro {
479 1.1 ichiro uWord val;
480 1.1 ichiro
481 1.1 ichiro DPRINTFN(0x100,
482 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
483 1.1 ichiro
484 1.1 ichiro USETW(val, aval);
485 1.1 ichiro
486 1.1 ichiro if (sc->sc_dying)
487 1.51 skrll return 0;
488 1.5 augustss
489 1.51 skrll return url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 2) ? -1 : 0;
490 1.1 ichiro }
491 1.1 ichiro
492 1.1 ichiro /* write 4bytes to register */
493 1.1 ichiro Static int
494 1.1 ichiro url_csr_write_4(struct url_softc *sc, int reg, int aval)
495 1.1 ichiro {
496 1.1 ichiro uDWord val;
497 1.1 ichiro
498 1.1 ichiro DPRINTFN(0x100,
499 1.38 dyoung ("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
500 1.1 ichiro
501 1.1 ichiro USETDW(val, aval);
502 1.1 ichiro
503 1.1 ichiro if (sc->sc_dying)
504 1.51 skrll return 0;
505 1.5 augustss
506 1.51 skrll return url_mem(sc, URL_CMD_WRITEMEM, reg, &val, 4) ? -1 : 0;
507 1.1 ichiro }
508 1.1 ichiro
509 1.1 ichiro Static int
510 1.1 ichiro url_init(struct ifnet *ifp)
511 1.1 ichiro {
512 1.1 ichiro struct url_softc *sc = ifp->if_softc;
513 1.1 ichiro struct mii_data *mii = GET_MII(sc);
514 1.29 dyoung const u_char *eaddr;
515 1.30 dyoung int i, rc, s;
516 1.1 ichiro
517 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
518 1.5 augustss
519 1.1 ichiro if (sc->sc_dying)
520 1.51 skrll return EIO;
521 1.1 ichiro
522 1.1 ichiro s = splnet();
523 1.1 ichiro
524 1.1 ichiro /* Cancel pending I/O and free all TX/RX buffers */
525 1.1 ichiro url_stop(ifp, 1);
526 1.1 ichiro
527 1.29 dyoung eaddr = CLLADDR(ifp->if_sadl);
528 1.1 ichiro for (i = 0; i < ETHER_ADDR_LEN; i++)
529 1.1 ichiro url_csr_write_1(sc, URL_IDR0 + i, eaddr[i]);
530 1.1 ichiro
531 1.1 ichiro /* Init transmission control register */
532 1.1 ichiro URL_CLRBIT(sc, URL_TCR,
533 1.1 ichiro URL_TCR_TXRR1 | URL_TCR_TXRR0 |
534 1.1 ichiro URL_TCR_IFG1 | URL_TCR_IFG0 |
535 1.1 ichiro URL_TCR_NOCRC);
536 1.1 ichiro
537 1.1 ichiro /* Init receive control register */
538 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_TAIL | URL_RCR_AD);
539 1.1 ichiro if (ifp->if_flags & IFF_BROADCAST)
540 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AB);
541 1.1 ichiro else
542 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AB);
543 1.1 ichiro
544 1.1 ichiro /* If we want promiscuous mode, accept all physical frames. */
545 1.1 ichiro if (ifp->if_flags & IFF_PROMISC)
546 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
547 1.1 ichiro else
548 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
549 1.1 ichiro
550 1.5 augustss
551 1.1 ichiro /* Load the multicast filter */
552 1.1 ichiro url_setmulti(sc);
553 1.1 ichiro
554 1.1 ichiro /* Enable RX and TX */
555 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_TE | URL_CR_RE);
556 1.1 ichiro
557 1.30 dyoung if ((rc = mii_mediachg(mii)) == ENXIO)
558 1.30 dyoung rc = 0;
559 1.30 dyoung else if (rc != 0)
560 1.30 dyoung goto out;
561 1.1 ichiro
562 1.1 ichiro if (sc->sc_pipe_tx == NULL || sc->sc_pipe_rx == NULL) {
563 1.1 ichiro if (url_openpipes(sc)) {
564 1.1 ichiro splx(s);
565 1.51 skrll return EIO;
566 1.1 ichiro }
567 1.1 ichiro }
568 1.51 skrll /* Initialize transmit ring */
569 1.51 skrll if (url_tx_list_init(sc)) {
570 1.51 skrll printf("%s: tx list init failed\n", device_xname(sc->sc_dev));
571 1.51 skrll splx(s);
572 1.51 skrll return EIO;
573 1.51 skrll }
574 1.51 skrll
575 1.51 skrll /* Initialize receive ring */
576 1.51 skrll if (url_rx_list_init(sc)) {
577 1.51 skrll printf("%s: rx list init failed\n", device_xname(sc->sc_dev));
578 1.51 skrll splx(s);
579 1.51 skrll return EIO;
580 1.51 skrll }
581 1.51 skrll /* Start up the receive pipe. */
582 1.51 skrll for (i = 0; i < URL_RX_LIST_CNT; i++) {
583 1.51 skrll struct url_chain *c = &sc->sc_cdata.url_rx_chain[i];
584 1.51 skrll
585 1.51 skrll usbd_setup_xfer(c->url_xfer, c, c->url_buf, URL_BUFSZ,
586 1.51 skrll USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, url_rxeof);
587 1.51 skrll (void)usbd_transfer(c->url_xfer);
588 1.51 skrll DPRINTF(("%s: %s: start read\n", device_xname(sc->sc_dev),
589 1.51 skrll __func__));
590 1.51 skrll }
591 1.1 ichiro
592 1.1 ichiro ifp->if_flags |= IFF_RUNNING;
593 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
594 1.1 ichiro
595 1.38 dyoung callout_reset(&sc->sc_stat_ch, hz, url_tick, sc);
596 1.1 ichiro
597 1.30 dyoung out:
598 1.30 dyoung splx(s);
599 1.30 dyoung return rc;
600 1.1 ichiro }
601 1.1 ichiro
602 1.1 ichiro Static void
603 1.1 ichiro url_reset(struct url_softc *sc)
604 1.1 ichiro {
605 1.1 ichiro int i;
606 1.5 augustss
607 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
608 1.1 ichiro
609 1.1 ichiro if (sc->sc_dying)
610 1.1 ichiro return;
611 1.1 ichiro
612 1.1 ichiro URL_SETBIT(sc, URL_CR, URL_CR_SOFT_RST);
613 1.1 ichiro
614 1.1 ichiro for (i = 0; i < URL_TX_TIMEOUT; i++) {
615 1.1 ichiro if (!(url_csr_read_1(sc, URL_CR) & URL_CR_SOFT_RST))
616 1.1 ichiro break;
617 1.1 ichiro delay(10); /* XXX */
618 1.1 ichiro }
619 1.1 ichiro
620 1.1 ichiro delay(10000); /* XXX */
621 1.1 ichiro }
622 1.1 ichiro
623 1.1 ichiro int
624 1.38 dyoung url_activate(device_t self, enum devact act)
625 1.1 ichiro {
626 1.32 cube struct url_softc *sc = device_private(self);
627 1.1 ichiro
628 1.38 dyoung DPRINTF(("%s: %s: enter, act=%d\n", device_xname(sc->sc_dev),
629 1.4 augustss __func__, act));
630 1.1 ichiro
631 1.1 ichiro switch (act) {
632 1.1 ichiro case DVACT_DEACTIVATE:
633 1.1 ichiro if_deactivate(&sc->sc_ec.ec_if);
634 1.1 ichiro sc->sc_dying = 1;
635 1.35 dyoung return 0;
636 1.35 dyoung default:
637 1.35 dyoung return EOPNOTSUPP;
638 1.1 ichiro }
639 1.1 ichiro }
640 1.1 ichiro
641 1.1 ichiro #define url_calchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
642 1.1 ichiro
643 1.1 ichiro
644 1.1 ichiro Static void
645 1.1 ichiro url_setmulti(struct url_softc *sc)
646 1.1 ichiro {
647 1.1 ichiro struct ifnet *ifp;
648 1.1 ichiro struct ether_multi *enm;
649 1.1 ichiro struct ether_multistep step;
650 1.51 skrll uint32_t hashes[2] = { 0, 0 };
651 1.1 ichiro int h = 0;
652 1.1 ichiro int mcnt = 0;
653 1.1 ichiro
654 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
655 1.1 ichiro
656 1.1 ichiro if (sc->sc_dying)
657 1.1 ichiro return;
658 1.1 ichiro
659 1.1 ichiro ifp = GET_IFP(sc);
660 1.1 ichiro
661 1.1 ichiro if (ifp->if_flags & IFF_PROMISC) {
662 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
663 1.1 ichiro return;
664 1.1 ichiro } else if (ifp->if_flags & IFF_ALLMULTI) {
665 1.1 ichiro allmulti:
666 1.1 ichiro ifp->if_flags |= IFF_ALLMULTI;
667 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AAM);
668 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAP);
669 1.1 ichiro return;
670 1.1 ichiro }
671 1.1 ichiro
672 1.1 ichiro /* first, zot all the existing hash bits */
673 1.1 ichiro url_csr_write_4(sc, URL_MAR0, 0);
674 1.1 ichiro url_csr_write_4(sc, URL_MAR4, 0);
675 1.1 ichiro
676 1.1 ichiro /* now program new ones */
677 1.1 ichiro ETHER_FIRST_MULTI(step, &sc->sc_ec, enm);
678 1.1 ichiro while (enm != NULL) {
679 1.1 ichiro if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
680 1.1 ichiro ETHER_ADDR_LEN) != 0)
681 1.1 ichiro goto allmulti;
682 1.1 ichiro
683 1.1 ichiro h = url_calchash(enm->enm_addrlo);
684 1.1 ichiro if (h < 32)
685 1.1 ichiro hashes[0] |= (1 << h);
686 1.1 ichiro else
687 1.1 ichiro hashes[1] |= (1 << (h -32));
688 1.1 ichiro mcnt++;
689 1.1 ichiro ETHER_NEXT_MULTI(step, enm);
690 1.1 ichiro }
691 1.1 ichiro
692 1.1 ichiro ifp->if_flags &= ~IFF_ALLMULTI;
693 1.1 ichiro
694 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AAM|URL_RCR_AAP);
695 1.1 ichiro
696 1.1 ichiro if (mcnt){
697 1.1 ichiro URL_SETBIT2(sc, URL_RCR, URL_RCR_AM);
698 1.1 ichiro } else {
699 1.1 ichiro URL_CLRBIT2(sc, URL_RCR, URL_RCR_AM);
700 1.1 ichiro }
701 1.1 ichiro url_csr_write_4(sc, URL_MAR0, hashes[0]);
702 1.1 ichiro url_csr_write_4(sc, URL_MAR4, hashes[1]);
703 1.1 ichiro }
704 1.1 ichiro
705 1.1 ichiro Static int
706 1.1 ichiro url_openpipes(struct url_softc *sc)
707 1.1 ichiro {
708 1.1 ichiro usbd_status err;
709 1.1 ichiro int error = 0;
710 1.1 ichiro
711 1.1 ichiro if (sc->sc_dying)
712 1.51 skrll return EIO;
713 1.5 augustss
714 1.1 ichiro sc->sc_refcnt++;
715 1.1 ichiro
716 1.1 ichiro /* Open RX pipe */
717 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkin_no,
718 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_rx);
719 1.1 ichiro if (err) {
720 1.1 ichiro printf("%s: open rx pipe failed: %s\n",
721 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
722 1.1 ichiro error = EIO;
723 1.1 ichiro goto done;
724 1.1 ichiro }
725 1.5 augustss
726 1.1 ichiro /* Open TX pipe */
727 1.1 ichiro err = usbd_open_pipe(sc->sc_ctl_iface, sc->sc_bulkout_no,
728 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_tx);
729 1.1 ichiro if (err) {
730 1.1 ichiro printf("%s: open tx pipe failed: %s\n",
731 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
732 1.1 ichiro error = EIO;
733 1.1 ichiro goto done;
734 1.1 ichiro }
735 1.1 ichiro
736 1.1 ichiro #if 0
737 1.1 ichiro /* XXX: interrupt endpoint is not yet supported */
738 1.1 ichiro /* Open Interrupt pipe */
739 1.1 ichiro err = usbd_open_pipe_intr(sc->sc_ctl_iface, sc->sc_intrin_no,
740 1.1 ichiro USBD_EXCLUSIVE_USE, &sc->sc_pipe_intr, sc,
741 1.1 ichiro &sc->sc_cdata.url_ibuf, URL_INTR_PKGLEN,
742 1.24 drochner url_intr, USBD_DEFAULT_INTERVAL);
743 1.1 ichiro if (err) {
744 1.1 ichiro printf("%s: open intr pipe failed: %s\n",
745 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
746 1.1 ichiro error = EIO;
747 1.1 ichiro goto done;
748 1.1 ichiro }
749 1.1 ichiro #endif
750 1.1 ichiro
751 1.1 ichiro done:
752 1.1 ichiro if (--sc->sc_refcnt < 0)
753 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
754 1.5 augustss
755 1.51 skrll return error;
756 1.1 ichiro }
757 1.1 ichiro
758 1.1 ichiro Static int
759 1.1 ichiro url_newbuf(struct url_softc *sc, struct url_chain *c, struct mbuf *m)
760 1.1 ichiro {
761 1.1 ichiro struct mbuf *m_new = NULL;
762 1.1 ichiro
763 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
764 1.1 ichiro
765 1.1 ichiro if (m == NULL) {
766 1.1 ichiro MGETHDR(m_new, M_DONTWAIT, MT_DATA);
767 1.1 ichiro if (m_new == NULL) {
768 1.1 ichiro printf("%s: no memory for rx list "
769 1.38 dyoung "-- packet dropped!\n", device_xname(sc->sc_dev));
770 1.51 skrll return ENOBUFS;
771 1.1 ichiro }
772 1.1 ichiro MCLGET(m_new, M_DONTWAIT);
773 1.1 ichiro if (!(m_new->m_flags & M_EXT)) {
774 1.1 ichiro printf("%s: no memory for rx list "
775 1.38 dyoung "-- packet dropped!\n", device_xname(sc->sc_dev));
776 1.1 ichiro m_freem(m_new);
777 1.51 skrll return ENOBUFS;
778 1.1 ichiro }
779 1.1 ichiro m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
780 1.1 ichiro } else {
781 1.1 ichiro m_new = m;
782 1.1 ichiro m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
783 1.1 ichiro m_new->m_data = m_new->m_ext.ext_buf;
784 1.1 ichiro }
785 1.1 ichiro
786 1.1 ichiro m_adj(m_new, ETHER_ALIGN);
787 1.1 ichiro c->url_mbuf = m_new;
788 1.1 ichiro
789 1.51 skrll return 0;
790 1.1 ichiro }
791 1.5 augustss
792 1.1 ichiro
793 1.1 ichiro Static int
794 1.1 ichiro url_rx_list_init(struct url_softc *sc)
795 1.1 ichiro {
796 1.1 ichiro struct url_cdata *cd;
797 1.1 ichiro struct url_chain *c;
798 1.1 ichiro int i;
799 1.1 ichiro
800 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
801 1.1 ichiro
802 1.1 ichiro cd = &sc->sc_cdata;
803 1.1 ichiro for (i = 0; i < URL_RX_LIST_CNT; i++) {
804 1.1 ichiro c = &cd->url_rx_chain[i];
805 1.1 ichiro c->url_sc = sc;
806 1.1 ichiro c->url_idx = i;
807 1.1 ichiro if (url_newbuf(sc, c, NULL) == ENOBUFS)
808 1.51 skrll return ENOBUFS;
809 1.1 ichiro if (c->url_xfer == NULL) {
810 1.51 skrll int error = usbd_create_xfer(sc->sc_pipe_rx, URL_BUFSZ,
811 1.51 skrll USBD_SHORT_XFER_OK, 0, &c->url_xfer);
812 1.51 skrll if (error)
813 1.51 skrll return error;
814 1.51 skrll c->url_buf = usbd_get_buffer(c->url_xfer);
815 1.1 ichiro }
816 1.1 ichiro }
817 1.5 augustss
818 1.51 skrll return 0;
819 1.1 ichiro }
820 1.1 ichiro
821 1.1 ichiro Static int
822 1.1 ichiro url_tx_list_init(struct url_softc *sc)
823 1.1 ichiro {
824 1.1 ichiro struct url_cdata *cd;
825 1.1 ichiro struct url_chain *c;
826 1.1 ichiro int i;
827 1.1 ichiro
828 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
829 1.1 ichiro
830 1.1 ichiro cd = &sc->sc_cdata;
831 1.1 ichiro for (i = 0; i < URL_TX_LIST_CNT; i++) {
832 1.1 ichiro c = &cd->url_tx_chain[i];
833 1.1 ichiro c->url_sc = sc;
834 1.1 ichiro c->url_idx = i;
835 1.1 ichiro c->url_mbuf = NULL;
836 1.1 ichiro if (c->url_xfer == NULL) {
837 1.51 skrll int error = usbd_create_xfer(sc->sc_pipe_tx, URL_BUFSZ,
838 1.51 skrll USBD_FORCE_SHORT_XFER, 0, &c->url_xfer);
839 1.51 skrll if (error)
840 1.51 skrll return error;
841 1.51 skrll c->url_buf = usbd_get_buffer(c->url_xfer);
842 1.1 ichiro }
843 1.1 ichiro }
844 1.5 augustss
845 1.51 skrll return 0;
846 1.1 ichiro }
847 1.1 ichiro
848 1.1 ichiro Static void
849 1.1 ichiro url_start(struct ifnet *ifp)
850 1.1 ichiro {
851 1.1 ichiro struct url_softc *sc = ifp->if_softc;
852 1.1 ichiro struct mbuf *m_head = NULL;
853 1.5 augustss
854 1.38 dyoung DPRINTF(("%s: %s: enter, link=%d\n", device_xname(sc->sc_dev),
855 1.4 augustss __func__, sc->sc_link));
856 1.1 ichiro
857 1.1 ichiro if (sc->sc_dying)
858 1.1 ichiro return;
859 1.1 ichiro
860 1.1 ichiro if (!sc->sc_link)
861 1.1 ichiro return;
862 1.1 ichiro
863 1.1 ichiro if (ifp->if_flags & IFF_OACTIVE)
864 1.1 ichiro return;
865 1.1 ichiro
866 1.1 ichiro IFQ_POLL(&ifp->if_snd, m_head);
867 1.1 ichiro if (m_head == NULL)
868 1.1 ichiro return;
869 1.1 ichiro
870 1.1 ichiro if (url_send(sc, m_head, 0)) {
871 1.1 ichiro ifp->if_flags |= IFF_OACTIVE;
872 1.1 ichiro return;
873 1.1 ichiro }
874 1.1 ichiro
875 1.1 ichiro IFQ_DEQUEUE(&ifp->if_snd, m_head);
876 1.1 ichiro
877 1.37 joerg bpf_mtap(ifp, m_head);
878 1.1 ichiro
879 1.1 ichiro ifp->if_flags |= IFF_OACTIVE;
880 1.1 ichiro
881 1.1 ichiro /* Set a timeout in case the chip goes out to lunch. */
882 1.1 ichiro ifp->if_timer = 5;
883 1.1 ichiro }
884 1.1 ichiro
885 1.1 ichiro Static int
886 1.1 ichiro url_send(struct url_softc *sc, struct mbuf *m, int idx)
887 1.1 ichiro {
888 1.1 ichiro int total_len;
889 1.1 ichiro struct url_chain *c;
890 1.1 ichiro usbd_status err;
891 1.1 ichiro
892 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev),__func__));
893 1.1 ichiro
894 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[idx];
895 1.1 ichiro
896 1.1 ichiro /* Copy the mbuf data into a contiguous buffer */
897 1.1 ichiro m_copydata(m, 0, m->m_pkthdr.len, c->url_buf);
898 1.1 ichiro c->url_mbuf = m;
899 1.1 ichiro total_len = m->m_pkthdr.len;
900 1.1 ichiro
901 1.7 bouyer if (total_len < URL_MIN_FRAME_LEN) {
902 1.7 bouyer memset(c->url_buf + total_len, 0,
903 1.7 bouyer URL_MIN_FRAME_LEN - total_len);
904 1.1 ichiro total_len = URL_MIN_FRAME_LEN;
905 1.7 bouyer }
906 1.51 skrll usbd_setup_xfer(c->url_xfer,c, c->url_buf, total_len,
907 1.51 skrll USBD_FORCE_SHORT_XFER, URL_TX_TIMEOUT, url_txeof);
908 1.1 ichiro
909 1.1 ichiro /* Transmit */
910 1.1 ichiro sc->sc_refcnt++;
911 1.1 ichiro err = usbd_transfer(c->url_xfer);
912 1.1 ichiro if (--sc->sc_refcnt < 0)
913 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
914 1.1 ichiro if (err != USBD_IN_PROGRESS) {
915 1.38 dyoung printf("%s: url_send error=%s\n", device_xname(sc->sc_dev),
916 1.1 ichiro usbd_errstr(err));
917 1.1 ichiro /* Stop the interface */
918 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_stop_task,
919 1.22 joerg USB_TASKQ_DRIVER);
920 1.51 skrll return EIO;
921 1.1 ichiro }
922 1.1 ichiro
923 1.38 dyoung DPRINTF(("%s: %s: send %d bytes\n", device_xname(sc->sc_dev),
924 1.4 augustss __func__, total_len));
925 1.1 ichiro
926 1.1 ichiro sc->sc_cdata.url_tx_cnt++;
927 1.1 ichiro
928 1.51 skrll return 0;
929 1.1 ichiro }
930 1.1 ichiro
931 1.1 ichiro Static void
932 1.51 skrll url_txeof(struct usbd_xfer *xfer, void *priv,
933 1.21 christos usbd_status status)
934 1.1 ichiro {
935 1.1 ichiro struct url_chain *c = priv;
936 1.1 ichiro struct url_softc *sc = c->url_sc;
937 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
938 1.1 ichiro int s;
939 1.1 ichiro
940 1.1 ichiro if (sc->sc_dying)
941 1.1 ichiro return;
942 1.1 ichiro
943 1.1 ichiro s = splnet();
944 1.1 ichiro
945 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
946 1.1 ichiro
947 1.1 ichiro ifp->if_timer = 0;
948 1.1 ichiro ifp->if_flags &= ~IFF_OACTIVE;
949 1.1 ichiro
950 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
951 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
952 1.1 ichiro splx(s);
953 1.1 ichiro return;
954 1.1 ichiro }
955 1.1 ichiro ifp->if_oerrors++;
956 1.38 dyoung printf("%s: usb error on tx: %s\n", device_xname(sc->sc_dev),
957 1.1 ichiro usbd_errstr(status));
958 1.1 ichiro if (status == USBD_STALLED) {
959 1.1 ichiro sc->sc_refcnt++;
960 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_tx);
961 1.1 ichiro if (--sc->sc_refcnt < 0)
962 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
963 1.1 ichiro }
964 1.1 ichiro splx(s);
965 1.1 ichiro return;
966 1.1 ichiro }
967 1.1 ichiro
968 1.1 ichiro ifp->if_opackets++;
969 1.1 ichiro
970 1.6 martin m_freem(c->url_mbuf);
971 1.1 ichiro c->url_mbuf = NULL;
972 1.1 ichiro
973 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
974 1.1 ichiro url_start(ifp);
975 1.1 ichiro
976 1.1 ichiro splx(s);
977 1.1 ichiro }
978 1.1 ichiro
979 1.1 ichiro Static void
980 1.51 skrll url_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
981 1.1 ichiro {
982 1.1 ichiro struct url_chain *c = priv;
983 1.1 ichiro struct url_softc *sc = c->url_sc;
984 1.1 ichiro struct ifnet *ifp = GET_IFP(sc);
985 1.1 ichiro struct mbuf *m;
986 1.51 skrll uint32_t total_len;
987 1.1 ichiro url_rxhdr_t rxhdr;
988 1.1 ichiro int s;
989 1.1 ichiro
990 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev),__func__));
991 1.1 ichiro
992 1.1 ichiro if (sc->sc_dying)
993 1.1 ichiro return;
994 1.1 ichiro
995 1.1 ichiro if (status != USBD_NORMAL_COMPLETION) {
996 1.1 ichiro if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
997 1.1 ichiro return;
998 1.1 ichiro sc->sc_rx_errs++;
999 1.1 ichiro if (usbd_ratecheck(&sc->sc_rx_notice)) {
1000 1.1 ichiro printf("%s: %u usb errors on rx: %s\n",
1001 1.38 dyoung device_xname(sc->sc_dev), sc->sc_rx_errs,
1002 1.1 ichiro usbd_errstr(status));
1003 1.1 ichiro sc->sc_rx_errs = 0;
1004 1.1 ichiro }
1005 1.1 ichiro if (status == USBD_STALLED) {
1006 1.1 ichiro sc->sc_refcnt++;
1007 1.18 augustss usbd_clear_endpoint_stall_async(sc->sc_pipe_rx);
1008 1.1 ichiro if (--sc->sc_refcnt < 0)
1009 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
1010 1.1 ichiro }
1011 1.1 ichiro goto done;
1012 1.1 ichiro }
1013 1.1 ichiro
1014 1.1 ichiro usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL);
1015 1.1 ichiro
1016 1.1 ichiro memcpy(mtod(c->url_mbuf, char *), c->url_buf, total_len);
1017 1.1 ichiro
1018 1.1 ichiro if (total_len <= ETHER_CRC_LEN) {
1019 1.1 ichiro ifp->if_ierrors++;
1020 1.1 ichiro goto done;
1021 1.1 ichiro }
1022 1.1 ichiro
1023 1.1 ichiro memcpy(&rxhdr, c->url_buf + total_len - ETHER_CRC_LEN, sizeof(rxhdr));
1024 1.1 ichiro
1025 1.1 ichiro DPRINTF(("%s: RX Status: %dbytes%s%s%s%s packets\n",
1026 1.38 dyoung device_xname(sc->sc_dev),
1027 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_BYTEC_MASK,
1028 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_VALID_MASK ? ", Valid" : "",
1029 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_RUNTPKT_MASK ? ", Runt" : "",
1030 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_PHYPKT_MASK ? ", Physical match" : "",
1031 1.1 ichiro UGETW(rxhdr) & URL_RXHDR_MCASTPKT_MASK ? ", Multicast" : ""));
1032 1.1 ichiro
1033 1.1 ichiro if ((UGETW(rxhdr) & URL_RXHDR_VALID_MASK) == 0) {
1034 1.1 ichiro ifp->if_ierrors++;
1035 1.1 ichiro goto done;
1036 1.1 ichiro }
1037 1.1 ichiro
1038 1.1 ichiro total_len -= ETHER_CRC_LEN;
1039 1.1 ichiro
1040 1.1 ichiro m = c->url_mbuf;
1041 1.1 ichiro m->m_pkthdr.len = m->m_len = total_len;
1042 1.52 ozaki m_set_rcvif(m, ifp);
1043 1.1 ichiro
1044 1.1 ichiro s = splnet();
1045 1.1 ichiro
1046 1.1 ichiro if (url_newbuf(sc, c, NULL) == ENOBUFS) {
1047 1.1 ichiro ifp->if_ierrors++;
1048 1.1 ichiro goto done1;
1049 1.1 ichiro }
1050 1.1 ichiro
1051 1.38 dyoung DPRINTF(("%s: %s: deliver %d\n", device_xname(sc->sc_dev),
1052 1.4 augustss __func__, m->m_len));
1053 1.50 ozaki if_percpuq_enqueue((ifp)->if_percpuq, (m));
1054 1.1 ichiro
1055 1.1 ichiro done1:
1056 1.1 ichiro splx(s);
1057 1.1 ichiro
1058 1.1 ichiro done:
1059 1.1 ichiro /* Setup new transfer */
1060 1.51 skrll usbd_setup_xfer(xfer, c, c->url_buf, URL_BUFSZ, USBD_SHORT_XFER_OK,
1061 1.51 skrll USBD_NO_TIMEOUT, url_rxeof);
1062 1.1 ichiro sc->sc_refcnt++;
1063 1.1 ichiro usbd_transfer(xfer);
1064 1.1 ichiro if (--sc->sc_refcnt < 0)
1065 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
1066 1.1 ichiro
1067 1.38 dyoung DPRINTF(("%s: %s: start rx\n", device_xname(sc->sc_dev), __func__));
1068 1.1 ichiro }
1069 1.1 ichiro
1070 1.1 ichiro #if 0
1071 1.33 cegger Static void url_intr(void)
1072 1.1 ichiro {
1073 1.1 ichiro }
1074 1.1 ichiro #endif
1075 1.1 ichiro
1076 1.1 ichiro Static int
1077 1.25 christos url_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1078 1.1 ichiro {
1079 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1080 1.1 ichiro int s, error = 0;
1081 1.1 ichiro
1082 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1083 1.1 ichiro
1084 1.1 ichiro if (sc->sc_dying)
1085 1.51 skrll return EIO;
1086 1.1 ichiro
1087 1.1 ichiro s = splnet();
1088 1.1 ichiro
1089 1.30 dyoung error = ether_ioctl(ifp, cmd, data);
1090 1.30 dyoung if (error == ENETRESET) {
1091 1.30 dyoung if (ifp->if_flags & IFF_RUNNING)
1092 1.30 dyoung url_setmulti(sc);
1093 1.30 dyoung error = 0;
1094 1.1 ichiro }
1095 1.1 ichiro
1096 1.1 ichiro splx(s);
1097 1.1 ichiro
1098 1.51 skrll return error;
1099 1.1 ichiro }
1100 1.1 ichiro
1101 1.1 ichiro Static void
1102 1.1 ichiro url_watchdog(struct ifnet *ifp)
1103 1.1 ichiro {
1104 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1105 1.1 ichiro struct url_chain *c;
1106 1.1 ichiro usbd_status stat;
1107 1.1 ichiro int s;
1108 1.5 augustss
1109 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1110 1.1 ichiro
1111 1.1 ichiro ifp->if_oerrors++;
1112 1.38 dyoung printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
1113 1.1 ichiro
1114 1.1 ichiro s = splusb();
1115 1.1 ichiro c = &sc->sc_cdata.url_tx_chain[0];
1116 1.1 ichiro usbd_get_xfer_status(c->url_xfer, NULL, NULL, NULL, &stat);
1117 1.1 ichiro url_txeof(c->url_xfer, c, stat);
1118 1.1 ichiro
1119 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1120 1.1 ichiro url_start(ifp);
1121 1.1 ichiro splx(s);
1122 1.1 ichiro }
1123 1.1 ichiro
1124 1.1 ichiro Static void
1125 1.1 ichiro url_stop_task(struct url_softc *sc)
1126 1.1 ichiro {
1127 1.1 ichiro url_stop(GET_IFP(sc), 1);
1128 1.1 ichiro }
1129 1.1 ichiro
1130 1.1 ichiro /* Stop the adapter and free any mbufs allocated to the RX and TX lists. */
1131 1.1 ichiro Static void
1132 1.23 christos url_stop(struct ifnet *ifp, int disable)
1133 1.1 ichiro {
1134 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1135 1.1 ichiro usbd_status err;
1136 1.1 ichiro int i;
1137 1.5 augustss
1138 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1139 1.1 ichiro
1140 1.1 ichiro ifp->if_timer = 0;
1141 1.1 ichiro
1142 1.1 ichiro url_reset(sc);
1143 1.1 ichiro
1144 1.38 dyoung callout_stop(&sc->sc_stat_ch);
1145 1.1 ichiro
1146 1.1 ichiro /* Stop transfers */
1147 1.1 ichiro /* RX endpoint */
1148 1.1 ichiro if (sc->sc_pipe_rx != NULL) {
1149 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_rx);
1150 1.1 ichiro if (err)
1151 1.1 ichiro printf("%s: abort rx pipe failed: %s\n",
1152 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
1153 1.1 ichiro }
1154 1.1 ichiro
1155 1.1 ichiro /* TX endpoint */
1156 1.1 ichiro if (sc->sc_pipe_tx != NULL) {
1157 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_tx);
1158 1.1 ichiro if (err)
1159 1.1 ichiro printf("%s: abort tx pipe failed: %s\n",
1160 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
1161 1.1 ichiro }
1162 1.1 ichiro
1163 1.1 ichiro #if 0
1164 1.1 ichiro /* XXX: Interrupt endpoint is not yet supported!! */
1165 1.1 ichiro /* Interrupt endpoint */
1166 1.1 ichiro if (sc->sc_pipe_intr != NULL) {
1167 1.1 ichiro err = usbd_abort_pipe(sc->sc_pipe_intr);
1168 1.1 ichiro if (err)
1169 1.1 ichiro printf("%s: abort intr pipe failed: %s\n",
1170 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
1171 1.1 ichiro err = usbd_close_pipe(sc->sc_pipe_intr);
1172 1.1 ichiro if (err)
1173 1.1 ichiro printf("%s: close intr pipe failed: %s\n",
1174 1.38 dyoung device_xname(sc->sc_dev), usbd_errstr(err));
1175 1.1 ichiro sc->sc_pipe_intr = NULL;
1176 1.1 ichiro }
1177 1.1 ichiro #endif
1178 1.1 ichiro
1179 1.1 ichiro /* Free RX resources. */
1180 1.1 ichiro for (i = 0; i < URL_RX_LIST_CNT; i++) {
1181 1.1 ichiro if (sc->sc_cdata.url_rx_chain[i].url_mbuf != NULL) {
1182 1.1 ichiro m_freem(sc->sc_cdata.url_rx_chain[i].url_mbuf);
1183 1.1 ichiro sc->sc_cdata.url_rx_chain[i].url_mbuf = NULL;
1184 1.1 ichiro }
1185 1.1 ichiro if (sc->sc_cdata.url_rx_chain[i].url_xfer != NULL) {
1186 1.51 skrll usbd_destroy_xfer(sc->sc_cdata.url_rx_chain[i].url_xfer);
1187 1.1 ichiro sc->sc_cdata.url_rx_chain[i].url_xfer = NULL;
1188 1.1 ichiro }
1189 1.1 ichiro }
1190 1.1 ichiro
1191 1.1 ichiro /* Free TX resources. */
1192 1.1 ichiro for (i = 0; i < URL_TX_LIST_CNT; i++) {
1193 1.1 ichiro if (sc->sc_cdata.url_tx_chain[i].url_mbuf != NULL) {
1194 1.1 ichiro m_freem(sc->sc_cdata.url_tx_chain[i].url_mbuf);
1195 1.1 ichiro sc->sc_cdata.url_tx_chain[i].url_mbuf = NULL;
1196 1.1 ichiro }
1197 1.1 ichiro if (sc->sc_cdata.url_tx_chain[i].url_xfer != NULL) {
1198 1.51 skrll usbd_destroy_xfer(sc->sc_cdata.url_tx_chain[i].url_xfer);
1199 1.1 ichiro sc->sc_cdata.url_tx_chain[i].url_xfer = NULL;
1200 1.1 ichiro }
1201 1.1 ichiro }
1202 1.1 ichiro
1203 1.51 skrll /* Close pipes */
1204 1.51 skrll /* RX endpoint */
1205 1.51 skrll if (sc->sc_pipe_rx != NULL) {
1206 1.51 skrll err = usbd_close_pipe(sc->sc_pipe_rx);
1207 1.51 skrll if (err)
1208 1.51 skrll printf("%s: close rx pipe failed: %s\n",
1209 1.51 skrll device_xname(sc->sc_dev), usbd_errstr(err));
1210 1.51 skrll sc->sc_pipe_rx = NULL;
1211 1.51 skrll }
1212 1.51 skrll
1213 1.51 skrll /* TX endpoint */
1214 1.51 skrll if (sc->sc_pipe_tx != NULL) {
1215 1.51 skrll err = usbd_close_pipe(sc->sc_pipe_tx);
1216 1.51 skrll if (err)
1217 1.51 skrll printf("%s: close tx pipe failed: %s\n",
1218 1.51 skrll device_xname(sc->sc_dev), usbd_errstr(err));
1219 1.51 skrll sc->sc_pipe_tx = NULL;
1220 1.51 skrll }
1221 1.51 skrll
1222 1.1 ichiro sc->sc_link = 0;
1223 1.1 ichiro ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1224 1.1 ichiro }
1225 1.1 ichiro
1226 1.1 ichiro /* Set media options */
1227 1.1 ichiro Static int
1228 1.1 ichiro url_ifmedia_change(struct ifnet *ifp)
1229 1.1 ichiro {
1230 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1231 1.1 ichiro struct mii_data *mii = GET_MII(sc);
1232 1.30 dyoung int rc;
1233 1.1 ichiro
1234 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1235 1.1 ichiro
1236 1.1 ichiro if (sc->sc_dying)
1237 1.51 skrll return 0;
1238 1.1 ichiro
1239 1.1 ichiro sc->sc_link = 0;
1240 1.30 dyoung if ((rc = mii_mediachg(mii)) == ENXIO)
1241 1.30 dyoung return 0;
1242 1.30 dyoung return rc;
1243 1.1 ichiro }
1244 1.1 ichiro
1245 1.1 ichiro /* Report current media status. */
1246 1.1 ichiro Static void
1247 1.1 ichiro url_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1248 1.1 ichiro {
1249 1.1 ichiro struct url_softc *sc = ifp->if_softc;
1250 1.1 ichiro
1251 1.38 dyoung DPRINTF(("%s: %s: enter\n", device_xname(sc->sc_dev), __func__));
1252 1.1 ichiro
1253 1.1 ichiro if (sc->sc_dying)
1254 1.1 ichiro return;
1255 1.1 ichiro
1256 1.30 dyoung ether_mediastatus(ifp, ifmr);
1257 1.1 ichiro }
1258 1.1 ichiro
1259 1.1 ichiro Static void
1260 1.1 ichiro url_tick(void *xsc)
1261 1.1 ichiro {
1262 1.1 ichiro struct url_softc *sc = xsc;
1263 1.1 ichiro
1264 1.1 ichiro if (sc == NULL)
1265 1.1 ichiro return;
1266 1.1 ichiro
1267 1.38 dyoung DPRINTFN(0xff, ("%s: %s: enter\n", device_xname(sc->sc_dev),
1268 1.4 augustss __func__));
1269 1.1 ichiro
1270 1.1 ichiro if (sc->sc_dying)
1271 1.1 ichiro return;
1272 1.1 ichiro
1273 1.1 ichiro /* Perform periodic stuff in process context */
1274 1.22 joerg usb_add_task(sc->sc_udev, &sc->sc_tick_task, USB_TASKQ_DRIVER);
1275 1.1 ichiro }
1276 1.1 ichiro
1277 1.1 ichiro Static void
1278 1.1 ichiro url_tick_task(void *xsc)
1279 1.1 ichiro {
1280 1.1 ichiro struct url_softc *sc = xsc;
1281 1.1 ichiro struct ifnet *ifp;
1282 1.1 ichiro struct mii_data *mii;
1283 1.1 ichiro int s;
1284 1.1 ichiro
1285 1.1 ichiro if (sc == NULL)
1286 1.1 ichiro return;
1287 1.1 ichiro
1288 1.38 dyoung DPRINTFN(0xff, ("%s: %s: enter\n", device_xname(sc->sc_dev),
1289 1.4 augustss __func__));
1290 1.1 ichiro
1291 1.1 ichiro if (sc->sc_dying)
1292 1.1 ichiro return;
1293 1.1 ichiro
1294 1.1 ichiro ifp = GET_IFP(sc);
1295 1.1 ichiro mii = GET_MII(sc);
1296 1.1 ichiro
1297 1.1 ichiro if (mii == NULL)
1298 1.1 ichiro return;
1299 1.1 ichiro
1300 1.1 ichiro s = splnet();
1301 1.1 ichiro
1302 1.1 ichiro mii_tick(mii);
1303 1.1 ichiro if (!sc->sc_link) {
1304 1.1 ichiro mii_pollstat(mii);
1305 1.1 ichiro if (mii->mii_media_status & IFM_ACTIVE &&
1306 1.1 ichiro IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1307 1.1 ichiro DPRINTF(("%s: %s: got link\n",
1308 1.38 dyoung device_xname(sc->sc_dev), __func__));
1309 1.1 ichiro sc->sc_link++;
1310 1.1 ichiro if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1311 1.1 ichiro url_start(ifp);
1312 1.1 ichiro }
1313 1.1 ichiro }
1314 1.1 ichiro
1315 1.38 dyoung callout_reset(&sc->sc_stat_ch, hz, url_tick, sc);
1316 1.1 ichiro
1317 1.1 ichiro splx(s);
1318 1.1 ichiro }
1319 1.1 ichiro
1320 1.1 ichiro /* Get exclusive access to the MII registers */
1321 1.1 ichiro Static void
1322 1.1 ichiro url_lock_mii(struct url_softc *sc)
1323 1.1 ichiro {
1324 1.38 dyoung DPRINTFN(0xff, ("%s: %s: enter\n", device_xname(sc->sc_dev),
1325 1.4 augustss __func__));
1326 1.1 ichiro
1327 1.1 ichiro sc->sc_refcnt++;
1328 1.27 xtraeme rw_enter(&sc->sc_mii_rwlock, RW_WRITER);
1329 1.1 ichiro }
1330 1.1 ichiro
1331 1.1 ichiro Static void
1332 1.1 ichiro url_unlock_mii(struct url_softc *sc)
1333 1.1 ichiro {
1334 1.38 dyoung DPRINTFN(0xff, ("%s: %s: enter\n", device_xname(sc->sc_dev),
1335 1.4 augustss __func__));
1336 1.1 ichiro
1337 1.27 xtraeme rw_exit(&sc->sc_mii_rwlock);
1338 1.1 ichiro if (--sc->sc_refcnt < 0)
1339 1.42 mrg usb_detach_wakeupold(sc->sc_dev);
1340 1.1 ichiro }
1341 1.1 ichiro
1342 1.1 ichiro Static int
1343 1.38 dyoung url_int_miibus_readreg(device_t dev, int phy, int reg)
1344 1.1 ichiro {
1345 1.1 ichiro struct url_softc *sc;
1346 1.51 skrll uint16_t val;
1347 1.1 ichiro
1348 1.1 ichiro if (dev == NULL)
1349 1.51 skrll return 0;
1350 1.1 ichiro
1351 1.38 dyoung sc = device_private(dev);
1352 1.1 ichiro
1353 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x\n",
1354 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg));
1355 1.1 ichiro
1356 1.1 ichiro if (sc->sc_dying) {
1357 1.1 ichiro #ifdef DIAGNOSTIC
1358 1.38 dyoung printf("%s: %s: dying\n", device_xname(sc->sc_dev),
1359 1.4 augustss __func__);
1360 1.1 ichiro #endif
1361 1.51 skrll return 0;
1362 1.1 ichiro }
1363 1.1 ichiro
1364 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1365 1.1 ichiro if (phy != 0) {
1366 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1367 1.38 dyoung device_xname(sc->sc_dev), __func__, phy));
1368 1.51 skrll return 0;
1369 1.1 ichiro }
1370 1.1 ichiro
1371 1.1 ichiro url_lock_mii(sc);
1372 1.1 ichiro
1373 1.1 ichiro switch (reg) {
1374 1.1 ichiro case MII_BMCR: /* Control Register */
1375 1.1 ichiro reg = URL_BMCR;
1376 1.1 ichiro break;
1377 1.1 ichiro case MII_BMSR: /* Status Register */
1378 1.1 ichiro reg = URL_BMSR;
1379 1.1 ichiro break;
1380 1.1 ichiro case MII_PHYIDR1:
1381 1.1 ichiro case MII_PHYIDR2:
1382 1.1 ichiro val = 0;
1383 1.1 ichiro goto R_DONE;
1384 1.1 ichiro break;
1385 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1386 1.1 ichiro reg = URL_ANAR;
1387 1.1 ichiro break;
1388 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1389 1.1 ichiro reg = URL_ANLP;
1390 1.1 ichiro break;
1391 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1392 1.1 ichiro reg = URL_MSR;
1393 1.1 ichiro break;
1394 1.1 ichiro default:
1395 1.1 ichiro printf("%s: %s: bad register %04x\n",
1396 1.38 dyoung device_xname(sc->sc_dev), __func__, reg);
1397 1.1 ichiro val = 0;
1398 1.1 ichiro goto R_DONE;
1399 1.1 ichiro break;
1400 1.1 ichiro }
1401 1.1 ichiro
1402 1.1 ichiro if (reg == URL_MSR)
1403 1.1 ichiro val = url_csr_read_1(sc, reg);
1404 1.1 ichiro else
1405 1.1 ichiro val = url_csr_read_2(sc, reg);
1406 1.1 ichiro
1407 1.1 ichiro R_DONE:
1408 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1409 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg, val));
1410 1.1 ichiro
1411 1.1 ichiro url_unlock_mii(sc);
1412 1.51 skrll return val;
1413 1.1 ichiro }
1414 1.1 ichiro
1415 1.1 ichiro Static void
1416 1.38 dyoung url_int_miibus_writereg(device_t dev, int phy, int reg, int data)
1417 1.1 ichiro {
1418 1.1 ichiro struct url_softc *sc;
1419 1.1 ichiro
1420 1.1 ichiro if (dev == NULL)
1421 1.1 ichiro return;
1422 1.1 ichiro
1423 1.38 dyoung sc = device_private(dev);
1424 1.1 ichiro
1425 1.1 ichiro DPRINTFN(0xff, ("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1426 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg, data));
1427 1.1 ichiro
1428 1.1 ichiro if (sc->sc_dying) {
1429 1.1 ichiro #ifdef DIAGNOSTIC
1430 1.38 dyoung printf("%s: %s: dying\n", device_xname(sc->sc_dev),
1431 1.4 augustss __func__);
1432 1.1 ichiro #endif
1433 1.1 ichiro return;
1434 1.1 ichiro }
1435 1.1 ichiro
1436 1.1 ichiro /* XXX: one PHY only for the RTL8150 internal PHY */
1437 1.1 ichiro if (phy != 0) {
1438 1.1 ichiro DPRINTFN(0xff, ("%s: %s: phy=%d is not supported\n",
1439 1.38 dyoung device_xname(sc->sc_dev), __func__, phy));
1440 1.1 ichiro return;
1441 1.1 ichiro }
1442 1.1 ichiro
1443 1.1 ichiro url_lock_mii(sc);
1444 1.1 ichiro
1445 1.1 ichiro switch (reg) {
1446 1.1 ichiro case MII_BMCR: /* Control Register */
1447 1.1 ichiro reg = URL_BMCR;
1448 1.1 ichiro break;
1449 1.1 ichiro case MII_BMSR: /* Status Register */
1450 1.1 ichiro reg = URL_BMSR;
1451 1.1 ichiro break;
1452 1.1 ichiro case MII_PHYIDR1:
1453 1.1 ichiro case MII_PHYIDR2:
1454 1.1 ichiro goto W_DONE;
1455 1.1 ichiro break;
1456 1.1 ichiro case MII_ANAR: /* Autonegotiation advertisement */
1457 1.1 ichiro reg = URL_ANAR;
1458 1.1 ichiro break;
1459 1.1 ichiro case MII_ANLPAR: /* Autonegotiation link partner abilities */
1460 1.1 ichiro reg = URL_ANLP;
1461 1.1 ichiro break;
1462 1.1 ichiro case URLPHY_MSR: /* Media Status Register */
1463 1.1 ichiro reg = URL_MSR;
1464 1.1 ichiro break;
1465 1.1 ichiro default:
1466 1.1 ichiro printf("%s: %s: bad register %04x\n",
1467 1.38 dyoung device_xname(sc->sc_dev), __func__, reg);
1468 1.1 ichiro goto W_DONE;
1469 1.1 ichiro break;
1470 1.1 ichiro }
1471 1.1 ichiro
1472 1.1 ichiro if (reg == URL_MSR)
1473 1.1 ichiro url_csr_write_1(sc, reg, data);
1474 1.1 ichiro else
1475 1.1 ichiro url_csr_write_2(sc, reg, data);
1476 1.1 ichiro W_DONE:
1477 1.1 ichiro
1478 1.1 ichiro url_unlock_mii(sc);
1479 1.1 ichiro return;
1480 1.1 ichiro }
1481 1.1 ichiro
1482 1.1 ichiro Static void
1483 1.44 matt url_miibus_statchg(struct ifnet *ifp)
1484 1.1 ichiro {
1485 1.1 ichiro #ifdef URL_DEBUG
1486 1.44 matt if (ifp == NULL)
1487 1.1 ichiro return;
1488 1.1 ichiro
1489 1.44 matt DPRINTF(("%s: %s: enter\n", ifp->if_xname, __func__));
1490 1.1 ichiro #endif
1491 1.1 ichiro /* Nothing to do */
1492 1.1 ichiro }
1493 1.1 ichiro
1494 1.1 ichiro #if 0
1495 1.1 ichiro /*
1496 1.1 ichiro * external PHYs support, but not test.
1497 1.1 ichiro */
1498 1.1 ichiro Static int
1499 1.38 dyoung url_ext_miibus_redreg(device_t dev, int phy, int reg)
1500 1.1 ichiro {
1501 1.38 dyoung struct url_softc *sc = device_private(dev);
1502 1.51 skrll uint16_t val;
1503 1.1 ichiro
1504 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x\n",
1505 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg));
1506 1.1 ichiro
1507 1.1 ichiro if (sc->sc_dying) {
1508 1.1 ichiro #ifdef DIAGNOSTIC
1509 1.38 dyoung printf("%s: %s: dying\n", device_xname(sc->sc_dev),
1510 1.4 augustss __func__);
1511 1.1 ichiro #endif
1512 1.51 skrll return 0;
1513 1.1 ichiro }
1514 1.1 ichiro
1515 1.1 ichiro url_lock_mii(sc);
1516 1.1 ichiro
1517 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy & URL_PHYADD_MASK);
1518 1.1 ichiro /*
1519 1.1 ichiro * RTL8150L will initiate a MII management data transaction
1520 1.1 ichiro * if PHYCNT_OWN bit is set 1 by software. After transaction,
1521 1.1 ichiro * this bit is auto cleared by TRL8150L.
1522 1.1 ichiro */
1523 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT,
1524 1.1 ichiro (reg | URL_PHYCNT_PHYOWN) & ~URL_PHYCNT_RWCR);
1525 1.1 ichiro for (i = 0; i < URL_TIMEOUT; i++) {
1526 1.1 ichiro if ((url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN) == 0)
1527 1.1 ichiro break;
1528 1.1 ichiro }
1529 1.1 ichiro if (i == URL_TIMEOUT) {
1530 1.38 dyoung printf("%s: MII read timed out\n", device_xname(sc->sc_dev));
1531 1.1 ichiro }
1532 1.5 augustss
1533 1.1 ichiro val = url_csr_read_2(sc, URL_PHYDAT);
1534 1.1 ichiro
1535 1.1 ichiro DPRINTF(("%s: %s: phy=%d reg=0x%04x => 0x%04x\n",
1536 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg, val));
1537 1.1 ichiro
1538 1.1 ichiro url_unlock_mii(sc);
1539 1.51 skrll return val;
1540 1.1 ichiro }
1541 1.1 ichiro
1542 1.1 ichiro Static void
1543 1.38 dyoung url_ext_miibus_writereg(device_t dev, int phy, int reg, int data)
1544 1.1 ichiro {
1545 1.38 dyoung struct url_softc *sc = device_private(dev);
1546 1.1 ichiro
1547 1.1 ichiro DPRINTF(("%s: %s: enter, phy=%d reg=0x%04x data=0x%04x\n",
1548 1.38 dyoung device_xname(sc->sc_dev), __func__, phy, reg, data));
1549 1.1 ichiro
1550 1.1 ichiro if (sc->sc_dying) {
1551 1.1 ichiro #ifdef DIAGNOSTIC
1552 1.38 dyoung printf("%s: %s: dying\n", device_xname(sc->sc_dev),
1553 1.4 augustss __func__);
1554 1.1 ichiro #endif
1555 1.1 ichiro return;
1556 1.1 ichiro }
1557 1.1 ichiro
1558 1.1 ichiro url_lock_mii(sc);
1559 1.1 ichiro
1560 1.1 ichiro url_csr_write_2(sc, URL_PHYDAT, data);
1561 1.1 ichiro url_csr_write_1(sc, URL_PHYADD, phy);
1562 1.1 ichiro url_csr_write_1(sc, URL_PHYCNT, reg | URL_PHYCNT_RWCR); /* Write */
1563 1.1 ichiro
1564 1.1 ichiro for (i=0; i < URL_TIMEOUT; i++) {
1565 1.1 ichiro if (url_csr_read_1(sc, URL_PHYCNT) & URL_PHYCNT_PHYOWN)
1566 1.1 ichiro break;
1567 1.1 ichiro }
1568 1.1 ichiro
1569 1.1 ichiro if (i == URL_TIMEOUT) {
1570 1.1 ichiro printf("%s: MII write timed out\n",
1571 1.38 dyoung device_xname(sc->sc_dev));
1572 1.1 ichiro }
1573 1.1 ichiro
1574 1.1 ichiro url_unlock_mii(sc);
1575 1.1 ichiro return;
1576 1.1 ichiro }
1577 1.1 ichiro #endif
1578